Method for optimizing performance of a link and electronic device

Abstract

The application discloses a link performance optimization method and an electronic device, relates to the technical field of storage systems, and is characterized in that a bus link to be optimized is accurately positioned through a global bus hierarchical topology architecture, and transmission performance optimization of the bus link is performed in a targeted manner according to real-time service data of the bus link to be optimized, so as to adapt to the real-time fluctuation state of the bus link, thereby improving the accuracy of link optimization and further improving storage performance.

Description

Technical Field

[0001] This application relates to the field of storage system technology, and in particular to link performance optimization methods and electronic devices. Background Technology

[0002] In fields such as high-performance computing, cloud computing, enterprise-level storage systems, and large-scale data centers, high storage performance is required. Current technologies that optimize storage performance using statically fixed parameters cannot adapt to real-time fluctuations in the network connection, resulting in low optimization accuracy. Summary of the Invention

[0003] This application provides a method and electronic device for optimizing link performance, in order to at least solve the problem of low accuracy in storage performance optimization in related technologies.

[0004] This application provides a method for optimizing link performance, including:

[0005] Determine the bus subtree in the global bus hierarchy topology architecture corresponding to the storage device, and determine the corresponding bus link based on the bus subtree;

[0006] Collect service data from the bus link, determine the target scenario corresponding to the service data, and determine the performance evaluation dimensions of the bus link based on the target scenario;

[0007] Based on performance evaluation dimensions and business data, determine performance data, iteratively adjust the link parameters of the bus link based on the performance data, obtain the adjustment parameters, and acquire the performance change data after each adjustment.

[0008] The performance optimization of the bus link is completed when the performance change data is less than or equal to the preset performance threshold.

[0009] This application also provides a link performance optimization device, including:

[0010] The acquisition module is used to determine the bus subtree in the global bus hierarchy topology architecture corresponding to the storage device, and to determine the corresponding bus link based on the bus subtree.

[0011] The acquisition module is used to collect business data from the bus link, determine the target scenario corresponding to the business data, and determine the performance evaluation dimensions of the bus link based on the target scenario.

[0012] The adjustment module is used to determine performance data based on performance evaluation dimensions and business data, iteratively adjust the link parameters of the bus link based on the performance data, obtain the adjustment parameters, and acquire the performance change data after each adjustment.

[0013] The optimization module is used to optimize the performance of the bus link until the performance change data is less than or equal to a preset performance threshold.

[0014] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for implementing the performance optimization method of any of the above-described links when executing the computer program.

[0015] This application also provides a non-volatile computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the above-described link performance optimization methods.

[0016] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described link performance optimization methods.

[0017] This application accurately locates the bus links to be optimized through a global bus-level topology architecture. Based on the real-time service data of the bus links to be optimized, the transmission performance of the bus links is optimized in a targeted manner to adapt to the real-time fluctuation status of the bus links, thereby improving the accuracy of link optimization and thus improving storage performance. Attached Figure Description

[0018] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram illustrating an application scenario of a link performance optimization method provided in an embodiment of this application.

[0020] Figure 2 A flowchart illustrating a link performance optimization method provided in an embodiment of this application;

[0021] Figure 3 A schematic diagram of the global bus hierarchy topology provided in the embodiments of this application;

[0022] Figure 4 A schematic diagram of a PCIe protocol message provided in an embodiment of this application;

[0023] Figure 5 A schematic diagram of the PCIe protocol specification provided for an embodiment of this application;

[0024] Figure 6 A flowchart illustrating another link performance optimization method provided in this application embodiment;

[0025] Figure 7A schematic diagram illustrating adaptive tuning provided in an embodiment of this application;

[0026] Figure 8 A schematic diagram illustrating the loop performance optimization provided in an embodiment of this application;

[0027] Figure 9 This is a schematic diagram of the structure of a link performance optimization device provided in an embodiment of this application;

[0028] Figure 10 A schematic diagram of another link performance optimization device provided in an embodiment of this application;

[0029] Figure 11 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0030] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0031] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0032] For example, in high-performance computing, cloud computing, enterprise-level storage systems, and large-scale data centers, where storage input / output (IO) performance requirements are stringent, the Non-Volatile Memory Express (NVMe) protocol enables high-speed data access to non-volatile storage devices through the high-speed Peripheral Component Interconnect Express (PCIe) interface. Its performance directly impacts the overall system throughput. With the iteration from PCIe version 3.0 to 8.0, single-link bandwidth has significantly improved.

[0033] In related technologies, the maximum payload size (MPS) configuration of PCIe links still follows the global minimum strategy from the Basic Input Output System (BIOS) stage.

[0034] This results in some storage devices not being able to fully utilize their hardware potential. Especially in mixed business scenarios (such as database transaction processing and video streaming coexisting), the input / output operations per second (IOPS) and bandwidth performance of NVMe disks are limited by the transmission efficiency of the PCIe link, affecting the storage performance of the storage devices.

[0035] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0036] The specific application environment architecture upon which the performance optimization methods for the link depend is described here. (References) Figure 1 The NVMe storage service layered model is divided into an upper NVMe software stack protocol processing layer and a lower PCIe hardware bus transmission layer, which fully presents the entire service chain from the customer's business issuing read and write requests to the backend solid-state drive completing data interaction.

[0037] The customer business on the left serves as the input source for IO requests. Business read and write requests are sent down to the NVMe software stack marked A. This layer has an NVMe read and write processing unit that performs protocol encapsulation and command distribution for business IO requests. It also has an IO model analysis function that analyzes business characteristics such as IO data block size and concurrency frequency in real time to distinguish different business operation scenarios.

[0038] The standardized I / O instructions are then transmitted down to the PCIe hardware transport layer of region B. In the underlying transport link, the instructions are first sent to the PCIe RP1 root port. The root port serves as the hardware entry and exit point for the processor to interact with the PCIe bus. It is configured with an independent MPS maximum payload size and corresponding cache resources. The instructions flow into the PCIe topology through the root port. The entire topology link also has its own dedicated MPS parameters and cache. The topology branch finally connects to the end PCIe-SSD storage device. The solid state drive (SSD) device also has its own independent MPS and cache resources. The underlying layer relies on the PCIe driver to manage the bus hardware and complete the PCIe data transmission.

[0039] In the entire link, the NVMe software stack is responsible for extracting service IO characteristics and outputting service data, while the PCIe driver is responsible for collecting bus transmission performance indicators. The data from both can be combined to calculate link performance change data. Meanwhile, the root port, bus topology, MPS of solid-state drive segment configuration, cache, etc. are adjustable link parameters.

[0040] Figure 2 A flowchart illustrating the link performance optimization method provided in this application embodiment is shown below. Figure 2 As shown, embodiments of this application provide a link performance optimization method, which is described in detail below:

[0041] S201. Determine the bus subtree in the global bus hierarchy topology corresponding to the storage device, and determine the corresponding bus link based on the bus subtree.

[0042] For example, the storage device can be a Non-Volatile Memory Express (NVMe) solid-state drive, connected to a server system or storage system (hereinafter referred to as the system) via a high-speed peripheral component interconnect express (PCIe) bus.

[0043] Optionally, when the storage device powers on normally, the bus subtree can be obtained from the local non-volatile storage medium, or by traversing the global bus hierarchy topology.

[0044] Optionally, when the system powers on and resets, the BIOS system first enumerates and initializes all PCIe devices, and then the operating system starts the kernel to scan the complete PCIe topology again.

[0045] Optionally, when a hot-plug event occurs, the system can detect the device change via an interrupt in the advanced configuration and power management interface and trigger a rescan. During the scan, the global bus hierarchy topology is traversed, the configuration space of each bus topology node is identified, and the node type and mounting relationships are obtained.

[0046] For example, the global bus hierarchy topology starts with the root complex inside the central processing unit and connects downwards to multiple root ports (RPs). Each root port can be expanded into a bus subtree that includes a high-speed peripheral interconnect bus switch (PCIe switch) and multiple end points.

[0047] The bus subtree starts from the root port and contains all subsequent levels of bus nodes and devices. A bus link is the physical transmission path between two endpoint devices for communication via PCIe, such as a channel from the root port to an endpoint device, or a channel from a switch to an endpoint device. During scanning, the system records the bus number, device number, function number (BDF), and upstream and downstream connections of each node, forming a complete topology tree.

[0048] For example, when determining the bus subtree corresponding to a storage device, identification is performed by reading the Class Code field in the storage device's configuration space. This field clearly identifies the device type; for example, Class Code 0x010802 indicates an NVMe solid-state drive. Once a storage device is detected, the process traces back up from that device node to the root port. All nodes along this traversal path together constitute the bus subtree corresponding to that storage device. This bus subtree is subsequently defined as the target range for performance optimization, and all link parameters within it are adjusted synchronously. By accurately identifying the bus subtree, ineffective optimization of subtrees containing non-storage devices (such as network interface cards) in the system is avoided, reducing unnecessary scanning and configuration overhead.

[0049] Below, in conjunction with Figure 3 The global bus hierarchical topology is described.

[0050] Figure 3 This is a schematic diagram of the global bus hierarchy topology provided in an embodiment of this application. Figure 3 As shown, the CPU root complex CPU-RC serves as the top-level initiator of the entire PCIe bus. CPU-RC branches out into multiple independent PCIe root ports RP1, RP2, RP3 and up to RPn. Each root port extends to form an independent bus branch, i.e., a bus subtree, that does not interfere with each other. The hardware configuration and the types of storage devices mounted on each branch are significantly different.

[0051] The branch from RP1 connects to both SAS cards and SSD1 peripherals, forming a short branch topology with a single port directly connecting multiple devices. The branch from RP2 connects to a PCIe-Switch chip, which expands to three channels to connect to SSD2, SSD3, and SSD4 solid-state drives, forming a complex long topology with multiple cascaded and parallel storage devices. The branch from RP3 connects to Connect-7 peripherals, and the branch from RPn can be flexibly expanded to include various unknown PCIe peripherals according to business needs.

[0052] The server PCIe topology has many branches, varying link lengths, and different types of mounted devices. Each branch has independent adjustable link parameters such as transmission buffers and MPS. If static link configuration is used, it cannot adapt to the hardware differences and service load of each topology branch.

[0053] The SAS card connects via the Small Computer System Interface (SCSI) protocol.

[0054] Below, in conjunction with Figure 4 Explanation of PCIe protocol messages.

[0055] Figure 4 This is a schematic diagram of a PCIe protocol message provided in an embodiment of this application. Figure 4 As shown, PCIe is a point-to-point serial protocol. Communication is initiated by the PCIe master device. Typically, both RC and EP have master capabilities. PCIe data transmission is organized in TLP form. According to the protocol, the Data Payload field in TLP is the effective payload of a TLP transmission. The length is configurable and ranges from 128 bytes to 4096 bytes.

[0056] Below, in conjunction with Figure 5 This section explains the PCIe protocol specification.

[0057] Figure 5 This is a schematic diagram of the PCIe protocol specification provided in an embodiment of this application. Figure 5 As shown, the payload size is negotiated between two adjacent PCIe devices, with the minimum value being the negotiated result. There are two PCIe subtrees starting from RP1 and RP2 respectively. The negotiation result between Dev1 and the PCIe-Switch is 128 bytes, the negotiation result between Dev2 and the PCIe-Switch is 128 bytes, and the negotiation result between the PCIe-Switch and RP1 is 128 bytes. Therefore, the final payload size for the RP1 link is 128 bytes, and the payload size for the RP2 link is 256 bytes.

[0058] In actual motherboard designs, PCIe topologies are more complex. To simplify processing, the BIOS typically sets a global minimum MPS (Maximum Per Second), meaning the MPS for all RPs is 128 bytes. This can limit the effective carrying capacity of some PCIe subtrees. According to the PCIe specification, for the same TLP (Transmission Per Message), a higher MPS results in a higher TLP payload and higher single-transmission efficiency. However, if the MPS value is too high, while single-transmission efficiency is higher, overall efficiency may decrease. This is because of the "PCIe link credit value." When the credit value between the PCIe-Switch and Dev1 is exhausted, even if a TLP sent by RP1 has reached the PCIe-Switch, it can only be cached in the PCIe-Switch's uplink cache. The PCIe-Switch can only forward it to Dev1 after Dev1 releases the credit value via DLLP. During NVMe service operation, if PCIe link performance cannot be maximized, the performance of PCIe-based NVMe services will also be affected.

[0059] Based on the above implementation method, by responding to power-on reset or hot-plug events, the global bus topology is automatically scanned and the bus subtree corresponding to the storage device is identified, thus achieving precise delineation of the optimization target range. This process avoids the tedious work of manually configuring topology information and can adapt to scenarios of dynamic device changes. It can be automatically triggered after the first power-on or after a device hot-plug, ensuring the real-time nature of the optimization process.

[0060] S202. Collect service data from the bus link, determine the target scenario corresponding to the service data, and determine the performance evaluation dimensions of the bus link based on the target scenario.

[0061] For example, business data includes input / output request information generated by the storage device during operation, specifically including metrics such as data block size, number of input / output operations (IOPS), data throughput, and latency. Real-time data collection is accomplished through the operating system's block device layer statistics interface or hardware performance monitoring counters. The system polls the performance counters of each storage device at fixed time intervals (e.g., 1 second). The collected business data is temporarily stored in a statistical table in memory for subsequent scenario assessment and performance analysis.

[0062] For example, target scenarios can be categorized based on the characteristics of business data, such as large-capacity input / output scenarios and small-capacity input / output scenarios. Large-capacity input / output scenarios typically correspond to applications such as video streaming and big data batch processing, where the data block size is larger than a preset value (e.g., 128KB); small-capacity input / output scenarios correspond to applications such as database transactions and online transactions, where the data block size is smaller than or equal to the preset value.

[0063] Different target scenarios have different performance requirements for the link: In high-capacity input and output scenarios, the effective data volume of a single data packet transmitted each time is large, and the total effective data transmission volume of the link (i.e., throughput capacity) becomes the core concern.

[0064] In scenarios with small-capacity input / output, each transmission of a single data packet is small, but the request volume is extremely large, making the single-transmission bandwidth and low-latency characteristics of the link even more critical.

[0065] Based on the above implementation methods, this application achieves precise matching between evaluation criteria and business types by collecting business data in real time, judging target scenarios, and dynamically selecting corresponding performance evaluation dimensions. This enables the adjustment of link parameters to focus on the performance indicators most valuable to actual business, avoiding resource waste caused by blind optimization.

[0066] S203. Based on the performance evaluation dimensions and business data, determine the performance data, iteratively adjust the link parameters of the bus link according to the performance data, obtain the adjustment parameters, and acquire the performance change data after each adjustment.

[0067] For example, link parameters are configurable parameters in high-speed peripheral interconnect bus protocols used to control data transmission behavior, such as the maximum payload size. The maximum payload size determines the maximum number of bytes in the data field of a single transport layer packet (TLP), with valid values ​​of 128 bytes, 256 bytes, 512 bytes, 1024 bytes, 2048 bytes, and 4096 bytes. Adjusting the link parameter modifies its current actual value, thereby changing the data carrying capacity of a single packet transmission.

[0068] For example, the collected bus link service data is parsed based on a preset performance evaluation dimension to determine the current link performance data, and the link parameters of the bus link are iteratively adjusted according to the performance data to generate corresponding adjustment parameters. At the same time, the performance change data corresponding to each parameter adjustment is obtained.

[0069] Among them, the performance data is the real-time performance index of the link under a single service sampling, and the performance change data is used to characterize the degree of deviation and fluctuation of the link performance relative to the baseline state during multiple iterations.

[0070] This solution employs an iterative approximation strategy to optimize link parameters. Taking the maximum effective payload size of PCIe as an example, if the performance change data obtained in the current iteration shows a performance improvement, the parameter will continue to be increased in the current adjustment direction, for example, from 128 bytes to 256 bytes; if the performance change data shows a performance decrease, the parameter adjustment direction will be reversed, for example, from 2048 bytes back to 1024 bytes. During the parameter iterative adjustment process, the value of the link parameter to be configured must not exceed the minimum value of the upper limit of the hardware capability of all devices in the same bus subtree, ensuring the hardware compatibility of the entire bus link. After each link parameter iterative adjustment is completed, service data is re-collected, performance data is updated, and a new round of performance change data is obtained, continuously performing closed-loop iterative optimization until the performance change data is less than or equal to the preset performance threshold, ultimately completing the performance optimization of the bus link. The adjustment parameters for each iteration are determined by the preset parameter adjustment direction and parameter adjustment step size.

[0071] S204. The performance optimization of the bus link is completed when the performance change data is less than or equal to the preset performance threshold.

[0072] For example, if the difference in performance change data is within a preset fluctuation threshold (e.g., 3%) in multiple consecutive adjustments (e.g., 2 or 3 consecutive adjustments), then the performance change data is determined to be less than or equal to the preset performance threshold.

[0073] For example, if the difference between the current adjusted real-time performance metric and the previous adjusted baseline metric does not exceed 3%, and the fluctuation range is also within 3%, the system determines that the current link parameters are close to the optimal value and stops further adjustments.

[0074] For example, once the performance change data is less than or equal to a preset performance threshold, the system determines the current link parameters as the final parameters. After optimization, the bus link's parameters, such as its maximum effective load size, are highly matched with the input-output model of the current business scenario, maximizing the link transmission efficiency.

[0075] Optionally, after performance optimization is completed, the system continues to monitor business data. If a significant change in the business model is detected (such as switching from a large input / output scenario to a small input / output scenario), the optimization process is restarted, and data is collected and adjusted again starting from step S202 to achieve adaptive optimization throughout the entire lifecycle.

[0076] Based on any of the above embodiments, the following, in conjunction with Figure 6 The detailed process of link performance optimization methods is explained.

[0077] Figure 6 This is a flowchart illustrating another link performance optimization method provided in an embodiment of this application. Figure 6As shown, the method includes the following steps:

[0078] S601, Read the device identifier of the storage device.

[0079] For example, the device identifier of a storage device is obtained through specific fields in the high-speed peripheral interconnect bus configuration space, which may include the device ID and the class code.

[0080] For example, the category code for an NVMe SSD is 0x010802. The system enumerates each bus node and uses I / O read / write commands to access the node configuration space at offset address 0x00 to read the vendor identifier and device identifier, and at offset address 0x0A to read the category code field. The device identifier is used to confirm the device type, ensuring that subsequent topology analysis is only performed on the target storage device.

[0081] S602. When the device identifier is not included in the local non-volatile storage medium, traverse multiple bus topology nodes of the global bus hierarchy topology architecture and determine the identifier field of each bus topology node from the configuration space of each bus topology node.

[0082] For example, a global bus hierarchical topology consists of multiple levels of bus topology nodes, including the root port, the uplink and downlink ports of the high-speed peripheral interconnect bus switch (PCIe switch), and the end point.

[0083] For example, the global bus topology traversal process is triggered only when the device identifier of the current storage device is not found in the local non-volatile storage medium. If the device identifier of the current storage device is found in the local non-volatile storage medium, the corresponding bus subtree is directly determined from the local non-volatile storage medium based on the device identifier to improve query efficiency.

[0084] Optionally, the traversal process starts from the root port and visits each node using either a depth-first or breadth-first strategy. Each node's configuration space contains an identification field, such as a header type and a bus number register, which indicate the type of the node (bridge device or endpoint device) and its hierarchical position in the topology.

[0085] S603. Match the identifier field of each bus topology node with the device identifier to determine the valid topology node with the mounted storage device from multiple bus topology nodes.

[0086] For example, the matching process compares the category code of each bus topology node with the category code of the storage device (e.g., 0x010802). When a node's category code matches that of a storage device, that node is identified as a valid topology node. For instance, during the traversal, if the category code of any device under the bus is found to be 0x010802, then this node is a valid topology node with an NVMe solid-state drive mounted on it.

[0087] S604. Determine the bus subtree based on the valid topology nodes.

[0088] For example, bus subtrees are identified in the global bus hierarchy topology, centered on valid topology nodes.

[0089] Based on the above implementation method, by accurately matching device identifiers and tracing back the topology path, the effective topology nodes and bus subtrees of mounted storage devices are automatically identified, avoiding interference from unrelated devices, thereby improving the accuracy of performance optimization and thus improving storage performance.

[0090] One feasible implementation method is to determine the bus subtree using the following methods:

[0091] From the global bus hierarchical topology architecture, determine the hierarchical relationships between valid topology nodes;

[0092] Based on the hierarchical relationship between superior and subordinate nodes, determine the topological branches of valid topological nodes;

[0093] Generate a bus subtree based on valid topology nodes and topology branches.

[0094] For example, starting from a valid topology node, the path traces back upwards to its root port. The traversal path sequentially passes through the parent node of the valid topology node, the parent node's parent node, and finally the root port. All nodes along this path (including the root port, switches, and end devices) together constitute the bus subtree corresponding to the storage device.

[0095] For example, if the bus number of an effective topology node is 10, its parent node is a switch with bus number 9, and the uplink port of the switch is connected to the root port with bus number 1, then the bus subtree contains all nodes on bus numbers 1, 9, and 10.

[0096] In this feasible implementation, the complex global topology is reduced to the smallest unit that needs to be optimized, providing an accurate target range for subsequent parameter adjustments, thereby improving the accuracy of performance optimization and thus improving storage performance.

[0097] S605: Collects service data from the bus link in real time and determines the performance evaluation dimensions of the bus link based on the target scenario corresponding to the service data.

[0098] It should be noted that the execution process of S605 is the same as that of S202, and will not be repeated here.

[0099] One feasible implementation approach is to determine performance evaluation dimensions using the following methods:

[0100] Determine the data block size characteristic parameters of the business data; based on the data block size characteristic parameters and preset parameter values, determine whether the target scenario is a large-capacity input / output scenario or a small-capacity input / output scenario; when the target scenario is a large-capacity input / output scenario, determine the performance evaluation dimension as data transmission throughput; when the target scenario is a small-capacity input / output scenario, determine the performance evaluation dimension as transmission bandwidth.

[0101] For example, the data block size feature parameter describes the payload bytes of each data packet in a business input / output request. The system calculates a weighted average or median as the feature parameter by statistically analyzing the data block size distribution of all input / output requests within a sampling period.

[0102] Optionally, the preset parameter value can be set to 128KB, which is determined based on the typical application characteristics of the high-speed peripheral interconnect bus protocol. When the characteristic parameter is greater than 128KB, the target scenario is judged to be a high-capacity input / output scenario, corresponding to applications such as video streaming or data backup; when the characteristic parameter is less than or equal to 128KB, the target scenario is judged to be a low-capacity input / output scenario, corresponding to applications such as database transactions or online transactions.

[0103] Optionally, preset parameter values ​​can also be dynamically adjusted based on storage device firmware characteristics or user profiles. For example, for low-latency devices, preset parameter values ​​can be reduced to 64KB to more sensitively capture small input / output scenarios.

[0104] To illustrate with a scenario example, in a system running video surveillance services, the data block size can be 256KB or 512KB. In this case, the characteristic parameter is greater than 128KB, the target scenario is determined to be a high-capacity input / output scenario, and the performance evaluation dimension is determined to be data transmission throughput (in MB / s). However, in a device running a transaction system, the data block size is concentrated at 4KB. In this case, the characteristic parameter is less than 128KB, the target scenario is determined to be a low-capacity input / output scenario, and the performance evaluation dimension is determined to be transmission bandwidth (characterized by IOPS).

[0105] In this feasible implementation, by quantifying the characteristics of data block size and comparing them with preset parameters, an objective determination of the target scenario is achieved. Then, a precise evaluation dimension based on throughput or transmission bandwidth is selected, ensuring the scenario adaptability of the performance evaluation direction, thereby improving storage performance.

[0106] S606. Determine performance data based on performance evaluation dimensions and business data.

[0107] One feasible implementation method is to determine performance data through the following means:

[0108] Based on the performance evaluation dimensions, the business data is normalized and filtered to obtain performance data;

[0109] The performance change data after each adjustment can be obtained through the following methods, including:

[0110] After each adjustment, acquire historical performance data of the bus link;

[0111] The adjusted performance data is time-series aligned and matched with historical performance data, and the aligned data is compared to obtain the index difference and fluctuation range.

[0112] The difference in indicators and the magnitude of fluctuations are defined as performance change data.

[0113] For example, normalization filtering refers to extracting only a subset of data that is relevant to the current performance evaluation dimension from the collected raw business data.

[0114] If the evaluation dimension is data transmission throughput, then the megabytes per second (MB / s) metric is selected from the business data; if the evaluation dimension is transmission bandwidth, then the number of input / output requests per second (IOPS) is selected. After normalization and filtering, real-time performance metric data is generated, which is the performance data of the claims. Normalization ensures that the selected data has a uniform dimension and sampling period, such as calculating the average MB / s or average IOPS within a 1-second time window, forming performance data with a single dimension and strong comparability.

[0115] After completing the link parameter adjustment, historical performance data is obtained. The performance data obtained after this adjustment is time-series aligned and matched with the historical performance data. The difference in indicators and the fluctuation range are compared and determined as the performance change data.

[0116] In this feasible implementation, by normalizing the filtering process, complex and multi-dimensional business data is compressed into a single-dimensional real-time indicator that directly corresponds to the evaluation dimension. This simplifies the comparative analysis process, improves the accuracy of performance data, and thus enhances storage performance.

[0117] For example, historical benchmark performance data is stored in system memory or non-volatile storage media, recording real-time performance data when the performance change was less than or equal to a preset performance threshold after the last adjustment. For instance, at the end of the previous optimization round, the system uses the last collected performance value as historical benchmark performance data for subsequent comparison. If it is the first optimization, the historical benchmark performance data is the performance data under the current system's default configuration, serving as an initial reference.

[0118] For example, time-series alignment matching refers to aligning real-time performance metric data with historical benchmark performance metric data on the timestamp to ensure that the sampling time windows of the two are consistent.

[0119] For example, if the historical benchmark performance data is the data from 5 seconds after the last adjustment, then the current real-time performance data is also the data from 5 seconds after the adjustment. During comparison, the aligned difference is calculated, for example, the current MB / s value minus the benchmark MB / s value; the resulting difference reflects the direction of performance change. The fluctuation range is obtained by calculating the standard deviation or range of the most recent (e.g., 3) real-time performance data, reflecting performance stability.

[0120] For example, the metric difference and fluctuation range together constitute a binary tuple of performance data. For instance, a metric difference of +12.5 MB / s (performance improvement) and a fluctuation range of 2.3% (stable) indicate that the current direction is upward optimization and the state is stable. Conversely, a metric difference of -8.5 IOPS (performance decline) and a fluctuation range of 4.1% (significant fluctuation) indicate that the current direction is reverse and the state is unstable. The performance data is passed as a whole to subsequent adjustment modules for their decision-making.

[0121] In this feasible implementation, the difference and fluctuation range are combined into unified performance data, which fully describes the deviation and stability of the link performance relative to the benchmark, providing comprehensive input information for optimization decisions, thereby improving storage performance.

[0122] S607. Adjust the link parameters of the bus link based on the performance data to obtain the adjustment parameters.

[0123] One feasible implementation method involves adjusting the link parameters of the bus link using the following approaches:

[0124] Based on the rise and fall of performance data, determine the parameter adaptation status and performance change rate of the bus link; based on the parameter adaptation status and performance change rate, adjust the link parameters of the bus link to obtain the adjustment parameters.

[0125] For example, the rise / fall status refers to the sign of the difference in performance metrics: a positive sign indicates an increase, and a negative sign indicates a decrease. Parameter fit status indicates the direction of deviation of the current link parameter from its optimal value. For example, if the difference remains positive, the parameter fit status is underfit (parameters are too small), and adjustments should continue in the positive direction; if the difference turns from positive to negative, the parameter fit status is overfit (parameters are too large), and adjustments should be made in the opposite direction. The performance change rate is reflected by the slope of the metric difference or the ratio of two consecutive differences. For example, if the difference was +5% in the previous adjustment and +3% in the current adjustment, the performance change rate shows a decelerating trend, indicating diminishing marginal returns, and the adjustment step size should be gradually reduced.

[0126] For example, the calculation of adjustment parameters is based on a combination of parameter fit status and performance change rate. If the parameter fit status is underfit and the performance change rate is accelerating, the current adjustment direction and step size are maintained; if the parameter fit status is underfit but the performance change rate is decelerating, the direction is maintained but the step size is decreased; if the parameter fit status is overfit, the adjustment is immediately reversed, and the step size is restored to the initial value. The final value of the adjustment parameter is calculated from the current link parameter value and the adjustment step size.

[0127] In this feasible implementation, by combining the rising and falling states and the performance change rate, dynamic control of the parameter adjustment direction and step size is achieved, avoiding overshoot or under-adjustment caused by fixed step size, enabling the link parameters to smoothly converge to the optimal value, improving the stability of the adjustment process, and thus improving storage performance.

[0128] One feasible implementation method involves iteratively adjusting the link parameters of the bus link using the following approach:

[0129] Based on the parameter adaptation status, determine the parameter adjustment direction; based on the performance change rate, determine the parameter adjustment step size; based on the parameter adjustment direction, perform step-by-step iterative adjustment of the link parameters according to the parameter adjustment step size to obtain the adjustment parameters.

[0130] For example, there are two directions for parameter adjustment: positive (increasing the link parameter value) and negative (decreasing the link parameter value). For instance, if the current link parameter is 256 bytes and the parameter adaptation status is underfitting, then the parameter adjustment direction is positive, adjusting towards 512 bytes; if the parameter adaptation status is overfitting, then the parameter adjustment direction is negative, adjusting towards 128 bytes.

[0131] Optionally, the parameter adjustment step size is set based on the performance change rate: when the performance change rate is greater than a preset threshold (e.g., 10%), a large step size adjustment of doubling / doubling the gear is used; when the performance change rate is less than the preset threshold, the adjustment span is reduced, and it is only tried between adjacent standard gears.

[0132] For example, step-by-step iterative adjustment refers to switching only one level at a time, and the link parameter values ​​are limited to the set of values ​​allowed by the high-speed peripheral interconnect bus protocol: {128, 256, 512, 1024, 2048, 4096} bytes. For instance, if the current link parameter is 128 bytes, the adjustment direction is positive, and the step size is a doubling increment, then the adjusted parameter is 256 bytes. In the next iteration, if the performance change rate still exceeds the threshold, the adjusted parameter is further increased to 512 bytes, until the 4096-byte upper limit is reached or performance data declines. If performance data begins to decline at 512 bytes, the adjustment is reversed to 256 bytes, completing the convergence judgment between adjacent levels.

[0133] To illustrate with a scenario example, on a bus subtree running a video service, the initial maximum payload size is 128 bytes. With iterative adjustments, performance data continuously improves, with positive performance differences at 256 bytes and 512 bytes, and a rate of change greater than 10%. When adjusted to 1024 bytes, the performance difference turns negative, and performance declines. At this point, the parameter adaptation status is determined to be overfitting, and the parameter adjustment direction is reversed to negative, reverting from 1024 bytes to 512 bytes. After multiple rounds of observation, it is confirmed that the performance change at 512 bytes is less than or equal to a preset performance threshold.

[0134] In this feasible implementation, the link parameters are finely tuned by adjusting and dynamically optimizing the direction and step size in a step-by-step iterative manner. While ensuring the convergence speed, the performance oscillation caused by large step size overshoot is avoided, ensuring the accuracy of the adjustment process and thus improving storage performance.

[0135] One feasible approach is to manage adjustments before implementation, including:

[0136] Trigger service flow control operations to temporarily suspend the data transmission and scheduling of new services; monitor the operation status of the bus link until the existing service data on the bus link is completely transmitted.

[0137] For example, before adjusting link parameters (such as maximum payload size), the system needs to ensure that there are no data packets being transmitted on the bus link to avoid errors in transport layer packet format or credit value calculation caused by inconsistencies between the new and original parameters. Service throttling and control operations are implemented through the flow control interface of the operating system's block device layer or driver layer, such as pausing the issuance of new input / output requests to NVMe hard drives.

[0138] Meanwhile, the system continuously monitors the queue of existing business data currently being processed, waiting for all data link layer packets (DLLPs) and transport layer packets (TLPs) of all issued input / output requests to be transmitted. Once the existing business data has been completely transmitted, the bus link is in an idle state, and adjusting the link parameters at this time will not cause data conflicts.

[0139] Optionally, the complete transmission of existing service data can be indicated by checking if the command completion queue ring in the driver layer is empty. If the last completed item in the completion queue has been processed by the system, it is determined that all existing service data has been transmitted.

[0140] In this feasible implementation, by triggering service rate limiting before parameter adjustment and waiting for existing data to complete, the security of the adjustment process is ensured, avoiding data corruption or link errors caused by asynchronous data transmission and parameter configuration, thus improving the reliability of the optimization process.

[0141] One feasible implementation method for optimizing the configuration is as follows:

[0142] When the performance change data is less than or equal to a preset performance threshold, determine the target link parameters of the bus link;

[0143] Store the target link parameters to local non-volatile storage media;

[0144] When the bus subtree is identified again, the target link parameters are retrieved for bus link configuration.

[0145] For example, the target link parameter is the currently configured link parameter value of the bus link when the performance change data is less than or equal to a preset performance threshold, such as a maximum effective payload size of 4096 bytes. The system writes this parameter value to a local non-volatile storage medium, such as the Baseboard Management Controller (BMC) or the electrically erasable programmable read-only memory (E2P) of the motherboard.

[0146] Optionally, during storage, the target link parameters are associated with and saved as topology characteristics of the bus subtree (such as root port number and device BDF number list) to form a mapping table. When the storage device is powered on and reset or a hot-plug event is triggered, the system rescans the topology, first checking the non-volatile storage medium for a matching mapping record. If the topology information matches, the target link parameters are directly read and configured to the bus link without re-executing the optimization process.

[0147] To illustrate with a scenario example, in a data center setting, an NVMe SSD is replaced due to a failure. After the new SSD is inserted and a hot-swap event is triggered, the system scans and finds that the bus subtree topology is completely identical to the previous one. It also reads from the non-volatile storage medium that the target maximum payload size corresponding to this subtree is 2048 bytes. The system immediately writes this value into the new SSD's configuration space, putting the bus link directly into an optimized state, significantly reducing the retuning time.

[0148] Below, in conjunction with Figure 7 The adaptive tuning is explained.

[0149] Figure 7 This is a schematic diagram illustrating adaptive tuning provided in an embodiment of this application. Figure 7 As shown, Part ① involves scanning the entire PCIe tree under the CPU through PCIe enumeration. During the scan, the PCIe subtree containing the NVMe hard drive is identified by the ClassCode field of the PCIe configuration space, and a maintenance table for each PCIe subtree is established. RP1 and RP2 are the target PCIe subtrees; other PCIe subtrees such as RP3 need to be filtered out, and the filtered PCIe topology set is fixed to the E2P of the motherboard where the CPU is located. Part ② involves periodically analyzing the customer's IO model and performing performance statistics when the customer is running business. Part ③ involves calculating the MPS based on the statistical results in Part ②, configuring it to the PCIe device, and then triggering the statistics in Part ② again. After repeating Parts ② and ③ several times until the performance is optimal, the IO analysis and MPS adjustment are stopped, and the current MPS value is fixed to the E2P of the motherboard where the CPU is located.

[0150] Below, in conjunction with Figure 8 The optimization of loop performance is explained.

[0151] Figure 8 This is a schematic diagram illustrating the loop performance optimization provided in an embodiment of this application. For example... Figure 8As shown, after the device powers on, a default value is configured for each PCIe RP during the BIOS phase. After the BIOS boots and completes the OS boot phase, the OS phase scans the PCIe topology again (for verification and resource allocation in complex scenarios). During this process, the discovered PCIe topology, such as the one shown, needs to be filtered by the PCIe device's ClassCode to determine the PCIe subtree where the NVMe-SSD resides (refer to Table 1). When a PCIe device is hot-plugged, the system receives an interrupt, triggering a new PCIe topology scan.

[0152] Table 1

[0153]

[0154] During the scan, information for each PCIe device is stored in a tree structure, as shown in Table 2. After the scan is complete, the motherboard E2P is first checked for any known, fixed, and optimized information. If so, the PCIe subtree information is compared (see Table 2). If they match perfectly, the MPS value is found in Table 3 and used directly without further optimization. If they do not match or the information in Tables 2 and 3 is missing from the E2P, the existing records in the E2P are deleted.

[0155] Table 2

[0156]

[0157] Table 3

[0158]

[0159] When the IO stream starts running, a timer is first started to count the data IO model within the time interval (see Table 4). After the time interval expires, the performance values ​​IOPS and bandwidth of each NVMe disk are counted (see Table 5).

[0160] Table 4

[0161]

[0162] Table 5

[0163]

[0164] Based on the typical IO selected from Table 2-3-4, customers generally have similar IO models when running on the same device. For example, running database services generally involves small IO (less than 128KB), while running video services generally involves large IO (greater than 128KB).

[0165] The sum of the current performance of all disks under the same RP is calculated and compared with the previous performance. If it is greater than the previous performance, optimization continues; if it is less than the previous performance, the current result is the optimal result. Record this in Table 3. The optimization method is to reset the MPS value of the PCIe link. For the first optimization, the MPS value starts from the minimum of 128 bytes, and is multiplied by 2 for each optimization, i.e.: 128->256->512->1024->2048->4096. If a fixed MPS value already exists, the MPS is adjusted in an increasing direction first. If the performance is lower, the decreasing direction is chosen, i.e., 4096->2048->1024->512->256->128. (The MPS value to be adjusted is <= the minimum MPS capability value of all PCIe devices under the same RP.) When reconfiguring the MPS, the IO module needs to be notified first. After this batch of IO is completed, time is reserved for MPS adjustment to prevent TLP message errors caused by inconsistencies between the new MPS and the previous one during IO transmission. After MPS adjustments are complete, the IO module is notified to resume IO delivery and the timer is reset. Because IO read / write performance itself fluctuates, a fluctuation range, such as 3%, can be added when comparing read / write performance values. As long as the current performance is within the fluctuation range of the previous one, tuning can be stopped, and the previous performance parameters should be used as the standard.

[0166] When customers change services online, the results of the previous optimization have been fixed, but may not be applicable. Further optimization can be performed based on the previous results.

[0167] In this feasible implementation, the optimization results are persistently stored and directly reused in subsequent events, thereby solidifying and accumulating optimization knowledge, reducing the time consumed by redundant tuning processes, and improving system response speed and performance, especially in scenarios with frequent hot-swapping or device replacement.

[0168] One feasible implementation method for optimizing link performance may also include:

[0169] Monitor power-on reset events and hot-plug events;

[0170] When a power-on reset event and / or hot-plug event is detected, the global bus hierarchy topology is scanned to obtain the updated bus subtree.

[0171] Determine the updated bus links corresponding to the updated bus subtree, and optimize the performance of the updated bus links.

[0172] For example, a power-on reset event is a reset signal triggered by the bus link being powered on again, and a hot-plug event is an interrupt signal generated when a storage device is connected or removed on the high-speed bus.

[0173] The system continuously monitors the two types of events mentioned above. Once either a power-on reset event or a hot-plug event is detected, a global bus-level topology scan process is initiated. The bus tree structure is retraced to identify the bus branches with the attached storage devices after the topology change, and an updated bus subtree is generated. The updated bus links are located through the bus topology hierarchy, and link performance optimization is performed on those links.

[0174] For example, if an NVMe SSD is added during server operation, triggering a PCIe hot-plug interrupt, the system starts a global bus topology scan, updates the bus subtree topology information, locates the bus link to which the newly added NVMe SSD belongs, and automatically performs adaptive performance tuning on this newly connected bus link.

[0175] In this feasible implementation, by monitoring the power-on reset event and hot-plug event of the bus link, the global bus-level topology is actively scanned and updated when the hardware topology changes. The bus subtree and corresponding bus links are updated synchronously, and performance optimization is re-executed, thereby improving storage performance.

[0176] One feasible implementation method for optimizing link performance may also include:

[0177] Monitor service data on the bus link;

[0178] When the change in business data is greater than or equal to a preset data threshold, the bus link performance is re-optimized.

[0179] For example, continuous collection and monitoring of service data during the operation of the bus link, including metrics such as IOPS and data throughput rate. Pre-configured data thresholds are used to determine the degree of service load fluctuation. The magnitude of service data changes is continuously statistically analyzed; when the magnitude of the change is greater than or equal to the preset data threshold, it is determined that the current service condition has changed significantly, and performance optimization of the bus link is then performed again.

[0180] For example, if a bus link has been running sequential read / write services for a long time and the business data is stable, but the upper layer service switches to a random read / write scenario, the IOPS index fluctuates significantly and the change exceeds the preset data threshold, the system will automatically restart the performance optimization process of the bus link to adapt to the new business conditions.

[0181] In this feasible implementation, business dynamics such as business load fluctuations and scenario switching are identified in real time, and the optimal parameters of the link are updated adaptively and iteratively according to the actual business conditions, so that the throughput and transmission bandwidth of the bus link always match the current real business needs and continuously ensure the storage performance of the storage device bus link.

[0182] As an example, if the firmware of a high-speed peripheral interconnect bus device supports configurable adjustment of the maximum payload size, the device's maximum payload capacity should be adjusted to the maximum allowed by the protocol (e.g., 4096 bytes) using a firmware configuration tool before the device is plugged into the system. For instance, the network interface card (NIC) firmware might default to supporting a maximum payload size of 512 bytes, but the actual hardware capability could reach 2048 bytes. By adjusting the capability to 2048 bytes using the NIC's firmware management tool before connecting it to the system, the system can attempt larger maximum payload sizes during optimization, expanding the tuning range and resulting in better transmission performance. In this example, through pre-configuration at the device firmware level, the selectable set of maximum payload sizes expands from [128, 256, 512] to [128, 256, 512, 1024, 2048], increasing the optimization space and potentially achieving higher single-transmission payload.

[0183] Figure 9 This is a schematic diagram of a link performance optimization device provided in an embodiment of this application. Figure 9 As shown, the performance optimization device 90 of the link may include: an acquisition module 91, a collection module 92, an adjustment module 93, and an optimization module 94.

[0184] The acquisition module 91 is used to determine the bus subtree in the global bus hierarchy topology architecture corresponding to the storage device, and to determine the corresponding bus link based on the bus subtree.

[0185] The acquisition module 92 is used to acquire service data from the bus link, determine the target scenario corresponding to the service data, and determine the performance evaluation dimensions of the bus link based on the target scenario.

[0186] The adjustment module 93 is used to determine performance data based on performance evaluation dimensions and business data, iteratively adjust the link parameters of the bus link based on the performance data, obtain the adjustment parameters, and acquire the performance change data after each adjustment.

[0187] The optimization module 94 is used to complete the performance optimization of the bus link until the performance change data is less than or equal to the preset performance threshold.

[0188] Optionally, module 91 can be executed. Figure 2 S201 in the embodiment.

[0189] Optionally, the acquisition module 92 can perform... Figure 2 S202 in the embodiment.

[0190] Optionally, adjustment module 93 can be executed. Figure 2 S203 in the embodiment.

[0191] Optionally, optimization module 94 can be executed. Figure 2 S204 in the embodiment.

[0192] In one possible implementation, the acquisition module 91 is specifically used for:

[0193] Read the device identifier of the storage device;

[0194] When the device identifier is not included in the local non-volatile storage medium, multiple bus topology nodes in the global bus hierarchy are traversed, and the identifier field of each bus topology node is determined from the configuration space of each bus topology node.

[0195] The identifier field of each bus topology node is matched with the device identifier to determine the valid topology node with the mounted storage device from multiple bus topology nodes;

[0196] Determine the bus subtree based on the valid topology nodes.

[0197] In one possible implementation, the acquisition module 91 is specifically used for:

[0198] From the global bus hierarchical topology architecture, determine the hierarchical relationships between valid topology nodes;

[0199] Based on the hierarchical relationship between superior and subordinate nodes, determine the topological branches of valid topological nodes;

[0200] Generate a bus subtree based on valid topology nodes and topology branches.

[0201] In one possible implementation, the acquisition module 92 is specifically used for:

[0202] Determine the data block size characteristic parameters of the business data;

[0203] Based on the data block size characteristic parameters and preset parameter values, the target scenario is determined to be either a large-capacity input / output scenario or a small-capacity input / output scenario.

[0204] When the target scenario is a high-capacity input / output scenario, the performance evaluation dimension is determined to be the data transmission throughput capacity;

[0205] When the target scenario is a small-capacity input / output scenario, the performance evaluation dimension is determined to be transmission bandwidth.

[0206] In one possible implementation, the adjustment module 93 is specifically used for:

[0207] Based on the performance evaluation dimensions, the business data is normalized and filtered to obtain the real-time performance index data of the bus link.

[0208] Obtain historical benchmark performance data for the bus link;

[0209] Real-time performance metrics data are time-series aligned and matched with historical benchmark performance metrics data, and the aligned performance metrics data are compared to obtain the metric difference and fluctuation range.

[0210] The difference in indicators and the fluctuation range are defined as performance data.

[0211] In one possible implementation, the adjustment module 93 is specifically used for:

[0212] Based on the rise and fall of performance data, determine the parameter adaptation status and performance change rate of the bus link.

[0213] Based on the parameter adaptation status and performance change rate, the link parameters of the bus link are adjusted to obtain the adjustment parameters.

[0214] In one possible implementation, the adjustment module 93 is specifically used for:

[0215] Determine the direction of parameter adjustment based on the parameter adaptation status;

[0216] Determine the parameter adjustment step size based on the rate of performance change;

[0217] Based on the parameter adjustment direction, the link parameters are iteratively adjusted in a step-by-step manner according to the parameter adjustment step size to obtain the adjustment parameters.

[0218] It should be noted that the link performance optimization device shown in the embodiments of this application can execute the technical solution shown in the above method embodiments, and its implementation principle and beneficial effects are similar, so they will not be described again here.

[0219] Figure 10 This is a schematic diagram of another link performance optimization device provided in an embodiment of this application. Figure 9 Based on the illustrated embodiments, as Figure 10 As shown, the performance optimization device 90 of the link also includes: a processing module 95, a storage module 96, a first update module 97, and a second update module 98.

[0220] Processing module 95 is used for:

[0221] Triggered business flow control operation, temporarily suspending the data transmission and scheduling of new business;

[0222] Monitor the operating status of the bus link until all existing service data on the bus link has been completely transmitted.

[0223] Storage module 96 is used for:

[0224] When the performance change data is less than or equal to a preset performance threshold, determine the target link parameters of the bus link;

[0225] Store the target link parameters to local non-volatile storage media;

[0226] When the bus subtree is identified again, the target link parameters are retrieved for bus link configuration.

[0227] The first update module 97 is used for:

[0228] Monitor power-on reset events and hot-plug events;

[0229] When a power-on reset event and / or hot-plug event is detected, the global bus hierarchy topology is scanned to obtain the updated bus subtree.

[0230] Determine the updated bus links corresponding to the updated bus subtree, and optimize the performance of the updated bus links.

[0231] The second update module 98 is used for:

[0232] Monitor service data on the bus link;

[0233] When the change in business data is greater than or equal to a preset data threshold, the bus link performance is re-optimized.

[0234] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0235] For a description of the features in the embodiment corresponding to the link performance optimization device, please refer to the relevant description in the embodiment corresponding to the link performance optimization method, which will not be repeated here.

[0236] Figure 11 A schematic diagram of the structure of the electronic device provided in this application. Figure 11 As shown, the electronic device 110 provided in this embodiment includes at least one processor 1101 and a memory 1102. Optionally, the electronic device 110 further includes a communication component 1103. The processor 1101, memory 1102, and communication component 1103 are connected via a bus.

[0237] In a specific implementation, at least one processor 1101 executes computer execution instructions stored in memory 1102, causing at least one processor 1101 to execute the above-described link performance optimization method embodiment.

[0238] The specific implementation process of processor 1101 can be found in the above method embodiments, and its implementation principle and technical effect are similar. It will not be repeated here.

[0239] In the above embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the application can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software modules within the processor.

[0240] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.

[0241] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0242] Embodiments of this application also provide a non-volatile computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described link performance optimization method embodiments at runtime.

[0243] In one exemplary embodiment, the aforementioned non-volatile computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0244] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described link performance optimization method embodiments.

[0245] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described link performance optimization method embodiments.

[0246] Any of the components, modules, units, parts, methods, and operations described herein can be implemented using software, firmware, hardware (e.g., fixed logic circuitry), manual processing, or any combination thereof. Alternatively or additionally, any functionality described herein can be performed at least in part by one or more hardware logic components, such as, but not limited to, a central processing unit (CPU), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), an application-specific standard product (ASSP), a system-on-a-chip (SoC), a complex programmable logic device (CPLD), a microprocessor (MCU), etc. The terms "system," "computing device," or "apparatus" as used herein encompass various means, devices, and machines for processing data, including, for example, one or more programmable processors, computers, SoCs, or combinations thereof. The apparatus may also include code that creates an execution environment for the computer program in question, such as code constituting processor firmware, a protocol stack, a database management system, an operating system, a cross-platform runtime environment, a virtual machine, or a combination thereof. The aforementioned computer program (also known as a program, software, software application, app, script, or code) can be written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages, and can be deployed in any form, including as a standalone program or as a module, component, subroutine, object, or other unit suitable for a computing environment.

[0247] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0248] The above provides a detailed description of a link performance optimization method and electronic device provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only intended to help understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of this application.

Claims

1. A method for optimizing the performance of a link, characterized in that, include: Determine the bus subtree in the global bus hierarchy topology architecture corresponding to the storage device, and determine the corresponding bus link based on the bus subtree; Collect service data from the bus link, determine the target scenario corresponding to the service data, and determine the performance evaluation dimensions of the bus link based on the target scenario; Based on the performance evaluation dimensions and the business data, performance data is determined, and the link parameters of the bus link are iteratively adjusted according to the performance data to obtain the adjustment parameters, and the performance change data after each adjustment is obtained. The performance optimization of the bus link is completed when the performance change data is less than or equal to a preset performance threshold. The iterative adjustment of the bus link parameters based on the performance data to obtain the adjustment parameters includes: Based on the rise and fall of the performance data, determine the parameter adaptation status and performance change rate of the bus link; Based on the parameter adaptation state, the parameter adjustment direction is determined. If the parameter adaptation state is under-adjusted, the parameter adjustment direction is positive; if the parameter adaptation state is over-adjusted, the parameter adjustment direction is negative. Based on the performance change rate, determine the parameter adjustment step size, wherein if the performance change rate is decelerating, decrease the parameter adjustment step size; if the performance change rate is accelerating, maintain the parameter adjustment step size. Adjusting the direction according to the parameters, and iteratively adjusting the link parameters step by step according to the parameter adjustment step size, to obtain the adjustment parameters.

2. The link performance optimization method according to claim 1, characterized in that, Determine the bus subtree in the global bus hierarchy topology corresponding to the storage device, including: Read the device identifier of the storage device; When the device identifier is not included in the local non-volatile storage medium, the multiple bus topology nodes of the global bus hierarchy are traversed, and the identifier field of each bus topology node is determined from the configuration space of each bus topology node. The identifier field of each bus topology node is matched with the device identifier to determine the valid topology node that mounts the storage device from multiple bus topology nodes; The bus subtree is determined based on the valid topology nodes.

3. The link performance optimization method according to claim 2, characterized in that, Determining the bus subtree based on the valid topology nodes includes: From the global bus hierarchical topology, determine the hierarchical relationship between the effective topology nodes; Based on the hierarchical relationship, determine the topological branch of the effective topological node; The bus subtree is generated based on the valid topology nodes and the topology branches.

4. The link performance optimization method according to claim 1, characterized in that, Based on the target scenario corresponding to the business data, determine the performance evaluation dimensions of the bus link, including: Determine the data block size characteristic parameters of the business data; Based on the data block size characteristic parameter and the preset parameter value, the target scenario is determined to be a large-capacity input / output scenario or a small-capacity input / output scenario; When the target scenario is a high-capacity input / output scenario, the performance evaluation dimension is determined to be data transmission throughput. When the target scenario is a small-capacity input / output scenario, the performance evaluation dimension is determined to be transmission bandwidth.

5. The link performance optimization method according to claim 1, characterized in that, Based on the performance evaluation dimensions and the business data, performance data is determined, including: The performance data is obtained by normalizing and filtering the business data according to the performance evaluation dimensions. Obtain performance change data after each adjustment, including: After each adjustment, acquire the historical performance data of the bus link; The adjusted performance data is time-series aligned and matched with the historical performance data, and the aligned data is compared to obtain the index difference and fluctuation range. The difference in the indicators and the fluctuation range are determined as the performance change data.

6. The link performance optimization method according to claim 1, characterized in that, Before adjusting the link parameters of the bus link, the method further includes: Triggered business flow control operation, temporarily suspending the data transmission and scheduling of new business; Monitor the operating status of the bus link until the existing service data of the bus link has been completely transmitted.

7. The link performance optimization method according to any one of claims 1-6, characterized in that, The method further includes: When the performance change data is less than or equal to a preset performance threshold, the target link parameters of the bus link are determined; The target link parameters are stored in a local non-volatile storage medium; In response to the re-identification of the bus subtree, the target link parameters are retrieved for bus link configuration.

8. The link performance optimization method according to any one of claims 1-6, characterized in that, The method further includes: Monitor power-on reset events and hot-plug events; When the power-on reset event and / or the hot-plug event are detected, the global bus hierarchy topology is scanned to obtain the updated bus subtree. Determine the updated bus links corresponding to the updated bus subtree, and optimize the performance of the updated bus links.

9. The link performance optimization method according to any one of claims 1-6, characterized in that, The method further includes: Monitor the service data of the bus link; When the change in the business data is greater than or equal to a preset data threshold, the bus link is re-optimized for performance.

10. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the link performance optimization method as described in any one of claims 1 to 9.

11. A non-volatile computer-readable storage medium, characterized in that, The non-volatile computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the link performance optimization method as described in any one of claims 1 to 9.

12. A computer program product, characterized in that, Includes a computer program, which, when executed by a processor, implements the steps of the link performance optimization method as described in any one of claims 1 to 9.

Images