A page table prefetch method, device, storage medium and electronic equipment

Abstract

The application discloses a page table prefetching method and device, a storage medium and an electronic device, relates to the chip technical field, and comprises the following steps: obtaining a virtual address stream; filtering out target addresses with continuous addresses from the virtual address stream, and dividing the target addresses into a continuous memory access block; determining address jump information between a plurality of continuous memory access blocks, analyzing whether the address jump information has periodicity, and predicting whether there is a next continuous memory access block after the current continuous memory access block; determining target prefetching information of the virtual address stream according to the periodicity analysis result, and performing page table prefetching according to the target prefetching information. The application determines periodicity and predicts the next continuous memory access block through the address jump information of the multiple continuous memory access blocks, generates target prefetching information, and performs page table prefetching, thereby improving the matching degree between the page table prefetching and the real memory access progress, reducing the bus bandwidth and TLB resource occupation caused by invalid page table prefetching, and reducing the memory access delay.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a page table prefetching method, apparatus, storage medium, and electronic device. Background Technology

[0002] During data access, there will be a speed difference between the chip's memory access speed and the computing unit's operation speed. This speed difference can be reduced by using page table prefetching to obtain the address mapping page table required for memory access in advance.

[0003] Currently, existing page table prefetching methods, when a memory access address cache miss is detected, prefetch page table entries of a fixed length in a fixed order and store the address mapping relationship corresponding to the page table entries into a translation lookaside buffer (TLB).

[0004] However, using this method can lead to insufficient prefetching, excessive prefetching, or invalid prefetching, resulting in a mismatch between the prefetched pages and the actual memory access progress, consuming bus bandwidth and TLB resources, and consequently failing to meet subsequent memory access needs, causing memory access delays. Summary of the Invention

[0005] In view of this, this application provides a page table prefetching method, apparatus, storage medium, and electronic device. The main purpose is to improve the technical problem in the prior art where insufficient prefetching, excessive prefetching, or invalid prefetching occurs, resulting in a mismatch between the prefetched pages and the actual memory access progress, occupying bus bandwidth and TLB resources, and thus failing to meet subsequent memory access needs and causing memory access delays.

[0006] Firstly, this application provides a page table prefetching method, including: Obtain a virtual address stream, which is generated according to the memory access target data according to the memory access requirements; Based on the address information of adjacent addresses in the virtual address stream, target addresses with continuous addresses are filtered out from the virtual address stream, and the target addresses are divided into a continuous memory access block. The target addresses are a set of valid virtual addresses in the virtual address stream that are continuous, have a constant step size, and meet the condition of address continuity. The continuous memory access block is a set of addresses in the virtual address stream with a constant difference between adjacent addresses. Determine the address transition information between multiple consecutive memory access blocks, and analyze whether the address transition information is periodic in order to predict whether there will be a next consecutive memory access block after the current consecutive memory access block; Based on the periodic analysis results, the target prefetch information of the virtual address stream is determined, and page table prefetching is performed according to the target prefetch information. The page table prefetching is used to access the target data.

[0007] Optionally, determining the address transition information between multiple consecutive memory access blocks and analyzing whether the address transition information is periodic to predict whether there is a next consecutive memory access block after the current consecutive memory access block includes: Based on the address information corresponding to the multiple consecutive memory access blocks, the first address difference information between the multiple consecutive memory access blocks is determined. The first address difference information is determined as the address jump information of multiple consecutive memory access blocks where address jumps occur; If the address transition information satisfies the periodicity condition, the address transition information is determined to be periodic, and it is determined that there is a next consecutive memory access block after the current consecutive memory access block. If the address transition information does not meet the periodicity condition, the address transition information is determined to be non-periodic, and it is determined that there is no next consecutive memory access block after the current consecutive memory access block.

[0008] Optionally, determining the target prefetch information of the virtual address stream based on the periodic analysis results, and performing page table prefetching according to the target prefetch information, includes: When the address transition information meets the periodic condition, the remaining page table prefetch information corresponding to the remaining address of the current consecutive memory access block and the page table prefetch information corresponding to the next consecutive memory access block are determined as the first target prefetch information, and page table prefetching is performed according to the first target prefetch information; The remaining page table prefetch information corresponding to the remaining address of the current consecutive memory access block is determined as the second target prefetch information, and a second prefetch instruction for the second target prefetch information is generated. Page table prefetching is performed according to the second prefetch instruction.

[0009] Optionally, when the address transition information satisfies the periodicity condition, determining the remaining page table prefetch information corresponding to the remaining address of the current consecutive memory access block and the page table prefetch information corresponding to the next consecutive memory access block as the first target prefetch information, and performing page table prefetching according to the first target prefetch information, includes: Based on the first address difference information, invalid address intervals between multiple consecutive memory access blocks are determined, and the prefetch information corresponding to the invalid address intervals is determined as invalid prefetch information. In the page table prefetch information corresponding to the next consecutive memory access block, the prefetch information other than the invalid prefetch information is determined as the next page table prefetch information; The remaining page table prefetch information corresponding to the remaining address of the current consecutive memory access block and the next page table prefetch information corresponding to the next consecutive memory access block are determined as the first target prefetch information; A first prefetch instruction is generated to prefetch the first target information, and page table prefetching is performed according to the first prefetch instruction.

[0010] Optionally, the step of filtering out consecutive target addresses from the virtual address stream based on the address information of adjacent addresses in the virtual address stream, and dividing the target addresses into a contiguous memory access block, includes: Based on the address information of adjacent addresses in the virtual address stream, determine the second address difference information of the adjacent addresses; The second address difference information is compared with the reference difference information to obtain the difference comparison result between the second address difference information and the reference difference information; If the difference comparison result satisfies the address continuation condition, the adjacent address is determined as the target address with address continuation, and the target address is divided into a continuum access block.

[0011] Optionally, the method further includes: Obtain the number of consecutive memory access blocks in the virtual address stream; When the quantity information is a contiguous memory block, the remaining page table prefetch information corresponding to the remaining address of the current contiguous memory block and the predicted page table prefetch information corresponding to the subsequent virtual addresses of the target quantity are determined as the third target prefetch information, and page table prefetching is performed according to the third target prefetch information.

[0012] Secondly, this application provides a page table prefetching device, comprising: The acquisition module is configured to acquire a virtual address stream, which is generated according to the memory access target data according to the memory access requirements. The filtering module is configured to filter out target addresses that are consecutive in the virtual address stream based on the address information of adjacent addresses in the virtual address stream, and divide the target addresses into a contiguous memory access block. The target addresses are a set of valid virtual addresses in the virtual address stream that are consecutive, have a constant step size, and meet the condition of address contiguousness. The contiguous memory access block is a set of addresses in the virtual address stream with a constant difference between adjacent addresses. The determination module is configured to determine address transition information between multiple consecutive memory access blocks, analyze whether the address transition information is periodic, and predict whether there is a next consecutive memory access block after the current consecutive memory access block. The prefetch module is configured to determine the target prefetch information of the virtual address stream based on the periodic analysis results, and perform page table prefetching according to the target prefetch information, wherein the page table prefetching is used to access the target data.

[0013] Thirdly, this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the page table prefetching method described in the first aspect.

[0014] Fourthly, this application provides an electronic device, including a storage medium, a processor, and a computer program stored on the storage medium and executable on the processor, wherein the processor executes the computer program to implement the page table prefetching method described in the first aspect.

[0015] By means of the above technical solution, this application provides a page table prefetching method, apparatus, storage medium, and electronic device, comprising: acquiring a virtual address stream; filtering out consecutive target addresses from the virtual address stream based on address information of adjacent addresses in the virtual address stream, and dividing the target addresses into a contiguous memory access block; determining address transition information between multiple contiguous memory access blocks, analyzing whether the address transition information is periodic, so as to predict whether there is a next contiguous memory access block after the current contiguous memory access block; determining the target prefetching information of the virtual address stream according to the periodic analysis result, and performing page table prefetching according to the target prefetching information. Compared with existing technologies, this application divides contiguous memory access blocks based on adjacent address information of virtual address streams, which can extract effective memory access intervals with stable step sizes; it determines periodicity and predicts the next contiguous memory access block by using address jump information of multiple contiguous memory access blocks, thereby identifying gaps between blocks and periodic memory access patterns; it generates corresponding target prefetch information based on periodic analysis results and performs page table prefetching, improving the matching degree between page table prefetching and actual memory access progress, reducing bus bandwidth and TLB resource occupation caused by invalid page table prefetching, and reducing memory access latency. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A schematic flowchart of a page table prefetching method provided in an embodiment of this application is shown; Figure 2 A schematic flowchart of a page table prefetching method provided in an embodiment of this application is shown; Figure 3 This illustration shows a schematic diagram of a page table prefetching device according to an embodiment of this application; Figure 4 A schematic diagram of the structure of an electronic device provided in an embodiment of this application is shown. Detailed Implementation

[0019] The embodiments of this application will now be described in more detail with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0020] To address the technical problem in existing technologies where insufficient, excessive, or invalid prefetching occurs, leading to a mismatch between prefetched pages and actual memory access progress, consuming bus bandwidth and TLB resources, and ultimately failing to meet subsequent memory access demands and causing memory access latency, this embodiment provides a page table prefetching method, such as... Figure 1 As shown, the method includes: Step 101: Obtain the virtual address stream.

[0021] The virtual address stream is generated according to the memory access requirements for the target data.

[0022] In this embodiment, the virtual address stream can be a continuous sequence of virtual addresses captured in real time and sorted according to the access time sequence by the address acquisition module of the Memory Management Unit (MMU) after the Neural Processing Unit (NPU) initiates a memory access request. The virtual address stream can serve as the original input data source for the memory access feature extraction module. For example, the virtual address stream in this embodiment may specifically include access addresses corresponding to the Number-Channels-Height-Width (NCHW) image tensor, two-dimensional operation matrix, model static weights, and one-dimensional sequences of text inference, as well as the address sequence output by the Direct Memory Access (DMA) module after slicing, edge patching, mirroring, dimensional transformation, and downsampling deformation.

[0023] In this embodiment, the target data can be tensor data that needs to be read or written during NPU neural network inference and training operations. The target data can include effective data required for chip operations such as image feature tensors, operation matrix data, model weight parameters, and sequence inference data. The target data can be stored in the chip's external memory or on-chip cache.

[0024] In the embodiments of this application, memory access requirements can be memory read / write requests, and memory access requirements can include, but are not limited to, information such as the virtual address identifier corresponding to the target data to be accessed, the data read / write length, and the data type.

[0025] In the embodiments of this application, this step can be performed by the address acquisition module built into the MMU in the chip. The address acquisition module can continuously monitor all memory access requests issued by the NPU, capture each virtual address to be accessed one by one, splice them in the order of requests to generate a complete virtual address stream, and transmit it to the downstream memory access feature extraction hardware circuit in real time. The existing NPU directly ported the traditional prefetching scheme of the central processing unit (CPU) does not collect all virtual addresses for feature statistics. It only triggers a fixed-length prefetch when the TLB is missing, and cannot perceive the tensor distribution pattern. The complete collection of address sequence in the embodiments of this application can provide a data foundation for subsequent adaptive prefetching.

[0026] Step 102: Based on the address information of adjacent addresses in the virtual address stream, filter out the target addresses that are consecutive in the virtual address stream and divide the target addresses into a consecutive memory access block.

[0027] The target address is a set of valid virtual addresses in the virtual address stream that are continuous, have a constant step size, and satisfy the address continuity condition. The contiguous memory access block is a set of addresses in the virtual address stream with a constant difference between adjacent addresses.

[0028] In this embodiment of the application, the address information of adjacent addresses can be the virtual address values ​​of two consecutive clock cycles in terms of timing. The address information can be used to calculate the address interval difference, which can be the basis for judging whether the address access is continuous.

[0029] In this embodiment, a contiguous memory access block can be a set of addresses within a virtual address stream where the difference between adjacent addresses is constant. A contiguous memory access block can correspond to a valid tensor data region in memory without padding or slice gaps. For example, in this embodiment, a contiguous memory access block can specifically be a single-channel convolution block, a complete weight matrix slice, or a long sequence of continuous feature segments. Multiple contiguous memory access blocks may have blank memory intervals with no valid data between them.

[0030] In this embodiment, the target address can be a set of valid virtual addresses in the virtual address stream that are continuous, have a constant step size, and satisfy the condition of address continuity. The target address can correspond to the valid address range in the chip memory that actually stores tensor data.

[0031] In the embodiments of this application, this step can be implemented by the lightweight hardware circuit built into the MMU in the chip. Only registers, subtractors, comparators, and linear accumulator counters need to be deployed. There is no need for floating-point arithmetic units and large-capacity on-chip static random access memory (SRAM). It has almost no negative impact on chip area and timing convergence. The lightweight hardware circuit can compare the differences of adjacent timing addresses one by one, and uniformly select the continuous addresses with constant differences as target addresses. Whenever the address difference changes abruptly, the current block statistics are terminated, the length attribute of the current continuous block is recorded, the base address difference is updated synchronously, and the counter is reset.

[0032] Step 103: Determine the address transition information between multiple consecutive memory access blocks, and analyze whether the address transition information is periodic in order to predict whether there will be a next consecutive memory access block after the current consecutive memory access block.

[0033] In this embodiment, the address jump information can be the address offset difference generated when two adjacent consecutive memory access blocks are interrupted, and the address jump information can characterize the total span of the blank memory interval between blocks.

[0034] In this embodiment, periodicity can refer to multiple sets of consecutively recorded address jump offset values ​​being completely identical, or exhibiting a fixed alternating memory access pattern. Periodicity can be used to predict whether there will be another valid tensor data after the current data block. For example, in this embodiment, memory access scenarios with periodicity can specifically be fixed-size image block convolution or equidistant matrix slice operations; memory access scenarios without periodicity can be random sparse matrix or random inference sequence access.

[0035] In the embodiments of this application, a transition history register group can be deployed internally in the lightweight hardware circuit to store the transition offset value generated by each block interrupt; whenever the continuous block partitioning process triggers the counter clearing operation, the lightweight hardware circuit can automatically record the transition difference and store it in the register; the lightweight hardware circuit can traverse multiple sets of historical transition values ​​in the register and compare the repetition pattern of the values ​​to complete the periodic determination; if a periodicity is determined, it is predicted that there is a next valid data block after the current continuous memory access block; if the transition values ​​are chaotic and irregular, it is determined that there is no subsequent valid block.

[0036] Step 104: Based on the periodic analysis results, determine the target prefetch information for the virtual address stream, and perform page table prefetching according to the target prefetch information.

[0037] Page table prefetching is used to access target data in memory.

[0038] In this embodiment, page table prefetching can be used to preload the page table entries (PTEs) that map virtual addresses to physical addresses into the TLB translation lookup buffer. Page table prefetching can reduce the speed difference between chip memory access speed and computing unit operation speed, and reduce long-latency memory lookup operations caused by TLB missing.

[0039] In this embodiment, the target prefetch information can be the range of valid page table addresses to be preloaded and the upper limit of the total number of prefetched pages. The upper limit of the number of prefetched pages can be dynamically configured through the MMU's built-in registers to adapt to various memory page granularities such as 4KB and 8KB.

[0040] Optionally, existing technologies use a fixed number of prefetched pages without considering the length of consecutive blocks and the characteristics of gaps between blocks. This easily leads to three types of defects: insufficient prefetching, excessive prefetching, and invalid prefetching with gaps. This wastes bus bandwidth between the L2 cache and memory, and a large number of invalid PTEs are injected into the TLB, causing cache pollution and reducing the cache hit rate of real business operations. The page table prefetching method of this application can be integrated into the MMU memory management unit of various NPUs and AI chips, and can be applied to hardware products such as neural network training chips, edge computing AI chips, and data center AI acceleration cards. The page table prefetching method of this application can handle various tensors such as convolutional feature maps, matrix partitioning, one-dimensional sequences, and static weights. It is compatible with DMA data transformation operations such as slice slicing, padding, mirroring, reshape dimensional rearrangement, and subsample downsampling, and adapts to various memory page granularities. This application performs page table prefetching based on target prefetch information, which can reduce invalid prefetch requests from the root, reduce bus occupation and TLB cache pollution, and improve the overall address translation efficiency of the System Memory Management Unit (SMMU).

[0041] Compared with existing technologies, this application divides contiguous memory access blocks based on adjacent address information of virtual address streams, which can extract effective memory access intervals with stable step sizes; it determines periodicity and predicts the next contiguous memory access block by using address jump information of multiple contiguous memory access blocks, thereby identifying gaps between blocks and periodic memory access patterns; it generates corresponding target prefetch information based on periodic analysis results and performs page table prefetching, improving the matching degree between page table prefetching and actual memory access progress, reducing bus bandwidth and TLB resource occupation caused by invalid page table prefetching, and reducing memory access latency.

[0042] As an optional approach, when performing the task of "determining address transition information between multiple consecutive memory access blocks, analyzing whether the address transition information is periodic to predict whether there will be another consecutive memory access block after the current consecutive memory access block", the following methods can be used, but are not limited to them, such as... Figure 2 As shown, it includes: Step 201: Based on the address information corresponding to the multiple consecutive memory access blocks, determine the first address difference information between the multiple consecutive memory access blocks.

[0043] In this embodiment of the application, the first address difference information can be the address interval length between two consecutive memory access blocks, and the first address difference information can directly correspond to the size of the blank memory interval formed by Padding and Slice.

[0044] In the embodiments of this application, whenever the continuous block statistics trigger counter is cleared, the lightweight hardware circuit can calculate the address offset corresponding to the current mutation, store the offset as the first address difference information in the jump history register group, and complete the acquisition of the jump raw data.

[0045] Step 202: Determine the first address difference information as the address jump information of multiple consecutive memory access blocks where address jumps have occurred.

[0046] In the embodiments of this application, the address transition information can be a set of multiple sets of first address differences.

[0047] Step 203: If the address transition information meets the periodicity condition, determine that the address transition information is periodic and determine that there is a next consecutive memory access block after the current consecutive memory access block.

[0048] In the embodiments of this application, the periodic condition can be that the first address difference of multiple consecutive memory access blocks is exactly the same, or that they alternate according to a fixed value.

[0049] In the embodiments of this application, all historical first address differences are traversed, and address transition information that meets the periodic conditions is determined to be periodic, and it is predicted that there will be a next valid continuous memory access block after the current continuous memory access block.

[0050] Step 204: If the address transition information does not meet the periodicity condition, determine that the address transition information is non-periodic and determine that there is no next consecutive memory access block after the current consecutive memory access block.

[0051] In the embodiments of this application, if multiple sets of first address differences do not have a fixed repetition pattern, it is determined that there is no periodicity, and it is determined that there is no next consecutive memory access block after the current consecutive memory access block.

[0052] As an optional approach, when executing "determining the target prefetch information of the virtual address stream based on the periodic analysis results and performing page table prefetching according to the target prefetch information", the following method can be used, but is not limited to: when the address transition information meets the periodic condition, the remaining page table prefetch information corresponding to the remaining address of the current consecutive memory access block and the page table prefetch information corresponding to the next consecutive memory access block are determined as the first target prefetch information, and page table prefetching is performed according to the first target prefetch information; the remaining page table prefetch information corresponding to the remaining address of the current consecutive memory access block is determined as the second target prefetch information, and a second prefetch instruction for the second target prefetch information is generated, and page table prefetching is performed according to the second prefetch instruction.

[0053] In this embodiment of the application, the first target prefetch information can be all valid prefetched content in a periodic memory access scenario. The first target prefetch information can include two parts: the remaining page table of the current contiguous block and the valid page table of the next contiguous block.

[0054] In this embodiment, the second target prefetch information can be prefetch content in a non-periodic memory access scenario, containing only the remaining page table of the current contiguous block, and will not generate prefetch requests for the next block or the gap between blocks.

[0055] In the embodiments of this application, in the periodic memory access scenario, the first target prefetch information can be selected to generate the hardware prefetch instruction, while in the non-periodic memory access scenario, only the second prefetch instruction is generated. The number of pages prefetched in both the periodic and non-periodic memory access scenarios is dynamically calculated based on the average length of historical consecutive blocks and the number of pages accessed in the current block. The prefetch upper limit is constrained by the register configuration threshold and will not exceed the effective data address range, which can solve the problems of insufficient prefetching and excessive prefetching caused by fixed prefetching.

[0056] As an optional approach, when executing the instruction "when address transition information meets periodic conditions, determine the remaining page table prefetch information corresponding to the remaining address of the current consecutive memory access block and the page table prefetch information corresponding to the next consecutive memory access block as the first target prefetch information, and perform page table prefetching according to the first target prefetch information", the following method can be used, but is not limited to: the method includes: determining invalid address intervals between multiple consecutive memory access blocks based on the first address difference information, and determining the prefetch information corresponding to the invalid address intervals as invalid prefetch information; in the page table prefetch information corresponding to the next consecutive memory access block, determining the prefetch information other than the invalid prefetch information as the next page table prefetch information; determining the remaining page table prefetch information corresponding to the remaining address of the current consecutive memory access block and the next page table prefetch information corresponding to the next consecutive memory access block as the first target prefetch information; generating a first prefetch instruction for the first target prefetch information, and performing page table prefetching according to the first prefetch instruction.

[0057] In this embodiment, the invalid address range can be the Padding or Slice blank memory segment corresponding to the first address difference, and the invalid prefetch information can be the PTE page table prefetch request corresponding to the blank range. For example, in this embodiment, invalid prefetch requests will continuously occupy the transmission bandwidth between the on-chip L2 cache and external memory, while also crowding out TLB storage space. A large number of useless address records will cover valid mapping entries, causing frequent TLB misses, lengthening address translation latency, and increasing the overall power consumption of the chip. This application reduces invalid prefetch requests by shielding the prefetching of invalid address ranges between blocks, which is different from the prefetching of general-purpose CPUs and graphics processing units (GPUs).

[0058] In this embodiment of the application, the entire range of blank addresses between blocks can be locked based on the first address difference. Invalid prefetch information corresponding to the blank intervals is removed, and only the page table prefetch content of two consecutive valid data blocks is retained to form the first target prefetch information. The first prefetch instruction is generated and sent to the translation queue to execute the page table prefetch, which can skip invalid pages between blocks and avoid gap prefetching.

[0059] As an optional approach, when performing the task of "selecting contiguous target addresses from the virtual address stream based on the address information of adjacent addresses in the virtual address stream and dividing the target addresses into a contiguous memory access block", the following method can be used, but is not limited to: determining the second address difference information of adjacent addresses based on the address information of adjacent addresses in the virtual address stream; comparing the second address difference information with the base difference information to obtain the difference comparison result between the second address difference information and the base difference information; and, if the difference comparison result satisfies the address contiguous condition, determining the adjacent addresses as contiguous target addresses and dividing the target addresses into a contiguous memory access block.

[0060] In this embodiment, the second address difference information can be the absolute value of the difference between the current virtual address and the previous virtual address, and the second address difference information can characterize the address movement span of a single memory access. For example, in this embodiment, the second address difference can be the absolute value of the difference between the virtual address captured at the current moment and the virtual address cached in the previous time frame.

[0061] In this embodiment, the baseline difference information can be a standard address step size threshold obtained from lightweight hardware circuit initialization configuration or dynamic learning. The baseline difference information can be used to determine whether adjacent virtual addresses are in a continuous memory access interval. The baseline difference information can be dynamically and adaptively updated according to different tensor memory access types, memory page granularity, and DMA morphing operation types of the NPU to adapt to multiple memory access scenarios.

[0062] In this embodiment of the application, the address continuity condition can be that the second address difference information calculated in real time completely matches the baseline difference information. The address continuity condition can be used as the core criterion for determining that adjacent virtual addresses belong to the same valid memory access interval. Adjacent addresses that meet the address continuity condition can be classified as consecutive valid memory access addresses.

[0063] In the embodiments of this application, the lightweight hardware circuit can be internally configured with a reference difference register and a linear accumulator counter. After each address difference calculation, the second address difference is compared with the reference difference stored in the register. If they are equal, the address continuity condition is met, and the counter increments. If the values ​​are not equal, the address is determined to have changed abruptly. The current accumulated value of the counter is stored as the length of the continuous memory access block in the continuous block length history register group, and the reference difference register is updated and the counter is reset synchronously. The above operation process relies only on basic addition, subtraction, and comparison circuits, which can reduce overhead and save computing resources.

[0064] As an alternative approach, but not limited to the following method, the method includes: obtaining the number of consecutive memory access blocks in the virtual address stream; when the number information is one consecutive memory access block, determining the remaining page table prefetch information corresponding to the remaining address of the current consecutive memory access block and the predicted page table prefetch information corresponding to the subsequent virtual addresses of the target number as the third target prefetch information, and performing page table prefetching according to the third target prefetch information.

[0065] In this embodiment, the number of consecutive memory access blocks can be the total number of valid consecutive memory access blocks, and the number information can be used to determine the memory access condition without historical jump records during initialization.

[0066] In this embodiment, the third target prefetch information can be the tentative prefetch content when only a single contiguous block exists. The target quantity can be configured as a small number of page tables, such as 1 to 2 pages, to detect the subsequent memory access step size pattern.

[0067] Optionally, if the virtual address stream cannot be divided into any stable contiguous memory access blocks and the address stride remains disordered, a conservative prefetch strategy is switched to prefetch only single-page table entries or prefetching is turned off directly to avoid cache pollution.

[0068] In the embodiments of this application, the continuous memory access block extraction, cycle determination, and prefetch generation are integrated into the MMU module in the chip, which is different from the external prefetch architecture of the cache controller. It can complete the pattern recognition at the address translation front end, and the prediction is more timely and the memory access latency is lower.

[0069] Compared with existing technologies, this application embodiment uses the first address difference between multiple consecutive memory access blocks as address transition information and determines the memory access pattern based on periodic conditions to achieve lightweight hardware identification of gaps between blocks without the need for complex computing units; by distinguishing between periodic scenarios to generate target prefetch information and issuing corresponding prefetch instructions, it achieves dynamic adjustment of the number of prefetched pages, avoiding insufficient or excessive prefetching; by locking invalid address intervals between blocks based on the first address difference, removing invalid prefetch information, and synthesizing the first target prefetch information, it actively shields invalid page table prefetching corresponding to Padding and Slice gaps, reducing TLB cache pollution; by calculating the second address difference between adjacent addresses and comparing it with the benchmark difference to divide consecutive memory access blocks, it achieves memory access feature extraction by relying only on addition and subtraction comparison circuits, reducing overhead and computing resources.

[0070] Furthermore, as Figure 1 and Figure 2 To specifically implement the method shown, this embodiment provides a page table prefetching device, such as... Figure 3 As shown, the device includes: an acquisition module 31, a filtering module 32, a determination module 33, and a pre-fetching module 34.

[0071] The acquisition module 31 is configured to acquire a virtual address stream, which is generated according to the memory access requirements of the target data. The filtering module 32 is configured to filter out target addresses that are consecutive in the virtual address stream based on the address information of adjacent addresses in the virtual address stream, and divide the target addresses into a contiguous memory access block. The target addresses are a set of valid virtual addresses in the virtual address stream that are consecutive, have a constant step size, and meet the condition of address contiguousness. The contiguous memory access block is a set of addresses in the virtual address stream with a constant difference between adjacent addresses. The determination module 33 is configured to determine the address transition information between multiple consecutive memory access blocks, analyze whether the address transition information is periodic, and predict whether there is a next consecutive memory access block after the current consecutive memory access block. The prefetch module 34 is configured to determine the target prefetch information of the virtual address stream based on the periodic analysis results, and perform page table prefetching according to the target prefetch information. The page table prefetching is used to access the target data in memory.

[0072] In some examples of this embodiment, the determining module 33 is specifically configured to determine first address difference information between multiple consecutive memory access blocks based on the address information corresponding to each of the multiple consecutive memory access blocks; determine the first address difference information as address jump information where address jumps occur in the multiple consecutive memory access blocks; if the address jump information meets the periodicity condition, determine that the address jump information is periodic and determine that there is a next consecutive memory access block after the current consecutive memory access block; if the address jump information does not meet the periodicity condition, determine that the address jump information is non-periodic and determine that there is no next consecutive memory access block after the current consecutive memory access block.

[0073] In some examples of this embodiment, the prefetch module 34 is specifically configured to, when the address transition information meets the periodic condition, determine the remaining page table prefetch information corresponding to the remaining address of the current consecutive memory access block and the page table prefetch information corresponding to the next consecutive memory access block as the first target prefetch information, and perform page table prefetching according to the first target prefetch information; determine the remaining page table prefetch information corresponding to the remaining address of the current consecutive memory access block as the second target prefetch information, generate a second prefetch instruction for the second target prefetch information, and perform page table prefetching according to the second prefetch instruction.

[0074] In some examples of this embodiment, the prefetch module 34 is further configured to: determine invalid address intervals between multiple consecutive memory access blocks based on the first address difference information; determine the prefetch information corresponding to the invalid address intervals as invalid prefetch information; determine the prefetch information other than invalid prefetch information in the page table prefetch information corresponding to the next consecutive memory access block as the next page table prefetch information; determine the remaining page table prefetch information corresponding to the remaining address of the current consecutive memory access block and the next page table prefetch information corresponding to the next consecutive memory access block as the first target prefetch information; generate a first prefetch instruction for the first target prefetch information; and perform page table prefetching according to the first prefetch instruction.

[0075] In some examples of this embodiment, the filtering module 32 is specifically configured to determine the second address difference information of adjacent addresses based on the address information of adjacent addresses in the virtual address stream; compare the second address difference information with the base difference information to obtain the difference comparison result between the second address difference information and the base difference information; if the difference comparison result satisfies the address continuity condition, the adjacent address is determined as the target address with address continuity, and the target address is divided into a continuous memory access block.

[0076] In some examples of this embodiment, the prefetch module 34 is further configured to obtain the number of consecutive memory access blocks in the virtual address stream; when the number information is one consecutive memory access block, the remaining page table prefetch information corresponding to the remaining address of the current consecutive memory access block and the predicted page table prefetch information corresponding to the subsequent virtual addresses of the target number are determined as the third target prefetch information, and page table prefetching is performed according to the third target prefetch information.

[0077] It should be noted that other corresponding descriptions of the functional units involved in the page table prefetching device provided in this embodiment can be found in [reference]. Figure 1 and Figure 2 The corresponding description in [the document] will not be repeated here.

[0078] Based on the above, Figure 1 and Figure 2 Accordingly, this embodiment also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the above-described method. Figure 1 and Figure 2 The method shown.

[0079] Based on this understanding, the technical solution of this application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as CD-ROM, USB flash drive, mobile hard drive, etc.) and includes several instructions to cause a computer device (such as personal computer, server, or network device, etc.) to execute the methods of various implementation scenarios of this application.

[0080] like Figure 4 The diagram shown is a hardware structure schematic of an electronic device according to the present invention, comprising: At least one processor 401; and, A memory 402 connected to the processing of at least one processor 401 terminal device; wherein, The memory 402 stores instructions that can be executed by at least one processor, such that the instructions are executed by at least one processor to enable the at least one processor to perform the page table prefetching method as described above.

[0081] Figure 4 Take a processor 401 as an example.

[0082] The electronic device may also include an input device 403 and an output device 404.

[0083] The processor 401, memory 402, input device 403, and output device 404 can be connected via a bus or other means. Figure 4 Taking the example of a connection between China and Israel via a bus.

[0084] Memory 402, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the program instructions / modules corresponding to the page table prefetching method in the embodiments of this application, for example, Figure 1 and Figure 2 The method flow is shown. The processor 401 executes various functional applications and terminal device processing by running non-volatile software programs, instructions, and modules stored in the memory 402, that is, it implements the page table prefetching method in the above embodiments.

[0085] Memory 402 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created according to the use of the page table prefetching method, etc. Furthermore, memory 402 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, memory 402 may optionally include memory remotely located relative to processor 401, and these remote memories may be connected via a network to means of performing the page table prefetching method. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, processing networks of mobile terminal devices, and combinations thereof.

[0086] Input device 403 can receive user clicks and generate signal inputs related to user settings and function control for the page table prefetching method. Output device 404 may include display devices such as a display screen.

[0087] One or more modules are stored in memory 402, and when run by one or more processors 401, the page table prefetching method in any of the above method embodiments is executed.

[0088] Optionally, the aforementioned physical devices may also include a user interface, a network interface, a camera, radio frequency (RF) circuitry, sensors, audio circuitry, a Wi-Fi module, etc. The user interface may include a display screen, input units such as a keyboard, etc., and optional user interfaces may also include USB interfaces, card reader interfaces, etc. The network interface may optionally include standard wired interfaces, wireless interfaces (such as Wi-Fi interfaces), etc.

[0089] Those skilled in the art will understand that the physical device structure provided in this embodiment does not constitute a limitation on the physical device, and may include more or fewer components, or combine certain components, or have different component arrangements.

[0090] The storage medium may also include an operating system and a processing module for network terminal devices. The operating system is a program that manages the hardware and software resources of the aforementioned physical devices, supporting the operation of information processing programs and other software and / or programs. The processing module for network terminal devices is used to enable terminal device processing between the various components within the storage medium, as well as terminal device processing with other hardware and software within the information processing physical device.

[0091] Through the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware platforms, or it can be implemented by hardware. By applying the scheme of this embodiment, compared with the existing technology, this application embodiment realizes lightweight hardware identification of the gap span between blocks by using the first address difference between multiple consecutive memory access blocks as address transition information and determining the memory access pattern according to the periodic conditions, without the need for complex computing units; by distinguishing between periodic scenarios to generate target prefetch information and issuing corresponding prefetch instructions, the number of prefetched pages can be dynamically adjusted to avoid insufficient or excessive prefetching; by locking the invalid address interval between blocks based on the first address difference, removing invalid prefetch information and synthesizing the first target prefetch information, the invalid page table prefetch corresponding to Padding and Slice gaps can be actively shielded, reducing TLB cache pollution; by calculating the second address difference between adjacent addresses and comparing it with the benchmark difference to divide consecutive memory access blocks, the memory access feature extraction can be completed by relying only on addition and subtraction comparison circuits, reducing overhead and computing resources.

[0092] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0093] The above are merely specific embodiments of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to these embodiments, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A page table prefetching method, characterized in that, include: Obtain a virtual address stream, which is generated according to the memory access target data according to the memory access requirements; Based on the address information of adjacent addresses in the virtual address stream, target addresses with continuous addresses are filtered out from the virtual address stream, and the target addresses are divided into a continuous memory access block. The target addresses are a set of valid virtual addresses in the virtual address stream that are continuous, have a constant step size, and meet the condition of address continuity. The continuous memory access block is a set of addresses in the virtual address stream with a constant difference between adjacent addresses. Determine the address transition information between multiple consecutive memory access blocks, and analyze whether the address transition information is periodic in order to predict whether there will be a next consecutive memory access block after the current consecutive memory access block; Based on the periodic analysis results, the target prefetch information of the virtual address stream is determined, and page table prefetching is performed according to the target prefetch information. The page table prefetching is used to access the target data. The step of determining address transition information between multiple consecutive memory access blocks and analyzing whether the address transition information has periodicity to predict whether there is a next consecutive memory access block after the current consecutive memory access block includes: Based on the address information corresponding to the multiple consecutive memory access blocks, the first address difference information between the multiple consecutive memory access blocks is determined. The first address difference information is determined as the address jump information of multiple consecutive memory access blocks where address jumps occur; If the address transition information satisfies the periodicity condition, the address transition information is determined to be periodic, and it is determined that there is a next consecutive memory access block after the current consecutive memory access block. If the address transition information does not meet the periodicity condition, the address transition information is determined to be non-periodic, and it is determined that there is no next consecutive memory access block after the current consecutive memory access block. The step of filtering out consecutive target addresses from the virtual address stream based on address information of adjacent addresses in the virtual address stream, and dividing the target addresses into a contiguous memory access block, includes: Based on the address information of adjacent addresses in the virtual address stream, determine the second address difference information of the adjacent addresses; The second address difference information is compared with the reference difference information to obtain the difference comparison result between the second address difference information and the reference difference information; If the difference comparison result satisfies the address continuation condition, the adjacent address is determined as the target address with address continuation, and the target address is divided into a continuum access block.

2. The method according to claim 1, characterized in that, The step of determining the target prefetch information of the virtual address stream based on the periodic analysis results, and performing page table prefetching according to the target prefetch information, includes: When the address transition information meets the periodic condition, the remaining page table prefetch information corresponding to the remaining address of the current consecutive memory access block and the page table prefetch information corresponding to the next consecutive memory access block are determined as the first target prefetch information, and page table prefetching is performed according to the first target prefetch information; The remaining page table prefetch information corresponding to the remaining address of the current consecutive memory access block is determined as the second target prefetch information, and a second prefetch instruction for the second target prefetch information is generated. Page table prefetching is performed according to the second prefetch instruction.

3. The method according to claim 2, characterized in that, When the address transition information satisfies the periodicity condition, the remaining page table prefetch information corresponding to the remaining address of the current consecutive memory access block and the page table prefetch information corresponding to the next consecutive memory access block are determined as the first target prefetch information, and page table prefetching is performed according to the first target prefetch information, including: Based on the first address difference information, invalid address intervals between multiple consecutive memory access blocks are determined, and the prefetch information corresponding to the invalid address intervals is determined as invalid prefetch information. In the page table prefetch information corresponding to the next consecutive memory access block, the prefetch information other than the invalid prefetch information is determined as the next page table prefetch information; The remaining page table prefetch information corresponding to the remaining address of the current consecutive memory access block and the next page table prefetch information corresponding to the next consecutive memory access block are determined as the first target prefetch information; A first prefetch instruction is generated to prefetch the first target information, and page table prefetching is performed according to the first prefetch instruction.

4. The method according to any one of claims 1-3, characterized in that, The method further includes: Obtain the number of consecutive memory access blocks in the virtual address stream; When the quantity information is a contiguous memory block, the remaining page table prefetch information corresponding to the remaining address of the current contiguous memory block and the predicted page table prefetch information corresponding to the subsequent virtual addresses of the target quantity are determined as the third target prefetch information, and page table prefetching is performed according to the third target prefetch information.

5. A page table prefetching device, characterized in that, include: The acquisition module is configured to acquire a virtual address stream, which is generated according to the memory access target data according to the memory access requirements. The filtering module is configured to filter out target addresses that are consecutive in the virtual address stream based on the address information of adjacent addresses in the virtual address stream, and divide the target addresses into a contiguous memory access block. The target addresses are a set of valid virtual addresses in the virtual address stream that are consecutive, have a constant step size, and meet the condition of address contiguousness. The contiguous memory access block is a set of addresses in the virtual address stream with a constant difference between adjacent addresses. The determination module is configured to determine address transition information between multiple consecutive memory access blocks, analyze whether the address transition information is periodic, and predict whether there is a next consecutive memory access block after the current consecutive memory access block. The prefetch module is configured to determine the target prefetch information of the virtual address stream based on the periodic analysis results, and perform page table prefetching according to the target prefetch information, wherein the page table prefetching is used to access the target data; The determining module is also configured to determine first address difference information between the multiple consecutive memory access blocks based on the address information corresponding to the multiple consecutive memory access blocks respectively; The first address difference information is determined as address transition information where address transitions occur in multiple consecutive memory access blocks; if the address transition information meets the periodicity condition, the address transition information is determined to be periodic, and it is determined that there is a next consecutive memory access block after the current consecutive memory access block; if the address transition information does not meet the periodicity condition, the address transition information is determined to be non-periodic, and it is determined that there is no next consecutive memory access block after the current consecutive memory access block. The filtering module is also configured to determine the second address difference information of the adjacent addresses based on the address information of the adjacent addresses in the virtual address stream; The second address difference information is compared with the reference difference information to obtain the difference comparison result between the second address difference information and the reference difference information; If the difference comparison result satisfies the address continuation condition, the adjacent address is determined as the target address with address continuation, and the target address is divided into a continuum access block.

6. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method of any one of claims 1 to 4.

7. An electronic device comprising a storage medium, a processor, and a computer program stored on the storage medium and executable on the processor, characterized in that, When the processor executes the computer program, it implements the method of any one of claims 1 to 4.

8. A computer program product, the computer program product comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the method as described in any one of claims 1 to 4.

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