Command control method and peripheral control system

Abstract

The application provides a command control method and a peripheral control system, and relates to the technical field of peripheral control. The method comprises the following steps: in response to a first interrupt triggered by a second processor, reading a command attribute parameter from a command area of a storage area of first system software in shared memory; wherein the first interrupt is an interrupt triggered after a plurality of parameters of commands are stored in the storage area of the first system software by any one of a plurality of system softwares of the second processor; the first system software is any one of the plurality of system softwares of the second processor; the command attribute parameter is analyzed to obtain a corresponding command type; according to the command type, a plurality of commands are read from a content area corresponding to the command type in the storage area of the first system software; and based on the plurality of commands, corresponding command operations on a peripheral are sequentially executed by a peripheral interface controller. The plurality of commands are previously merged commands and are sequentially and continuously executed, and are not interrupted by other commands, thereby ensuring the reliability of peripheral operations.

Description

Technical Field

[0001] This application relates to the field of peripheral control technology, and more specifically, to a command control method and a peripheral control system. Background Technology

[0002] In existing SoCs (System on Chip), the application processor can directly access the peripheral interface controller, and the application processor has multiple processor cores that run different system software simultaneously.

[0003] In related technologies, when multiple system software programs on an application processor need to access the peripheral interface controller, configuration and data corruption can easily occur. For example, if two system software programs on the application processor both need to read data from a peripheral device through the peripheral interface controller, and one system software program sends an instruction to the input / output processor to set the read data configuration, but before reading the data, the other system software program sends a new instruction to the input / output processor to reset the read data configuration, this will cause the next command from one system software program to actually read incorrect data.

[0004] In related technologies, multiple system software programs on the application processor can access the peripheral interface controller, which can easily lead to unreliable operation of peripherals. Summary of the Invention

[0005] The purpose of this application is to provide a command control method and peripheral control system to address the shortcomings of the prior art and solve the aforementioned technical problems in the related art.

[0006] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows: In a first aspect, embodiments of this application provide a command control method applied to a first processor, wherein the first processor and a second processor are communicatively connected, and the first processor is also communicatively connected to a peripheral interface controller, the method comprising: In response to a first interrupt triggered by the second processor, command attribute parameters are read from the command area of ​​the storage region of the first system software in shared memory; wherein, the first interrupt is triggered after the first system software in the second processor stores the parameters of multiple commands in the storage region of the first system software; the first system software is any one of the multiple system software of the second processor; The command attribute parameters are parsed to obtain the corresponding command type, wherein the command type includes: configuration command type and data command type; According to the command type, the plurality of commands are read from the content area corresponding to the command type in the storage area of ​​the first system software, and the plurality of commands include at least: configuration commands and data commands; Based on the multiple commands, the peripheral interface controller sequentially executes the corresponding command operations on the peripherals.

[0007] Optionally, the first system software in the second processor is configured to store the command attribute parameters of the configuration command and the data command in the command area of ​​the storage space of the first system software, store the content parameters of the configuration command in the configuration parameter area of ​​the storage space of the first system software, and store the content parameters of the data command in the configuration parameter area and the data area of ​​the storage space of the first system software. The step of reading the plurality of commands from the content area corresponding to the command type in the storage area of ​​the first system according to the command type includes: According to the configuration command type, the configuration command is read from the configuration parameter area of ​​the storage space of the first system; According to the data command type, the data command is read from the configuration parameter area and data area of ​​the storage space of the first system.

[0008] Optionally, the step of reading command attribute parameters from the command area of ​​the storage region of the first system software in shared memory in response to a first interrupt triggered by the second processor includes: The first interrupt triggered by the second processor through the target register group corresponding to the first system software is obtained, wherein the multiple system software in the second processor each has a corresponding register group, and the shared memory has multiple storage areas corresponding to the register group; Determine multiple storage regions corresponding to the target register group from the shared memory; In response to the first interrupt, the storage area of ​​the first system software is determined from multiple storage areas corresponding to the target register group according to the target interrupt bit of the first interrupt; The command attribute parameters are read from the command area of ​​the storage space of the first system software.

[0009] Optionally, the multiple system software deployed in the second processor are divided into security system software and non-security system software. Different system software in the security system software corresponds to the same register group, different system software in the non-security system software corresponds to the same register group, and security system software and non-security system software correspond to different register groups. Different system software in the security system software corresponds to different interrupt bits, and different system software in the non-security system software corresponds to different interrupt bits.

[0010] Optionally, the method further includes: During the process of sequentially executing the multiple command-corresponding operations on the peripheral device through the peripheral interface controller, if a command sent by the second system software of the second processor is received, wherein the second system software is any system software other than the first system software among the multiple system software; Return the occupancy information of the peripheral interface controller to the second processor.

[0011] Optionally, before executing corresponding command operations on the peripherals sequentially through the peripheral interface controller based on the plurality of commands, the method further includes: Based on the first interrupt triggered by the second processor, determine the request type of the first system software; If the request type of the first system software is a non-secure request, then the multiple commands are filtered to obtain multiple filtered commands. The step of sequentially executing corresponding command operations on peripherals through the peripheral interface controller based on the multiple commands includes: Based on the filtered commands, the peripheral device is sequentially executed with corresponding command operations through the peripheral interface controller.

[0012] Optionally, the filtering process for the plurality of commands to obtain filtered commands includes: The target configuration command for peripheral capacity setting among the multiple commands is filtered to obtain the filtered multiple commands; Send a security error message to the second processor regarding the target configuration command.

[0013] Optionally, the filtering process for the plurality of commands to obtain filtered commands includes: Determine the data command among the plurality of commands; Based on the starting address and the amount of data processed by the data command, determine whether the operation on the data command involves the security zone of the peripheral device; If the security zone of the peripheral device is involved, the data commands are filtered to obtain multiple filtered commands; Send a security error message for the data command to the second processor.

[0014] Optionally, the step of sequentially executing corresponding command operations on peripherals through the peripheral interface controller based on the plurality of commands includes: Write the registers in the peripheral interface controller based on the configuration command among the multiple commands; Based on the data command among the multiple commands, the registers in the peripheral interface controller are configured, and data operations are performed on the peripheral through the peripheral interface controller.

[0015] Optionally, configuring the registers in the peripheral interface controller based on the data command among the plurality of commands, and performing data operations on the peripheral through the peripheral interface controller, includes: If the data command is a read data command, the registers in the peripheral interface controller are configured based on the read data command, and the peripheral is read from the peripheral through the peripheral interface controller.

[0016] Optionally, configuring the registers in the peripheral interface controller based on the data command among the plurality of commands, and performing data operations on the peripheral through the peripheral interface controller, includes: If the data command is a target data command, the registers in the peripheral interface controller are configured according to the target data command, wherein the target data command is a write data command or an erase data command; The target data command is sent to the peripheral interface controller so that the peripheral can be operated on by the peripheral interface controller, wherein the target data operation is a write data operation or an erase data operation; In response to a second interrupt triggered by the peripheral interface controller, the next command of the target data command among the plurality of commands is processed.

[0017] Secondly, embodiments of this application also provide a peripheral control system, including: a first processor, a second processor, and a peripheral interface controller; the second processor and the first processor are communicatively connected, and the first processor and the peripheral interface controller are communicatively connected; The first processor is used to execute the command control method described in any of the first aspects above.

[0018] The beneficial effects of this application are as follows: This application provides a command control method, which may include: responding to a first interrupt triggered by a second processor, reading command attribute parameters from the command area of ​​the storage region of a first system software in shared memory; wherein, the first interrupt is an interrupt triggered after the first system software in the second processor stores parameters of multiple commands into the storage region of the first system software; the first system software is any one of multiple system software programs of the second processor; parsing the command attribute parameters to obtain the corresponding command type, wherein the command type includes: configuration command type and data command type; according to the command type, reading multiple commands from the content area corresponding to the command type in the storage region of the first system software, the multiple commands including at least: configuration commands and data commands; based on the multiple commands, sequentially executing the corresponding command operations on the peripherals through a peripheral interface controller. In the second processor, the first system software stores the parameters of multiple commands in its storage area, thus merging the multiple commands. After the first processor reads out the multiple commands, it executes the corresponding command operations on the peripherals sequentially through the peripheral interface controller based on these multiple commands. These multiple commands were previously merged and were executed sequentially and continuously. During the execution of multiple commands, the first processor does not process access requests from other system software in the multiple system software, that is, the continuous execution of these multiple commands will not be interrupted by other commands, ensuring the reliability of peripheral operation. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the structure of a peripheral control system provided in an embodiment of this application; Figure 2 A schematic diagram of the software architecture of a peripheral control system provided for an embodiment of this application; Figure 3 A schematic diagram of the hardware architecture of a peripheral control system provided in an embodiment of this application; Figure 4 A flowchart illustrating a command control method provided in this application embodiment. Figure 1 ; Figure 5 A flowchart illustrating a command control method provided in this application embodiment. Figure 2 ; Figure 6A flowchart illustrating a command control method provided in this application embodiment. Figure 3 ; Figure 7 A flowchart illustrating a command control method provided in this application embodiment. Figure 4 ; Figure 8 A flowchart illustrating a command control method provided in this application embodiment. Figure 5 ; Figure 9 A flowchart illustrating a command control method provided in this application embodiment. Figure 6 ; Figure 10 A flowchart illustrating a command control method provided in this application embodiment. Figure 7 ; Figure 11 A flowchart illustrating a command control method provided in this application embodiment. Figure 8 ; Figure 12 A flowchart illustrating a command control method provided in this application embodiment. Figure 9 ; Figure 13 This application provides a complete flowchart of a command control method according to an embodiment of the present application. Figure 14 This is a schematic diagram of the structure of a command control device provided in an embodiment of this application. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of this application, but not all embodiments.

[0022] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0023] In the description of this application, it should be noted that if the terms "upper", "lower", etc. appear to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship that the product of this application is usually placed in, it is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0024] Furthermore, the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Additionally, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0025] It should be noted that, where there is no conflict, the features in the embodiments of this application can be combined with each other.

[0026] Figure 1 This is a schematic diagram of the structure of a peripheral control system provided in an embodiment of this application, such as... Figure 1 As shown, the peripheral control system may include: a first processor, a second processor, and a peripheral interface controller; the second processor and the first processor are connected in communication, and the first processor and the peripheral interface controller are connected in communication. The peripheral interface controller is also connected to peripherals.

[0027] In some implementations, the first processor can be an I / O processor (Input / Output Processor), the second processor can be an AP processor (Application Processor), and the peripheral interface controller can be a QSPI (Queued Serial Peripheral Interface) controller.

[0028] Of course, the first processor and the second processor can also be other types of processors, and the peripheral interface controller can also be other types of controllers. This application does not impose specific limitations on these aspects.

[0029] Figure 2 A schematic diagram of the software architecture of a peripheral control system provided in this application embodiment is shown below. Figure 2 As shown, the second processor has multiple processor cores and runs multiple different system software programs simultaneously. Optionally, these multiple system software programs may include: operating system software, firmware software, module software, and execution environment software. For example... Figure 2As shown, the first processor has a non-secure register set, a secure register set, multiple storage areas in shared memory, a protocol layer, a device driver, and a controller driver. Figure 2 As shown, a peripheral interface controller is deployed on the hardware. The peripheral interface controller interacts with the peripheral device. For example, the peripheral interface controller can be a QSPI controller.

[0030] The second processor and the first processor communicate via insecure register sets, secure register sets, and shared memory. Operating system software and firmware software in the second processor send insecure requests to the first processor through two memory locations corresponding to the insecure register sets; module-level system software and execution environment software in the second processor send secure requests to the first processor through two memory locations corresponding to the secure register sets. Specifically, each system software corresponds to one memory location in the shared memory, and the memory locations corresponding to multiple system software programs are different. The insecure or secure register sets are responsible for notification, while the memory locations are responsible for transmitting commands, parameters, and data.

[0031] Figure 3 A schematic diagram of the hardware architecture of a peripheral control system provided in this application embodiment is shown below. Figure 3 As shown, the system bus connects a second processor, a peripheral bus, and a first processor bus. The second processor has multiple core clusters, each with multiple cores; for example, each core cluster can have four cores. The peripheral bus is connected to a peripheral interface controller, which in turn is connected to peripherals and the first processor.

[0032] like Figure 3 As shown, the first processor, shared memory, registers, and SRAM (Static Random Access Memory) are connected to the first processor bus. The first processor also has a core and cache.

[0033] It is worth noting that the second processor, as the application processor, runs different system software, while the first processor, as the I / O processor, handles QSPI requests sent by the second processor. The peripheral interface controller, located under the peripheral bus, responds to the access requests of the first processor, reads and writes data in the peripherals, and returns the data to the first processor.

[0034] This application also provides a command control method applied to a first processor in a peripheral control system. The following is an explanation of the command control method provided by this application.

[0035] Figure 4 A flowchart illustrating a command control method provided in this application embodiment. Figure 1 ,like Figure 4 As shown, the method may include: S101, responding to the first interrupt triggered by the second processor, read command attribute parameters from the command area of ​​the storage region of the first system software in shared memory.

[0036] The first interrupt is triggered after the first system software in the second processor stores the parameters of multiple commands into the storage area of ​​the first system software; the first system software is any one of the multiple system software of the second processor.

[0037] In some implementations, the first system software in the second processor stores the parameters of multiple commands in the storage area of ​​the first system software, which enables the merging of multiple commands of the first system software. Subsequently, the second processor can trigger a first interrupt. In response to the first interrupt, the first processor reads the command attribute parameters from the command area of ​​the storage area of ​​the first system software in the shared memory.

[0038] It should be noted that each system software corresponds to a different storage area in the shared memory.

[0039] S102. Parse the command attribute parameters to obtain the corresponding command type.

[0040] The command types include configuration command types and data command types.

[0041] In some implementations, a QSPI task in the first processor is used to read command attribute parameters from the command area of ​​the storage region of the first system software in shared memory, and then parse the command attribute parameters to obtain the corresponding command type.

[0042] S103. Based on the command type, read multiple commands from the content area corresponding to the command type in the storage area of ​​the first system software.

[0043] Among these, multiple commands include at least: configuration commands and data commands.

[0044] In some implementations, a corresponding processing function is invoked based on the command type to read multiple commands from the content area corresponding to the command type in the storage space of the first system software. Different command types invoke different processing functions, and the content area to be read also differs for different command types. The storage space of the first system software includes at least a command area and a content area.

[0045] In this embodiment of the application, multiple command attribute parameters can be read from the command area of ​​the storage region of the first system software in the shared memory, and the multiple command attribute parameters can be parsed to obtain multiple command types; according to these multiple command types, multiple commands can be read from the content area corresponding to the command type in the storage region of the first system software.

[0046] Of course, a command attribute parameter can be read from the command area of ​​the storage space of the first system software; then, based on the parsing of the command attribute parameter, the corresponding command type can be obtained; then, a command can be read from the content area corresponding to the command type in the storage space of the first system software. Then, the next command attribute parameter can be read from the command area of ​​the storage space of the first system software, and the above steps can be repeated to obtain the next command. In this way, multiple commands can be obtained in the end.

[0047] S104. Based on multiple commands, the peripheral interface controller sequentially executes the corresponding command operations on the peripherals.

[0048] In this process, the second processor provides atomic operations to the first processor. Multiple commands in the storage area of ​​the first system software in the shared memory are merged into a single merged instruction. This ensures that the multiple commands are executed independently, continuously, and without interruption, thereby ensuring reliable operation of peripherals based on these multiple commands.

[0049] In practical applications, multiple commands may have a sequential order. Multiple commands can be read out first, and the peripheral interface controller can execute the corresponding command operations on the peripheral device sequentially. Alternatively, each time a command is read out, the peripheral interface controller executes the corresponding command operation on the peripheral device based on that command; then the next command is read out, and the peripheral interface controller executes the corresponding command operation on the peripheral device based on that next command. This application does not impose specific limitations on this approach.

[0050] It is important to note that the first processor can only process requests from other system software in the second processor after all these commands have been executed. During the execution of these commands, the first processor cannot process requests from other system software in the second processor. These other system software programs refer to all system software programs other than the first system software. Since the commands were previously merged, other commands can only be executed after these commands have been executed sequentially and continuously, thus ensuring reliable operation of peripherals based on these commands.

[0051] For example, in related technologies, if system software a and system software b in multiple system software of the second processor both need to read data from peripherals through the peripheral interface controller, system software a sends a configuration command to the first processor to set the data reading configuration. Before reading the data, system software b sends a new configuration command to the first processor to reset the data reading configuration, such as the read address or chip select settings being different. This will cause errors in the data actually read by system software a based on the data reading instruction (the instruction following the configuration instruction). (The main reason here is that the configuration of system software a is overwritten by the configuration of system software b, so a data reading error occurs.)

[0052] In this embodiment, the configuration commands and read data commands of system software a are merged within the shared memory storage area of ​​system software a. The first processor reads these commands from the storage area of ​​system software a and, based on them, executes the configuration and read data operations of system software a sequentially and continuously through the peripheral interface controller. This ensures that the configuration and read commands of system software a can be executed sequentially and continuously without interruption by instructions from other system software besides system software a (e.g., system software b). This avoids the problem of data errors caused by the configuration of system software a being overwritten by the configuration of system software b, thus guaranteeing reliable operation of peripherals.

[0053] In summary, this application provides a command control method, which may include: responding to a first interrupt triggered by a second processor, reading command attribute parameters from the command area of ​​the storage region of a first system software in shared memory; wherein, the first interrupt is an interrupt triggered after the first system software in the second processor stores parameters of multiple commands in the storage region of the first system software; the first system software is any one of multiple system software of the second processor; parsing the command attribute parameters to obtain the corresponding command type, wherein the command type includes: configuration command type and data command type; according to the command type, reading multiple commands from the content area corresponding to the command type in the storage region of the first system software, the multiple commands including at least: configuration commands and data commands; based on the multiple commands, executing the corresponding command operations on the peripherals sequentially through the peripheral interface controller. In the second processor, the first system software stores the parameters of multiple commands in its storage area, thus merging multiple commands. After the first processor reads out the multiple commands, it executes the corresponding command operations on the peripherals sequentially through the peripheral interface controller. These multiple commands were previously merged and executed sequentially. During the execution of multiple commands, the first processor does not handle access requests from other system software in the multiple system software, that is, the continuous execution of these multiple commands will not be interrupted by other commands, ensuring the reliability of peripheral operation.

[0054] Optionally, the first system software in the second processor is used to store the command attribute parameters of the configuration command and the data command in the command area of ​​the storage space of the first system software, store the content parameters of the configuration command in the configuration parameter area of ​​the storage space of the first system software, and store the content parameters of the data command in the configuration parameter area and the data area of ​​the storage space of the first system software.

[0055] The command attribute parameters for configuration commands and data commands can include: command type, command length, command fields, etc.

[0056] In some implementations, the configuration command parameters may include at least one of the following: chip select, frequency division factor, data address, transmission mode (single-wire, dual-wire, quad-wire), etc. The data command parameters may include: read command parameters, write command parameters, or erase command parameters.

[0057] Optionally, Figure 5 A flowchart illustrating a command control method provided in this application embodiment. Figure 2 ,like Figure 5 As shown, the process of reading multiple commands from the content area corresponding to the command type in the storage area of ​​the first system according to the command type in S103 above may include: S201. Based on the configuration command type, read the configuration command from the configuration parameter area of ​​the storage area of ​​the first system.

[0058] S202. Based on the data command type, read the data command from the configuration parameter area and data area of ​​the storage area of ​​the first system.

[0059] In some implementations, based on the configuration command type, the corresponding processing function is called to read the configuration command from the configuration parameter area of ​​the storage space of the first system; based on the data command type, the corresponding processing function is called to read the data command from the configuration parameter area and data area of ​​the storage space of the first system.

[0060] The storage area of ​​the first system includes a command area, a configuration parameter area, and a data area. For example, the specific contents of the command area, configuration parameter area, and data area in the storage area of ​​the first system can be found in Table 1.

[0061] Table 1

[0062] Optionally, Figure 6 A flowchart illustrating a command control method provided in this application embodiment. Figure 3 ,like Figure 6 As shown, the process of reading command attribute parameters from the command area of ​​the storage region of the first system software in shared memory in response to the first interrupt triggered by the second processor in S101 above may include: S301. Obtain the first interrupt triggered by the second processor through the target register group corresponding to the first system software.

[0063] In the second processor, multiple system software programs each have corresponding register sets, and the shared memory has multiple storage areas corresponding to the register sets.

[0064] like Figure 2 As shown, among multiple system software programs, operating system software and firmware software correspond to the non-secure register set, while module software and execution environment software correspond to the secure register set. The non-secure register set corresponds to two storage areas: the storage area for the operating system software and the storage area for the firmware software. The secure register set corresponds to two storage areas: the storage area for the module software and the storage area for the execution environment software.

[0065] In some implementations, the first system software sends a target interrupt bit to the target register group corresponding to the first system software, triggering a first interrupt through the target register group. The target register group can notify the first processor of the first interrupt to inform the first processor that there is a command to be executed. This command is multiple commands, i.e., a merged command. The first processor can obtain the first interrupt.

[0066] It should be noted that the target register set can be either a secure register set or a non-secure register set. When the first system software is an operating system or firmware system software, the target register set is a non-secure register set; when the first system software is a module-based system software or an execution environment-based system software, the target register set is a secure register set.

[0067] S302. Determine multiple storage ranges corresponding to the target register group from shared memory.

[0068] Among them, such as Figure 2 As shown, two memory regions corresponding to either a non-secure register set or a secure register set can be determined from shared memory.

[0069] S303. Respond to the first interrupt and determine the storage area of ​​the first system software from multiple storage areas corresponding to the target register group according to the target interrupt bit of the first interrupt.

[0070] In some implementations, in response to a first interrupt, the storage area of ​​the first system software can be determined from the two storage areas corresponding to the target register group based on the target interrupt bit of the first interrupt.

[0071] In this embodiment, both operating system software and firmware software correspond to non-secure register sets, but the target interrupt bits used by the operating system software and firmware software are different. Similarly, both module software and execution environment software correspond to non-secure register sets, but the target interrupt bits used by the module software and execution environment software are different.

[0072] S304. Read command attribute parameters from the command area of ​​the storage space of the first system software.

[0073] Optionally, the multiple system software deployed in the second processor are divided into secure system software and non-secure system software. Different system software in the secure system software corresponds to the same register group, different system software in the non-secure system software corresponds to the same register group, and secure system software and non-secure system software correspond to different register groups. Different system software in the secure system software corresponds to different interrupt bits, and different system software in the non-secure system software corresponds to different interrupt bits.

[0074] Among them, such as Figure 2 As shown, operating system software and firmware software are classified as insecure system software, while module software and execution environment software are classified as secure system software. The storage areas for each system software on shared memory are different.

[0075] In this embodiment, the operating system software and firmware software send insecure requests to the first processor through the insecure register group and the two memory ranges corresponding to the insecure register group. The interrupt bit for the operating system software can be ap2rv_intr_state0, and the memory range can be shmem 0x800~0xbff; the interrupt bit for the firmware software can be ap2rv_intr_state1, and the memory range can be shmem 0xc00~0xfff. For example, the operating system software can be an OS (Operating System), and the firmware software can be UEFI (Unified Extensible Firmware Interface).

[0076] Additionally, both module-type system software and execution environment-type system software send security requests to the first processor through the security register set and its corresponding two memory ranges. The interrupt bit for module-type system software can be ap2rv_intr_state0, and the memory range can be shmem 0x00~0x3ff; the interrupt bit for execution environment-type system software can be ap2rv_intr_state1, and the memory range can be shmem 0x400~0x7ff. For example, the module-type system software could be an MM (Memory Management) module, and the execution environment-type system software could be an OPTEE (Open Portable Trusted Execution Environment).

[0077] Optionally, Figure 7 A flowchart illustrating a command control method provided in this application embodiment. Figure 4 ,like Figure 7 As shown, the method may further include: S401. During the process of sequentially executing multiple command-corresponding operations on peripherals through the peripheral interface controller, if a command is received from the second system software of the second processor.

[0078] The second system software is any system software other than the first system software among multiple system software.

[0079] S402, Return the occupancy information of the peripheral interface controller to the second processor.

[0080] It should be noted that the first processor can only process commands sent by the second system software of the second processor after multiple command-related operations have been completed. If multiple command-related operations are in progress, and a command is received from the second system software of the second processor, the processor returns peripheral interface controller occupancy information to the second processor to inform the second system software that the request cannot be responded to at this time. The peripheral interface controller occupancy information is used to indicate that the peripheral interface controller's resources are occupied.

[0081] Optionally, Figure 8 A flowchart illustrating a command control method provided in this application embodiment. Figure 5 ,like Figure 8 As shown, before the process in S104 above where the peripheral interface controller sequentially executes corresponding command operations on the peripherals based on multiple commands, the method may further include: S501. Determine the request type of the first system software based on the first interrupt triggered by the second processor.

[0082] In this process, the first processor responds to the first interrupt, performs interrupt clearing, and sends a message to wake up the QSPI task in the first processor. The QSPI task can determine the attribute of the command, i.e. the request type of the first system software, through the target register group from which the command originates.

[0083] In some implementations, the target register set to be triggered is determined based on the first interrupt triggered by the second processor, and the request type of the first system software is determined to be either a non-secure request or a secure request based on the target register set.

[0084] Specifically, if the target register group is a non-secure request, the request type of the first system software is a non-secure request; if the target register group is a secure request, the request type of the first system software is a secure request.

[0085] S502. If the request type of the first system software is a non-secure request, then the multiple commands are filtered to obtain the filtered multiple commands.

[0086] In some implementations, if the request type of the first system software is a non-secure request, a preset filtering algorithm is used to filter multiple commands to obtain multiple filtered commands.

[0087] The process in S104 above, which involves executing corresponding command operations on peripherals sequentially through the peripheral interface controller based on multiple commands, may include: S503: Based on multiple filtered commands, the peripheral interface controller sequentially executes the corresponding command operations on the peripherals.

[0088] In practical applications, after executing multiple filtered commands, the execution result is returned to the second processor; for the filtered commands, a security error is returned directly to the second processor.

[0089] In addition, if the request type of the first system software is a security request, there is no need to filter multiple commands. The peripheral interface controller executes the command operations corresponding to multiple commands sequentially on the peripheral device. After executing multiple commands, the execution result is returned to the second processor.

[0090] Optionally, Figure 9 A flowchart illustrating a command control method provided in this application embodiment. Figure 6 ,like Figure 9 As shown, the process of filtering multiple commands in S502 above to obtain filtered commands may include: S601. Filter the target configuration command for peripheral capacity setting among multiple commands to obtain multiple filtered commands.

[0091] The target configuration command is used to set the capacity of peripherals. For example, the peripheral can be Flash (Flash Memory).

[0092] S602, Send a security error message to the second processor regarding the target configuration command.

[0093] Specifically, the first processor sends a security error message for the target configuration command to the first system software of the second processor, and the first system software of the second processor can receive the security error message for the target configuration command.

[0094] In summary, the first processor provides different register sets and memory areas to different system software on the second processor, distinguishing requests from different systems on the second processor. Once the different systems are identified, it can be determined whether the request from the first processor is secure or insecure. Secure requests can access all peripherals on the chip, while insecure requests require further evaluation. If the processing area involves a secure region, the request is not executed, and a security error is returned to the first processor. This ensures secure command operations on peripherals.

[0095] Optionally, Figure 10 A flowchart illustrating a command control method provided in this application embodiment. Figure 7 ,like Figure 10 As shown, the process of filtering multiple commands in S502 above to obtain filtered commands may include: S701, Determine the data command among multiple commands.

[0096] Among them, data commands can be read commands, write commands, or erase commands.

[0097] S702. Based on the starting address of the data command and the amount of data processed, determine whether the operation on the data command involves the security zone of the peripheral device.

[0098] In some implementations, the starting address of the read command and the amount of data read are used to determine whether the operation of the read command involves the secure area of ​​the peripheral device; the starting address of the write command and the amount of data written are used to determine whether the operation of the write command involves the secure area of ​​the peripheral device; the starting address of the erase command and the erase command type are used to determine the erase range and whether the operation of the erase command involves the secure area of ​​the peripheral device.

[0099] It should be noted that during the startup phase, after the first processor has started up, if a security system is running, the security system sends a security zone configuration command to the first processor. The first processor then records the security zone in its software, thus setting the security zone for the peripheral device.

[0100] S703. If the security zone of peripheral devices is involved, the data commands are filtered to obtain multiple filtered commands.

[0101] S704: Send a security error message for the data command to the second processor.

[0102] It should be noted that the first system software of the second processor sends a security error message to the command for the filtered data.

[0103] Optionally, Figure 11 A flowchart illustrating a command control method provided in this application embodiment. Figure 8 ,like Figure 11 As shown, based on multiple commands, the peripheral interface controller sequentially executes corresponding command operations on the peripherals, including: S801: Write to the registers in the peripheral interface controller based on the configuration command among multiple commands.

[0104] Specifically, based on the configuration command among multiple commands, the registers in the peripheral interface controller are written so that the peripheral interface controller can sequentially execute the command operations corresponding to the configuration command on the peripherals.

[0105] S802: Based on the data command among multiple commands, configure the registers in the peripheral interface controller, and perform data operations on the peripherals through the peripheral interface controller.

[0106] In this embodiment, based on the data command among multiple commands, a series of configurations are performed on the registers in the peripheral interface controller, such as instruction bytes, chip select, transmission protocol, and frequency division coefficient, to read or write the data registers or memory-mapped addresses in the peripheral interface controller.

[0107] Optionally, the process in S802 described above, which configures the registers in the peripheral interface controller based on the data command among multiple commands and performs data operations on the peripheral through the peripheral interface controller, may include: If the data command is a read data command, the registers in the peripheral interface controller are configured based on the read data command, and the peripheral interface controller is used to perform read data operations on the peripherals.

[0108] In some implementations, in response to a read data command, the peripheral device reads the data register in the peripheral interface controller, sends the read data to the data register of the peripheral interface controller, and then the first processor reads the data from the data register of the peripheral interface controller.

[0109] In addition, for write data commands, the first processor writes the data of the write data command to the data register in the peripheral interface controller, and the peripheral interface controller sends the data in the data register to the peripheral.

[0110] In other implementations, for a read data command, the peripheral interface controller reads the memory-mapped address. Memory mapping refers to mapping the address of a peripheral to the address space of the first processor, for example, mapping it to 0~0x100000. When the first processor reads data at address 0x100, the peripheral interface controller will read the peripheral at address 0x100.

[0111] In addition, for write data commands, the first processor writes the data of the write data command to 0x100, and the read peripheral interface controller rewrites the data to the 0x100 location of the peripheral.

[0112] Figure 12 A flowchart illustrating a command control method provided in this application embodiment. Figure 9 ,like Figure 12 As shown, the process in S802 above, which configures the registers in the peripheral interface controller based on the data command among multiple commands and performs data operations on the peripheral through the peripheral interface controller, may include: S901. If the data command is a target data command, configure the registers in the peripheral interface controller according to the target data command.

[0113] The target data command is either a write data command or an erase data command.

[0114] In some implementations, if the data command is a target data command, the instruction byte, chip select, transmission protocol, and frequency division factor are set in the registers of the peripheral interface controller according to the target data command, and the peripheral address is set.

[0115] S902. Send the target data command to the peripheral interface controller so that the peripheral interface controller can perform target data operations on the peripheral device. The target data operation is either a write data operation or an erase data operation.

[0116] In this embodiment, the data in the target data command is written to the address mapping area of ​​the peripheral interface controller. For the command transmission method of memory-mapped address, a write buffer register is configured, the QSPI task is suspended, and the peripheral interface controller sends the data in the buffer to the peripheral to perform target data operation on the peripheral.

[0117] S903 responds to the second interrupt triggered by the peripheral interface controller and processes the next command among multiple commands for the target data command.

[0118] It should be noted that after the peripheral interface controller sends all the data in the buffer to the peripheral, it responds to the second interrupt triggered by the peripheral interface controller. The first processor responds to the second interrupt, clears the interrupt in the interrupt service function, sends a message queue to wake up the QSPI task in the first processor, returns the target data command to continue subsequent processing, and processes the next command of the target data command among multiple commands until all commands are executed.

[0119] In this embodiment, the first processor controls the peripheral interface controller to send a WIP command (a command to query the write in progress status) to the peripheral to determine that the peripheral programming instructions have been executed. The first processor fills in the return value based on the success or failure of the command execution and triggers an RV2AP interrupt to notify the second application processor that the command execution is complete.

[0120] Figure 13 This is a complete flowchart illustrating a command control method provided in an embodiment of this application, as shown below. Figure 13 As shown, the device driver on the second processor fills multiple commands into a message structure in shared memory, triggering the first interrupt.

[0121] like Figure 13 As shown, the first processor receives commands, obtains peripheral tasks, and then determines whether the request from the second processor is a security request. If it is not a security request, the command is parsed and filtered; if it is a security request, the command is parsed and executed. If it is a configuration command, the peripheral interface controller is written to; if it is a data command, the configuration of the peripheral interface controller is changed, and data transmission configuration is performed.

[0122] After the first processor sends all the data to the peripheral interface controller, it triggers a write interrupt. The interrupt service routine on the peripheral interface controller handles the interrupt, and then the first processor fills the return value and triggers a register interrupt. The second processor can then obtain the data and the return value.

[0123] In summary, in this embodiment of the application, the software layer of the first processor encapsulates the peripheral interface controller and provides an atomic operation interface for the second processor. A single instruction can execute multiple commands, avoiding out-of-order access when multiple software systems access the device. Regardless of which system is running on the second processor, reliable operation of the peripherals can be ensured.

[0124] Furthermore, the sharing of the same peripheral between secure and non-secure system software saves costs. During startup, the secure system can send an instruction to the first processor to designate a specific address region of the peripheral as a secure region, which is recorded in the first processor software. Subsequently, requests from non-secure systems that involve the secure region will not be executed, and a security error will be returned to the second processor, effectively preventing the leakage of secure data.

[0125] The following describes the command control device and storage medium used to execute the command control method provided in this application. For the specific implementation process and technical effects, please refer to the relevant content of the command control method above, which will not be repeated below.

[0126] Figure 14 This is a schematic diagram of the structure of a command and control device provided in an embodiment of this application, as shown below. Figure 14 As shown, the device includes: The first reading module 101 is used to read command attribute parameters from the command area of ​​the storage area of ​​the first system software in the shared memory in response to a first interrupt triggered by the second processor; wherein, the first interrupt is an interrupt triggered after the first system software in the second processor stores the parameters of multiple commands in the storage area of ​​the first system software; the first system software is any one of the multiple system software of the second processor; The parsing module 102 is used to parse the command attribute parameters to obtain the corresponding command type, wherein the command type includes: configuration command type and data command type; The second reading module 103 is used to read the plurality of commands from the content area corresponding to the command type in the storage area of ​​the first system software according to the command type. The plurality of commands include at least: configuration commands and data commands. The execution module 104 is used to execute corresponding command operations on the peripherals sequentially through the peripheral interface controller based on the multiple commands.

[0127] Optionally, the first system software in the second processor is configured to store the command attribute parameters of the configuration command and the data command in the command area of ​​the storage space of the first system software, store the content parameters of the configuration command in the configuration parameter area of ​​the storage space of the first system software, and store the content parameters of the data command in the configuration parameter area and the data area of ​​the storage space of the first system software. The second reading module 103 is specifically used to read the configuration command from the configuration parameter area of ​​the storage area of ​​the first system according to the configuration command type; and to read the data command from the configuration parameter area and the data area of ​​the storage area of ​​the first system according to the data command type.

[0128] Optionally, the first reading module 101 is specifically configured to acquire the first interrupt triggered by the second processor through the target register group corresponding to the first system software, wherein the plurality of system software in the second processor each has a corresponding register group, and the shared memory has a plurality of storage areas corresponding to the register groups; determine the plurality of storage areas corresponding to the target register group from the shared memory; respond to the first interrupt, and determine the storage area of ​​the first system software from the plurality of storage areas corresponding to the target register group according to the target interrupt bit of the first interrupt; and read the command attribute parameters from the command area of ​​the storage area of ​​the first system software.

[0129] Optionally, the multiple system software deployed in the second processor are divided into security system software and non-security system software. Different system software in the security system software corresponds to the same register group, different system software in the non-security system software corresponds to the same register group, and security system software and non-security system software correspond to different register groups. Different system software in the security system software corresponds to different interrupt bits, and different system software in the non-security system software corresponds to different interrupt bits.

[0130] Optionally, the device further includes: The receiving module is configured to, during the process of sequentially executing the multiple command-corresponding operations on the peripheral device through the peripheral interface controller, if it receives a command sent by the second system software of the second processor, wherein the second system software is any system software other than the first system software among the multiple system software; The return module is used to return the occupancy information of the peripheral interface controller to the second processor.

[0131] Optionally, the device further includes: The determination module is used to determine the request type of the first system software based on the first interrupt triggered by the second processor; The filtering module is used to filter the multiple commands if the request type of the first system software is an insecure request, so as to obtain the multiple filtered commands. The execution module 104 is specifically used to execute corresponding command operations on the peripheral device sequentially through the peripheral interface controller based on the filtered multiple commands.

[0132] Optionally, the filtering module is specifically used to filter the target configuration command for peripheral capacity setting among the plurality of commands to obtain the filtered plurality of commands; and to send a security error message for the target configuration command to the second processor.

[0133] Optionally, the filtering module is specifically used to determine the data command among the plurality of commands; determine whether the operation on the data command involves the security area of ​​the peripheral device based on the starting address and the amount of data processed by the data command; if it involves the security area of ​​the peripheral device, then filter the data command to obtain the filtered plurality of commands; and send a security error message for the data command to the second processor.

[0134] Optionally, the execution module 104 is specifically used to write to the registers in the peripheral interface controller based on the configuration command among the plurality of commands; to configure the registers in the peripheral interface controller based on the data command among the plurality of commands; and to perform data operations on the peripheral through the peripheral interface controller.

[0135] Optionally, the execution module 104 is specifically used to configure the registers in the peripheral interface controller based on the read data command if the data command is a read data command, and to perform read data operation on the peripheral through the peripheral interface controller.

[0136] Optionally, the execution module 104 is specifically configured to: if the data command is a target data command, configure the registers in the peripheral interface controller according to the target data command, wherein the target data command is a write data command or an erase data command; send the target data command to the peripheral interface controller to perform target data operations on the peripheral through the peripheral interface controller, wherein the target data operation is a write data operation or an erase data operation; and respond to a second interrupt triggered by the peripheral interface controller to process the next command among the plurality of commands for the target data command.

[0137] The above-described device is used to execute the method provided in the foregoing embodiments, and its implementation principle and technical effect are similar, so they will not be described again here.

[0138] These modules can be one or more integrated circuits configured to implement the above methods, such as one or more Application Specific Integrated Circuits (ASICs), one or more Digital Signal Processors (DSPs), or one or more Field Programmable Gate Arrays (FPGAs). Alternatively, when a module is implemented using processing element scheduler code, the processing element can be a general-purpose processor, such as a Central Processing Unit (CPU) or other processor capable of calling program code. Furthermore, these modules can be integrated together as a System-on-a-Chip (SoC).

[0139] Optionally, this application also provides a program product, such as a computer-readable storage medium, including a program that, when executed by a processor, performs the above-described method embodiments.

[0140] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0141] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0142] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in a combination of hardware and software functional units.

[0143] The integrated units implemented as software functional units described above can be stored in a computer-readable storage medium. These software functional units, stored in a storage medium, include several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute some steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0144] The above are merely preferred embodiments of this application and are not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A command control method, characterized in that, The method, applied to a first processor, wherein a communication connection exists between the first processor and a second processor, and the first processor also has a communication connection with a peripheral interface controller, comprises: In response to a first interrupt triggered by the second processor, command attribute parameters are read from the command area of ​​the storage region of the first system software in shared memory; wherein, the first interrupt is triggered after the first system software in the second processor stores the parameters of multiple commands in the storage region of the first system software; the first system software is any one of the multiple system software of the second processor; The command attribute parameters are parsed to obtain the corresponding command type, wherein the command type includes: configuration command type and data command type; According to the command type, the plurality of commands are read from the content area corresponding to the command type in the storage area of ​​the first system software, and the plurality of commands include at least: configuration commands and data commands; Based on the multiple commands, the peripheral interface controller sequentially executes the corresponding command operations on the peripherals.

2. The method according to claim 1, characterized in that, The first system software in the second processor is used to store the command attribute parameters of the configuration command and the data command in the command area of ​​the storage space of the first system software, store the content parameters of the configuration command in the configuration parameter area of ​​the storage space of the first system software, and store the content parameters of the data command in the configuration parameter area and the data area of ​​the storage space of the first system software. The step of reading the plurality of commands from the content area corresponding to the command type in the storage area of ​​the first system according to the command type includes: According to the configuration command type, the configuration command is read from the configuration parameter area of ​​the storage space of the first system; According to the data command type, the data command is read from the configuration parameter area and data area of ​​the storage space of the first system.

3. The method according to claim 1, characterized in that, The response to the first interrupt triggered by the second processor reads command attribute parameters from the command area of ​​the storage region of the first system software in shared memory, including: The first interrupt triggered by the second processor through the target register group corresponding to the first system software is obtained, wherein the multiple system software in the second processor each has a corresponding register group, and the shared memory has multiple storage areas corresponding to the register group; Determine multiple storage regions corresponding to the target register group from the shared memory; In response to the first interrupt, the storage area of ​​the first system software is determined from multiple storage areas corresponding to the target register group according to the target interrupt bit of the first interrupt; The command attribute parameters are read from the command area of ​​the storage space of the first system software.

4. The method according to claim 3, characterized in that, The multiple system software deployed in the second processor are divided into security system software and non-security system software. Different system software in the security system software corresponds to the same register group, different system software in the non-security system software corresponds to the same register group, and security system software and non-security system software correspond to different register groups. Different system software in the security system software corresponds to different interrupt bits, and different system software in the non-security system software corresponds to different interrupt bits.

5. The method according to claim 1, characterized in that, The method further includes: During the process of sequentially executing the multiple command-corresponding operations on the peripheral device through the peripheral interface controller, if a command sent by the second system software of the second processor is received, wherein the second system software is any system software other than the first system software among the multiple system software; Return the occupancy information of the peripheral interface controller to the second processor.

6. The method according to claim 3, characterized in that, Before the peripheral interface controller sequentially executes corresponding command operations on the peripherals based on the plurality of commands, the method further includes: Based on the first interrupt triggered by the second processor, determine the request type of the first system software; If the request type of the first system software is a non-secure request, then the multiple commands are filtered to obtain multiple filtered commands. The step of sequentially executing corresponding command operations on peripherals through the peripheral interface controller based on the multiple commands includes: Based on the filtered commands, the peripheral device is sequentially executed with corresponding command operations through the peripheral interface controller.

7. The method according to claim 6, characterized in that, The filtering process for the multiple commands to obtain filtered commands includes: The target configuration command for peripheral capacity setting among the multiple commands is filtered to obtain the filtered multiple commands; Send a security error message to the second processor regarding the target configuration command.

8. The method according to claim 6, characterized in that, The filtering process for the multiple commands to obtain filtered commands includes: Determine the data command among the plurality of commands; Based on the starting address and the amount of data processed by the data command, determine whether the operation on the data command involves the security zone of the peripheral device; If the security zone of the peripheral device is involved, the data commands are filtered to obtain multiple filtered commands; Send a security error message for the data command to the second processor.

9. The method according to claim 1, characterized in that, The step of sequentially executing corresponding command operations on peripherals through the peripheral interface controller based on the multiple commands includes: Write the registers in the peripheral interface controller based on the configuration command among the multiple commands; Based on the data command among the multiple commands, the registers in the peripheral interface controller are configured, and data operations are performed on the peripheral through the peripheral interface controller.

10. The method according to claim 9, characterized in that, The configuration of registers in the peripheral interface controller based on the data command among the plurality of commands, and the data operation on the peripheral through the peripheral interface controller, includes: If the data command is a read data command, the registers in the peripheral interface controller are configured based on the read data command, and the peripheral is read from the peripheral through the peripheral interface controller.

11. The method according to claim 9, characterized in that, The configuration of registers in the peripheral interface controller based on data commands from the plurality of commands, and the performance of data operations on the peripheral through the peripheral interface controller, includes: If the data command is a target data command, the registers in the peripheral interface controller are configured according to the target data command, wherein the target data command is a write data command or an erase data command; The target data command is sent to the peripheral interface controller so that the peripheral can be operated on by the peripheral interface controller, wherein the target data operation is a write data operation or an erase data operation; In response to a second interrupt triggered by the peripheral interface controller, the next command of the target data command among the plurality of commands is processed.

12. A peripheral control system, characterized in that, include: First processor, second processor, and peripheral interface controller; The second processor and the first processor are connected in communication, and the first processor and the peripheral interface controller are connected in communication. The first processor is used to execute the command control method according to any one of claims 1-11.

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