Implementing amp and smp configurable bus architecture and method, device

Abstract

The application discloses a bus architecture and method and device realizing AMP and SMP configuration, relates to the technical field of vehicle-mounted chips, and the architecture comprises a plurality of processing components, a global coherent bus and a storage controller. The processing component comprises a processor cluster and a local coherent bus, a plurality of processor cores are arranged in the processor cluster, and the local coherent buses of the processing components are connected with the global coherent bus. The global coherent bus is used for connecting the storage controller to access external storage and for maintaining cache consistency between the processor clusters. A consistency control unit is arranged between the local coherent bus of each processing component and the global coherent bus, the consistency control unit is internally provided with consistency control logic, and the consistency control logic is used for realizing AMP mode or SMP mode configuration. The application can realize no hardware consistency between AMP systems to ensure the isolation of different OS and the management of hardware consistency between SMP systems.

Description

Technical Field

[0001] This application relates to the field of automotive chip technology, specifically to a method and device for implementing configurable bus architectures of AMP and SMP. Background Technology

[0002] Currently, all CPU cores in automotive chips target three domains: cluster (instrument cluster), IVI (in-vehicle infotainment system), and ADAS (advanced driver assistance system). They run three different operating systems according to AMP (Asymmetric Multiprocessing), or run the functions of the three domains under a single OS Hypervisor.

[0003] However, an automotive chip can either be implemented using AMP, which would make it impossible to achieve data consistency between multiple CPU clusters if SMP (Symmetric MultiProcessing) is to be run; or it can be implemented using SMP, which would result in poor isolation between CPU clusters of different operating systems if AMP is to be run. Summary of the Invention

[0004] This application provides a configurable bus architecture, method, and device for implementing AMP and SMP, which can achieve hardware consistency between AMP systems to ensure a certain degree of isolation between different OSes and hardware consistency management between SMP systems.

[0005] In a first aspect, embodiments of this application provide a configurable bus architecture for implementing AMP and SMP, wherein the configurable bus architecture for implementing AMP and SMP includes multiple sets of processing components, a global consistency bus, and a storage controller; The processing components include a processor cluster and a local consistency bus, and the processor cluster is configured with multiple processor cores, and the local consistency bus of each processing component is connected to the global consistency bus. The global consistency bus is used to connect the storage controller to access external storage and to maintain cache consistency between processor clusters. Each processing component has a consistency control unit between its local consistency bus and global consistency bus. The consistency control unit has built-in consistency control logic to implement AMP mode or SMP mode configuration.

[0006] In conjunction with the first aspect, in one implementation, in each processing component, the processor cluster is connected to a local consistency bus via CHI, and the local consistency bus is connected to a global consistency bus via CHI.

[0007] In conjunction with the first aspect, in one implementation, the processor cores within the processor cluster operate in SMP mode.

[0008] In conjunction with the first aspect, in one implementation, each processor cluster corresponds to a local consistency bus, which has a built-in snoop filter for achieving cache consistency between processor cores within the processor cluster.

[0009] In conjunction with the first aspect, in one implementation, the global consistency bus has a built-in snooping filter for maintaining cache consistency among processor clusters and supports configurable number of DVM nodes.

[0010] Secondly, embodiments of this application provide a method for implementing configurable AMP and SMP, based on the bus architecture described above. The method for implementing configurable AMP and SMP includes: After the consistency control unit is powered on, the operating system configuration table built into the consistency control unit is configured. The operating system configuration table is used to record the OS running on the processor cluster corresponding to each local consistency bus. Based on the operating system configuration table, the consistency control unit analyzes and determines the working mode between each local consistency bus and the global consistency bus; The working modes between the local consistency bus and the global consistency bus include consistency mode and non-consistency mode.

[0011] In conjunction with the second aspect, in one implementation, the consistency mode specifically refers to: Snoopable read, snoopable write, and DVM requests issued by the local consistency bus are directly passed through to the global consistency bus. The local consistency bus and the global consistency bus directly connect via the consistency handshake protocols syscoreq and syscoack in the AMBA standard CHI protocol. Snoop requests issued by the global consistency bus are directly passed through to the local consistency bus.

[0012] In conjunction with the second aspect, in one implementation, the inconsistency mode specifically refers to: Snoopable read and snoopable write requests issued by the local consistency bus are converted into nonsnoopable read and non snoopable write requests and then sent to the global consistency bus. At the same time, the relevant responses of the global consistency bus are processed to conform to the CHI protocol. The DVM request issued by the local consistency bus is directly responded to with a response conforming to the CHI protocol, and is not sent to the global consistency bus. The syscoreq output loopback of the local coherence bus drives the syscoack input, while the syscoreq of the global coherence bus is set to zero. The built-in snooping filter of the global consistency bus does not record the cache within the local consistency bus or the local cache state within the corresponding processor cluster. At the same time, the global consistency bus does not broadcast the DVM request to the corresponding local consistency bus after receiving it according to the CHI protocol.

[0013] In conjunction with the second aspect, in one implementation, the method for making AMP and SMP configurable further includes: According to the operating system configuration table, configure the DVM node to which each CHI interface belongs in the global consistency bus. The DVM node only broadcasts on the CHI interface that shares the same DVM node, and different DVM nodes do not broadcast to each other.

[0014] Thirdly, embodiments of this application provide a device for implementing AMP and SMP configurability. The device for implementing AMP and SMP configurability includes a processor, a memory, and a program for implementing AMP and SMP configurability stored in the memory and executable by the processor. When the program for implementing AMP and SMP configurability is executed by the processor, it implements the steps of the method for implementing AMP and SMP configurability described above.

[0015] The beneficial effects of the technical solutions provided in this application include: By adopting a bus architecture that includes multiple processing components, a global consistency bus, and a storage controller, the processing components include processor clusters and local consistency buses. Each processor cluster is configured with multiple processor cores, and the local consistency bus of each processing component is connected to the global consistency bus. The global consistency bus is used to connect the storage controller to access external storage and to maintain cache consistency between processor clusters. Each processing component has a consistency control unit between its local consistency bus and the global consistency bus. The consistency control unit has built-in consistency control logic to implement AMP mode or SMP mode configuration. This allows a single chip to manage the consistency state of each processor cluster when implementing AMP or SMP, thereby optimizing system performance. Attached Figure Description

[0016] Figure 1This is a schematic diagram illustrating the structure of the configurable bus architecture for AMP and SMP implemented in this application. Figure 2 A flowchart illustrating the method for implementing configurable AMP and SMP in this application; Figure 3 This is a schematic diagram of the hardware structure of the device that implements AMP and SMP configurability in this application. Detailed Implementation

[0017] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0019] In the first aspect, embodiments of this application provide a configurable bus architecture for AMP and SMP, so that on the same chip, the bootloader configures the coherency mode of different processor clusters according to the requirements of AMP / SMP, controls the transaction behavior on CHI (Coherent Hub Interface), and achieves hardware consistency between AMP systems to ensure a certain degree of isolation between different OSs and hardware consistency management between SMP systems.

[0020] In one embodiment, reference is made to Figure 1 , Figure 1 This is a schematic diagram illustrating the structure of the configurable bus architecture for AMP and SMP implemented in this application. Figure 1 As shown, the configurable bus architecture for AMP and SMP includes: multiple processing components, a globally consistent bus, and a storage controller.

[0021] The processing components include a processor cluster and a local consistency bus. The processor cluster is configured with multiple processor cores, and the local consistency bus of each processing component is connected to the global consistency bus. The global consistency bus is used to connect the storage controller to access external storage and to maintain cache consistency among processor clusters. Each processing component has a consistency control unit between its local consistency bus and the global consistency bus. The consistency control unit has built-in consistency control logic to implement AMP mode or SMP mode configuration.

[0022] In each processing component, the processor cluster is connected to the local consistency bus via CHI, and the local consistency bus is connected to the global consistency bus via CHI. The processor cores within the processor cluster operate in SMP mode; each processor cluster corresponds to a local consistency bus, which has a built-in listener filter to ensure cache consistency between processor cores within the processor cluster; the global consistency bus has a built-in listener filter to maintain cache consistency between processor clusters and supports configurable DVM (Distributed Virtual Memory) nodes.

[0023] The following combination Figure 1 The configurable bus architecture for implementing AMP and SMP in this application is described in detail.

[0024] In one possible implementation, the bus architecture of this application includes a total of four processor clusters, each of which can be configured with multiple processor cores. The processor clusters are connected to a local coherency fabric via a CHI (Content-Based Hierarchy) interface. The local coherency fabrics of the four processor clusters are then connected to a global coherency fabric via the CHI. A coherency control unit is located between the local and global coherency fabrics. This coherency control unit has built-in coherency control logic to implement AMP or SMP mode configurations. The global coherency fabric connects to a memory controller to access external memory and is responsible for maintaining cache coherency among the processor clusters. The processor clusters, local coherency fabric, and global coherency fabric use the standard CHI interface.

[0025] Specifically, each processor cluster can deploy multiple processor cores, which operate in SMP mode. All processor cores within a single processor cluster are connected to a local coherence bus.

[0026] Each processor cluster corresponds to a local consistency bus, which has a built-in snoop filter responsible for maintaining cache consistency among processor cores within the corresponding cluster. All local consistency buses are connected to the global consistency bus through a consistency control unit.

[0027] Secondly, embodiments of this application also provide a method for implementing configurable AMP and SMP modes, based on the bus architecture described above. This bus architecture includes multiple processing components, a global consistency bus, and a storage controller. Each processing component includes a processor cluster and a local consistency bus, with multiple processor cores configured within the processor cluster. The local consistency bus of each processing component is connected to the global consistency bus. The global consistency bus is used to connect the storage controller to access external storage and to maintain cache consistency between processor clusters. Each processing component's local consistency bus and the global consistency bus are connected by a consistency control unit, which incorporates consistency control logic to implement AMP or SMP mode configuration.

[0028] In each processing component, the processor cluster is connected to the local consistency bus via CHI, and the local consistency bus is connected to the global consistency bus via CHI. The processor cores within the processor cluster operate in SMP mode. Each processor cluster corresponds to a local consistency bus, which has a built-in listener filter to ensure cache consistency between processor cores within the cluster. The global consistency bus has a built-in listener filter to maintain cache consistency between processor clusters and supports configurable DVM node count.

[0029] In one embodiment, reference is made to Figure 2 , Figure 2 This is a flowchart illustrating the method for implementing configurable AMP and SMP in this application. Figure 2 As shown, the methods for implementing configurability in AMP and SMP include: S1: After the consensus control unit is powered on, configure the operating system configuration table built into the consensus control unit. The operating system configuration table is used to record the OS running on the processor cluster corresponding to each local consensus bus. Specifically, each coherence control unit has a built-in operating system configuration table, which is configured by other boot CPUs (boot cores) that are not on the coherencyfabric (coherence bus) after power-on. The contents of the operating system configuration table are the OS running on the processor cluster corresponding to each local coherence bus. Taking four processor clusters as an example, the OS combination running on a single processor cluster can be shown in Table 1 below. Table 1. OS Combinations Running on the Processor Cluster

[0030] In Table 1, the different numbers after OS represent different operating systems; S2: Based on the operating system configuration table, the consistency control unit analyzes and determines the working mode between each local consistency bus and the global consistency bus; among which, the working mode between the local consistency bus and the global consistency bus includes consistency mode and non-consistency mode.

[0031] Furthermore, in one embodiment, the consistency mode is specifically as follows: Snoopable read, snoopable write, and DVM requests issued by the local consistency bus are directly passed through to the global consistency bus. The local consistency bus and the global consistency bus directly connect via the consistency handshake protocols syscoreq and syscoack in the AMBA (Advanced Microcontroller Bus Architecture) standard CHI protocol, which are high sequentially after power-on; among them, syscoreq and syscoack are used to allow requesting nodes to join or leave the global cache consistency domain. Snoop requests issued by the global consistency bus are directly passed through to the local consistency bus. These snoop requests include DVM snoop (distributed virtual memory snoop).

[0032] Furthermore, in one embodiment, the non-consistent mode specifically refers to: Snoopable read and snoopable write requests issued by the local consistency bus are converted into nonsnoopable read and nonsnoopable write requests and then sent to the global consistency bus. At the same time, the relevant responses of the global consistency bus are processed to conform to the CHI protocol. The DVM request issued by the local consistency bus is directly responded to with a response conforming to the CHI protocol, and is not sent to the global consistency bus. The syscoreq output loopback of the local consistency bus drives the syscoack input, while the syscoreq of the global consistency bus is set to zero. The built-in listening filter of the global consistency bus does not record the cache within the local consistency bus or the local cache state within the processor cluster corresponding to the local consistency bus. At the same time, the global consistency bus does not broadcast the DVM request to the corresponding local consistency bus after receiving it according to the CHI protocol.

[0033] See Table 2 below for an example of the adaptive matching working mode of the consistency control unit based on the operating system configuration table.

[0034] Table 2. Working Mode of Adaptive Matching of Consistency Control Unit

[0035] In Table 2, A represents the consistent mode and B represents the inconsistent mode.

[0036] Furthermore, in one embodiment, the method for implementing AMP and SMP configurability according to this application further includes: According to the operating system configuration table, the operating system needs to configure the DVM node to which each CHI interface belongs in the global consistency bus. The DVM node only broadcasts on the CHI interface of the same DVM node, and different DVM nodes do not broadcast to each other, thereby achieving DVM isolation between AMP systems.

[0037] Thirdly, embodiments of this application provide a device that enables AMP and SMP configuration. The device that enables AMP and SMP configuration can be a personal computer (PC), a laptop computer, a server, or other device with data processing capabilities.

[0038] Reference Figure 3 , Figure 3 This is a schematic diagram of the hardware structure of a device that implements AMP and SMP configurability according to an embodiment of this application. In this embodiment, the device implementing AMP and SMP configurability may include a processor, memory, a communication interface, and a communication bus.

[0039] The communication bus can be of any type and is used to interconnect the processor, memory, and communication interface.

[0040] Communication interfaces include input / output (I / O) interfaces, physical interfaces, and logical interfaces used to implement device interconnection within AMP and SMP configurable devices, as well as interfaces used to implement interconnection between AMP and SMP configurable devices and other devices (such as other computing devices or user equipment). Physical interfaces can be Ethernet interfaces, fiber optic interfaces, ATM interfaces, etc.; user equipment can be displays, keyboards, etc.

[0041] Memory can be various types of storage media, such as random access memory (RAM), read-only memory (ROM), non-volatile RAM (NVRAM), flash memory, optical storage, hard disk, programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), etc.

[0042] The processor can be a general-purpose processor, which can call programs stored in memory that implement AMP and SMP configurability, and execute the methods for implementing AMP and SMP configurability provided in the embodiments of this application. For example, the general-purpose processor can be a central processing unit (CPU). The methods executed when the programs implementing AMP and SMP configurability are called can be referred to the various embodiments of the methods for implementing AMP and SMP configurability in this application, and will not be repeated here.

[0043] Those skilled in the art will understand that Figure 3 The hardware structure shown does not constitute a limitation of this application and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0044] The terms "comprising" and "having," and any variations thereof, in the specification, claims, and accompanying drawings of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such process, method, product, or apparatus. The terms "first," "second," and "third," etc., are used to distinguish different objects, etc., and do not indicate a sequence, nor do they limit "first," "second," and "third" to different types.

[0045] In the description of the embodiments of this application, terms such as "exemplary," "for example," or "for instance" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplary," "for example," or "for instance" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary," "for example," or "for instance" is intended to present the relevant concepts in a concrete manner.

[0046] In the description of the embodiments of this application, unless otherwise stated, " / " means "or". For example, A / B can mean A or B. The "and / or" in the text is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. In addition, in the description of the embodiments of this application, "multiple" means two or more.

[0047] In some processes described in the embodiments of this application, multiple operations or steps are included in a specific order. However, it should be understood that these operations or steps may not be executed in the order they appear in the embodiments of this application, or they may be executed in parallel. The sequence number of the operation is only used to distinguish different operations, and the sequence number itself does not represent any execution order. In addition, these processes may include more or fewer operations, and these operations or steps may be executed sequentially or in parallel, and these operations or steps may be combined.

[0048] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes several instructions to cause a terminal device to execute the methods described in the various embodiments of this application.

[0049] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A configurable bus architecture for implementing AMP and SMP, characterized in that, The configurable bus architecture for implementing AMP and SMP includes multiple processing components, a global consistency bus, and a storage controller; The processing components include a processor cluster and a local consistency bus, and the processor cluster is configured with multiple processor cores, and the local consistency bus of each processing component is connected to the global consistency bus. The global consistency bus is used to connect the storage controller to access external storage and to maintain cache consistency between processor clusters. Each processing component has a consistency control unit between its local consistency bus and global consistency bus. The consistency control unit has built-in consistency control logic to implement AMP mode or SMP mode configuration. The consistency control logic switches the working mode between the local consistency bus and the global consistency bus to a consistent mode or a non-consistent mode based on the operating system configuration table built into the consistency control unit. Switching to the consistent mode corresponds to the SMP mode, and switching to the non-consistent mode corresponds to the AMP mode.

2. The configurable bus architecture for implementing AMP and SMP as described in claim 1, characterized in that: In each processing component, the processor cluster is connected to the local consistency bus via CHI, and the local consistency bus is connected to the global consistency bus via CHI.

3. The configurable bus architecture for implementing AMP and SMP as described in claim 1, characterized in that: The processor cores within the processor cluster operate in SMP mode.

4. The configurable bus architecture for implementing AMP and SMP as described in claim 1, characterized in that: Each processor cluster corresponds to a local consistency bus, which has a built-in snoop filter to achieve cache consistency between processor cores within the processor cluster.

5. A configurable bus architecture for implementing AMP and SMP as described in claim 1, characterized in that: The global consistency bus has a built-in snoop filter to maintain cache consistency between processor clusters and supports configurable DVM node numbers.

6. A method for implementing configurable AMP and SMP, based on the bus architecture described in any one of claims 1 to 5, characterized in that, The methods for making AMP and SMP configurable include: After the consistency control unit is powered on, the operating system configuration table built into the consistency control unit is configured. The operating system configuration table is used to record the OS running on the processor cluster corresponding to each local consistency bus. Based on the operating system configuration table, the consistency control unit analyzes and determines the working mode between each local consistency bus and the global consistency bus; The working modes between the local consistency bus and the global consistency bus include consistency mode and non-consistency mode.

7. A method for implementing configurable AMP and SMP as described in claim 6, characterized in that, The consistency mode is specifically as follows: Snoopable read, snoopable write, and DVM requests issued by the local consistency bus are directly passed through to the global consistency bus. The local consistency bus and the global consistency bus directly connect via the consistency handshake protocols syscoreq and syscoack in the AMBA standard CHI protocol. Snoop requests issued by the global consistency bus are directly passed through to the local consistency bus.

8. A method for implementing configurable AMP and SMP as described in claim 6, characterized in that, The inconsistency mode specifically refers to: Snoopable read and snoopable write requests issued by the local consistency bus are converted into non-snoopable read and non-snoopable write requests and then sent to the global consistency bus. At the same time, the relevant responses of the global consistency bus are processed to conform to the CHI protocol. The DVM request issued by the local consistency bus is directly responded to with a response conforming to the CHI protocol, and is not sent to the global consistency bus. The syscoreq output loopback of the local coherence bus drives the syscoack input, while the syscoreq of the global coherence bus is set to zero. The built-in snooping filter of the global consistency bus does not record the cache within the local consistency bus or the local cache state within the corresponding processor cluster. At the same time, the global consistency bus does not broadcast the DVM request to the corresponding local consistency bus after receiving it according to the CHI protocol.

9. A method for implementing configurable AMP and SMP as described in claim 6, characterized in that, The method for making AMP and SMP configurable also includes: According to the operating system configuration table, configure the DVM node to which each CHI interface belongs in the global consistency bus. The DVM node only broadcasts on the CHI interface that shares the same DVM node, and different DVM nodes do not broadcast to each other.

10. A device that implements AMP and SMP configurability, characterized in that, The device for implementing AMP and SMP configurability includes a processor, a memory, and a program for implementing AMP and SMP configurability stored in the memory and executable by the processor, wherein when the program for implementing AMP and SMP configurability is executed by the processor, it implements the steps of the method for implementing AMP and SMP configurability as claimed in any one of claims 6 to 9.

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