An ATE test script generation method and system

Abstract

The application discloses an ATE test script generation method and system, and relates to the field of memory chip testing. The method comprises the following steps: obtaining an original test task queue for a memory chip; extracting stress parameters of each test item and inputting the parameters into a charge relaxation prediction model to output a reference relaxation time; dividing the test items into charge-sensitive and non-charge-sensitive test items; scheduling and sequencing each test item to obtain an initial execution sequence; determining whether the interval between the pre- and post-sequences of adjacent execution test items is less than the reference relaxation time and whether the post-sequenced test item is a charge-sensitive test item, and confirming the existence of a timing conflict; selecting a target non-charge-sensitive test item with an execution duration satisfying a preset condition and inserting the target non-charge-sensitive test item between the pre- and post-sequences of test items to generate an updated execution sequence and a target automatic test equipment script according to the updated execution sequence. The application solves the problems of false testing caused by incomplete charge release after high-stress testing of a memory chip and blind waiting which seriously slows down the testing efficiency.

Description

Technical Field

[0001] The present invention relates to the field of memory chip testing, and more specifically, relates to an ATE test script generation method and system. Background Art

[0002] Before delivery from the factory, memory chips need to undergo a variety of tests performed by automatic test equipment. The automatic test equipment applies voltage to the chip under test, sends instructions, writes data, and reads data according to the test script, and judges whether the chip is qualified based on the returned results. For NAND Flash, 3D NAND and other non-volatile memory chips, some tests act directly on memory cells, while other tests mainly act on peripheral logic, power pins or control registers.

[0003] The storage state of a memory chip is usually related to the charge state in the memory cell, as well as to the threshold voltage and the read window. After the chip undergoes high-voltage erasure, high-current programming or other high-stress operations, a short-term residual charge state may exist inside the memory cell. This state does not always disappear instantly, but may take a certain period of time to gradually release and stabilize. During this process, the threshold voltage of the memory cell may undergo transient drift, and the read window may also experience transient offset. For tests such as pin connectivity tests or register scans, such transient changes usually have little impact; but for read margin tests, threshold voltage distribution tests or error judgment tests, their impact may be directly reflected in the test results.

[0004] There are already technologies related to memory testing and memory cell threshold states in existing Chinese patents. For example, the patent with publication number CN108648780B discloses a test system including a host computer, a configuration memory, a memory under test, a main control FPGA and a verification FPGA. This system sends commands to the main control FPGA through the host computer to realize the selection, configuration and erasure operations of the memory under test, and is used to meet the test requirements of the configuration memory for long-term heat preservation in a low-temperature environment, so as to improve the test efficiency and accuracy under low-temperature test conditions. This patent also states that Flash memory cells exhibit threshold changes before and after programming, and the read current needs to be compared with the reference current during reading.

[0005] In addition, the patent with publication number CN112614531A discloses a reading method for a 3D memory device. According to the programming sequence of the memory cells, this method applies different bit line voltages to the memory cell strings during reading, so as to reduce the positive drift and broadening of the threshold voltage caused by the BPD effect, thereby increasing the read window margin and reducing the read disturb effect. This patent also states that the difference in threshold voltage between memory cells will reduce the read margin and may adversely affect the retention characteristics.

[0006] Therefore, it is evident that there is a close relationship between the accuracy of memory testing and the threshold state of the memory cells. Existing technologies have addressed the impact of the test environment, threshold voltage variations, and read margin on memory test or read results. However, during the script generation process of automated test equipment, test items are typically still arranged according to the engineer's preset functional order, test category, or equipment execution habits. Script generation systems focus more on whether test items are complete, whether the execution flow is coherent, and whether the test equipment can recognize the corresponding instructions, while giving less consideration to the short-term residual impact of the previous test item on the internal charge state of the memory chip, and also less consideration to whether the subsequent test item is easily affected by this residual state.

[0007] In actual mass production testing, if read tolerance testing, threshold voltage distribution testing, or bit error rate determination testing are performed immediately after high-voltage erasure, high-current programming, or high-stress testing, the internal charge state of the chip may not have yet stabilized. The results obtained at this time do not necessarily represent a true chip failure, but may be transient anomalies caused by improper timing of the test items. This can lead to a normally qualified chip being incorrectly identified as a failure, thus affecting yield statistics and production screening results.

[0008] One readily conceivable approach is to add a fixed waiting time after the high-stress test, allowing the charge inside the memory cell to gradually stabilize. However, automated testing equipment is expensive, and production line testing time directly impacts output per unit time. If the waiting time is set too short, false failures are still difficult to avoid; if the waiting time is set too long, the testing equipment will idle, reducing testing efficiency. Therefore, existing script generation methods cannot simultaneously ensure test accuracy and throughput, necessitating a test item scheduling method that considers the charge relaxation characteristics of the memory chip when generating test scripts. Summary of the Invention

[0009] The technical problem to be solved by the present invention is to provide an ATE test script generation method and system to solve the problems mentioned in the background art.

[0010] To achieve the above objectives, the present invention adopts the following technical solution:

[0011] A method for generating ATE test scripts includes the following steps:

[0012] Obtain the original test task queue for the memory chip, the original test task queue including multiple test items; extract the stress parameters of each test item, and input the stress parameters into a pre-trained charge relaxation prediction model, and output the reference relaxation time corresponding to each test item by the charge relaxation prediction model;

[0013] Each test item is divided into charge-sensitive test items and non-charge-sensitive test items; each test item in the original test task queue is scheduled and sorted to obtain an initial execution sequence; when it is determined that the time interval between the preceding test item and the following test item in the adjacent execution order in the initial execution sequence is less than the reference relaxation time corresponding to the preceding test item, and the following test item is a charge-sensitive test item, a timing conflict is confirmed.

[0014] When a timing conflict is confirmed, at least one target non-charge sensitive test item whose execution time meets the preset condition is selected from each of the non-charge sensitive test items, and the target non-charge sensitive test item is inserted between the preceding test item and the following test item to generate an update execution sequence;

[0015] The target automated test device script is generated using the update execution sequence.

[0016] Furthermore, the stress parameters include the applied voltage amplitude and the voltage application duration; the execution duration meeting the preset condition means that the sum of the individual execution durations of all selected target non-charge-sensitive test items is greater than or equal to the reference relaxation time corresponding to the preceding test item.

[0017] Furthermore, the training process of the charge relaxation prediction model includes:

[0018] Acquire the actual charge release evolution data of the historical memory chip under different applied voltage amplitudes and different voltage application durations, and extract the time value corresponding to the decay of the actual charge release evolution data to a steady state as the true relaxation time label;

[0019] The obtained applied voltage amplitude and the voltage application duration are combined as training input samples;

[0020] The initial prediction model is trained under supervision using the training input samples and the actual relaxation time labels. The model weights are updated by minimizing the error between the predicted relaxation time output by the initial prediction model and the actual relaxation time labels, thus obtaining the trained charge relaxation prediction model.

[0021] Furthermore, the step of inserting the target non-charge-sensitive test item between the preceding test item and the following test item includes:

[0022] Extract the individual execution time of each of the candidate non-charge-sensitive test items;

[0023] Multiple non-charge-sensitive test items are selected sequentially according to a preset priority order, and their corresponding individual execution times are accumulated. When the total accumulated time reaches the reference relaxation time, the selected multiple non-charge-sensitive test items are used as the target non-charge-sensitive test items to generate a target combination.

[0024] Insert all target non-charge-sensitive test items within the target combination between the preceding test item and the following test item.

[0025] Furthermore, the process of classifying the aforementioned test items into charge-sensitive test items and non-charge-sensitive test items includes:

[0026] Extract the electrical pin operation attributes of each of the test items;

[0027] The test item whose electrical pin operation attribute is to read the threshold voltage of the memory cell in the memory chip is determined to be a charge-sensitive test item;

[0028] Peripheral logic test items whose electrical pin operation attributes are independent of the threshold voltage state of the memory cell and do not trigger the state flip of the memory cell are determined to be non-charge sensitive test items; the peripheral logic test items include any one or more of the following: pin connectivity test items, DC leakage current measurement test items, and basic control register scan test items.

[0029] Furthermore, during the generation of the updated execution sequence, the power consumption feature tags of all scheduled test items preceding the preceding test item in the initial execution sequence and the execution duration of each scheduled test item are extracted.

[0030] The power consumption feature label and the corresponding execution time are input into a pre-trained time-series thermodynamic mapping model, and the time-series thermodynamic mapping model outputs the virtual temperature index when the preceding test item is completed.

[0031] Extract the temperature and relaxation time acceleration mapping table configured in the pre-built scaling compensation model, match the scaling coefficient corresponding to the virtual temperature index in the temperature and relaxation time acceleration mapping table, and output the product of the baseline relaxation time and the scaling coefficient as the corrected relaxation time.

[0032] The modified relaxation time is used to replace the baseline relaxation time used in the step of confirming the existence of timing conflicts.

[0033] Furthermore, the training process of the time-series thermodynamic mapping model includes:

[0034] Acquire real thermal imaging evolution data of the test chip when executing a combination of test items with different power consumption feature labels, and extract the actual temperature value of each node where the scheduled test item has been executed as a temperature supervision label;

[0035] Input the corresponding power consumption feature tag combination and the corresponding execution time combination into the initial thermodynamic mapping model;

[0036] Extract the predicted temperature index output by the initial thermodynamic mapping model, calculate the error between the predicted temperature index and the temperature supervision label, update the model weights based on the error, and obtain the trained time-series thermodynamic mapping model.

[0037] Furthermore, when a timing conflict is confirmed, the total available time of all available non-charge-sensitive test items that have not yet been scheduled is calculated.

[0038] Compare the total available time with the baseline relaxation time corresponding to the preceding test item;

[0039] When the total available time is determined to be less than the baseline relaxation time, the preceding test item is split into multiple micro-stress slice test items, such that the slice relaxation time re-output by each micro-stress slice test item after being input into the charge relaxation prediction model is less than or equal to the single execution time of any available non-charge-sensitive test item.

[0040] Furthermore, after splitting the preceding test item into multiple micro-stress slice test items, all the micro-stress slice test items are distributed in the update execution sequence, and at least one available non-charge-sensitive test item is configured between any two adjacent micro-stress slice test items in the execution order.

[0041] The present invention also discloses an ATE test script generation system, including an acquisition module, a prediction module, a partitioning module, a detection module, a scheduling module and a generation module;

[0042] The acquisition module is used to acquire the original test task queue for the memory chip, the original test task queue including multiple test items;

[0043] The prediction module is used to extract the stress parameters of each of the test items, input the stress parameters into a pre-trained charge relaxation prediction model, and output the reference relaxation time corresponding to each of the test items by the charge relaxation prediction model.

[0044] The division module is used to divide each of the test items into charge-sensitive test items and non-charge-sensitive test items;

[0045] The detection module is used to schedule and sort each test item in the original test task queue to obtain an initial execution sequence. When it is determined that the time interval between the preceding test item and the following test item in the adjacent execution order in the initial execution sequence is less than the reference relaxation time corresponding to the preceding test item, and the following test item is a charge-sensitive test item, a timing conflict is confirmed.

[0046] The scheduling module is used to select at least one target non-charge sensitive test item whose execution time meets a preset condition from each of the non-charge sensitive test items when a timing conflict is confirmed, and insert the target non-charge sensitive test item between the preceding test item and the following test item to generate an update execution sequence.

[0047] The generation module is used to generate a target automated test device script using the update execution sequence.

[0048] The advantage of this invention over existing technologies lies in its ability to predict the corresponding reference relaxation time based on the stress parameters of the test items when generating the automatic test equipment script. Furthermore, it categorizes test items into charge-sensitive and non-charge-sensitive test items based on whether they are affected by residual charge states. When there is insufficient interval between a high-stress preceding test item and a charge-sensitive following test item in the initial execution sequence, the system can identify a timing conflict and insert a non-charge-sensitive test item with a sufficient execution duration between them. Consequently, subsequent read tolerance tests, threshold voltage-related tests, or bit error rate determination tests can be performed after the charge state within the memory cell has stabilized, thereby reducing false failures caused by residual charge, charge release processes, and threshold voltage transient drift.

[0049] This invention does not simply increase idle time; instead, it fills the charge relaxation window with non-charge-sensitive test items that would otherwise need to be executed. Peripheral logic test items such as pin connectivity tests, DC leakage current measurements, and basic control register scans typically have electrical pin operation attributes that are independent of the memory cell threshold voltage state and do not trigger memory cell state transitions. Therefore, these test items can be executed during memory cell recovery, without significantly interfering with charge release after preceding high-stress tests, while still completing effective testing tasks. This reduces the pure idle time of automated test equipment, improves the utilization rate of the test process, and enhances test throughput while ensuring test accuracy.

[0050] This invention can also train a charge relaxation prediction model based on the applied voltage amplitude and duration, allowing different relaxation times to correspond to different intensities of erase, program, or stress tests. Since the charge release process of a memory cell is closely related to the intensity and duration of the preceding applied voltage, model prediction can avoid all test items sharing a fixed waiting value. For weaker stress test items, unnecessary buffer time can be reduced; for stronger stress test items, a more sufficient recovery window can be provided, thereby improving the targeting and accuracy of script scheduling.

[0051] This invention further incorporates a timing thermodynamic mapping model to correct the relaxation time. During continuous testing, memory chips accumulate heat, and temperature affects the charge release rate. By using the power consumption characteristic tags and execution duration of scheduled test items, the virtual temperature index at the completion of preceding test items can be estimated. Then, the baseline relaxation time is scaled and compensated based on the mapping relationship between temperature and relaxation time. This makes timing conflict judgments more consistent with the current testing environment, reducing excessive waiting or insufficient recovery caused by temperature differences.

[0052] This invention can also, when the total duration of remaining available non-charge-sensitive test items is insufficient, split the preceding high-stress test item into multiple micro-stress slice test items and distribute these slices in the updated execution sequence, ensuring that at least one available non-charge-sensitive test item is configured between adjacent micro-stress slices. This method utilizes the technical characteristic that the degree of charge perturbation is related to the duration of a single applied voltage, reducing the recovery requirements after each continuous stress operation, and enabling the limited number of non-charge-sensitive test items to cover multiple shorter relaxation windows. This further reduces pure waiting time and lowers the risk of misjudgment caused by immediately executing charge-sensitive tests after continuous high-stress operations. Attached Figure Description

[0053] Figure 1 This is a flowchart of the method of the present invention;

[0054] Figure 2 This is a comparison diagram of the temporal structure before and after the sequence scheduling of the present invention;

[0055] Figure 3 This is a training data flow graph of the prediction model of this invention;

[0056] Figure 4 This is the logic diagram for the combination of test items and the determination of time accumulation in this invention;

[0057] Figure 5 This is a diagram of the thermodynamic compensation and relaxation time correction architecture of the present invention;

[0058] Figure 6 This is a diagram showing the breakdown and alternating scheduling of micro-stress slice test items in this invention;

[0059] Figure 7 This is a diagram illustrating the relationship between the testing environment and physical hardware in this invention. Detailed Implementation

[0060] The specific embodiments of the present invention will now be described with reference to the accompanying drawings.

[0061] This invention provides an ATE test script generation method for rearranging the execution order of test items in a test script based on their impact on the charge state of memory cells during mass production testing or engineering verification testing of memory chips. This method is primarily applicable to non-volatile memory chips, especially those where data state is characterized by the charge state of memory cells and threshold voltage distribution, such as NAND Flash and 3D NAND. The automated test equipment can be a dedicated memory ATE or a general-purpose semiconductor test device with voltage application capability, signal measurement capability, digital channel control capability, test mode generation capability, and script interpretation capability, such as… Figure 7 As shown.

[0062] In one embodiment, the overall process of the ATE test script generation method is as follows: Figure 1 As shown.

[0063] The script generation device first obtains the raw test task queue for the memory chip. This raw test task queue can be configured by the test engineer in the host computer software, or it can be imported from an existing test program template. For mass production testing scenarios, the raw test task queue can also come from a test plan file. For engineering verification scenarios, the raw test task queue can also come from a chip verification database.

[0064] The original test task queue includes multiple test items. Test items can be stress tests applied to the memory array, read tests, or peripheral logic tests. For example, test items can be erase stress tests or programming stress tests. Test items can also be read tolerance tests, threshold voltage distribution scan tests, or bit error rate determination tests. For scenarios where the threshold voltage of the memory cells is not directly read, test items can also be pin connectivity tests, DC leakage current measurement tests, or basic control register scan tests. In the chip industry, stress testing can be electrical stress, thermal stress, read-write cycle stress, holding stress, etc. For example: applying a higher programming voltage, causing the memory cell to experience a stronger electric field than a normal read, can be called voltage stress or programming stress. Continuously performing a large number of erase or programming operations, causing the memory cell to experience repeated charge injection and release, can be called cycle stress. Performing holding tests or accelerated aging tests at higher temperatures can be called thermal stress or temperature stress.

[0065] Each test item can carry basic information for identification, such as test identifier, test category, and target address range. Each test item can also carry execution information for generating the ATE script. For example, a test item can carry the voltage application method or the sequence of instructions to be expanded. Test items can also carry the estimated execution time. To support subsequent thermal compensation processing, each test item can also carry a power consumption characteristic tag. To complete result judgment after script execution, each test item can also carry result judgment rules. In this way, the script generation device can not only identify the functional purpose of each test item but also obtain information about its impact on charge state and test timing.

[0066] After obtaining the original test task queue, the script generation device extracts the stress parameters for each test item. The stress parameters include at least the applied voltage amplitude and the voltage application duration. The applied voltage amplitude can be the voltage applied to a word line, or the voltage applied to a bit line or source line. For some memory chips, the applied voltage amplitude can also correspond to the voltage at the well region, power pin, or other relevant nodes. The range of the applied voltage amplitude can be configured according to the chip process and test equipment capabilities, for example, from 0.5V to 25V.

[0067] The voltage application duration can be the duration of a single high-voltage pulse or a continuously programmed duration. For erase-type tests, the voltage application duration can be the erase hold time. For cyclic stress tests, the voltage application duration can be the cumulative time of multiple stress cycles. The voltage application duration can range from 1 μs to 100 s.

[0068] When a test item contains multiple voltage stages, the stage with the greatest impact on the charge state of the memory cell can be extracted as the stress parameter. For a more precise reflection of the test item's influence on the memory cell, the multiple voltage stages can be converted into separate model input features, allowing the model to consider multiple stress processes simultaneously. This approach avoids estimating relaxation time solely based on the test item name, ensuring that subsequent prediction processes reflect the specific voltage intensity and duration differences.

[0069] After extracting the stress parameters, the script generation device inputs these parameters into a pre-trained charge relaxation prediction model. The charge relaxation prediction model outputs the reference relaxation time for each test item. Here, the reference relaxation time refers to the time required for the residual charge state inside the memory cell to gradually release and for the threshold voltage to drift into a relatively stable range after a given voltage amplitude and duration. This time is not a fixed waiting value, but a predicted result that varies with the test stress intensity. The reference relaxation time for strong erase tests, strong programming tests, or long-term high-voltage hold tests is typically longer. For low-voltage tests, short-time tests, or test items involving only peripheral logic, the corresponding reference relaxation time can be shorter, or even configured to be 0.

[0070] The charge relaxation prediction model can be implemented using a regression prediction model. In one embodiment, the charge relaxation prediction model employs a multilayer perceptron. This model has a simple structure and is easy to deploy on an ATE host computer or test program compilation server. In another embodiment, the charge relaxation prediction model can also employ a tree model or a temporal neural network. Tree models can be used for scenarios with small sample sizes and low feature dimensions. Temporal neural networks can be used for scenarios that require input of multiple pulse stress histories.

[0071] Taking a multilayer perceptron as an example, the model input layer receives two main features: the applied voltage amplitude and the voltage application duration. Depending on the testing requirements, the input layer can also receive auxiliary features. These auxiliary features can describe voltage polarity or the number of pulses. For memory chips undergoing partitioned testing, auxiliary features can also describe the memory array region identifiers. Hidden layers can be set to 2 to 5 layers, with 16 to 256 neurons per layer. The activation function can be ReLU or GELU. The output layer outputs a non-negative time value, which is the reference relaxation time. The unit of the reference relaxation time can be μs, ms, or s, and should be consistent with the time unit in the ATE script.

[0072] The training data stream of the charge relaxation prediction model is as follows Figure 3 As shown. During training, the actual charge release evolution data of the historical memory chip under different applied voltage amplitudes and durations are first acquired. The actual charge release evolution data can be obtained through threshold voltage distribution scanning. If the test platform does not support a complete threshold distribution scan, approximate data can be obtained through read window boundary scanning. For some chips, actual charge release evolution data can also be constructed using cell current sampling results, bit error rate versus time curves, or equivalent charge release curves.

[0073] The data acquisition process can involve repeatedly reading the threshold voltage distribution or bit error rate of the target memory cell at fixed sampling intervals after performing a high-voltage erase test, programming test, or stress test, forming a data sequence that changes over time. Subsequently, the time value corresponding to the decay to a steady state is extracted from the actual charge release evolution data as the true relaxation time label.

[0074] Actual charge release evolution data does not necessarily require direct measurement of the internal charge of the memory cell; instead, it can be obtained indirectly through external measurable parameters related to the charge state of the memory cell. In one embodiment, a preset charge perturbation operation is first performed on the sample memory chip. This charge perturbation operation can be a high-voltage erase operation, a programming pulse operation, or a continuous read / write cycle operation. After the charge perturbation operation is completed, monitoring and reading are performed on the same target memory region at multiple sampling time points. Monitoring and reading can employ a threshold voltage distribution scanning method, i.e., by changing the reading reference voltage and statistically analyzing the reading results under different reference voltages, the threshold voltage distribution of the target memory region is obtained. Monitoring and reading can also employ a read window boundary scanning method, i.e., reading the target memory region under several candidate reading reference voltages and determining the read window boundary that meets the bit error rate requirement. Monitoring and reading can also employ a bit error rate sampling method under a fixed reference voltage, i.e., repeatedly reading a preset data pattern under the same reading conditions and recording the change in bit error rate over time. The threshold voltage distribution, read window boundary, or bit error rate sequence obtained at each sampling time point forms the actual charge release evolution data. It should be noted that the monitoring and reading methods used in the training phase, such as threshold voltage distribution scanning, read window boundary scanning, or bit error rate sampling, do not contradict the purpose of this invention to avoid premature execution of charge-sensitive test items in the mass production test script. On the contrary, it is precisely because these monitoring and reading methods are sensitive to the charge state of the memory cells that they can reflect changes in threshold voltage, read window, or bit error rate performance during residual charge release, thereby constructing actual charge release evolution data. The monitoring and reading in the training phase is an observation method, the purpose of which is to obtain sample data of charge state changes over time, and is not used to determine whether the chip under test is qualified. The charge-sensitive test items in the mass production test script are formal judgment tests, the purpose of which is to evaluate the chip's read tolerance, threshold voltage distribution, or bit error rate performance. If the formal judgment test is executed too early after the preceding charge disturbance test item, its result may be affected by the transient residual charge caused by the preceding test item, thus producing false failures. Therefore, this invention does not exclude charge-sensitive test items, but rather arranges a more appropriate execution sequence for charge-sensitive test items in the actual testing phase.

[0075] The steady-state condition can be configured based on test engineering experience. For example, if the average threshold voltage changes by less than 1mV to 20mV over 3 to 10 consecutive samples, it can be considered to have entered a steady-state condition. Similarly, if the bit error rate changes by less than 0.01% to 1% over consecutive samples, it can also be considered to have entered a steady-state condition. This steady-state determination criterion is used to generate training labels and does not change the determination rules during ATE script execution.

[0076] Training samples consist of a combination of applied voltage amplitude and voltage application duration. During training, the training input samples are fed into the initial prediction model to obtain the predicted relaxation time. Then, the error between the predicted relaxation time and the true relaxation time label is calculated. The error can be expressed as mean squared error or mean absolute error. For training data with a small number of outliers, Huber error can also be used. Model weights are updated via backpropagation and an optimizer. The optimizer can be Adam. If computational resources need to be reduced, RMSProp or stochastic gradient descent can also be used. The number of training epochs can be 50 to 500, the batch size can be 16 to 512, and the learning rate can be 0.0001 to 0.01. After training, the model parameters are fixed into a charge relaxation prediction model and invoked during the script generation phase.

[0077] After obtaining the baseline relaxation time for each test item, the script generation device classifies the test items into charge-sensitive and non-charge-sensitive test items. This classification process is not merely based on test name; rather, it extracts the electrical pin operation attributes of each test item. These attributes describe whether the test item reads the memory cell threshold voltage and whether it depends on the read window boundary. They also reflect whether the test item triggers a memory cell state transition and whether it only affects peripheral logic or power pins.

[0078] When the electrical pin operation attribute of a test item is to read the threshold voltage of a memory cell within the memory chip, that test item is classified as a charge-sensitive test item. Read tolerance tests are typical charge-sensitive tests because their determination depends on the read window boundaries. Threshold voltage distribution tests are also charge-sensitive tests because they directly reflect the threshold state of the memory cell. Read window scan tests, bit error rate determination tests, and data retention characteristic read tests can also be classified as charge-sensitive tests. Performing these tests immediately after high-voltage stress may misjudge short-term threshold drift as actual failure.

[0079] When the electrical pin operation attribute of a test item is unrelated to the threshold voltage state of the memory cell and does not trigger a state transition of the memory cell, the test item is determined to be a non-charge-sensitive test item. Non-charge-sensitive test items can be peripheral logic test items. Pin connectivity test items are a typical type of peripheral logic test item, primarily determining whether the test channel and chip pins are open or short-circuited. DC leakage current measurement test items can also be used as peripheral logic test items, primarily measuring leakage current in power supply pins, input / output pins, or control pins. Basic control register scan test items can also be used as non-charge-sensitive test items, primarily verifying whether the register access link or basic control bit read / write is normal. These types of test items do not read the memory cell threshold voltage or change the data state of the memory array, therefore they are suitable for insertion into the charge recovery window for execution.

[0080] After classifying the test items, the script generation device schedules and sorts the test items in the original test task queue to obtain an initial execution sequence. The initial execution sequence can retain the engineer's original order or be sorted conventionally by test category. For scenarios requiring reduced device switchover time, sorting can also be performed based on address continuity, device resource usage, and channel switching frequency. This sorting stage is used to create an executable base version and is not directly output as the final script.

[0081] Subsequently, the script generation device checks whether there are timing conflicts between adjacent test items in the initial execution sequence, such as... Figure 2 As shown. Specifically, for preceding and subsequent test items in the initial execution sequence that are executed in adjacent order, the time interval between them is calculated. This time interval is the actual time elapsed between the end of the preceding test item's execution and the start of the subsequent test item's execution. It can include existing waiting time in the script, as well as configuration time required for ATE channel switching, range switching, power stabilization, and mode switching. If there is already a test action between them that does not read the memory cell threshold voltage and does not trigger a memory cell state transition, the execution time of that test action can also be included in this time interval.

[0082] If the time interval is less than the reference relaxation time corresponding to the preceding test item, and the following test item is a charge-sensitive test item, then a timing conflict is confirmed. This means that the preceding test item may have just caused a charge disturbance in the memory cell, while the following test item happens to be reading the threshold voltage or bit error state. In this case, the test results are easily contaminated by the transient charge release process. If thermal compensation is used, the aforementioned reference relaxation time can be replaced by a corrected relaxation time.

[0083] Upon confirming a timing conflict, the script generation device does not simply insert pure wait instructions. Instead, it selects at least one target non-charge-sensitive test item from the non-charge-sensitive test items whose execution duration meets a preset condition. This target non-charge-sensitive test item is then inserted between the preceding and following test items to generate an updated execution sequence. Meeting the preset execution duration condition means that the sum of the individual execution durations of all selected target non-charge-sensitive test items is greater than or equal to the baseline relaxation time corresponding to the preceding test item. In practice, the existing effective time interval between the preceding and following test items can also be included in the recovery window. If the existing time interval is included, the sum of the execution durations of the target non-charge-sensitive test items only needs to be supplemented to make up the difference between the baseline relaxation time and the existing time interval. This method avoids repeatedly adding unnecessary buffer time.

[0084] In one embodiment, the process of inserting a target non-charge-sensitive test item is as follows: Figure 4 As shown, the script generation device first extracts the individual execution duration of candidate non-charge-sensitive test items. Candidate non-charge-sensitive test items are preferentially selected from test items whose execution positions have not yet been fixed. If a non-charge-sensitive test item has already appeared in a later position in the original test task queue and has been selected as the target non-charge-sensitive test item, it needs to be removed from its original later position after being inserted between preceding and subsequent test items. This avoids the same test item being executed repeatedly in the target script.

[0085] The execution time of a single test item can be derived from test item metadata or obtained through historical execution records. For test items lacking historical records, the execution time of a single test item can also be estimated by the ATE compiler based on the number of instructions. If the test item includes sampling actions or wait cycles, the estimation process can also incorporate the number of samplings and wait cycles into the calculation. If there are channel configuration changes between test items, channel switching time can be further factored in.

[0086] Subsequently, multiple non-charge-sensitive test items are selected sequentially according to a preset priority order, and their corresponding individual execution times are accumulated. The preset priority order can be determined based on several factors. For example, priority may be given to whether the test item has already been executed near the current test phase. It may also be considered whether the test item occupies the same test resources or requires the same voltage range. For test platforms with high ATE resource switching overhead, test items with shorter switching overhead may be prioritized. In actual scheduling, test items with low switching overhead or those that cause minimal disruption to the overall test process may be prioritized. If a test item has high compatibility with preceding and following test resources, its scheduling priority can be increased.

[0087] When the accumulated total reaches the baseline relaxation time, the selected non-charge-sensitive test items are used as target non-charge-sensitive test items to generate a target combination. All target non-charge-sensitive test items within this target combination are then inserted between the preceding and following test items. If multiple candidate combinations can all reach the baseline relaxation time, the combination with the total execution time closest to the baseline relaxation time can be selected to avoid excessive insertion leading to an increase in overall test time. Alternatively, the combination with the fewest device switching operations can be selected to reduce ATE resource reconfiguration overhead.

[0088] For example, if the baseline relaxation time for a preceding erase stress test item is 12ms, and the immediately following test item is a threshold voltage distribution scan test item, with an original interval of 1ms between them, then there is a timing conflict. Among the candidate non-charge-sensitive test items, the pin connectivity test item has an execution time of 4ms. Another candidate test item is the DC leakage current measurement test item, with an execution time of 5ms. Yet another candidate test item is the basic control register scan test item, with an execution time of 3ms. The script generation device can combine these three test items and insert them between the preceding erase stress test item and the threshold voltage distribution scan test item, making the total duration of the inserted test items reach 12ms. In this way, the threshold voltage distribution scan is executed after the charge state of the memory cell tends to stabilize, and the peripheral logic test is also completed normally. If the scheduling logic also includes the original 1ms interval in the recovery window, then a combination of non-charge-sensitive test items with a total duration of not less than 11ms can be selected.

[0089] In a further embodiment, during the generation of the update execution sequence, the relaxation time can also be corrected by taking into account the thermal accumulation state of the chip during previous testing processes, such as... Figure 5 As shown. The charge release rate of memory chips is typically affected by temperature. Continuous high-power testing can cause the chip temperature to rise, and temperature changes may alter the residual charge release rate. To make conflict judgment more closely resemble actual test conditions, the script generation device extracts the power consumption feature tags of all scheduled test items preceding the preceding test item in the initial execution sequence, and extracts the execution duration of each scheduled test item.

[0090] Power consumption characteristic labels can be discrete. For example, test items can be labeled as low power, medium power, or high power. Power consumption characteristic labels can also be numerical, such as normalized power consumption levels between 0 and 1. Numerical labels can be calculated based on supply current, voltage level, or channel activity.

[0091] The script generation device inputs power consumption feature labels and corresponding execution durations into a pre-trained time-series thermodynamic mapping model. The model then outputs a virtual temperature index at the completion of the preceding test item. The virtual temperature index can be understood as the chip's thermal state estimated by the model. It does not need to be completely identical to the measured temperature on the chip surface, but it must have a stable mapping relationship with the charge relaxation rate. The virtual temperature index can be configured from 0 to 1, or it can be directly expressed in Celsius, such as 25°C to 125°C.

[0092] The temporal thermodynamic mapping model can be implemented using a neural network capable of handling temporal inputs. One embodiment employs a gated recurrent unit. The model input consists of power consumption feature labels arranged in execution order and a combination of execution durations. The hidden states represent the thermal accumulation states during the test process, and the output layer provides the virtual temperature index of the current node. In another embodiment, the temporal thermodynamic mapping model can employ a Long Short-Term Memory network or a Transformer encoder. To reduce deployment complexity, an exponentially decaying thermal model combined with a small regression network can be used, allowing the model to consider both the temperature rise caused by high-power testing and the heat dissipation during low-power or idle phases.

[0093] The training process of the time-series thermodynamic mapping model involves acquiring real thermal imaging evolution data of the test chip when executing combinations of test items with different power consumption characteristic labels, and extracting the actual temperature values ​​of each scheduled test item completion node as temperature supervision labels. Real thermal imaging evolution data can be acquired by an infrared thermal imager or by an on-chip temperature sensor. For scenarios where it is inconvenient to directly acquire the internal temperature of the chip, temperature data can be acquired using surface thermocouples or ATE environmental monitoring equipment.

[0094] During training, the corresponding power consumption feature labels and execution duration combinations are input into the initial thermodynamic mapping model to obtain the predicted temperature index. Subsequently, the error between the predicted temperature index and the temperature supervision label is calculated, and the model weights are updated based on this error. The error can be the mean squared error or the mean absolute error. The number of training epochs can be 50 to 300, the learning rate can be 0.0001 to 0.01, and the batch size can be 8 to 128. After training, a time-series thermodynamic mapping model is obtained for the script generation stage.

[0095] After obtaining the virtual temperature index, the script generation device extracts the temperature and relaxation time acceleration mapping table configured in the pre-built scaling compensation model. It matches the scaling factor corresponding to the virtual temperature index in this mapping table and outputs the product of the baseline relaxation time and the scaling factor as the corrected relaxation time. The scaling factor can be pre-calibrated based on chip process experiments, with a value range of 0.2 to 2.0. If higher temperatures accelerate charge release, the corresponding scaling factor can be less than 1. If, under certain process conditions, increased temperature leads to a longer transient drift, the corresponding scaling factor can be greater than 1. When determining whether there is a timing conflict, the script generation device replaces the baseline relaxation time with the corrected relaxation time. In this way, the scheduling result can simultaneously consider the stress of previous tests and the current thermal state, avoiding the use of the same fixed recovery window under high or low temperature conditions.

[0096] In another embodiment, when a timing conflict is confirmed, the script generation device also calculates the total available duration of all available non-charge-sensitive test items that have not yet been scheduled. Available non-charge-sensitive test items are those not yet scheduled in the update execution sequence, but which can still be moved to the vicinity of the current conflict location for execution, and whose movement will not disrupt other necessary test dependencies. The script generation device compares the total available duration with the baseline relaxation time corresponding to the preceding test item. If the total available duration is greater than or equal to the baseline relaxation time, the aforementioned method of inserting target combinations can still be used.

[0097] If the total available time is less than the baseline relaxation time, it indicates that the remaining peripheral logic test items are insufficient to cover the recovery window required after the preceding high-stress test. In this case, directly adding pure wait time would reduce ATE utilization. Therefore, this invention breaks down the preceding test items into multiple micro-stress slice test items, such as... Figure 6 As shown.

[0098] Micro-stress slice test items are shorter test segments derived from a continuous high-stress test item. Each micro-stress slice test item performs the same or similar test objectives, but with a shorter duration of a single applied voltage. Micro-stress slice test items can also be formed by reducing the address range covered in a single pass. For cyclic stress tests, micro-stress slice test items can also be formed by reducing the number of pulse cycles per pass. Due to the reduced duration of a single stress pass, the residual charge perturbation caused by each slice is also relatively reduced, resulting in a shorter slice relaxation time when re-output after inputting the charge relaxation prediction model.

[0099] During the segmentation process, the script generation device determines the slice size based on the individual execution time of available non-charge-sensitive test items. To ensure that each available non-charge-sensitive test item can cover the recovery requirements after a micro-stress slice, the shortest individual execution time among all available non-charge-sensitive test items can be determined first. Then, the stress parameters of the micro-stress slice test items are adjusted so that the slice relaxation time obtained after re-inputting each micro-stress slice test item into the charge relaxation prediction model is less than or equal to the shortest individual execution time. In this way, even if the available non-charge-sensitive test item with the shortest execution time is selected, a sufficient recovery window can be provided between adjacent micro-stress slices.

[0100] Granularity of the split can be achieved by reducing the duration of a single voltage application, or by reducing the number of pages or blocks in a single test. For tests performed on word lines, this can also be achieved by reducing the number of word lines covered in a single test. For programming or erase cycle tests, this can also be achieved by reducing the number of cycles per test. The total number of micro-stress slice test items after splitting should complete the test coverage and stress target of the original preceding test items to avoid omissions in the original test items due to splitting.

[0101] After splitting the preceding test items into multiple micro-stress slice test items, the script generation device distributes all micro-stress slice test items throughout the update execution sequence and controls the execution order of any two adjacent micro-stress slice test items to be configured with at least one available non-charge-sensitive test item. In this way, a long continuous stress process is transformed into multiple short stress processes, with peripheral logic test items interspersed between adjacent short stress processes. This approach reduces the residual charge accumulation caused by a single continuous stress event and utilizes a limited number of non-charge-sensitive test items to cover multiple shorter relaxation windows. After all micro-stress slice test items have been executed, the previously affected charge-sensitive test items are then executed, making the read results closer to the stable state of the memory cell.

[0102] After generating the update execution sequence, the script generation device can check again whether timing conflicts still exist in the update execution sequence. If new timing conflicts still exist, the insertion of non-charge-sensitive test items, thermal compensation correction, or micro-stress slice scheduling continues until there are no timing conflicts to be handled in the update execution sequence, or the preset number of scheduling iterations is reached. The number of scheduling iterations can be set from 2 to 20. The purpose of setting an upper limit on the number of iterations is to avoid the scheduling process from not ending due to too many test item dependencies in extreme task queues. If timing conflicts that cannot be eliminated still exist after reaching the upper limit of the number of iterations, a minimum necessary waiting time can be inserted at the corresponding position to ensure the testing accuracy of the final script.

[0103] After generating the final update execution sequence, the script generation device uses this sequence to generate the target automated test equipment script. The script generation process can begin by expanding the test item instructions, converting each test item into an instruction block that the ATE (Automatic Test Equipment) can recognize. Subsequently, the script generation device configures the ATE channels based on the package of the chip under test and the connection relationship with the test board, establishing a mapping between the test channels and the chip pins. After completing the basic hardware configuration, the script generation device calls the timing set matching the current test item and configures the voltage source and measurement unit required for the test. Then, the script generation device references the corresponding pattern file, binds the test result variables to the corresponding test items, and writes the result judgment conditions. This step-by-step generation method avoids writing the script generation process as a simple string of configuration names and facilitates understanding of the function of each configuration step for those skilled in the art.

[0104] For non-charge-sensitive test items inserted into the relaxation window, the script generation device converts them into instruction blocks recognizable by the ATE (Automatic Test Equipment) while maintaining their original decision logic. For split micro-stress slice test items, the script generation device divides the address range, loop count, or voltage duration of the original test item into multiple instruction blocks, ensuring that all slices collectively cover the test scope of the original test item. The final output target automated test equipment script can be a test program compileable and executable for common memory ATE platforms, or a test flow file for a specific vendor's ATE platform. As long as the script can control the test equipment to execute each test item according to the updated execution sequence, the scheduling objective of this invention can be achieved.

[0105] In one specific implementation scenario, the original test task queue includes five test items sequentially. The first test item is a high-voltage erase stress test item, and the second test item is a threshold voltage distribution scan test item. The following three test items are a pin connectivity test item, a DC leakage current measurement test item, and a basic control register scan test item, respectively. The script generation device extracts the applied voltage amplitude of the high-voltage erase stress test item as 18V and the voltage application duration as 8ms. The charge relaxation prediction model outputs the reference relaxation time corresponding to this high-voltage erase stress test item as 15ms. The threshold voltage distribution scan test item is classified as a charge-sensitive test item because it reads the threshold voltage of the memory cell. The following three peripheral logic test items are classified as non-charge-sensitive test items because they do not depend on the threshold voltage of the memory cell and do not trigger memory cell state transitions.

[0106] In the initial execution sequence, the high-voltage erase stress test item and the threshold voltage distribution scan test item are adjacent, with an interval of 0.5ms, which is less than 15ms, thus confirming a timing conflict. The script generation device selects three non-charge-sensitive test items with execution durations of 5ms, 6ms, and 4ms, respectively, and inserts them between the high-voltage erase stress test item and the threshold voltage distribution scan test item. After insertion, the three non-charge-sensitive test items originally located in subsequent positions are removed from their original positions to avoid duplicate execution. The threshold voltage distribution scan test item is executed after a 15ms effective recovery window, reducing the probability of misjudgment caused by threshold voltage transient drift.

[0107] In another specific implementation scenario, the preceding test item is a high-current programmed stress test item with a baseline relaxation time of 30ms, while the total duration of the currently unscheduled available non-charge-sensitive test items is only 12ms. The script generation device splits this high-current programmed stress test item into three micro-stress slice test items, with the voltage application duration of each slice being approximately 1 / 3 of the original. The split stress parameters are input into the charge relaxation prediction model, and the output slice relaxation times are all less than or equal to the shortest single execution time among the available non-charge-sensitive test items. Subsequently, the script generation device first executes the first micro-stress slice test item, then the pin connectivity test item; then the second micro-stress slice test item, then the DC leakage current measurement test item; then the third micro-stress slice test item, then the basic control register scan test item. After completing the alternating scheduling, the subsequent bit error rate determination test item is executed. This scheduling method does not require an additional 30ms pure waiting time and also avoids executing the bit error rate determination test immediately after continuous high stress.

[0108] This invention also provides an ATE test script generation system. The system includes an acquisition module, a prediction module, a partitioning module, a detection module, a scheduling module, and a generation module. The acquisition module acquires the original test task queue for the memory chip. The prediction module extracts the stress parameters of each test item and calls a pre-trained charge relaxation prediction model to output the baseline relaxation time corresponding to each test item. The partitioning module divides the test items into charge-sensitive test items and non-charge-sensitive test items based on their electrical pin operation attributes. The detection module schedules and sorts the test items in the original test task queue to obtain an initial execution sequence, and confirms a timing conflict when the time interval between adjacent preceding and following test items is insufficient and the following test item is a charge-sensitive test item. The scheduling module selects a target non-charge-sensitive test item whose execution duration meets the condition from the non-charge-sensitive test items when a timing conflict exists, and inserts it between the preceding and following test items to generate an updated execution sequence. The generation module generates a target automated test equipment script based on the updated execution sequence.

[0109] In a further embodiment, the prediction module may also include a model training submodule. The model training submodule is used to acquire actual charge release evolution data of historical memory chips under different voltage amplitudes and different voltage application durations, extract true relaxation time labels, combine the applied voltage amplitude and voltage application duration as training input samples, and use the training input samples and true relaxation time labels to perform supervised training on the initial prediction model.

[0110] The scheduling module may also include a combination selection submodule and a slice scheduling submodule. The combination selection submodule is used to accumulate the execution time of candidate non-charge-sensitive test items according to a preset priority and generate a target combination that meets the relaxation time requirements. The slice scheduling submodule is used to split the preceding test item into multiple micro-stress slice test items when the total available non-charge-sensitive test item time is insufficient, and to alternately distribute the micro-stress slice test items and available non-charge-sensitive test items into the update execution sequence.

[0111] In a further embodiment, the system may also include a thermal compensation module. The thermal compensation module extracts the power consumption characteristic tags and execution duration of the scheduled test items, calls the timing thermodynamic mapping model to output the virtual temperature index when the preceding test item is completed, obtains the scaling factor based on the temperature-relaxation time acceleration mapping table, and then uses the scaling factor to correct the baseline relaxation time. When the detection module performs timing conflict judgment, it prioritizes using the corrected relaxation time.

[0112] This structure allows the system to handle multiple influencing factors within a single script generation logic. On one hand, the system can adjust the recovery time based on stress intensity differences; on the other hand, it can select insertion objects based on test item sensitivity differences. For test procedures with thermal accumulation, the system can also adjust the relaxation time. Furthermore, when there are insufficient remaining non-sensitive test resources, the system can reduce the single recovery requirement through micro-stress slicing.

[0113] The modules described above can be deployed in the ATE host computer or in the test program compilation server. For engineering verification scenarios, the modules can also be deployed in the chip verification platform. For mass production scenarios, the modules can also be deployed in the production line test management system. Each module can be implemented by software programs or by hardware circuits in conjunction with software. For example, a processor can execute program instructions, and memory can store model parameters and test item configuration data. If higher data processing speed is required, an FPGA or dedicated acceleration unit can be introduced. The communication interface is used to transmit test tasks and generated results between the script generation device, test equipment, and database.

[0114] Model parameters can be stored in a local database, a configuration file, or a remote server. A test item attribute table records the category and electrical pin operation attributes of each test item. A temperature and relaxation time acceleration mapping table determines the scaling factor during the thermal compensation phase. A test item execution duration library estimates the time length for insertable test items during the combination selection phase. ATE script templates convert update execution sequences into script files that can be compiled and executed by specific test equipment. The above data can be stored in the same or different locations depending on the test platform deployment method.

[0115] The generated target automated test equipment script is compiled and sent to the ATE (Automatic Test Equipment). The ATE then applies voltage to the memory chip, sends commands, performs measurements, and outputs test results according to the updated execution sequence. This method eliminates reliance on manual experience in script generation, incorporating charge relaxation behavior, thermal state, and test item mobility into the scheduling logic. This reduces false failures while improving ATE test time utilization.

[0116] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A method for generating ATE test scripts, characterized in that, Includes the following steps: Obtain the original test task queue for the memory chip, the original test task queue including multiple test items; extract the stress parameters of each test item, and input the stress parameters into a pre-trained charge relaxation prediction model, and output the reference relaxation time corresponding to each test item by the charge relaxation prediction model; Each test item is divided into charge-sensitive test items and non-charge-sensitive test items; each test item in the original test task queue is scheduled and sorted to obtain an initial execution sequence; when it is determined that the time interval between the preceding test item and the following test item in the adjacent execution order in the initial execution sequence is less than the reference relaxation time corresponding to the preceding test item, and the following test item is a charge-sensitive test item, a timing conflict is confirmed. When a timing conflict is confirmed, at least one target non-charge sensitive test item whose execution time meets the preset condition is selected from each of the non-charge sensitive test items, and the target non-charge sensitive test item is inserted between the preceding test item and the following test item to generate an update execution sequence; The stress parameters include the applied voltage amplitude and the voltage application duration; The execution time meeting the preset condition means that the sum of the individual execution times of all selected target non-charge sensitive test items is greater than or equal to the reference relaxation time corresponding to the preceding test item; When a timing conflict is confirmed, the total available time of all available non-charge-sensitive test items that have not yet been scheduled is calculated. Compare the total available time with the baseline relaxation time corresponding to the preceding test item; When it is determined that the total available time is less than the baseline relaxation time, the preceding test item is split into multiple micro-stress slice test items, so that the slice relaxation time re-output by each micro-stress slice test item after being input into the charge relaxation prediction model is less than or equal to the single execution time of any available non-charge sensitive test item. After splitting the preceding test item into multiple micro-stress slice test items, all the micro-stress slice test items are distributed in the update execution sequence, and at least one available non-charge-sensitive test item is configured between any two adjacent micro-stress slice test items in the execution order. The target automated test device script is generated using the update execution sequence.

2. The method according to claim 1, characterized in that, The training process of the charge relaxation prediction model includes: Acquire the actual charge release evolution data of the historical memory chip under different applied voltage amplitudes and different voltage application durations, and extract the time value corresponding to the decay of the actual charge release evolution data to a steady state as the true relaxation time label; The obtained applied voltage amplitude and the voltage application duration are combined as training input samples; The initial prediction model is trained under supervision using the training input samples and the actual relaxation time labels. The model weights are updated by minimizing the error between the predicted relaxation time output by the initial prediction model and the actual relaxation time labels, thus obtaining the trained charge relaxation prediction model.

3. The method according to claim 1, characterized in that, The step of inserting the target non-charge-sensitive test item between the preceding test item and the following test item includes: Extract the individual execution time of each of the candidate non-charge-sensitive test items; Multiple non-charge-sensitive test items are selected sequentially according to a preset priority order, and their corresponding individual execution times are accumulated. When the total accumulated time reaches the reference relaxation time, the selected multiple non-charge-sensitive test items are used as the target non-charge-sensitive test items to generate a target combination. Insert all target non-charge-sensitive test items within the target combination between the preceding test item and the following test item.

4. The method according to claim 1, characterized in that, The process of classifying the aforementioned test items into charge-sensitive test items and non-charge-sensitive test items includes: Extract the electrical pin operation attributes of each of the test items; The test item whose electrical pin operation attribute is to read the threshold voltage of the memory cell in the memory chip is determined to be a charge-sensitive test item; Peripheral logic test items whose electrical pin operation attributes are independent of the threshold voltage state of the memory cell and do not trigger the state flip of the memory cell are determined to be non-charge sensitive test items; the peripheral logic test items include any one or more of the following: pin connectivity test items, DC leakage current measurement test items, and basic control register scan test items.

5. The method according to claim 1, characterized in that, During the generation of the update execution sequence, the power consumption feature tags of all scheduled test items preceding the preceding test item in the initial execution sequence and the execution duration of each scheduled test item are extracted. The power consumption feature label and the corresponding execution time are input into a pre-trained time-series thermodynamic mapping model, and the time-series thermodynamic mapping model outputs the virtual temperature index when the preceding test item is completed. Extract the temperature and relaxation time acceleration mapping table configured in the pre-built scaling compensation model, match the scaling coefficient corresponding to the virtual temperature index in the temperature and relaxation time acceleration mapping table, and output the product of the baseline relaxation time and the scaling coefficient as the corrected relaxation time. The modified relaxation time is used to replace the baseline relaxation time used in the step of confirming the existence of timing conflicts.

6. The method according to claim 5, characterized in that, The training process of the time-series thermodynamic mapping model includes: Acquire real thermal imaging evolution data of the test chip when executing a combination of test items with different power consumption feature labels, and extract the actual temperature value of each node where the scheduled test item has been executed as a temperature supervision label; Input the corresponding power consumption feature tag combination and the corresponding execution time combination into the initial thermodynamic mapping model; Extract the predicted temperature index output by the initial thermodynamic mapping model, calculate the error between the predicted temperature index and the temperature supervision label, update the model weights based on the error, and obtain the trained time-series thermodynamic mapping model.

7. An ATE test script generation system, used to implement the method of claim 1, characterized in that, It includes an acquisition module, a prediction module, a partitioning module, a detection module, a scheduling module, and a generation module; The acquisition module is used to acquire the original test task queue for the memory chip, the original test task queue including multiple test items; The prediction module is used to extract the stress parameters of each of the test items, input the stress parameters into a pre-trained charge relaxation prediction model, and output the reference relaxation time corresponding to each of the test items by the charge relaxation prediction model. The division module is used to divide each of the test items into charge-sensitive test items and non-charge-sensitive test items; The detection module is used to schedule and sort each test item in the original test task queue to obtain an initial execution sequence. When it is determined that the time interval between the preceding test item and the following test item in the adjacent execution order in the initial execution sequence is less than the reference relaxation time corresponding to the preceding test item, and the following test item is a charge-sensitive test item, a timing conflict is confirmed. The scheduling module is used to select at least one target non-charge sensitive test item whose execution time meets a preset condition from each of the non-charge sensitive test items when a timing conflict is confirmed, and insert the target non-charge sensitive test item between the preceding test item and the following test item to generate an update execution sequence. The generation module is used to generate a target automated test device script using the update execution sequence.

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