Physical memory protection method, electronic device, computer readable medium and computer program product

Abstract

The present disclosure provides a physical memory protection method, an electronic device, a computer readable medium and a computer program product. The method is applied to an MMU lookup unit. In an address conversion process, a page table mapping granularity determined by a page table check and a security protection granularity determined by a security check are obtained. In response to the security protection granularity being smaller than the page table mapping granularity, a first valid page size is set as the security protection granularity, and a downgrade flag is generated. A first address mapping relationship including the downgrade flag is generated, and the first address mapping relationship is stored in an MMU storage unit. The downgrade flag is used to trigger a security check on a memory access request based on the security protection granularity when the memory access request hits an entry with the downgrade flag in the MMU storage unit. In the embodiment of the present disclosure, the physical address interval involved in each memory access can be subjected to a security check, eliminating the protection blind area caused by the mismatch of the granularity, and enhancing the memory security of the system.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a physical memory protection method, electronic device, computer-readable medium, and computer program product. Background Technology

[0002] In current memory protection mechanisms, memory access protection primarily relies on Physical Memory Protection (PMP) or the page table's own permission checking mechanism. PMP technology isolates memory regions by configuring address segments in registers. Limited by the number of registers, PMP supports a maximum of 64 regions, making fine-grained process-level isolation impossible. Furthermore, region sizes must be powers of 2 and naturally aligned, preventing protection of arbitrary address ranges. Configuration management requires the involvement of M Mode (machine mode) firmware; S Mode OS cannot configure it independently. Page table permission protection is a more commonly used and finer-grained approach, managed by the S Mode OS. It typically requires setting corresponding address access permissions for different access types (e.g., read, write, execute). Different processes can use the same virtual address mapped to different physical pages, naturally preventing direct boundary crossings between processes. However, if the MMU (Memory Management Unit) is disabled or the configuration mode is not enabled, page table protection is completely ineffective, allowing DMA (Direct Memory Access) devices to directly access physical addresses, posing a security risk.

[0003] In a single trusted execution environment, a combination of both approaches is typically used to ensure the correctness of memory accesses. However, in confidential computing scenarios, when multiple cloud tenants share the same physical server, the workload of a tenant (usually an application or virtual machine) relies on hardware-based isolation mechanisms managed by the host or privileged software. Traditional host software, such as operating systems or hypervisors, often has unrestricted access to system memory, devices, and hardware isolation components, such as the MMU or PMP physical address protection registers. This design significantly expands the scope of the Trusted Computing Base (TCB), thereby increasing the potential attack surface. Summary of the Invention

[0004] This disclosure provides a physical memory protection method, an electronic device, a computer-readable medium, and a computer program product.

[0005] In a first aspect, embodiments of this disclosure provide a physical memory protection method applied to a memory management unit (MMU) lookup unit, the method comprising:

[0006] During address translation, the page table mapping granularity determined by page table checks and the security protection granularity determined by security checks are obtained.

[0007] In response to the security protection granularity being smaller than the page table mapping granularity, the first effective page size is set to the security protection granularity, and a degradation flag is generated;

[0008] A first address mapping relationship including the degradation flag is generated, and the first address mapping relationship is stored in the MMU storage unit; the degradation flag is used to trigger a security check on the memory access request based on the security protection granularity when the memory access request hits an entry with the degradation flag in the MMU storage unit.

[0009] Secondly, embodiments of this disclosure provide an electronic device, including a memory and a processor; the memory stores a computer program that can be executed by the processor, and when the computer program is executed by the processor, it implements the physical memory protection method described above.

[0010] Thirdly, embodiments of this disclosure provide a computer-readable medium storing a computer program that, when executed by a processor, implements the physical memory protection method described above.

[0011] Fourthly, embodiments of this disclosure also provide a computer program product, including a computer program that, when executed by a processor, implements the physical memory protection method as described above.

[0012] The physical memory protection method of this disclosure is applied to the MMU lookup unit. During address translation, the page table mapping granularity determined by page table checks and the security protection granularity determined by security checks are obtained. In response to a security protection granularity being smaller than the page table mapping granularity, the first effective page size is set to the security protection granularity, and a degradation flag is generated. A first address mapping relationship including the degradation flag is generated and stored in the MMU storage unit. The degradation flag is used to trigger a security check on the memory access request based on the security protection granularity when the memory access request hits an entry with the degradation flag in the MMU storage unit. In the case of a mismatch between the page table mapping granularity and the security protection granularity, this disclosure downgrades the page table mapping granularity to be consistent with the security protection granularity, ensuring that the physical address range involved in each memory access can pass the security check, eliminating the protection blind spot caused by the granularity mismatch, and enhancing the memory security of the system. Attached Figure Description

[0013] In the accompanying drawings of the embodiments disclosed herein:

[0014] Figure 1 This is a schematic diagram of the structure of the MMU provided in an embodiment of this disclosure.

[0015] Figure 2 This is a flowchart illustrating the physical memory protection method provided in an embodiment of the present disclosure.

[0016] Figure 3 This is a schematic diagram of the structure of a virtual address in sv39 mode provided in an embodiment of this disclosure.

[0017] Figure 4 This is a schematic diagram of a security inspection process provided in an embodiment of the present disclosure.

[0018] Figure 5 This is a schematic diagram illustrating the page table checking and security checking process provided in the embodiments of this disclosure.

[0019] Figure 6 This is a schematic block diagram illustrating the composition of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0020] To enable those skilled in the art to better understand the technical solutions of this disclosure, the physical memory protection method, electronic device, computer-readable medium, and computer program product provided in the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0021] The present disclosure will be described more fully below with reference to the accompanying drawings; however, the embodiments shown may be embodied in different forms, and the present disclosure should not be construed as limited to the embodiments set forth below. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will enable those skilled in the art to fully understand the scope of the disclosure.

[0022] The accompanying drawings are provided to further illustrate this disclosure and form part of the specification. They are used together with the detailed embodiments to explain this disclosure and do not constitute a limitation thereof. These and other features and advantages will become more apparent to those skilled in the art from the description of detailed embodiments with reference to the accompanying drawings.

[0023] Unless otherwise specified, each embodiment and feature of this disclosure may be used individually or in combination with other embodiments and features thereof.

[0024] Those skilled in the art will understand that various changes in form and detail may be made to the embodiments of this disclosure without departing from the scope of this disclosure as set forth by the appended claims.

[0025] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. The term "and / or" as used in this disclosure includes any and all combinations of one or more of the associated enumerated entries. The singular forms "a" and "the" as used in this disclosure are also intended to include the plural forms, unless the context clearly indicates otherwise. The terms "comprising," "made of," etc., as used in this disclosure specify the presence of the stated feature, integral, step, operation, element, and / or component, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0026] Unless otherwise specified, all terms used in this disclosure (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined in this disclosure.

[0027] This disclosure is not limited to the embodiments shown in the accompanying drawings, but includes modifications to the configuration based on the manufacturing process. Therefore, the areas illustrated in the drawings are schematic, and the shapes of the areas shown illustrate specific shapes of areas of an element, but are not intended to be limiting.

[0028] In multi-tenant data center environments, host software, hardware devices, device drivers, cloud operators, orchestration services, and the workloads of other tenants are all considered potential threat vectors. Therefore, in many application scenarios, it is necessary to build an isolated supervisory domain that can express differentiated trust models and support secure access control of platform resources to achieve more granular security assurance and a trusted execution environment.

[0029] In the extension of the RISC-V (Reduced Instruction Set Computer V) privileged architecture, the introduction of a multi-supervisor domain physical address space isolation mechanism enables fine-grained and differentiated access control over memory and other platform resources, effectively reducing the scope of the Control Block (TCB) and improving overall system security. Each supervisor domain is bound to a specific physical address region and is physically isolated from other supervisor domains, with only the Root Domain Security Manager (RDSM) possessing global physical address access permissions. The Supervisor Domain Identifier (SDID) serves as an identifier for inter-domain isolation and is used to construct domain-based physical address protection fences. The security of the supervisor domain relies on the TCB, which is jointly constructed by the RDSM (software component) and hardware entities to enforce the supervisor domain's isolation policy. However, traditional host software, such as operating systems or virtual machine monitors, often has unrestricted access to system memory, devices, and hardware isolation components. This design significantly expands the scope of the TCB, thereby increasing the potential attack surface.

[0030] To address the aforementioned technical problems, this disclosure provides a physical memory protection method applied to an MMU lookup unit. Figure 1 This is a schematic diagram of the structure of the MMU provided in the embodiments of this disclosure, such as... Figure 1 As shown, the MMU includes:

[0031] The MMU control unit is used to receive requests from the data / instruction end, such as address translation requests, and distribute the information to the MMU lookup unit according to priority.

[0032] The MMU lookup unit includes an address translation module and a degradation module. The address translation module is used for address translation, that is, traversing the multi-level page table structure, finding the physical page number corresponding to the virtual address in the page table entries, calculating the physical address based on the physical page number, and checking the access permissions for the physical address (including the base addresses of each level of page table obtained during the traversal). The degradation module is used to compare the page table mapping granularity corresponding to the physical address with the security protection granularity if the security check of the physical address passes, take the smaller one as the final page table mapping granularity, and generate the address mapping.

[0033] The MMU storage unit is used to store address mappings so that subsequent requests for the same memory address can be quickly matched.

[0034] Figure 2 This is a flowchart illustrating the physical memory protection method provided in the embodiments of this disclosure, combined with... Figure 2 and Figure 3 As shown, the physical memory protection method includes the following steps:

[0035] Step S11: During the address translation process, obtain the page table mapping granularity determined by the page table check and the security protection granularity determined by the security check.

[0036] The front-end processing unit of the MMU sends memory access requests to the MMU control unit. These requests carry information such as the first virtual address and access type, which can include reading data / writing data. The MMU control unit queries and filters these memory access requests according to a preset priority strategy, selecting one to send to the MMU storage unit. The selected memory access request can be either an instruction area request or a data area request.

[0037] In the MMU storage unit, an address mapping entry is queried based on the first virtual address. If no match is found, the current pending memory access request is sent to the address translation module of the MMU lookup unit after priority arbitration by the MMU control unit, so that the first virtual address can be translated into a physical address. In this embodiment, the address translation process includes a page table check process and a security check process.

[0038] During page table checking, the page table is loaded from memory. Based on the virtual address carried in the memory access request, it is traversed according to the multi-level page table structure. Finally, the physical page number is found in the page table entry, and the candidate final physical address (i.e., the first target physical address) is calculated based on the physical page number. The page size corresponding to the traversal termination position (i.e., the page table mapping granularity) is also recorded. After the page table check of a certain level is completed, the lookup unit initiates an MPTE (MPt Page Table Entry, Secure Memory Page Table) check, i.e., a security check, to check the access permissions of the current level page table base address. After completing the final MPTE check, the security protection granularity determined by this security check is recorded.

[0039] In step S12, in response to the security protection granularity being smaller than the page table mapping granularity, the first effective page size is set to the security protection granularity, and a degradation flag is generated.

[0040] The degradation module compares the security protection granularity with the page table mapping granularity. If the security protection granularity is smaller than the page table mapping granularity, the page table mapping granularity degradation mechanism is triggered, which means that the page size finally returned to the previous level is downgraded to a smaller security protection granularity, and a degradation flag is generated.

[0041] Table 1 shows the scenarios where page table mapping granularity is degraded under Sv57, Sv48, and Sv39 modes:

[0042] Table 1

[0043]

[0044] As can be seen from Table 1, as long as the security protection granularity returned by the security check is smaller than the page table mapping granularity returned by the page table check, it meets the degradation condition, and the effective page size returned to the front-end processing unit of the MMU needs to be downgraded according to the security granularity.

[0045] Step S13: Generate a first address mapping relationship including a degradation flag, and store the first address mapping relationship in the MMU storage unit; the degradation flag is used to trigger a security check on the memory access request based on the security protection granularity when the memory access request hits an entry with the degradation flag in the MMU storage unit.

[0046] The degradation flag affects not only the return path of the MMU's front-end processing unit but also the backfill path of the MMU processing unit. The backfill path is the path for reclaiming data; the results returned by the MMU lookup unit are backfilled into the MMU storage unit, and the degradation flag is simultaneously stored in its corresponding entry.

[0047] In addition to the first virtual address, the first target physical address, access permissions, and / or the first effective page size, the first address mapping relationship also includes a degradation flag, indicating that page degradation has occurred in this first address mapping relationship. The MMU lookup unit sends the first address mapping relationship including the degradation flag to the MMU storage unit, and the first address mapping relationship is stored as an entry in the MMU storage unit. When other memory access requests arrive subsequently, if they hit the entry in the MMU storage unit and the entry has a degradation flag, a security check based on the granularity of security protection is required, i.e., a final-level MPTE check, to ensure that the precise address of this memory access falls within the authorized small block, rather than directly using the cached physical address, thus avoiding protection blind spots and improving system security.

[0048] The physical memory protection method of this disclosure is applied to the MMU lookup unit. During address translation, the page table mapping granularity determined by page table checks and the security protection granularity determined by security checks are obtained. In response to a security protection granularity being smaller than the page table mapping granularity, the first effective page size is set to the security protection granularity, and a degradation flag is generated. A first address mapping relationship including the degradation flag is generated and stored in the MMU storage unit. The degradation flag is used to trigger a security check on the memory access request based on the security protection granularity when the memory access request hits an entry with the degradation flag in the MMU storage unit. In the case of a mismatch between the page table mapping granularity and the security protection granularity, this disclosure downgrades the page table mapping granularity to be consistent with the security protection granularity, ensuring that the physical address range involved in each memory access can pass the security check, eliminating the protection blind spot caused by the granularity mismatch, and enhancing the memory security of the system.

[0049] In some embodiments, the first address mapping relationship includes a first virtual address and a first target physical address; wherein, the first target physical address is obtained by aligning and correcting the first physical page number determined by the page table check based on the security protection granularity and the first virtual address; the first virtual address is the virtual address that requests memory access during the address translation process.

[0050] The first target physical address is the final physical address. It should be noted that if the page table mapping granularity is not downgraded, the final physical address is calculated based on the first physical page number obtained from the page check of the last level page. If the page table mapping granularity is downgraded, the final physical address cannot be directly calculated based on the first physical page number obtained from the page check of the last level page. Instead, the first physical page number determined by the page table check is first aligned and corrected, and then the final physical address is calculated based on the corrected physical page number.

[0051] In some embodiments, the first address mapping relationship may further include access permissions and / or a first effective page size, wherein the access permissions are determined based on the results of page table checks and security checks.

[0052] In some embodiments, the step of determining access permissions includes the following steps:

[0053] Step S31: Obtain the page table entries determined by the page table check, and obtain the basic page table permissions from the page table entries.

[0054] During the page table check process, when traversing the page table, the page table entry (PTE) corresponding to the first virtual address is read. The page table entry contains the basic access permission bits for that memory page, such as read / write bits, user / privilege bits, and executable bits. These basic access permission bits are used to characterize the basic page table permissions and are set by the operating system when the page table is created.

[0055] Step S32: Obtain the access permission decision result determined by the security check.

[0056] In the page table mapping granularity degradation process, the system introduces the concept of security protection granularity. When the page table mapping granularity (e.g., 2MB) is larger than the security protection granularity (e.g., 4KB), the page table mapping granularity degradation mechanism is triggered. At this time, the MMU performs additional security checks, such as querying the memory protection table or the granular protection table. In scenarios such as RDMA (Remote Direct Memory Access), the memory protection table stores access permissions (e.g., read-only, read-write) and valid access keys (R_Key) for memory regions. The security check process verifies whether the permissions of the memory access request match the permissions recorded in the memory protection table. In security architectures such as ArmRME, the granular protection table defines the security attributes of each memory granule at the physical address level. The security check process verifies whether the security domain of the current memory access has the right to access the physical memory with that security attribute.

[0057] Step S33: Determine access permissions based on the basic page table permissions and access permission adjudication results.

[0058] Typically, the final access permission is the intersection of the more restrictive of the underlying page table permissions and the access permission decision result. For example, if the underlying page table permissions are read-write, but the region in the memory protection table is marked as read-only, then the final access permission is read-only. The final access permission, along with the first target physical address and the first effective page size, is returned to the preceding processing unit as an address translation result.

[0059] It should be noted that if a page table mapping granularity downgrade is triggered, the security protection granularity becomes smaller, and the effective mapping range will be reduced to the security protection granularity. However, the access permissions within this security protection granularity are still based on the results of the above comprehensive adjudication. The downgrade mainly affects address alignment and mapping range, rather than directly changing the permission bits themselves.

[0060] In this embodiment, page table checks and security checks are performed first, followed by a degradation determination. If it is determined that a page table mapping granularity degradation is required, the final physical address is then calculated. Therefore, in some embodiments, the physical memory protection method may further include the following steps:

[0061] Step S21: In response to the security protection granularity being smaller than the page table mapping granularity, extract the page offset corresponding to the security protection granularity from the first virtual address; the first virtual address is the virtual address requested for memory access during the address translation process.

[0062] If the security protection granularity is smaller than the page table mapping granularity, a page table mapping granularity degradation mechanism is triggered. In this case, the page offset corresponding to the security protection granularity is extracted from the first virtual address. For example, for a security protection granularity of 4KB, the lower 12 bits of the first virtual address are extracted as the page offset.

[0063] In a virtual address, the bits between the security protection granularity offset bits and the page table mapping granularity offset bits identify which specific security block the target address falls within. For example, if the page table is 1GB granularity (offset bits are the lower 30 bits) and the security protection granularity is 4KB (offset bits are the lower 12 bits), then bits [29:12] of the virtual address represent the page offset of that 4KB block within a 1GB big page.

[0064] Step S22: Align and correct the first physical page number based on the first virtual address and the security protection granularity to obtain a second physical page number that aligns the first physical page number to the boundary of the security protection granularity; the first physical page number is determined based on page table checks.

[0065] The final level page table check determines the first physical page number. In this step, the physical starting address corresponding to the first physical page number is address-aligned with a security protection granularity of 4KB, and the aligned physical address is shifted right by the page offset bits to obtain the downgraded second physical page number.

[0066] Step S23: Concatenate the second physical page number and the page offset to obtain the first target physical address. The first target physical address is the physical address obtained by converting the first virtual address during the address translation process.

[0067] In the case of page table mapping granularity degradation, the calculation process of the second physical address is a step-by-step, corrective process. Based on a smaller security protection granularity, the first physical page number obtained by regular page table traversal is re-aligned and corrected to ensure that the physical address used in the end strictly corresponds to a complete memory region that has passed the security check.

[0068] In some embodiments, after concatenating the second physical page number and the page offset to obtain the first target physical address (i.e., step S23), and after setting the first effective page size to the security protection granularity, the physical memory protection method may further include the following steps: within the current clock cycle, returning the first target physical address, the first effective page size, and access permissions to the front-end processing unit of the MMU to which the MMU lookup unit belongs; wherein, the access permissions are determined after page table checks and security checks. The front-end processing unit of the MMU to which the MMU lookup unit belongs refers to the processor core unit that initiates the memory access request to the MMU. After downgrading the page table mapping granularity, returning the secure memory access information (i.e., the first target physical address, the first effective page size, and access permissions) obtained by the MMU lookup unit to the front-end processing unit of the MMU within the current clock cycle can avoid further table lookup processes, speed up the overall MMU access process, and enable the instruction or data end to obtain the physical address as soon as possible, thereby further improving performance.

[0069] In some embodiments, after obtaining the page table mapping granularity determined by the page table check and the security protection granularity determined by the security check, the physical memory protection method further includes the following steps:

[0070] Step S12': In response to the security protection granularity being greater than or equal to the page table mapping granularity, a second address mapping relationship is generated and stored in the MMU storage unit.

[0071] The degradation module compares the security protection granularity with the page table mapping granularity. If the security protection granularity is greater than or equal to the page table mapping granularity, the page table mapping granularity degradation mechanism will not be triggered. There is no need to reduce the granularity of the effective page size or set a degradation flag. After generating the second address mapping relationship, the second address mapping relationship is stored in the MMU storage unit.

[0072] In some embodiments, the second address mapping relationship may include a first virtual address and a second target physical address; the second target physical address is determined based on the first physical page number determined by page table checking after the page table mapping granularity degradation judgment.

[0073] In some embodiments, the second address mapping relationship may further include access permissions and / or a second effective page size, wherein the second effective page size is a page table mapping granularity, which is determined during the page table check process, i.e., the page table mapping granularity.

[0074] In some embodiments, after determining the second target physical address and the second effective page size, the physical memory protection method may further include the following steps: within the current clock cycle, returning the second target physical address, the second effective page size, and access permissions to the front-end processing unit of the MMU to which the MMU lookup unit belongs; wherein the access permissions are determined after page table checks and security checks.

[0075] In some embodiments, after storing the first address mapping relationship in the MMU memory unit, the physical memory protection method may further include the following steps:

[0076] Step S14: In response to the received memory access request hitting an entry in the MMU storage unit and the entry having a degradation flag, a security check at the security protection granularity is performed based on the second virtual address carried in the memory access request.

[0077] like Figure 1 As shown in Scenario 2, when the MMU receives a memory access request, if the request matches an entry in the MMU storage unit and the entry carries a degradation flag, it indicates that when the entry was created, due to page table mapping granularity degradation, the entry did not record the physical address of the entire large area (e.g., 1GB) of the original page table mapping, but rather a smaller, contiguous security address block aligned and corrected according to security protection granularity (e.g., 4KB). The system only performed a complete security check on the specific 4KB block corresponding to the previously accessed virtual address, while the other 4KB blocks within the entire large area (1GB) of the original page table mapping were not security checked in that operation. Therefore, the physical address corresponding to this entry cannot be used directly. The current memory access request must be resent to the MMU lookup unit through the MMU control unit, allowing the MMU lookup unit to re-perform a security check based on the virtual address carried in this memory access request, using a finer-grained security protection granularity, to determine whether the memory access is permitted.

[0078] An entry marked with a downgrade flag is not a completely trusted, directly usable cache entry. The existence of the downgrade flag ensures that memory access requests to downgraded regions that have already hit the cache will still undergo independent, precise, and fine-grained security checks, thus completely blocking security vulnerabilities that bypass security checks due to cache hits. It should be noted that this security check only performs a security lookup check on the last-level page table, eliminating the need for security checks on all levels of page tables, which can speed up the memory access process.

[0079] In some embodiments, after storing the first address mapping relationship in the MMU memory unit, the physical memory protection method may further include the following steps:

[0080] Step S14': In response to a received memory access request hitting an entry in the MMU storage unit and the entry not having a degradation flag, determine the physical address, access permissions, and effective page size corresponding to the entry, and return this information to the MMU's front-end processing unit.

[0081] like Figure 1 As shown in Scenario 1, when the MMU receives a memory access request, if the request matches an entry in the MMU's storage unit and the entry does not have a degradation flag, it means that no page table mapping granularity degradation occurred when the entry was created. Therefore, the address mapping represented by the cached entry is complete and secure. Its page size (i.e., page mapping granularity) is consistent with or larger than the security protection granularity. Therefore, the entire physical page mapped by this entry has undergone a complete security check, and the entry can be fully trusted. No additional verification or calculation is required, and the physical address, access permissions, and effective page size corresponding to the entry can be directly returned to the MMU's front-end processing unit.

[0082] In some embodiments, before obtaining the page table mapping granularity determined by the page table check and the security protection granularity determined by the security check (i.e., step S11), the physical memory protection method may further include the following steps: during the page table check process, for each level of page table, after completing the page table check to obtain the physical base address of the next level page table, a security check is performed based on the physical base address of the next level page table; in response to the security check passing, a page table check is performed on the next level page table until the security check of the last level page table passes, thereby obtaining the security protection granularity, which is the security protection granularity on which the security check of the last level page table is based.

[0083] The following combination Figures 3 to 5 The process of page table checking and security checking is explained in detail.

[0084] Figure 3 This is a schematic diagram of the structure of a virtual address in Sv39 mode provided in an embodiment of this disclosure, as shown below. Figure 3As shown, in Sv39 mode, the 39-bit virtual address issued by the CPU is fixedly divided into four segments by the hardware:

[0085] VA[38:30] = VPN[2] → 9 bit → index L1 level page table (root page table);

[0086] VA[29:21] = VPN[1] → 9 bit → index L2 level page table;

[0087] VA[20:12] = VPN[0] → 9 bit → index L3 level page table (final page table);

[0088] VA[11:0] = Offset → 12bit → Offset within the page (not checked, directly retained).

[0089] The high 27 bits of the virtual address are used for multi-level page table checks, while the low 12 bits are only used to assemble the final physical address. That is, a page table check is performed every 9 bits, and no page table check is performed on the low 12 bits.

[0090] Figure 5 This is a schematic diagram illustrating the page table checking and security checking process provided for embodiments of this disclosure. Figure 5 As shown, Figure 5 Positions 1, 2, and 3 in the table correspond to the three levels of page tables L1-L3 respectively: at position 1, the physical base address of the L2 level page table is obtained by using VPN[2] to look up the L1 level page table; at position 2, the physical base address of the L3 level page table is obtained by using VPN[1] to look up the L2 level page table; at position 3, the first physical page number of the final data page is obtained by using VPN[0] to look up the L3 level page table, which is used to generate the final physical address HPA.

[0091] Page table checks can end at any level of the page table. If a big page flag is found in the L1 level page table, the page table mapping granularity is 1GB, and the page table check ends at position 1. If a big page flag is found in the L2 level page table, the page table mapping granularity is 2MB, and the page table check ends at position 2. Otherwise, proceed to the L3 level page table, where the page table mapping granularity is 4KB, and the page table check ends at position 3.

[0092] Figure 4 This is a schematic diagram of the security inspection process provided in an embodiment of the present disclosure. Figure 4 A three-level MPTE lookup process is shown. The security check takes physical address information as input, calculates the index through a series of non-fixed masks and step sizes, and performs security checks according to the multi-level structure of the Security Protection Table (MPT).

[0093] In the Level 1 MPTE check (L1 MPT Walk), the lookup parameters are as follows: the L1-level MPT table is 4 KiB in size and contains 8K (8192) entries. Starting from the base address of the L1-level MPT table, an addition operation is performed using the offset extracted from the original physical address to locate the specific MPT L1 entry. Each MPT L1 entry corresponds to a 4 KiB address space. This entry is then read to obtain the physical base address of the L2-level MPT table. In other words, each MPT L1 entry corresponds to and covers a 4 KiB physical address space, pointing to the base address of the L2-level MPT table.

[0094] Using the base address of the L2-level MPT table parsed from the L1 entry, the second-level MPTE check is performed. In the second-level MPTE check (L2 MPT Walk), the lookup parameters are: the L2-level MPT table is 16 MiB in size, containing 2M (2097152) entries. Starting from the base address of the L2-level MPT table obtained in the previous step, and combining it with another part of the physical address (Offset), the specific MPT L2 entry is located. Each MPT L2 entry corresponds to a 32 MiB address space. This entry is read to obtain the physical base address of the L3-level MPT table. In other words, each MPT L2 entry corresponds to and covers 32 MiB of physical address space, pointing to the base address of the L3-level MPT table.

[0095] Using the base address of the L3-level MPT table resolved from the L2 entry, the third-level MPTE check is performed. In the third-level MPTE check (L3 MPT Walk), the lookup parameters are: the L3-level MPT table is 8 KiB in size and contains 1024 entries. Starting from the base address of the L3-level MPT table obtained in the previous step, and combining it with the remaining valid bits of the physical address, the specific MPT L3 entry is located. Each MPT L3 entry covers 64 TiB of physical address space. This entry is then read, and the table lookup ends.

[0096] Figure 5 This is a schematic diagram illustrating the page table checking and security check process provided in an embodiment of the present disclosure. Figure 5 Using position 1 and MPTL1 → position 2 and MPTL1 → position 3 and MPTL1, Figure 3 Corresponding page table checks and Figure 4 The corresponding safety check lock steps are sewn together. For example... Figure 5 As shown, before the page table check begins, the validity of the current context (SDID / domain ID, etc.) and the location of the root MPT table are confirmed.

[0097] At position 1, perform an L1 level page table check (MPT L1), that is, use VPN[2] to check the L1 level page table to obtain the physical base address (i.e., physical page number) of the L2 level page table; use the physical base address of the L2 level page table according to Figure 4 The method index MPT is used to determine whether access to the physical memory where the L2 page table is located is allowed. If the security check passes (i.e., access is allowed), the check of the next level page table continues.

[0098] At position 2, perform L2 level page table check (MPT L2), that is, use VPN[1] to check the L2 level page table to obtain the physical base address of the L3 level page table; use the physical base address of the L3 level page table according to Figure 4 The method index MPT is used to confirm whether access to the physical memory where the L3 page table is located is allowed. If the security check passes, the check of the next level page table continues.

[0099] At position 3, perform L3 level page table check (MPT L3), that is, use VPN[0] to look up the L3 level page table to obtain the physical page number of the data page, and obtain the final physical address HPA based on the physical page number. Perform a security check on the final HPA to obtain the security protection granularity. At this time, compare the page table mapping granularity with the security protection granularity and make a reduction judgment.

[0100] After each level of page table check is completed, a security check is immediately performed using the output physical base address. Page table checks and security checks are not parallel and independent processes, but rather a lockstep alternation between page table check output and security check. Finally, the MPT L3 provides the security granularity for comparison with the page table mapping granularity, so as to trigger or not trigger the generation of a degradation flag.

[0101] It should be noted that page table checks can end at any level; different ending positions represent different page table mapping granularities. The same applies to security checks. Page table checks end earlier than security checks, meaning the page table only undergoes a lookup at position 1, while the physical base address undergoes two or three lookups; or the page table undergoes page table checks at positions 1 and 2, while the physical base address undergoes three security checks.

[0102] The effective page size returned by the MMU to the front-end processing unit is reduced to the smaller of the page mapping granularity and the security granularity. Upon receiving the effective page size, the MMU's front-end processing unit, such as the instruction or data unit, will not distinguish whether the effective page size is the original page size or a downgraded effective page size. It will continue to execute the original processing logic according to the received effective page size, ensuring that the enhanced memory access security has zero impact on the core logic of the front-end processor, achieving maximum compatibility.

[0103] The physical address is constructed by concatenating the high-order bits (physical page number) and the low-order bits (page offset). The number of bits for the page offset is determined by the effective page size, which is derived from the low-order portion of the virtual address. Without sending a page mapping granularity downgrade, the effective page size returned by the MMU is the original page table mapping granularity (e.g., 2MB). When concatenating the physical address, the low log2(2MB) = 21 bits of the virtual address are used as the page offset and concatenated with the physical page number returned by the MMU to obtain the complete physical address. In other words, all the low-order bits of the virtual address become offsets and are used directly.

[0104] When the page table mapping granularity is downgraded, assuming a 1GB granularity and a 4KB security granularity, the effective page size returned by the MMU is downgraded to 4KB. During physical address concatenation, the high-order bits of the physical address originate from the high-order portion of the physical address returned by the MMU (physical page number). The low-order bits of the physical address use the lowest log2(4KB) = 12 bits of the virtual address as the page offset. Therefore, bits 12 to 29 of the virtual address (bits that would normally be located within a 1GB page) are no longer considered part of the page offset after the page table mapping granularity is downgraded. The MMU incorporates this bit information when calculating the returned 4KB base address to ensure that the returned base address points to the correct, security-checked 4KB block. Thus, in the case of downgraded page table mapping granularity, the final concatenated physical address has its high-order bits pointing to a secure 4KB block, and its low-order bits (offset) precisely located within that 4KB block, guaranteeing that memory access falls entirely within the authorized area.

[0105] This disclosure relates to the field of processor security and can be applied to systems supporting RISC-CV architecture. From an architectural perspective, page table access protection mechanisms rely on operating system (OS) configuration, while secure access protection is led by the RDSM (Real-Time Management System). These two mechanisms are designed independently, forming a two-layer protection mechanism. Memory access protection is a core aspect of processor security. This disclosure can be applied to secure access control in confidential computing scenarios while maintaining compatibility with traditional page table access mechanisms. Under an independently configured two-layer checking framework, physical address access permissions are double-verified, ensuring that page table mapping checks are satisfied without violating security policy configurations, thereby achieving a balance between security and performance.

[0106] This disclosure embodiment is based on a page table mapping granularity degradation mechanism. By reducing the effective page size, it achieves more comprehensive memory access protection, preventing unprotected addresses from accessing physical memory. The address translation result is returned to the MMU's front-end processing unit in the current clock cycle. Instead of performing a full security check within a large page, a single security check is performed based on the security protection granularity, reducing the number of lookups.

[0107] This embodiment of the disclosure identifies the page table mapping granularity and the security protection granularity. When the page table mapping granularity is greater than the security protection granularity, the page table mapping granularity returned to the previous level is reduced in level to achieve consistency with the security protection granularity, thereby avoiding the leakage of security information.

[0108] This embodiment of the disclosure returns the final secure memory access information (final physical address, access permissions after security checks, and effective page size) to the front-end processing unit of the MMU in the current cycle after downgrading the page table mapping granularity. This avoids further table lookup processes, speeds up the overall MMU access process, and enables the instruction or data end to obtain the physical address as soon as possible, thereby further improving performance.

[0109] In this embodiment, the degradation flag is stored in the entry corresponding to the address mapping relationship. If the subsequent memory access table lookup hits the entry, the data corresponding to the entry is read directly and only the final security table lookup protection is performed, which speeds up the access process.

[0110] This disclosure also provides an electronic device, Figure 6 This is a schematic block diagram of the electronic device provided in the embodiments of this disclosure, such as... Figure 6 As shown, the electronic device includes: at least one processor 601; at least one memory 602; and one or more I / O interfaces 603 connected between the processor 601 and the memory 602; wherein the memory 602 stores one or more computer programs that can be executed by at least one processor 601, and the one or more computer programs are executed by at least one processor 601 to enable at least one processor 601 to perform the above-described physical memory protection method.

[0111] In this embodiment of the disclosure, the processor 601 is a device with data processing capabilities, including but not limited to a central processing unit (CPU); the memory is a device with data storage capabilities, including but not limited to random access memory (RAM), more specifically such as SDRAM, DDR, etc., read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH); the I / O interface, or read-write interface, is connected between the processor and the memory, enabling information interaction between the memory and the processor, including but not limited to a data bus (Bus).

[0112] This disclosure also provides a computer-readable medium, which includes a computer program that, when executed by a processor, implements the aforementioned physical memory protection method.

[0113] This disclosure also provides a computer program product, which includes a computer program that, when executed by a processor, implements the aforementioned physical memory protection method.

[0114] Those skilled in the art will understand that all or some of the steps, systems, and devices disclosed above, as functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0115] In hardware implementations, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be executed by several physical components working together.

[0116] Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit (CPU), digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media and communication media. In embodiments of this disclosure, computer storage media include volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, and any other media that can be used to store desired information and can be accessed by a computer. In embodiments of this disclosure, communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

Claims

1. A method for protecting physical memory, characterized in that, The method, applied to the memory management unit (MMU) lookup unit, includes: During address translation, the page table mapping granularity determined by page table checks and the security protection granularity determined by security checks are obtained. In response to the security protection granularity being smaller than the page table mapping granularity, the first effective page size is set to the security protection granularity, and a degradation flag is generated; A first address mapping relationship including the degradation flag is generated, and the first address mapping relationship is stored in the MMU storage unit; the degradation flag is used to trigger a security check on the memory access request based on the security protection granularity when the memory access request hits an entry with the degradation flag in the MMU storage unit.

2. The method according to claim 1, characterized in that, The first address mapping relationship also includes a first virtual address and a first target physical address; wherein, the first target physical address is obtained by aligning and correcting the first physical page number determined by the page table check based on the security protection granularity and the first virtual address; the first virtual address is the virtual address requested for memory access during the address translation process.

3. The method according to claim 1, characterized in that, The first address mapping relationship also includes access permissions and / or the first effective page size, wherein the access permissions are determined based on the results of the page table check and the results of the security check.

4. The method according to claim 3, characterized in that, The steps for determining the access permissions include: Obtain the page table entries determined by the page table check, and obtain the basic page table permissions from the page table entries; Obtain the access permission decision result determined by the security check; Access permissions are determined based on the basic page table permissions and the access permission adjudication result.

5. The method according to claim 1, characterized in that, Also includes: In response to the fact that the security protection granularity is smaller than the page table mapping granularity, the page offset corresponding to the security protection granularity is extracted from the first virtual address; The first virtual address is the virtual address requested for memory access during the address translation process; Based on the first virtual address and the security protection granularity, the first physical page number is aligned and corrected to obtain a second physical page number that is aligned with the boundary of the security protection granularity. The first physical page number is determined based on the page table check; The second physical page number and the page offset are concatenated to obtain the first target physical address, which is the physical address obtained by converting the first virtual address during the address translation process.

6. The method according to claim 5, characterized in that, After concatenating the second physical page number and the page offset to obtain the first target physical address, and after setting the first effective page size to the security protection granularity, the method further includes: Within the current clock cycle, the first target physical address, the first effective page size, and access permissions are returned to the front-end processing unit of the MMU to which the MMU lookup unit belongs; wherein, the access permissions are determined after the page table check and the security check.

7. The method according to claim 1, characterized in that, After obtaining the page table mapping granularity determined by the page table check and the security protection granularity determined by the security check, the method further includes: In response to the security protection granularity being greater than or equal to the page table mapping granularity, a second address mapping relationship is generated and stored in the MMU storage unit.

8. The method according to claim 1, characterized in that, After storing the first address mapping relationship in the MMU storage unit, the method further includes: In response to a received memory access request that hits an entry in the MMU storage unit and that the entry carries the degradation flag, a security check at the security protection granularity is performed based on the second virtual address carried in the memory access request.

9. The method according to claim 1, characterized in that, Before obtaining the page table mapping granularity determined by the page table check and the security protection granularity determined by the security check, the method further includes: During the page table inspection process, for each level of page table, after completing the page table inspection of the page table and obtaining the physical base address of the next level page table, a security check is performed based on the physical base address of the next level page table; in response to the security check passing, the page table inspection of the next level page table is performed until the security check of the last level page table passes, thus obtaining the security protection granularity, which is the security protection granularity on which the security inspection of the last level page table is based.

10. An electronic device, characterized in that, It includes a memory and a processor; the memory stores a computer program that can be executed by the processor, and when the computer program is executed by the processor, it implements the physical memory protection method according to any one of claims 1 to 9.

11. A computer-readable medium, characterized in that, The device contains a computer program that, when executed by a processor, implements the physical memory protection method according to any one of claims 1 to 9.

12. A computer program product, characterized in that, It includes a computer program that, when executed by a processor, implements the physical memory protection method according to any one of claims 1 to 9.

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