Method, system, and medium for automatically converting simulation waveforms to ATE test vectors

Abstract

The application relates to the technical field of semiconductor testing and electronic design automation, and provides a method, a system and a medium for automatically converting simulation waveforms into ATE test vectors, wherein a test excitation is run through a simulation tool, changes of top-level input and output port signals are recorded into a standard waveform exchange format VCD waveform file by using a system task of a hardware description language, a vector format conversion tool is called to convert the VCD waveform file into a vector format VEC file containing only top-level port logic values, time point step alignment preprocessing is performed on the VEC file, and finally, based on a time difference value between adjacent time points in an aligned time point sequence and a preset step length, the number of repetitions between each adjacent time point pair is calculated to fold and express the formatted signal vector, so that the simulation waveforms are automatically converted into an ATE test pattern file, the test program development efficiency is improved, accuracy is ensured, and reusability is enhanced.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor testing and electronic design automation (EDA) technology, and relates to a method, system and medium for automatically converting simulation waveforms into ATE test vectors. Background Technology

[0002] In the integrated circuit (IC) design and production testing process, after the chip design is completed and verified by pre-simulation, its functional behavior needs to be converted into test vector files executable by automated test equipment (ATE). Typical test vector files include pin definition files. .dec), test plan file ( .pln) and test graphic files ( .pat (i.e., PAT file). Among them, the pin definition file and test plan file form the stable skeleton of the test program, exhibiting high inheritability. This is because they constitute a general framework for the test program; engineers typically only need to make minor adjustments, such as modifying pin mappings or adding new test items, to reuse it. In contrast, the test graphic file contains frequently changing test content and has low inheritability.

[0003] The traditional technique for generating test pattern files involves test engineers directly writing them based on chip specifications. However, this method has the following drawbacks: numerous chip interface signals and complex timing sequences lead to a large workload for manual writing and are prone to errors; test pattern files are strongly dependent on specific chip designs, and once the design changes or different chips are tested, the original test pattern files are essentially unusable and need to be rewritten; there is no unified universal standard for test pattern file formats in the ATE field, and the formats of different manufacturers vary greatly, making test program portability difficult and lacking standardization; front-end simulation has generated a large amount of verification stimuli and waveform data, but this data cannot be directly reused for ATE test generation, resulting in repetitive work and a waste of simulation resources.

[0004] Some existing technologies attempt to convert simulated waveforms into ATE vectors through fixed-period segmentation. However, this method assumes that the signal changes according to a fixed period, which cannot flexibly adapt to different test timing granularity requirements and does not support vector folding and compression. Therefore, there is an urgent need for a method to flexibly generate ATE test patterns to improve test program development efficiency, ensure accuracy, and enhance reusability. Summary of the Invention

[0005] To address the problems existing in the prior art, this invention proposes a method, system, and medium for automatically converting simulation waveforms into ATE test vectors, which can automatically convert simulation waveforms into ATE test graphics.

[0006] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions: On the one hand, a method for automatically converting simulation waveforms into ATE test vectors is provided, including the following steps: The test stimulus is run using simulation tools, and the changes in the top-level input / output port signals are recorded as standard waveform exchange format VCD waveform files using system tasks in hardware description language; the VCD waveform files only record signal values ​​at the time points when the signal changes. The vector format conversion tool is invoked to convert the VCD waveform file into a vector format VEC file containing only the logic values ​​of the top-level ports. The conversion includes extracting the logic values ​​of the top-level ports at each transition time point in the VCD waveform file, forming a two-dimensional vector table with time as the row index and the top-level port signal as the column index. The VEC file undergoes time step alignment preprocessing. This preprocessing includes removing time points in the VEC file whose time values ​​are less than a preset step size and their corresponding data rows. The remaining time points are then aligned to integer multiples of the preset step size according to a preset rounding direction. Specifically, when the rounding direction is upward, the data is aligned to the smallest integer multiple of the original time value that is greater than or equal to the original time value. When the rounding direction is downward, the data is aligned to the largest integer multiple of the original time value that is less than or equal to the original time value. When multiple different original time points are aligned to the same integer multiple of the time value, only the data row with the largest original time value is retained, and the rest are discarded. Based on the time difference between adjacent time points in the aligned time point sequence and the preset step size, the number of repetitions between each pair of adjacent time points is calculated. The number of repetitions is used to fold and express the formatted signal vector, generating a test graphic PAT file that conforms to the format of the ATE platform of the automated test equipment.

[0007] In one embodiment, the preset step size and preset rounding direction are obtained by parsing a configuration file. The process of parsing the configuration file includes: Read the global configuration section in the configuration file to obtain global configuration parameters; Identify the name pattern markers in the configuration file and obtain the corresponding local configuration parameters for the name pattern. When the same configuration item is defined in both global configuration parameters and name pattern local configuration parameters, the name pattern local configuration parameters override the global configuration parameters. The configuration parameters also include at least one of the following: signal spacing, signal type redefinition configuration, fixed value configuration, ignore time rule configuration, and serial input parallel output annotation configuration.

[0008] In one embodiment, the method for automatically converting the simulation waveform into an ATE test vector further includes: Parse the VEC file to obtain the original list of signal names; Read the additional signal definition section in the configuration file, which is delimited by a start marker and an end marker, and obtain the name and attributes of the additional signals; The additional signals are embedded into the corresponding positions in the original signal name list according to the insertion positions indicated by the start and end markers, forming a uniform signal sequence for subsequent formatting.

[0009] In one embodiment, the process of calculating the number of repetitions between adjacent time point pairs based on the time difference between adjacent time points in the aligned time point sequence and a preset step size includes: Arrange the aligned time points into a sequence in ascending chronological order. ; For each pair of adjacent time points T i-1 and T i ,according to Calculate the number of repetitions (RPT) between adjacent time points. i , where step_length is the preset step size, i=1,2,…,N.

[0010] In one embodiment, the method for automatically converting the simulation waveform into ATE test vectors further includes repairing the X-state of the input signal in the VEC file: Check the input signals with an invalid level X in the first and second sorted data rows of the VEC file; For the input signal in state X, search row by row along the column containing the signal in the direction of increasing time to locate the first row with a definite logic value of 0 or 1; To determine the logic value to replace the X value of the input signal in the first or second data row.

[0011] In one embodiment, before generating the test graph PAT file, the data rows of the VEC file are formatted for ATE format: For signals whose signal type is configured as input, the logical value of the signal at each time point is mapped to a binary character 0 or 1. For signals whose signal type is configured as output, the logic value of the signal at each time point is mapped to a low-level character L, a high-level character H, or an invalid level character X. Read the fixed value configuration and force the target signal specified in the fixed value configuration to be assigned the constant value set in the fixed value configuration; Read the ignore time rule configuration, and forcibly convert the value of the output signal to X for the time period specified in the ignore time rule configuration; Read the signal spacing and insert the corresponding number of separators between each adjacent signal column according to the spacing value specified in the signal spacing.

[0012] In one embodiment, the method for automatically converting the simulation waveform into ATE test vectors further includes an automatic generation process for serial input parallel output annotations: After reading the concatenation syntax expression defined in the serial input parallel output comment configuration, extract the multi-signal identifier sequence and end-order indicator that participate in serial sampling; the end-order indicator includes the most significant bit priority and the least significant bit priority; Read the enable signal identifier and valid level value defined in the serial input parallel output comment configuration; Traverse the formatted data rows at each time point. When the value of the enable signal in the current data row matches the effective level value, acquire the current value of each signal in the multi-signal identifier sequence, construct a multi-bit wide word according to the bit arrangement direction specified by the end sequence indicator, and append the multi-bit wide word to the sampling buffer. When the value of the enable signal in the current data line does not match the effective level value, all the multi-bit wide words accumulated in the sampling buffer are concatenated into a complete bit string in the order of acquisition time, the bit string is converted into a hexadecimal value, and a serial input parallel output annotation containing the hexadecimal value is generated in the current data line. When the value of the enable signal changes from a non-matching data row to a matching data row for the first time, a sampling start marker annotation is generated.

[0013] In one embodiment, the process of generating a test graphic PAT file conforming to the format of the automated test equipment (ATE) platform includes: Append the aligned time value corresponding to each data row to the end of each data row to form a vector time point annotation; Generate a folded PAT file; in this process, all data lines after formatting are scanned, and consecutive line segments with identical vector values ​​are identified. For each line segment, the vector value of the first line is retained, and the number of repetitions is used as the repetition instruction to replace the remaining repetitive lines, resulting in a compressed test graphic file suitable for production testing scenarios. Generate an expanded PAT file; in this process, all formatted data rows are output in chronological order without folding or compressing any rows, resulting in an expanded test graphic file that retains complete timing information. In this process, the folded version of the PAT file and the expanded version of the PAT file are generated simultaneously in the same conversion process.

[0014] On the other hand, a system for automatically converting simulation waveforms into ATE test vectors is also provided, including: The VCD generation module controls the simulation tool to record changes in the top-level input / output port signals as VCD waveform files through system tasks in the hardware description language; the VCD waveform files only record signal values ​​at the points in time when the signal changes. The VCD to VEC module is used to convert VCD waveform files into VEC files that contain only the logic values ​​of the top-level ports. The conversion includes extracting the logic values ​​of the top-level ports at each transition time point in the VCD waveform file and forming a two-dimensional vector table with time as the row index and the top-level port signals as the column index. The VEC preprocessing module is used to perform time point step size alignment preprocessing on VEC files. The alignment preprocessing includes removing time points in the VEC file whose time values ​​are less than a preset step size and their corresponding data rows, and aligning the time values ​​of the remaining time points to integer multiples of the preset step size according to a preset rounding direction. Specifically, when the rounding direction is upward, the alignment is to the smallest integer multiple of the original time value that is greater than or equal to the original time value; when the rounding direction is downward, the alignment is to the largest integer multiple of the original time value that is less than or equal to the original time value. When multiple different original time points are aligned to the same integer multiple of time value, only the data row with the largest original time value is retained and the rest are discarded. The file generation module is used to calculate the number of repetitions between adjacent time points based on the time difference between adjacent time points in the aligned time point sequence and the preset step size. The number of repetitions is used to fold and express the formatted signal vector to generate a test graphic PAT file that conforms to the format of the ATE platform of the automated test equipment.

[0015] On another front, a computer-readable storage medium is also provided, on which a computer program is stored, which, when executed by a processor, implements the method described above for automatically converting simulation waveforms into ATE test vectors.

[0016] One of the above technical solutions has the following advantages and beneficial effects: The method, system, and medium for automatically converting simulated waveforms into ATE test vectors described above involve running test stimuli using simulation tools, recording the changes in top-level input / output port signals into a standard waveform exchange format VCD waveform file using a system task in a hardware description language, and then calling a vector format conversion tool to convert the VCD waveform file into a vector format VEC file containing only the logic values ​​of the top-level ports. The VEC file is then preprocessed with time step alignment. Finally, based on the time difference between adjacent time points in the aligned time sequence and the preset step size, the number of repetitions between each pair of adjacent time points is calculated. The number of repetitions is used to fold and represent the formatted signal vector, generating a test graphic PAT file conforming to the ATE platform format. This achieves automatic conversion of simulated waveforms into ATE test graphic files, improving test program development efficiency, ensuring accuracy, and enhancing reusability. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a flowchart illustrating a method for automatically converting simulation waveforms into ATE test vectors in one embodiment. Figure 2 This is a schematic diagram of the overall process in one embodiment; Figure 3 This is a schematic diagram of the VEC to PAT conversion process in one embodiment; Figure 4 This is a schematic diagram illustrating the global and local configuration coverage relationship in one embodiment; Figure 5 This is a schematic diagram illustrating a time-point preprocessing example in one embodiment; Figure 6 This is a schematic diagram of SIPO sampling and annotation generation in one embodiment; Figure 7 This is a schematic diagram comparing the folding and unfolding modes in one embodiment; wherein, Figure 7 (a) is the unfolded mode. Figure 7 (b) is the folded mode; Figure 8 This is a block diagram of the module architecture of a system that automatically converts simulation waveforms into ATE test vectors in one embodiment. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention.

[0020] It should be noted that, in this document, the reference to "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The presentation of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will understand that the embodiments described herein can be combined with other embodiments. The term "and / or" as used herein refers to any combination of one or more of the associated listed items, and all possible combinations, and includes such combinations.

[0021] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0022] It is understood that this invention aims to solve the following technical problems: First, how to improve the inheritance of test programs to reduce the risks caused by secondary programming. Second, how to automatically process VCD waveform files generated by pre-simulation to generate test graphic files that meet the requirements of a specific ATE platform. Third, how to retain chip input stimuli and expected outputs during the conversion process, and remove internal signal redundancy and eliminate clock signal interference. Fourth, how to achieve flexible and configurable time granularity alignment and vector folding compression under event-driven non-uniform time point distribution conditions. Fifth, how to achieve dual-mode output of folded and unfolded test graphic files to adapt to different scenarios of production testing and debugging analysis.

[0023] In one embodiment, such as Figure 1 As shown, a method for automatically converting simulation waveforms into ATE test vectors is provided, which may include the following processing steps S10 to S16: S10, run the test stimulus through the simulation tool, and use the system task of the hardware description language to record the changes of the top-level input and output port signals as a standard waveform exchange format VCD waveform file; the VCD waveform file only records the signal value at the time point when the signal changes.

[0024] Specifically, in the pre-simulation environment, test stimuli are run using standard simulation tools such as VCS or ModelSim. In the top-level test platform, system tasks (such as $dumpvars and $dumpfile) in the hardware description language SystemVerilog record signal changes from the top-level input / output (I / O) ports to a VCD file. The user specifies the output path of the VCD file via command-line arguments.

[0025] Because the VCD format follows the IEEE 1364 standard, it only records the time points when the signal value changes. Therefore, the VCD file stores discrete transition time points and their corresponding signal values, rather than the values ​​at every moment on a continuous time axis. Users can design the input excitation signal according to the step size characteristics of the ATE machine, aligning the edges of the excitation signal changes with the ATE test cycle.

[0026] S12, invoke the vector format conversion tool to convert the VCD waveform file into a vector format VEC file containing only the logic values ​​of the top-level ports; the conversion includes extracting the logic values ​​of the top-level ports at each transition time point in the VCD waveform file to form a two-dimensional vector table with time as the row index and the top-level port signal as the column index.

[0027] Specifically, this step utilizes external tools such as vcd2vec or a self-developed VCD parser to read the VCD file and parse its hierarchical signal structure. VCD files typically contain all signals in the chip design, including top-level port signals, internal signals of each submodule, and clock signals. This step extracts the logic values ​​of the top-level ports and discards all signals from internal modules, thus eliminating information redundancy. Simultaneously, the clock signal, as a periodic reference signal, has deterministic transitions in each cycle and does not need to be included in the excitation vector; therefore, the clock signal is excluded from the output vector table. After the above filtering, the remaining signals are arranged according to time points, forming a two-dimensional table structure with time as the row, signal as the column, and each cell representing the logic value of the signal at the current time point. Each row of the resulting VEC file corresponds to a signal transition time point, and each column corresponds to a retained top-level port signal.

[0028] S14, Perform time step alignment preprocessing on the VEC file; the alignment preprocessing includes removing time points in the VEC file whose time values ​​are less than the preset step size and the corresponding data rows, and aligning the time values ​​of the remaining time points to integer multiples of the preset step size according to the preset rounding direction; wherein, when the rounding direction is upward, it is aligned to the smallest integer multiple of the original time value that is greater than or equal to the original time value, and when the rounding direction is downward, it is aligned to the largest integer multiple of the original time value that is less than or equal to the original time value. When multiple different original time points are aligned to the same integer multiple of time value, only the data row with the largest original time value is retained and the rest are discarded.

[0029] Specifically, the preset step size is a configurable parameter controlling the granularity of time alignment, measured in nanoseconds, representing the duration of a basic test cycle in ATE testing. The rounding direction is a configurable parameter controlling the alignment strategy, with options for rounding up or rounding down. This step first iterates through all time points in the VEC file, removing those time points whose time values ​​are strictly less than the preset step size, along with their corresponding complete data rows, from the processing sequence. These removed time points are typically located at the beginning of the simulation, and their duration is much shorter than a complete test cycle, making it impossible to form a valid test vector on the ATE.

[0030] Subsequently, for each retained time point, an alignment operation is performed according to the rounding direction setting. When the rounding direction is set to round up, the time value is aligned upwards to an integer multiple greater than or equal to the minimum step size of that time value; when the rounding direction is set to round down, the time value is aligned downwards to an integer multiple less than or equal to the maximum step size of that time value. Since VCD files only record at signal transitions, the intervals between the original time points are uneven. Therefore, after rounding and alignment, multiple data lines with different original time values ​​may be aligned to the same integer multiple time value. For such repetitions, this step selects to retain the line with the largest original time value and deletes the remaining repetitive aligned data lines. The principle behind this processing is that the largest original time value means that the signal state recorded in that data line is closest to the alignment time and best represents the actual logical value of each signal at that alignment time.

[0031] S16. Based on the time difference between adjacent time points in the aligned time point sequence and the preset step size, calculate the number of repetitions between each pair of adjacent time points, and use the number of repetitions to fold and express the formatted signal vector to generate a test graphic PAT file that conforms to the format of the ATE platform of the automatic test equipment.

[0032] Specifically, after completing the time step alignment preprocessing, a sequence of aligned time points is obtained, arranged in ascending order of time. For each pair of adjacent time points in the sequence, their time difference is calculated, and the time difference is divided by the preset step size to obtain the number of repetitions between that pair of adjacent time points. The physical meaning of the number of repetitions can be: in ATE testing, the number of test cycles in which the signal value remains unchanged between the previous aligned time point and the next aligned time point. In the PAT file, for multiple consecutive test cycles with identical vector values, there is no need to repeat them line by line. Instead, they are represented as a single vector combined with the repetition count instruction, which is folded to significantly reduce the size of the PAT file. The signal vectors in the PAT file are formatted, with input signals represented as binary values ​​0 or 1, and output signals represented as low level L, high level H, or invalid level X. In addition, the aligned time value corresponding to each row vector is appended as a comment at the end of each row vector to enhance readability and suitability for subsequent waveform positioning and debugging.

[0033] It is understood that this embodiment uses the standard waveform exchange format VCD to automatically generate the test graphics PAT file required by the automatic test equipment ATE, which can be integrated into the main running script (run.py) for one-click execution.

[0034] The method described above for automatically converting simulated waveforms into ATE test vectors involves running test stimuli using simulation tools, recording the changes in top-level input / output port signals into a standard waveform exchange format VCD waveform file using system tasks in a hardware description language, and then calling a vector format conversion tool to convert the VCD waveform file into a vector format VEC file containing only the logic values ​​of the top-level ports. The VEC file is then preprocessed with time step alignment. Finally, based on the time difference between adjacent time points in the aligned time sequence and the preset step size, the number of repetitions between each pair of adjacent time points is calculated. The number of repetitions is used to fold and represent the formatted signal vector, generating a test graphic PAT file that conforms to the ATE platform format. This method automatically converts simulated waveforms into ATE test graphic files, improving test program development efficiency, ensuring accuracy, and enhancing reusability.

[0035] Among them, such as Figure 2 As shown, it can output both folded and expanded PAT files simultaneously. The folded PAT file uses repetition count instructions to fold repeated test vectors to adapt to production testing scenarios, while the expanded PAT file fully expands all time points to adapt to debugging and waveform comparison scenarios. The folded and expanded versions are output simultaneously in the same conversion process.

[0036] Thus, through VCD event-driven recording, VEC intermediate simplification, time-point step-size alignment preprocessing, and time difference-based repetition count pre-calculation, a fully automated conversion from simulation waveforms to ATE test vectors is achieved. Compared with existing technologies that directly cut simulation waveforms at fixed periods or sample them periodically and then compress them a posteriori, this design filters out internal signal redundancy and eliminates clock signal interference through the VEC intermediate format, solves the adaptation problem of non-uniform distribution of VCD event-driven time points through step-size alignment preprocessing, and achieves vector folding expression deeply coupled with the preset step-size alignment mechanism through time difference pre-calculation. This results in higher automation, greater configuration flexibility, and better debugging traceability.

[0037] In one embodiment, such as Figure 3 and Figure 4 As shown, the preset step size and preset rounding direction in step S14 above are obtained by parsing the configuration file. The process of parsing the configuration file may specifically include the following steps: Read the global configuration section in the configuration file to obtain the global configuration parameters. Identify the name pattern markers in the configuration file and obtain the corresponding name pattern (NAME_PATTERN) local configuration parameters, such as SPI_PATTERN (a standard timing waveform sequence / test vector used to verify or test the SPI interface). When the same configuration item is defined in both the global configuration parameters and the name pattern local configuration parameters, the name pattern local configuration parameters override the global configuration parameters. The configuration parameters also include at least one of the following: signal spacing (signal_space), signal type redefinition (input / output) configuration, fixed value (fixed_value) configuration, dont_care_time rule configuration, and serial input parallel output (SIPO) annotation configuration.

[0038] Specifically, the configuration file uses a text format and is divided into a global configuration section and an optional name-pattern local configuration section. The global configuration section defines default parameter values ​​applicable to all test modes, including basic parameters such as the preset step length, rounding direction, and signal spacing. Name-pattern local configuration sections are identified by name-pattern tags, and the parameter definitions within them only apply to the test mode specified by that name-pattern tag. When the system parses the configuration file, it first loads all parameters from the global configuration section as baseline values. Then, it checks if a name-pattern tag matching the current test mode name exists. If it does, it reads the parameters from that local configuration section and overwrites the corresponding global configuration parameters with the local configuration parameters.

[0039] This coverage mechanism allows a single configuration file to contain parameter configurations for multiple test modes simultaneously. Users can switch test modes without modifying or replacing the configuration file; they only need to specify different mode names in the command line. The preset step size controls the granularity of time alignment, i.e., the duration of a basic test cycle in ATE testing. The signal spacing controls the number of separators between signal columns in the formatted output, enhancing the file's human readability. The rounding direction controls the time alignment strategy; rounding up and rounding down are suitable for different timing constraints. The signal type redefinition configuration allows users to reassign a signal of a default type in VCD as an input or output type. The fixed value configuration forces a specified signal to a constant value. The ignore time rule configuration marks a specified output signal as not participating in comparison for a specified time period. The serial input parallel output annotation configuration defines rules for serial sampling and annotation generation of multiple parallel signals.

[0040] In one embodiment, the method for automatically converting the above-mentioned simulation waveform into ATE test vectors, after resolving the configuration file, may further include the following processing: Parse the VEC file to obtain the original signal name list; read the additional signal definition section in the configuration file delimited by start and end markers to obtain the names and attributes of the additional signals; embed the additional signals into the corresponding positions in the original signal name list according to the insertion positions indicated by the start and end markers to form a uniform signal sequence for subsequent formatting.

[0041] Specifically, the VEC file only contains the top-level port signals extracted and retained from the VCD. In actual ATE testing, it may be necessary to add additional signals to the vector, such as independent clock signals not recorded by the VCD, power supplies or reference signals provided by the test equipment, etc. The configuration file is marked with a start tag. <begin>and end marker <end>Define an additional signal definition section where the user lists the names and attributes of the additional signals, such as signal type and default values. The positions of the start and end markers in the original signal list determine the specific positions in the signal sequence where these additional signals are inserted; for example, a clock signal can be inserted at the very beginning of the signal sequence. The resulting unified signal sequence will contain a complete arrangement of the original VEC signal and the additional signals, for use in subsequent formatting steps.

[0042] In one embodiment, such as Figure 5 As shown, regarding step S16 above, the process of calculating the number of repetitions between each pair of adjacent time points based on the time difference between adjacent time points in the aligned time point sequence and the preset step size can specifically include the following processing: Arrange the aligned time points into a sequence in ascending chronological order. For each pair of adjacent time points T i-1 and T i ,according to Calculate the number of repetitions (RPT) between adjacent time points. i , where step_length is the preset step size, i=1,2,…,N.

[0043] Taking specific values ​​as an example, assuming that after the alignment preprocessing in step S14, the obtained alignment time point sequence is 0 nanoseconds, 200 nanoseconds, and 400 nanoseconds, with a preset step size of 100 nanoseconds. For the pair of adjacent time points T0=0 and T1=200, the time difference is 200 nanoseconds, and RPT1=200 / 100=2, indicating that there are two test cycles between 0 nanoseconds and 200 nanoseconds, during which the signal value remains unchanged. For the pair of adjacent time points T1=200 and T2=400, the time difference is also 200 nanoseconds, and RPT2=200 / 100=2, indicating that there are also two test cycles between 200 nanoseconds and 400 nanoseconds.

[0044] In the folded version of the PAT file, the above information can be expressed as follows: a line of vector values ​​at 0 nanoseconds, followed by a repeat instruction repeated twice; then a line of vector values ​​at 200 nanoseconds, followed by a repeat instruction repeated twice; and finally a line of vector values ​​at 400 nanoseconds and a stop instruction. Meanwhile, the expanded version of the PAT file will output five lines for 0 nanoseconds, 100 nanoseconds, 200 nanoseconds, 300 nanoseconds, and 400 nanoseconds, for easy comparison.

[0045] By using this method of pre-calculating the number of repetitions based on time difference, the number of repetitions in this embodiment is tightly coupled with the preset step size alignment mechanism. When the user adjusts the preset step size configuration, the number of repetitions automatically changes accordingly, without the need to redesign the vector structure.

[0046] In one embodiment, the method for automatically converting the simulation waveform into ATE test vectors described above may further include the following operation to repair the X-state (i.e., invalid level X-state) of the input signal in the VEC file, either before the time step alignment preprocessing of the VEC file in step S14 or after the conversion to the VEC file in step S12: Check the input signals with invalid level X in the first and second sorted data rows of the VEC file; for the input signal with X state, search row by row along the column where the signal is located in the direction of increasing time to locate the first row with a definite logic value of 0 or 1; replace the X value of the input signal with X state in the first or second data row with the determined logic value.

[0047] It's understandable that the purpose of X-state repair is to eliminate the interference caused by the brief invalid levels generated during the initialization phase of the simulation environment on subsequent vector generation. In pre-simulation, when the simulator initializes at time zero, some registers or signals may not yet have been assigned definite values, exhibiting an invalid level X. This X-state is usually cleared by the reset logic or initialization stimulus in the design within the first few time points of the simulation.

[0048] However, the VCD file accurately records these initial X values. If not processed during subsequent vector generation, these X values ​​may be propagated into the formatted vector, leading to unexpected test results during ATE testing. This embodiment's X-state repair only applies to the first and second lines of the VEC file, because in a normal design, invalid levels during the initialization phase will not persist beyond the third time point. The repair strategy is a backward search, i.e., searching line by line from the line containing the X state in the direction of increasing time, taking the first occurrence of a definite logic value (0 or 1) as the replacement value.

[0049] In one embodiment, such as Figure 3 As shown, before generating the test graphic PAT file, step S16 may also include formatting each data row of the VEC file in ATE format as follows: For signals configured as inputs, the logic values ​​of the signal at each time point are mapped to binary characters 0 or 1. Input signals are signals driven to the chip input pins by the test equipment; their logic values ​​only need to distinguish between low and high levels, and therefore can be mapped to simple 0 and 1 characters.

[0050] For signals configured as outputs, the logic values ​​of the signal at each time point are mapped to a low-level character L, a high-level character H, or an invalid level character X. The output signal is the chip's response to the input stimulus, captured and compared by the test equipment. L indicates that a low level is expected to be captured, H indicates that a high level is expected to be captured, and X indicates that the output value at that moment is not included in the comparison.

[0051] The system reads the fixed-value configuration and forces the target signal specified in the configuration to be assigned the constant value set in the fixed-value configuration. After reading the fixed-value configuration, it iterates through all data rows. For the target signal specified in the configuration, regardless of its value in the original VEC data or its value after input-output mapping, it can be replaced with the constant value set in the fixed-value configuration. This is suitable for test scenarios that require injecting a fixed reference level into the vector.

[0052] Read the ignore time rule configuration, and forcibly convert the value of the output signal to X within the time period specified in the ignore time rule configuration.

[0053] The `dont_care_time` rule configuration can be understood to include three elements: the target output signal identifier, the start time value, and the end time value. Upon reading the `dont_care_time` rule configuration, for the specified target output signal, the value of the output signal is forcibly converted to X at each time point within the closed interval from the start time value to the end time value. In ATE testing, X signifies that the output signal is not included in the comparison within the current test cycle; that is, the test equipment does not judge the output result of this signal. Therefore, it can be applied to time periods when the chip output is not yet stable or the output result is not meaningful.

[0054] Read the signal spacing and insert the corresponding number of separators between each adjacent signal column according to the spacing value specified in the signal spacing.

[0055] As you can understand, the signal_space configuration specifies the number of blank separators inserted between adjacent signal columns. In the formatted output of a PAT file, the character values ​​of each signal are tightly packed by default, making them difficult for users to read and inspect. The signal_space configuration, by inserting a specified number of separators between adjacent signal columns, makes the output visually appear as a neatly aligned table, improving the efficiency of manual review and troubleshooting.

[0056] In one embodiment, the method for automatically converting the simulation waveform into ATE test vectors may further include an automatic generation process for Serial Input Parallel Output (SIPO) annotations, which are used to reflect the serial data content carried by multiple parallel signals in a readable hexadecimal form in a PAT file during a specific enable time period.

[0057] After reading the concatenation syntax expression defined in the serial input parallel output comment configuration, extract the multi-signal identifier sequence and end order indicator that participate in serial sampling; the end order indicator includes the most significant bit priority and the least significant bit priority; read the enable signal identifier and valid level value defined in the serial input parallel output comment configuration.

[0058] Specifically, such as Figure 6 As shown, firstly, the serial input parallel output comment configuration is read. This configuration contains two core definitions: a concatenation syntax expression and an enable signal definition. The concatenation syntax expression adopts a common concatenation syntax format in hardware description languages, such as {IN4,IN3,IN2,IN1}.<LSB, MSB> Ending pointer<LSB, MSB> Used to indicate the bit arrangement direction when constructing a multi-bit wide word, including<MSB, LSB> Most significant bit first MSB and<LSB, MSB> There are two options for Least Significant Bit (LSB) priority. For example, a typical concatenation syntax expression is {IN4,IN3,IN2,IN1}, which, combined with the end-order indicators MSB and LSB, indicates that the values ​​of the four signals IN4, IN3, IN2, and IN1 are combined as the most significant bit to the least significant bit of a multi-bit wide word. The enable signal definition contains two elements: the identifier of the enable signal and its valid level value. The valid level value specifies the logic value at which sampling is initiated by the enable signal.

[0059] The process iterates through the formatted data rows at each time point. When the enable signal value in the current data row matches the valid level value, the current value of each signal in the multi-signal identifier sequence is acquired. A multi-bit wide word is then constructed according to the bit arrangement direction specified by the end sequence indicator and appended to the sampling buffer. During the iteration process, the value of the enable signal in the current data row is continuously monitored to ensure it matches the valid level value.

[0060] When the value of the enable signal in the current data line does not match the effective level value, all the multi-bit wide words accumulated in the sampling buffer are concatenated into a complete bit string in the order of acquisition time, the bit string is converted into a hexadecimal value, and a serial input parallel output annotation containing the hexadecimal value is generated in the current data line; when the value of the enable signal changes from a non-matching data line to a matching data line for the first time, a sampling start mark annotation (i.e., # begin sample) is generated.

[0061] Specifically, when the value of the enable signal matches the valid level value, the sampling state is entered. In the sampling state, the data is processed according to the concatenation syntax expression {IN4,IN3,IN2,IN1}.<LSB, MSB> The system reads the formatted values ​​of each signal in the current data line sequentially, based on the order of the signal identifier IN and the bit arrangement direction specified by the end-order indicator. These values ​​are then concatenated into a multi-bit wide word and appended to the sampling buffer. If the data line is the first data line in the acquisition state, a sampling start marker is generated for that data line.

[0062] When the enable signal value does not match the valid level value, the system enters output mode if the sampling buffer is not empty. In output mode, all accumulated multi-bit wide words in the sampling buffer are concatenated into a complete bit string according to the chronological order of acquisition. This bit string is converted to a hexadecimal value, and a serial input parallel output comment containing this hexadecimal value is generated in the current data line. The comment format is #SIPO:0x.... After outputting, the sampling buffer is cleared to prepare for the next sampling.

[0063] The aforementioned multi-signal SIPO sampling mechanism embeds a complete serial data capture state machine into the PAT file. The effective time period of the enable signal defines the transmission window of the serial data, the concatenation syntax defines the arrangement of data bits, and the hexadecimal output provides a user-readable data digest.

[0064] In one embodiment, the process of generating the test graphic PAT file conforming to the format of the automated test equipment (ATE) platform in step S16 may further include the following processing: Append the aligned time value corresponding to each data line to the end of the data line to form a vector time point annotation. The annotation format is #(time value)ns. The vector time point annotation allows each line of the PAT file to be independently traced back to the corresponding time in the simulation waveform without relying on the context to infer the time position of the vector line, which greatly improves the readability of the PAT file.

[0065] Generate a folded PAT file; in this process, all formatted data rows are scanned, and rows with consecutive vector values ​​that are exactly the same are identified. For each row, the vector value of the first row is retained and the number of repetitions is used as the repetition instruction to replace the remaining repetitive rows, resulting in a compressed test graphic file suitable for production testing scenarios.

[0066] It's understandable that identical vector values ​​mean that the signal character values ​​in each line within a segment are completely identical. For each such segment, only the complete vector value of the first line is retained, and the output of the remaining lines within that segment is replaced with the repetition count as the parameter for the repetition count instruction. Taking a segment with three identical vectors as an example, the folded output format is a repetition count instruction with the first line's vector value as one line and the repetition count instruction repeated twice. Finally, a stop instruction is output after the vector line corresponding to the last time point. The folded PAT file is suitable for production testing scenarios, as its file size is significantly smaller than the expanded version, reducing the storage and loading burden on ATE equipment.

[0067] Generate an expanded PAT file; in this process, all formatted data rows are output in chronological order without folding or compressing any rows, resulting in an expanded test graphic file that retains complete timing information. The folded and expanded PAT files are generated simultaneously in the same conversion process.

[0068] As can be understood, when generating the expanded PAT file, all formatted data rows are output in chronological order without folding or compressing any rows. A vector is output for each time point that is an integer multiple of the aligned time step. For intermediate time points filled with repetitions between the original aligned time points, their vector values ​​are inherited from the previous aligned time point. The expanded PAT file retains complete timing information, making it suitable for debugging, troubleshooting, and cycle-by-cycle comparison with simulation waveforms. Engineers can match each line of the expanded PAT file with the corresponding time point in the simulation waveform to quickly locate locations where vector values ​​differ from expected values.

[0069] Folded PAT file (i.e.) _folded.pat file) and expanded PAT file (i.e. The _expanded.pat file is generated simultaneously within the same conversion process, allowing users to obtain both versions of the file after running the conversion script once, without needing to execute separate conversion commands. (Example: Comparison of folded and expanded modes) Figure 7 As shown, TS1 is the reference timing step, and STOP is the timing termination marker. Figure 7 (a) is the unfolded mode. Figure 7 (b) is the folded mode.

[0070] The above method can be summarized as the following concatenation execution: The main running script (run.py) connects the above three steps in a unified command-line interface: it receives the VCD save path as a parameter, sequentially calls VCS simulation, VCD to VEC conversion and VEC to PAT conversion, and finally outputs a PAT file.

[0071] In some implementations, a complete conversion process for the above method is also provided: Suppose there is a top-level module `top` of a chip, whose ports include a clock signal `clk`, a reset signal `rst_n`, a 4-bit input data bus `data_in[3:0]`, and a 4-bit output data bus `data_out[3:0]`. The user wants to convert the VCD file generated by the top-level file `testbench`, which was written in the pre-simulation stage, into a PAT file executable by Chroma 3360.

[0072] Write the simulation script: Add an initial block to the top-level file `testbench` to generate waveform files (specify the waveform file name as `sim.vcd`, record signal changes at all levels, starting from the top-level signal of the module). Configure ATE parameters, such as writing a `vec2pat` file to define the signal type, preset step size of 100ns, signal spacing of 1, and SIPO rules, etc. Run the main script (i.e., execute `python run.py . / output / sim.vcd`).

[0073] The system response is as follows: The simulation tool is automatically started to run the simulation, and the system task in the test platform is used to generate the sim.vcd file; the vcd2vec tool is called to read sim.vcd, extract the logic values ​​of the ten top-level ports rst_n, data_in[3:0] and data_out[3:0], filter out the signals of each sub-module inside the chip, exclude the clock signal clk from the output vector table, and generate the sim.vec file; the vec2pat.py script is called to read sim.vec and the configuration file, and performs signal list construction, time step size alignment preprocessing, X-state repair, repetition count calculation, data formatting, serial input parallel output annotation generation and dual-mode output in sequence, and finally generates two files sim_folded.pat and sim_expanded.pat.

[0074] Load the sim_folded.pat file along with the pin definition file and test plan file into the ATE instrument to perform chip testing. When the chip design changes, users only need to modify the stimulus in the test platform and rerun the pythonrun.py command to obtain an updated PAT file, without manually rewriting the test vectors. Furthermore, if the test timing granularity needs to be adjusted, simply modify the preset step size parameter value in the configuration file and rerun the test; the system will automatically recalculate the alignment time points and the number of repetitions.

[0075] Taking the time point preprocessing and repetition calculation steps in the above complete conversion process as an example, the impact of parameter adjustment on the output is demonstrated.

[0076] Based on the same top-level module of the chip mentioned above, assuming the time point sequence extracted from the VEC file is 0 nanoseconds, 50 nanoseconds, 150 nanoseconds, and 320 nanoseconds, with the initial preset step size set to 100 nanoseconds and the rounding direction set to round up. After time point step size alignment preprocessing, the 50 nanosecond time point is deleted because it is smaller than the preset step size, 150 nanoseconds is rounded up to 200 nanoseconds, and 320 nanoseconds is rounded up to 400 nanoseconds. The aligned time point sequence is 0 nanoseconds, 200 nanoseconds, and 400 nanoseconds. The repetition count is calculated as follows: 0 to 200 is 2 repetitions, and 200 to 400 is 2 repetitions.

[0077] If the user adjusts the preset step size to 200 nanoseconds and re-executes the transformation, the 50 nanosecond and 150 nanosecond times are both less than 200 nanoseconds and are therefore deleted. The 320 nanosecond time is rounded up to 400 nanoseconds, resulting in an aligned time sequence of 0 nanoseconds and 400 nanoseconds. The repetition count is calculated as follows: the time difference between 0 and 400 is 400 nanoseconds, which, divided by the preset step size of 200 nanoseconds, yields two repetitions. It is evident that adjusting the preset step size parameter automatically causes a linked change in the preprocessing result and the number of repetitions, eliminating the need for manual intervention by the user in the intermediate process.

[0078] The method described above for automatically converting simulation waveforms into ATE test vectors eliminates the need for manual intervention throughout the entire process, from simulation waveforms to ATE test graphics, significantly reducing test development workload and avoiding errors caused by manual coding. The main runtime script links simulation execution, format simplification, and intelligent conversion into a unified command-line interface. Users only need to specify the VCD file save path to generate a PAT file with a single click, achieving a high degree of automation. Utilizing existing pre-simulation test stimuli to directly generate PAT files means that after chip design changes, only rerunning the simulation is required to update the test graphics. Furthermore, a two-level parameter management mechanism—global configuration and name-mode local configuration—allows the same configuration file to serve multiple test modes simultaneously without maintaining multiple independent configuration files, significantly improving the test program's inheritance and reusability.

[0079] It also supports a wealth of configurations, including adjustable preset step size, selectable rounding direction, variable signal spacing, fixed value enforcement, ignoring time rules, and multi-signal serial input parallel output annotations, adapting to different testing scenarios. The preset step size controls the granularity of time alignment, the rounding direction (up or down) determines the alignment strategy, signal spacing enhances output readability, and fixed values ​​and ignoring time rules meet the need for fine-grained control of specific signals and time periods, offering high flexibility. It outputs both folded and expanded versions of the PAT file. The folded version meets the efficiency requirements of production testing, while the expanded version facilitates engineers' comparison of simulation waveforms with ATE expected values. Vector execution time annotations are appended to the end of each vector line, along with hexadecimal annotations for multi-signal serial input parallel output, significantly improving the readability and traceability of the PAT file. VCD is an IEEE standard format supported by all mainstream EDA tools, ensuring the universality of the input source, independent of specific simulators, and forming a standardized input. The script incorporates numerous configuration checks and time point alignment warnings to help users quickly locate problems. It issues a warning when multiple original time points are aligned to the same integer multiple, making the time point preprocessing process transparent and traceable, achieving comprehensive error detection.

[0080] It should be understood that, although Figure 1 The steps are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order in which these steps are executed; they can be performed in other orders. Figure 1 At least some of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0081] In one embodiment, such as Figure 8 As shown, a system for automatically converting simulation waveforms into ATE test vectors is also provided, including a VCD generation module 11, a VCD to VEC conversion module 13, a VEC preprocessing module 15, and a file generation module 17. The VCD generation module 11 controls the simulation tool to record changes in the top-level input / output port signals as VCD waveform files through system tasks in a hardware description language; the VCD waveform files only record signal values ​​at the time points when signal transitions occur. The VCD to VEC conversion module 13 converts the VCD waveform files into VEC files containing only the logic values ​​of the top-level ports; the conversion includes extracting the logic values ​​of the top-level ports at each transition time point in the VCD waveform file, filtering out internal signals in the VCD waveform file, and excluding clock signals from the output vector table, forming a two-dimensional vector table with time as the row index and the top-level port signals as the column index.

[0082] VEC preprocessing module 15 is used to perform time point step size alignment preprocessing on VEC files. The alignment preprocessing includes removing time points in the VEC file whose time values ​​are less than a preset step size and the corresponding data rows, and aligning the time values ​​of the remaining time points to integer multiples of the preset step size according to a preset rounding direction. Specifically, when the rounding direction is upward, the alignment is to the smallest integer multiple of the original time value that is greater than or equal to the original time value; when the rounding direction is downward, the alignment is to the largest integer multiple of the original time value that is less than or equal to the original time value. When multiple different original time points are aligned to the same integer multiple of time value, only the data row with the largest original time value is retained and the rest are discarded.

[0083] The file generation module 17 is used to calculate the number of repetitions between adjacent time points based on the time difference between adjacent time points in the aligned time point sequence and the preset step size, and to use the number of repetitions to fold and express the formatted signal vector to generate a test graphic PAT file that conforms to the format of the ATE platform of the automatic test equipment.

[0084] The parity check module formal verification system, which automatically generates the above attributes, runs test stimuli through simulation tools. Using a hardware description language system task, it records the changes in the top-level input / output port signals as a standard waveform exchange format VCD waveform file. Then, it calls a vector format conversion tool to convert the VCD waveform file into a vector format VEC file containing only the logic values ​​of the top-level ports. Next, it performs time step alignment preprocessing on the VEC file. Finally, based on the time difference between adjacent time points in the aligned time sequence and the preset step size, it calculates the repetition count between each pair of adjacent time points. Using the repetition count, it folds the formatted signal vector to generate a test graphic PAT file conforming to the ATE platform format. This achieves automatic conversion of simulation waveforms into ATE test graphic files, improving test program development efficiency, ensuring accuracy, and enhancing reusability.

[0085] It is understood that the specific limitations of the system for automatically converting the above-mentioned simulation waveforms into ATE test vectors can be understood by referring to the corresponding explanations and limitations of the various embodiments of the method for automatically converting simulation waveforms into ATE test vectors above, and will not be repeated here.

[0086] Each module in the system that automatically converts the simulated waveforms into ATE test vectors can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware or independently of a device with data processing capabilities, or stored in software within the memory of the aforementioned device, so that the processor can call and execute the operations corresponding to each module. The aforementioned device can be, but is not limited to, various types of computer equipment already existing in the art.

[0087] In one embodiment, a computer-readable storage medium is also provided, on which a computer program is stored, which, when executed by a processor, implements a method embodiment for automatically converting any of the above-described simulation waveforms into ATE test vectors.

[0088] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided by this invention can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), memory bus DRAM (RDRAM), and interface DRAM (DRDRAM), etc.

[0089] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0090] The above embodiments merely illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of protection of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and all such modifications and improvements fall within the scope of protection of the present invention.< / end> < / begin>

Claims

1. A method for automatically converting simulated waveforms into ATE test vectors, characterized in that, Including the following steps: The test stimulus is run using simulation tools, and the changes in the top-level input / output port signals are recorded as standard waveform exchange format VCD waveform files using system tasks in hardware description language; the VCD waveform files only record signal values ​​at the time points when the signal changes. The vector format conversion tool is invoked to convert the VCD waveform file into a vector format VEC file containing only the logic values ​​of the top-level ports; the conversion includes extracting the logic values ​​of the top-level ports in the VCD waveform file at each transition time point to form a two-dimensional vector table with time as the row index and the top-level port signal as the column index; The VEC file is preprocessed with time step alignment. The alignment preprocessing includes removing time points in the VEC file whose time values ​​are less than a preset step size and their corresponding data rows, and aligning the time values ​​of the remaining time points to integer multiples of the preset step size according to a preset rounding direction; wherein, when the rounding direction is upward, the alignment is to the smallest integer multiple of the original time value that is greater than or equal to the original time value, and when the rounding direction is downward, the alignment is to the largest integer multiple of the original time value that is less than or equal to the original time value. When multiple different original time points are aligned to the same integer multiple of time value, only the data row with the largest original time value is retained and the rest are discarded. Based on the time difference between adjacent time points in the aligned time point sequence and the preset step size, the number of repetitions between each pair of adjacent time points is calculated. The number of repetitions is used to fold and express the formatted signal vector, generating a test graphic PAT file that conforms to the format of the ATE platform of the automated test equipment.

2. The method for automatically converting simulation waveforms into ATE test vectors according to claim 1, characterized in that, The preset step size and the preset rounding direction are obtained by parsing a configuration file. The process of parsing the configuration file includes: Read the global configuration section in the configuration file to obtain the global configuration parameters; Identify the name pattern markers in the configuration file and obtain the local configuration parameters of the name pattern corresponding to the name pattern markers; When the same configuration item is defined in both the global configuration parameter and the name pattern local configuration parameter, the name pattern local configuration parameter overrides the global configuration parameter. The configuration parameters also include at least one of the following: signal spacing, signal type redefinition configuration, fixed value configuration, time ignore rule configuration, and serial input parallel output annotation configuration.

3. The method for automatically converting simulation waveforms into ATE test vectors according to claim 2, characterized in that, Also includes: Parse the VEC file to obtain the original list of signal names; Read the additional signal definition section in the configuration file, which is delimited by a start marker and an end marker, to obtain the name and attributes of the additional signals; The additional signals are embedded into the corresponding positions in the original signal name list according to the insertion positions indicated by the start and end marks, forming a uniform signal sequence for subsequent formatting.

4. The method for automatically converting simulation waveforms into ATE test vectors according to claim 1, characterized in that, The process of calculating the number of repetitions between adjacent time points based on the time difference between adjacent time points in the aligned time point sequence and a preset step size includes: Arrange the aligned time points into a sequence in ascending chronological order. ; For each pair of adjacent time points T i-1 and T i ,according to Calculate the number of repetitions (RPT) between adjacent time points. i , where step_length is the preset step size, i=1,2,…,N.

5. The method for automatically converting simulation waveforms into ATE test vectors according to claim 1, characterized in that, This also includes repairing the X state of the input signal in the VEC file: Check the input signals with an invalid level X in the first and second sorted data rows of the VEC file; For the input signal of state X, search row by row along the column where the signal is located in the direction of increasing time to locate the first row with a definite logic value of 0 or 1; To determine the logical value to replace the X value of the input signal of the X state in the first data row or the second data row.

6. The method for automatically converting simulation waveforms into ATE test vectors according to claim 2, characterized in that, Before generating the test graph PAT file, the process also includes formatting each data row of the VEC file to the ATE format: For signals whose signal type is configured as input, the logical value of the signal at each time point is mapped to a binary character 0 or 1. For signals whose signal type is configured as output, the logic value of the signal at each time point is mapped to a low-level character L, a high-level character H, or an invalid level character X. Read the fixed value configuration and force the target signal specified in the fixed value configuration to be assigned the constant value set in the fixed value configuration; Read the ignore time rule configuration, and forcibly convert the value of the output signal to X for the time period specified in the ignore time rule configuration; Read the signal spacing and insert the corresponding number of separators between each adjacent signal column according to the spacing value specified in the signal spacing.

7. The method for automatically converting simulation waveforms into ATE test vectors according to claim 6, characterized in that, It also includes an automatic generation process for serial input parallel output comments: After reading the concatenation syntax expression defined in the serial input parallel output comment configuration, extract the multi-signal identifier sequence and end-order indicator that participate in serial sampling; the end-order indicator includes the most significant bit priority and the least significant bit priority; Read the enable signal identifier and valid level value defined in the serial input parallel output comment configuration; Traverse the formatted data rows at each time point. When the value of the enable signal in the current data row matches the effective level value, acquire the current value of each signal in the multi-signal identifier sequence, construct a multi-bit wide word according to the bit arrangement direction specified by the end sequence indicator, and append the multi-bit wide word to the sampling buffer. When the value of the enable signal in the current data line does not match the effective level value, all the multi-bit wide words accumulated in the sampling buffer are concatenated into a complete bit string in the order of acquisition time, the bit string is converted into a hexadecimal value, and a serial input parallel output annotation containing the hexadecimal value is generated in the current data line. When the value of the enable signal changes from a non-matching data row to a matching data row for the first time, a sampling start marker annotation is generated.

8. The method for automatically converting simulation waveforms into ATE test vectors according to claim 7, characterized in that, The process of generating test graphic PAT files that conform to the format of the ATE platform for automated test equipment includes: Append the aligned time value corresponding to each data row to the end of each data row to form a vector time point annotation; Generate a folded PAT file; in this process, all data lines after formatting are scanned, and consecutive line segments with identical vector values ​​are identified. For each line segment, the vector value of the first line is retained, and the number of repetitions is used as the repetition instruction to replace the remaining repetitive lines, resulting in a compressed test graphic file suitable for production testing scenarios. Generate an expanded PAT file; in this process, all formatted data rows are output in chronological order without folding or compressing any rows, resulting in an expanded test graphic file that retains complete timing information. In this process, the folded version of the PAT file and the expanded version of the PAT file are generated simultaneously in the same conversion process.

9. A system for automatically converting simulated waveforms into ATE test vectors, characterized in that, include: The VCD generation module is used to control the simulation tool to record the changes of the top-level input / output port signals as VCD waveform files through the system tasks of the hardware description language. The VCD waveform file only records the signal value at the time point when the signal changes; The VCD to VEC module is used to convert the VCD waveform file into a VEC file containing only the logic values ​​of the top-level ports; the conversion includes extracting the logic values ​​of the top-level ports in the VCD waveform file at each transition time point to form a two-dimensional vector table with time as the row index and the top-level port signal as the column index; The VEC preprocessing module is used to perform time step alignment preprocessing on the VEC file; The alignment preprocessing includes removing time points in the VEC file whose time values ​​are less than a preset step size and their corresponding data rows, and aligning the time values ​​of the remaining time points to integer multiples of the preset step size according to a preset rounding direction; wherein, when the rounding direction is upward, the alignment is to the smallest integer multiple of the original time value that is greater than or equal to the original time value, and when the rounding direction is downward, the alignment is to the largest integer multiple of the original time value that is less than or equal to the original time value. When multiple different original time points are aligned to the same integer multiple of time value, only the data row with the largest original time value is retained and the rest are discarded. The file generation module is used to calculate the number of repetitions between adjacent time points based on the time difference between adjacent time points in the aligned time point sequence and a preset step size, and to use the number of repetitions to fold and express the formatted signal vector to generate a test graphic PAT file that conforms to the format of the ATE platform of the automated test equipment.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the method for automatically converting the simulation waveform into an ATE test vector as described in any one of claims 1 to 8.

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