Embedded flash memory self-test system and method based on MBIST and LBIST

Abstract

The application discloses a kind of embedded Flash memory self-test system and method based on MBIST and LBIST, it is related to integrated circuit test technical field, for solving the technical problem that existing external automatic test equipment tests Flash memory, leading to test difficult to cover chip internal complex connection path, and cannot carry out integrity verification in real time;The embedded Flash memory self-test system based on MBIST and LBIST of the application, including embedded Flash memory module, memory built-in self-test module, logic built-in self-test module and control and state register module;Memory built-in self-test module is used to execute Flash memory test and report error;Logic built-in self-test module is used to test logic circuit;Control and state register module is used to control the test trigger of memory built-in self-test and logic built-in self-test to Flash memory.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit testing technology, and more specifically, to an embedded Flash memory self-testing system and method based on MBIST and LBIST. Background Technology

[0002] With the continuous development of integrated circuit technology, the capacity and complexity of memory embedded in System-on-Chips (SoCs) are increasing. Among them, embedded Flash memory, due to its non-volatility and reprogrammability, is widely used in microcontrollers, smart cards, and IoT devices. However, as process dimensions shrink, Flash memory may develop defects during manufacturing or fail due to issues such as erase / write fatigue and data retention during long-term use, seriously affecting the reliability and lifespan of the chip.

[0003] Existing technologies test Flash memory using traditional external Automatic Test Equipment (ATE), which makes it difficult to cover the complex internal connection paths of the chip, and the chip cannot be verified for integrity in real time by the test equipment before power-on or before critical functions are executed. Summary of the Invention

[0004] The purpose of this invention is to provide an embedded Flash memory self-testing system and method based on MBIST and LBIST, to solve the technical problems of existing external automatic test equipment for testing Flash memory, which makes it difficult to cover the complex internal connection paths of the chip, and the inability to perform real-time integrity verification of the chip before power-on or execution of critical functions. In view of this, the present invention achieves this through the following solution.

[0005] In a first aspect, the present invention provides an embedded Flash memory self-test system based on MBIST and LBIST, comprising an embedded Flash memory module, a memory-built-in self-test module, a logic-built-in self-test module, and a control and status register module; wherein: The embedded Flash memory module includes multiple memory arrays that support read, program, and erase operations. Each memory array consists of Flash memory cells arranged in rows and columns. The built-in self-test module of the memory is integrated inside the chip and connected to the embedded Flash memory module, used to perform Flash memory tests and report errors; The built-in self-test module is integrated inside the chip and is used to test the logic circuit. The control and status register module manages the test process of the built-in memory self-test and the logic built-in self-test through software-configurable registers, stores test status and error information, and controls the triggering of the built-in memory self-test for the Flash memory; MBIST represents the built-in memory self-test, and LBIST represents the logic built-in self-test.

[0006] Compared with existing technologies, the embedded Flash memory self-test system based on MBIST and LBIST of the present invention can be configured with an embedded Flash memory module, a memory built-in self-test module, a logic built-in self-test module, and a control and status register module. Each module is defined as follows: the embedded Flash memory module contains multiple memory arrays, supports read, program, and erase operations, and each memory array is composed of Flash memory cells arranged in rows and columns; the memory built-in self-test module is integrated inside the chip and connected to the embedded Flash memory module, used to perform Flash memory tests and report errors; the logic built-in self-test module is integrated inside the chip and used to test logic circuits; the control and status register module manages the test process of the memory built-in self-test and logic built-in self-test through software-configurable registers, stores test status and error information, and triggers the memory built-in self-test to start testing the Flash; where MBIST stands for Memory Built-In-Self Test, and LBIST stands for Logic Built-In-Self Test. Based on the above technical solutions, this embedded Flash memory self-test system supports in-depth testing after manufacturing, rapid checks before power-on / use, and on-demand testing during runtime, covering the entire process from chip production to disposal. Furthermore, after completing logic self-test through built-in logic self-test, the built-in memory self-test is triggered to perform integrity checks on the Flash memory, helping to detect memory faults early in the boot process, thereby reducing boot failures caused by program loading errors. Built-in memory self-test reduces reliance on external automated testing equipment, shortens manufacturing testing time, and lowers testing costs. The rapid checks integrated with the built-in logic self-test require no additional external intervention. Furthermore, test algorithms, test ranges, and trigger conditions can be flexibly configured through registers to adapt to different application scenarios and reliability requirements. It can also promptly detect manufacturing defects and early-use faults, improving product yield and long-term reliability. The mandatory integrity check at power-on provides important safety assurance for safety-critical applications (such as automotive electronics and medical devices). The above-mentioned technical solution of the present invention solves the technical problem that existing external automatic testing equipment for testing Flash memory makes it difficult to cover the complex internal connection paths of the chip, and the chip cannot be verified for integrity in real time by the testing equipment before power-on or before the execution of critical functions.

[0007] Furthermore, in the embedded Flash memory self-test system based on MBIST and LBIST of the present invention, the built-in self-test module of the memory includes a test mode controller, an address generator, a data generator, and a desired data calculator; wherein: The test mode controller is used to receive external test commands or internal trigger signals, select and start the test algorithm; The address generator is used to generate a test address sequence covering the Flash storage array; The data generator is used to generate the test data pattern to be written; The expected data calculator is used to calculate the expected output data based on the written data and the expected read results.

[0008] Furthermore, in the embedded Flash memory self-test system based on MBIST and LBIST of the present invention, the built-in self-test module of the memory also includes a comparator; The comparator is used to compare the actual data read with the expected data, generate a comparison result, summarize the comparison result, record the error address, error type and error count, and output an error report through the test port.

[0009] Furthermore, in the embedded Flash memory self-test system based on MBIST and LBIST of the present invention, the built-in self-test module includes a startup sequence controller, a test vector generator, a response analyzer, and a built-in self-test-Flash trigger interface; wherein: The startup sequence controller is used to execute a preset startup self-test sequence after the chip is powered on and reset or wake-up. The test vector generator is used to generate test vectors for logic circuits; The response analyzer is used to capture and analyze the response of the logic circuit; The built-in self-test-Flash trigger interface is used to send a request signal to the built-in self-test module of the memory to start the Flash test when the configuration allows.

[0010] Furthermore, in the embedded Flash memory self-test system based on MBIST and LBIST of the present invention, the control and status register module includes a built-in self-test control register and a built-in self-test status register. The built-in self-test control register in the memory is used to select the test algorithm, specify the test range, start or stop the built-in self-test in the memory, and read the test status. The built-in memory self-test status register is used to store the execution results, error flags, and error counts of the built-in memory self-test.

[0011] Furthermore, in the embedded Flash memory self-test system based on MBIST and LBIST of the present invention, the control and status register module also includes a built-in self-test-Flash enable bit, a Flash test mode bit, and an error log register. The built-in logic self-test-Flash enable bit is used to enable or disable the Flash test triggered by the built-in logic self-test. The Flash test mode bit is used to determine whether the current Flash is in test mode; The error log register is used to record error details from the most recent or historical tests.

[0012] Furthermore, the embedded Flash memory self-testing system based on MBIST and LBIST of the present invention also includes a mode selection and arbitration logic module; The mode selection and arbitration logic module is used to receive memory built-in self-test start requests from different sources, arbitrate according to system mode and preset priority, and decide whether to respond and start the memory built-in self-test module to test the Flash memory.

[0013] Furthermore, in the embedded Flash memory self-test system based on MBIST and LBIST of the present invention, the priorities from high to low are external test requests, logic-built-in self-test trigger requests, and software requests.

[0014] Secondly, the present invention provides a self-testing method for embedded Flash memory based on MBIST and LBIST, utilizing the aforementioned self-testing system for embedded Flash memory based on MBIST and LBIST, comprising: The chip enters test mode. The test equipment configures the built-in self-test module of the memory through the control and status register module, selects the deep test algorithm, and specifies that the entire Flash memory array is to be tested. Upon receiving the configuration command, the mode selection and arbitration logic module starts the built-in self-test module of the memory. The built-in self-test module of the memory executes the deep test algorithm, writes test data modes to each address in sequence, and performs read and erase operations according to the algorithm requirements. The comparator compares the read data with the expected data in real time and records all error information; After the test is completed, a report is output through the test port for quality analysis and screening; The chip is reset and released upon power-on or wake-up from deep sleep. The built-in logic self-test module starts and executes its logic self-test sequence; When the built-in self-test reaches the preset Flash checkpoint, it checks the built-in self-test-Flash enable bit; if the enable bit is valid, the built-in self-test module generates a control flow trigger signal. Upon receiving the control flow trigger signal, the mode selection and arbitration logic module determines that there is no higher priority request and then sends a start command to the built-in self-test module in the memory.

[0015] Compared with the prior art, the beneficial effects of the embedded Flash memory self-testing method based on MBIST and LBIST of the present invention are the same as those of the embedded Flash memory self-testing system based on MBIST and LBIST described in the above technical solution, and will not be repeated here.

[0016] Furthermore, in the embedded Flash memory self-testing method based on MBIST and LBIST of the present invention, after issuing a start command to the built-in self-test module of the memory, it further includes: The memory has a built-in self-test module that performs tests, verifies only sectors, and performs a read of all sectors to check for connectivity and faults, and runs the March algorithm. If an error is detected during testing, the built-in self-test of the memory will interrupt or pull the system reset signal low to prevent the system from continuing to start, enter safe mode, or report an error. After the test is completed, the results are written to the built-in self-test status register and error log register in the memory for subsequent firmware queries. Attached Figure Description

[0017] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings: Figure 1 This is a schematic diagram of the structure of a memory-built-in self-test module in this invention; Figure 2 This is a flowchart illustrating an embedded Flash memory self-testing system based on MBIST and LBIST according to the present invention. Detailed Implementation

[0018] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0019] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0020] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0021] Existing technologies test Flash memory using traditional external Automatic Test Equipment (ATE), which makes it difficult to cover the complex internal connection paths of the chip, and the chip cannot be verified for integrity in real time by the test equipment before power-on or before critical functions are executed.

[0022] To address the aforementioned technical problems, this invention provides an embedded Flash memory self-test system based on MBIST and LBIST, comprising an embedded Flash memory module, a memory-built-in self-test module, a logic-built-in self-test module, and a control and status register module; wherein: The embedded Flash memory module includes multiple memory arrays that support read, program, and erase operations. Each memory array consists of Flash memory cells arranged in rows and columns. The built-in self-test module of the memory is integrated inside the chip and connected to the embedded Flash memory module, used to perform Flash memory tests and report errors; The built-in self-test module is integrated inside the chip and is used to test the logic circuit. The control and status register module manages the test process of the built-in memory self-test and the logic built-in self-test through software-configurable registers, stores test status and error information, and controls the triggering of the built-in memory self-test for Flash memory tests.

[0023] This invention provides an embedded Flash memory self-test system based on MBIST and LBIST, supporting in-depth post-manufacturing testing, rapid power-on / use pre-test checks, and on-demand runtime testing, covering the entire chip lifecycle from production to disposal. Furthermore, after completing logic self-tests through built-in logic self-tests, the system triggers built-in memory self-tests to perform integrity checks on the Flash memory, helping to detect memory faults early in the boot process and reducing boot failures caused by program loading errors. Simultaneously, the introduction of built-in memory self-tests reduces reliance on external automated testing equipment, shortens manufacturing testing time, and lowers testing costs. Moreover, the rapid checks integrated with the built-in logic self-tests require no additional external intervention. Furthermore, this invention allows for flexible configuration of test algorithms, test ranges, and trigger conditions via registers to adapt to different application scenarios and reliability requirements. It enables timely detection of manufacturing defects and early-use faults, improving product yield and long-term reliability. In particular, the mandatory integrity check at power-on provides crucial safety assurance for safety-critical applications (such as automotive electronics and medical devices). In summary, this invention effectively solves the technical problem that existing external automatic testing equipment is unable to cover the complex internal connection paths of chips, and that the integrity of chips cannot be verified in real time before power-on or before the execution of critical functions.

[0024] To better understand the present invention, the following specific embodiments further illustrate the content of the present invention, but the content of the present invention is not limited to the following embodiments.

[0025] Example 1 This embodiment provides an embedded Flash memory self-test system based on MBIST and LBIST, including an embedded Flash memory module, a memory-built-in self-test module, a logic-built-in self-test module, a control and status register module, and a mode selection and arbitration logic module; wherein: The embedded Flash memory module contains multiple memory arrays that support read, program, and erase operations. Each memory array consists of Flash memory cells arranged in rows and columns.

[0026] The built-in self-test module is integrated inside the chip and connected to the embedded Flash memory module to perform Flash memory tests and report errors. Furthermore, the built-in self-test module of the memory includes a test mode controller, an address generator, a data generator, a expected data calculator, and a comparator; wherein: The test mode controller is used to receive external test commands or internal trigger signals, select and start the test algorithm; The address generator is used to generate a test address sequence that covers the Flash memory array; The data generator is used to generate test data patterns for writing; The expected data calculator is used to calculate the expected output data based on the data written and the expected read results; The comparator is used to compare the actual data read with the expected data, generate a comparison result, summarize the comparison result, record the error address, error type and error count, and output an error report through the test port.

[0027] The built-in logic self-test module is integrated inside the chip for testing logic circuits; Furthermore, the built-in self-test module includes a startup sequence controller, a test vector generator, a response analyzer, and a built-in self-test-Flash trigger interface; wherein: The startup sequence controller is used to execute a preset startup self-test sequence after the chip is powered on, reset, or woken up. The test vector generator is used to generate test vectors for logic circuits; A response analyzer is used to capture and analyze the response of a logic circuit; The built-in self-test-Flash trigger interface is used to send a request signal to the memory built-in self-test module to start a flash test when the configuration allows.

[0028] The control and status register module manages the test process of the memory-built-in self-test and logic-built-in self-test through software-configurable registers, stores test status and error information, and controls the test triggering of the flash memory by the memory-built-in self-test and logic-built-in self-test. Furthermore, the control and status register module includes a memory-built-in self-test control register, a memory-built-in self-test status register, a logic-built-in self-test-Flash enable bit, a Flash test mode bit, and an error log register; wherein: The built-in memory self-test control register is used to select the test algorithm, specify the test range, start or stop the built-in memory self-test, and read the test status; The built-in memory self-test status register is used to store the execution results, error flags, and error counts of the built-in memory self-test; The built-in logic self-test - Flash enable bit is used to enable or disable Flash tests triggered by the built-in logic self-test; The Flash test mode bit is used to determine whether the Flash is currently in test mode; The error log register is used to record error details from the most recent or historical tests.

[0029] The mode selection and arbitration logic module is used to receive memory built-in self-test start requests from different sources, and arbitrates them according to the system mode and preset priority to decide whether to respond to and start the memory built-in self-test module to test the Flash memory; the priorities from high to low are external test requests, logic built-in self-test trigger requests, and software requests.

[0030] Example 2 In a first aspect, this embodiment provides an embedded Flash memory self-test system based on MBIST and LBIST, including an embedded Flash memory module, a memory-built-in self-test module, a logic-built-in self-test module, a control and status register module, and a mode selection and arbitration logic module; wherein: An embedded Flash memory module contains multiple memory arrays, each consisting of rows and columns of Flash memory cells, supporting read, program (write), and erase operations. The Flash memory in the embedded Flash memory module has a standard interface, including an address bus, a data bus, control signals (such as chip select, write enable, and output enable), and a high-voltage generation circuit (for the high voltage Vpp required for programming and erasing; Vpp stands for Programming Voltage).

[0031] The built-in self-test module is integrated inside the chip and connects directly to the aforementioned embedded Flash memory module. Please refer to [link / reference needed]. Figure 1 The internal architecture of the built-in self-test module in the memory of this embodiment is as follows: Figure 1 As shown, the built-in self-test module of this memory includes a Test Mode Controller (TMC), an address generator, a data generator, a desired data calculator, and a comparator. The TMC receives external test commands or internal trigger signals, selects and initiates the required test algorithm. The address generator generates a test address sequence covering the entire or part of the Flash memory array. The data generator generates test data patterns for writing, including all 0s, all 1s, checkerboard, walking 1s / 0s, March C+ algorithm sequences, etc. The desired data calculator calculates the desired output data based on the written data and the expected read result. The comparator compares the actual data read from the Flash with the desired data, generates a comparison result, summarizes the comparison results, records the error address, error type (such as bit error, word line / bit line failure), and error count, and can output an error report through a dedicated test port (such as JTAG, short for Joint Test Action Group).

[0032] The built-in self-test module is integrated inside the chip and is mainly used to test the core logic circuit. In this embodiment, the built-in self-test module includes a startup sequence controller, a test vector generator, a response analyzer, and a built-in self-test-Flash trigger interface. The startup sequence controller executes a preset startup self-test sequence after a power-on reset (POR) or a specific wake-up event. The test vector generator generates test vectors for the logic circuit. The response analyzer captures and analyzes the responses of the logic circuit. The built-in self-test-Flash trigger interface sends a request signal to the built-in self-test module to start Flash testing when the configuration allows. In this embodiment, the built-in self-test module includes a dedicated Flash integrity check trigger signal, denoted as `LBIST_FLASH_CHECK_REQ`, which means: to notify the control and status register module to start the built-in self-test to test the embedded Flash memory; when the built-in self-test startup sequence reaches a specific stage (usually after the core logic self-test and before system initialization), this trigger signal is generated if the configuration allows.

[0033] The control and status register module of this embodiment includes a set of status and control registers that can be read and written by software (such as a bootloader or firmware). This control and status register module includes a memory-built-in self-test control register, a memory-built-in self-test status register, a logical built-in self-test-Flash enable bit, a Flash test mode bit, and an error log register. The memory-built-in self-test control register is used to select the test algorithm, specify the test range (full array / partial sector), start / stop the memory-built-in self-test, and read the test status (running / completed / failed). The memory-built-in self-test status register is used to store the execution result (pass / fail), error flags, error counts, etc., of the memory-built-in self-test. The logical built-in self-test-Flash enable bit is a software-configurable bit used to enable or disable the Flash test triggered by the logical built-in self-test. The Flash test mode bit is used to indicate whether the current Flash is in test mode. The error log register is used to record error details of the most recent or historical tests.

[0034] The mode selection and arbitration logic module in this embodiment is used to receive the `TEST_MODE` signal from an external test port (such as a JTAG test access port controller), the `LBIST_FLASH_CHECK_REQ` signal from the built-in self-test module, and a software request from the Control and Status Register (CSR). The `TEST_MODE` signal indicates whether the chip is in a test mode forced by external forces (such as manufacturing test, debugging, or rework diagnostic mode), and serves as one of the key enabling conditions for the mode selection and arbitration logic module to determine whether to allow the initiation of self-test operations such as memory built-in self-test / logic built-in self-test. Furthermore, the mode selection and arbitration logic module in this embodiment is also used to arbitrate and decide whether to start the memory built-in self-test module to test the Flash based on a preset priority (e.g., external test > logic built-in self-test trigger > software request) and the current state; furthermore, when the `LBIST_FLASH_CHECK_REQ` signal is valid and the `logic built-in self-test-Flash enable bit` is set, the module issues a start instruction to the memory built-in self-test module and may specify a fast, low-power test algorithm (such as simply reading all sector IDs and status registers, or executing a fast March algorithm).

[0035] Further, please refer to Figure 2 , Figure 2The workflow of the embedded Flash memory self-test system based on MBIST and LBIST described in this embodiment mainly includes post-manufacturing deep testing, post-power-on deep testing, and software request testing. Specifically, in the post-manufacturing deep testing stage (dominated by the memory's built-in self-test), the chip enters test mode (via JTAG or other test interfaces), and the test equipment configures the memory's built-in self-test module through the control and status registers, selecting a deep testing algorithm (such as March). (C+) specifies testing the entire Flash array; the mode selection logic receives `TEST_MODE` and the configuration command, and starts the built-in memory self-test module; the built-in memory self-test module executes the selected algorithm, writes test data modes to each address in sequence, and performs read, erase, and other operations according to the algorithm requirements; further, the comparator compares the read data with the expected data in real time and records all error information. After the test is completed, a detailed report is output through the test port for quality analysis and screening; further, in the deep test phase after power-on (triggered by the built-in logic self-test), the chip powers on or wakes from deep sleep, is reset and released, the built-in logic self-test module starts, and executes its standard logic self-test sequence. When the built-in logic self-test reaches the preset "Flash checkpoint", it checks the `built-in logic self-test - Flash enable bit`. If the enable bit is valid, the built-in logic self-test module generates the `LBIST_FLASH_CHECK_REQ` signal. The mode selection and arbitration logic module receives this signal and determines that there is no error. A higher priority request sends a start command to the built-in self-test module (WPT) and may specify a fast test algorithm (such as "fast read verification" or "lightweight March"). Further, the WPT performs a fast test, which may only verify critical sectors (such as the bootloader area), perform a read of all sectors to check for basic connectivity and the absence of large-scale faults, or run a simplified March algorithm. The March algorithm is a type of fault detection algorithm specifically designed for memory testing. It traverses the memory address space in a specific order (sequential, reverse, or a specific pattern) by executing a series of specific read / write operations to detect faulty units in the hardware. During the test, if a serious error (such as damage to a critical sector) is found, the WPT can interrupt or directly pull the system reset signal low to prevent the system from continuing to boot, enter safe mode, or report an error. After the test is completed, the results are written to the WPT status register and error log register for subsequent firmware queries.Furthermore, during runtime software testing, system software (such as operating system or application firmware) can request online testing of a specific Flash area (such as the data area to be written) by writing to the built-in self-test control register during operation. The mode selection logic processes this request (considering priority and system load), initiates the built-in self-test to execute the test of the specified area, and provides the test results for software decision-making, such as marking bad blocks, triggering data migration, or reporting errors.

[0036] Secondly, this embodiment provides a self-testing method for embedded Flash memory based on MBIST and LBIST. Utilizing the aforementioned embedded Flash memory self-testing system based on MBIST and LBIST, the embedded Flash memory self-testing method of this embodiment includes: The chip enters test mode. The test equipment configures the built-in self-test module of the memory through the control and status register module, selects the deep test algorithm, and specifies that the entire Flash memory array is to be tested. Upon receiving the configuration command, the mode selection and arbitration logic module starts the built-in self-test module of the memory. The built-in self-test module of the memory executes the deep test algorithm, writes test data modes to each address in sequence, and performs read and erase operations according to the algorithm requirements. The comparator compares the read data with the expected data in real time and records all error information; After the test is completed, a report is output through the test port for quality analysis and screening; The chip is reset and released upon power-on or wake-up from deep sleep. The built-in logic self-test module starts and executes its logic self-test sequence; When the built-in self-test reaches the preset Flash checkpoint, it checks the built-in self-test-Flash enable bit; if the enable bit is valid, the built-in self-test module generates a control flow trigger signal. Upon receiving the control flow trigger signal, the mode selection and arbitration logic module determines that there is no higher priority request and then sends a start command to the built-in self-test module in the memory. The memory has a built-in self-test module that performs tests, verifies only sectors, and performs a read of all sectors to check for connectivity and faults, and runs the March algorithm. If an error is detected during testing, the built-in self-test of the memory will interrupt or pull the system reset signal low to prevent the system from continuing to start, enter safe mode, or report an error. After the test is completed, the results are written to the built-in self-test status register and error log register in the memory for subsequent firmware queries.

[0037] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0038] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A self-testing system for embedded Flash memory based on MBIST and LBIST, characterized in that, This includes an embedded Flash memory module, a memory-built-in self-test module, a logic-built-in self-test module, and a control and status register module; among which: The embedded Flash memory module includes multiple memory arrays that support read, program, and erase operations. Each memory array consists of Flash memory cells arranged in rows and columns. The built-in self-test module of the memory is integrated inside the chip and connected to the embedded Flash memory module, used to perform Flash memory tests and report errors; The built-in self-test module is integrated inside the chip and is used to test the logic circuit. The control and status register module manages the test process of the memory-built-in self-test and the logic-built-in self-test through software-configurable registers, stores test status and error information, and controls the triggering of the memory-built-in self-test on the Flash memory; MBIST represents the memory-built-in self-test, and LBIST represents the logic-built-in self-test. The built-in self-test module includes a startup sequence controller, a test vector generator, a response analyzer, and a built-in self-test-Flash trigger interface. The startup sequence controller is used to execute a preset startup self-test sequence after the chip is powered on and reset or wake-up. The test vector generator is used to generate test vectors for the logic circuit. The response analyzer is used to capture and analyze the response of the logic circuit. The built-in self-test-Flash trigger interface is used to send a request signal to the built-in self-test module to start Flash testing when the configuration allows.

2. The embedded Flash memory self-testing system based on MBIST and LBIST according to claim 1, characterized in that, The built-in self-test module of the memory includes a test mode controller, an address generator, a data generator, and a desired data calculator; wherein: The test mode controller is used to receive external test commands or internal trigger signals, select and start the test algorithm; The address generator is used to generate a test address sequence covering the Flash storage array; The data generator is used to generate the test data pattern to be written; The expected data calculator is used to calculate the expected output data based on the written data and the expected read results.

3. The embedded Flash memory self-testing system based on MBIST and LBIST according to claim 2, characterized in that, The built-in self-test module of the memory also includes a comparator; The comparator is used to compare the actual data read with the expected data, generate a comparison result, summarize the comparison result, record the error address, error type and error count, and output an error report through the test port.

4. The embedded Flash memory self-testing system based on MBIST and LBIST according to claim 3, characterized in that, The control and status register module includes a built-in self-test control register and a built-in self-test status register. The built-in self-test control register in the memory is used to select the test algorithm, specify the test range, start or stop the built-in self-test in the memory, and read the test status. The built-in memory self-test status register is used to store the execution results, error flags, and error counts of the built-in memory self-test.

5. The embedded Flash memory self-testing system based on MBIST and LBIST according to claim 4, characterized in that, The control and status register module also includes a built-in self-test-Flash enable bit, a Flash test mode bit, and an error log register. The built-in logic self-test-Flash enable bit is used to enable or disable the Flash test triggered by the built-in logic self-test. The Flash test mode bit is used to determine whether the current Flash is in test mode; The error log register is used to record error details from the most recent or historical tests.

6. The embedded Flash memory self-testing system based on MBIST and LBIST according to claim 5, characterized in that, It also includes a mode selection and arbitration logic module; The mode selection and arbitration logic module is used to receive memory built-in self-test start requests from different sources, arbitrate according to system mode and preset priority, and decide whether to respond and start the memory built-in self-test module to test the Flash memory.

7. The embedded Flash memory self-testing system based on MBIST and LBIST according to claim 6, characterized in that, The priorities, from highest to lowest, are external test requests, logic-built-in self-test triggered requests, and software requests.

8. A self-testing method for embedded Flash memory based on MBIST and LBIST, characterized in that, The embedded Flash memory self-test system based on MBIST and LBIST according to any one of claims 1 to 7 includes: The chip enters test mode. The test equipment configures the built-in self-test module of the memory through the control and status register module, selects the deep test algorithm, and specifies that the entire Flash memory array is to be tested. Upon receiving the configuration command, the mode selection and arbitration logic module starts the built-in self-test module of the memory. The built-in self-test module of the memory executes the deep test algorithm, writes test data modes to each address in sequence, and performs read and erase operations according to the algorithm requirements. The comparator compares the read data with the expected data in real time and records all error information; After the test is completed, a report is output through the test port for quality analysis and screening; The chip is reset and released upon power-on or wake-up from deep sleep. The built-in logic self-test module starts and executes its logic self-test sequence; When the built-in self-test reaches the preset Flash checkpoint, it checks the built-in self-test-Flash enable bit; if the enable bit is valid, the built-in self-test module generates a control flow trigger signal. Upon receiving the control flow trigger signal, the mode selection and arbitration logic module determines that there is no higher priority request and then sends a start command to the built-in self-test module in the memory.

9. The self-testing method for embedded Flash memory based on MBIST and LBIST according to claim 8, characterized in that, After issuing the start command to the built-in self-test module in the memory, the process also includes: The memory has a built-in self-test module that performs tests, verifies only sectors, and performs a read of all sectors to check for connectivity and faults, and runs the March algorithm. If an error is detected during testing, the built-in self-test of the memory will interrupt or pull the system reset signal low to prevent the system from continuing to start, enter safe mode, or report an error. After the test is completed, the results are written to the built-in self-test status register and error log register in the memory for subsequent firmware queries.

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