An SRAM noise edge analysis method, device, system and storage medium

Abstract

The application discloses an SRAM noise margin analysis method and device, system and storage medium, and relates to the technical field of integrated circuits. The application creatively finds that, on a Bit distribution diagram, points of read-write test passing are often distributed around a line segment, so that the noise margin corresponding to the entire SRAM can be defined on a straight line. The application firstly acquires read-write test results, read noise margin and write noise margin of each Bit in the SRAM to be tested, then obtains a Bit distribution diagram, adopts a straight line fitting mode to fit all points on the Bit distribution diagram, and obtains a fitting line, which corresponds to the straight line of the noise margin corresponding to the entire SRAM; finally, the noise margin line segment of the SRAM to be tested is obtained from the fitting line according to the read-write test results of each Bit, so that the noise margin corresponding to the SRAM to be tested can be reliably analyzed.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to an SRAM noise edge analysis method, apparatus, system, and storage medium. Background Technology

[0002] Static RAM (SRAM) is widely used in large-scale integrated circuits (VLSI) due to its performance and compatibility advantages. To improve SRAM yield, the industry uses auxiliary circuitry to improve read noise margin (RSNM) and write noise margin (WM).

[0003] Read noise margin is the maximum DC noise voltage that a data node (such as the one storing '0') inside a memory cell can withstand during a read operation without accidentally flipping the data. Write noise margin is the minimum bit line voltage difference or other metric required to successfully flip the data inside a memory cell (such as writing from '0' to '1') during a write operation. More broadly, it reflects the "write capability margin" of a cell against feedback from existing data when writing new data.

[0004] In improving SRAM yield, Write Performance (WM) and Read Stability Notification (RSNM) are key factors determining SRAM yield. Currently, the industry uses butterfly curves to measure RSNM and write current / voltage scanning methods to measure WM. Practice has shown that write capability and read stability are contradictory. Improving read stability (e.g., increasing the pull-down transistor size or decreasing the path transistor size) weakens write capability; conversely, enhancing write capability (e.g., increasing the path transistor size) worsens read stability. Therefore, while existing technologies that measure RSNM and WM separately have a certain degree of accuracy, they lack reliability for SRAM process guidance.

[0005] An SRAM consists of multiple 6T or 4T SRAM circuits, each forming a one-bit storage cell. Improving SRAM yield requires evaluating the overall read / write capability of the SRAM. This necessitates identifying the noise edge of the SRAM, which represents a suitable read / write capability range. This range describes the circuit system's ability to maintain normal operation even in the presence of noise. Generally, a larger noise edge range indicates a stronger ability of the circuit system to maintain normal operation. However, current technology lacks a reliable method for analyzing the noise edge of SRAM. Summary of the Invention

[0006] This invention provides a method, apparatus, system, and storage medium for SRAM noise edge analysis, which provides a relatively reliable solution for analyzing noise edges corresponding to SRAM.

[0007] The first aspect of this invention discloses a method for SRAM noise edge analysis, the method comprising: Perform read and write tests on each bit in the SRAM under test, and obtain the read and write test results for each bit; Measure the read noise margin and write noise margin of each bit in the SRAM under test; Obtain a bit distribution map, wherein the horizontal and vertical axes of the bit distribution map are read noise tolerance and write noise tolerance, respectively, and each point on the bit distribution map represents the read noise tolerance and write noise tolerance corresponding to 1 bit; A straight line fitting method is used to fit all points on the Bit distribution map to obtain a fitted line; Based on the read and write test results of each bit, the noise edge segment of the SRAM under test is obtained from the fitted line.

[0008] As an optional implementation, in the first aspect of the present invention, obtaining the noise edge segment of the SRAM under test from the fitted line based on the read / write test results of each bit includes: For each bit, if the read / write test result of the bit is that the read / write function is normal, then the weight value of the bit is set to the first value; if the read / write test result of the bit is that at least one read or write operation fails, then the weight value of the bit is set to the second value. Iterate through each target point set on the fitting line. For each target point, obtain a set of points within a preset range around the target point. Determine the target weight corresponding to the target point based on the weight values ​​of all points in the set. For all the target points, a first endpoint and a second endpoint are obtained based on the target weights corresponding to all the target points. The first endpoint and the second endpoint are the inflection points where the target weight values ​​of the target points on the fitted line change. Based on the first endpoint and the second endpoint, the noise edge segment of the SRAM under test is obtained from the fitted line.

[0009] As an optional implementation, in the first aspect of the present invention, obtaining a set of points within a preset range surrounding each target point includes: For each target point, the N surrounding points on the Bit distribution map that are closest to the target point in order of distance are obtained, and the N surrounding points are used as the point set within a preset range around the target point. And, determining the target weight corresponding to the target point based on the weight values ​​corresponding to all points in the point set includes: The target weight corresponding to the target point is obtained by summing the weight values ​​of the N surrounding points within the point set.

[0010] As an optional implementation, in the first aspect of the invention, the SRAM under test is manufactured in the following manner: The process parameters corresponding to the circuit structure of each bit in the SRAM under test are obtained. The process parameters include one or more of transistor size, channel doping concentration, and gate oxide thickness. The process parameters are adjusted based on a Gaussian distribution so that each parameter in the process parameters corresponding to all the bit circuit structures satisfies a Gaussian distribution within a preset value range, thereby obtaining the distributed process parameters corresponding to each bit circuit structure. The SRAM under test is manufactured based on the aforementioned distributed process parameters.

[0011] As an optional implementation, in the first aspect of the present invention, adjusting the process parameters based on a Gaussian distribution includes: For each process parameter: Based on the current values ​​corresponding to the process parameters, a Gaussian distribution curve with the mean of the current values ​​is generated. Within a preset numerical range, a segment of the Gaussian distribution curve is extracted, and M adjustment values ​​are uniformly obtained on this segment, where M is the number of the Bit circuit structures. The values ​​of the process parameters corresponding to the M bit circuit structures are replaced with M adjustment values ​​so that the process parameters corresponding to the M bit circuit structures satisfy a Gaussian distribution within a preset value range.

[0012] As an optional implementation, in the first aspect of the present invention, the method further includes: Set simulated MOS parameters, which are matched with the process parameters of the SRAM under test. The simulated MOS parameters include one or more of the following: threshold voltage, saturation current, subthreshold swing, drain-induced barrier reduction, gate-induced leakage current, and statistical mismatch parameters. The simulated SRAM is simulated based on the simulated MOS parameters to obtain the simulated read noise margin and write noise margin values ​​corresponding to the simulated SRAM. Determine whether the simulated read noise margin value and the simulated write noise margin value are located on the noise edge corresponding to the noise edge segment; if not, adjust the simulated MOS parameters and re-perform the simulation until the simulated read noise margin value and the simulated write noise margin value are located on the noise edge, and determine that the simulated read noise margin value and the simulated write noise margin value at this time are the final simulated read noise margin value and the simulated write noise margin value.

[0013] As an optional implementation, in the first aspect of the present invention, determining whether the simulated read noise tolerance value and the simulated write noise tolerance value are located on the noise edge corresponding to the noise edge segment includes: Based on the noise edge segment, calculate the average read noise tolerance and average write noise tolerance corresponding to the noise edge segment; Calculate the difference between the simulated read noise tolerance value and the average read noise tolerance value; calculate the difference between the simulated write noise tolerance value and the average write noise tolerance value. Determine whether the read noise tolerance difference and the write noise tolerance difference are both less than a preset difference threshold, thereby determining whether the simulated read noise tolerance value and the simulated write noise tolerance value are located on the noise edge corresponding to the noise edge segment.

[0014] A second aspect of the present invention discloses an SRAM noise edge analysis apparatus, the apparatus comprising: The read / write test module is used to perform read / write tests on each bit in the SRAM under test and obtain the read / write test results for each bit. The noise analysis module is used to measure the read noise margin and write noise margin of each bit in the SRAM under test. The data analysis module is used to obtain a bit distribution map, wherein the horizontal and vertical axes of the bit distribution map are read noise tolerance and write noise tolerance, respectively, and each point on the bit distribution map represents the read noise tolerance and write noise tolerance corresponding to 1 bit; The line fitting module is used to fit all points on the Bit distribution map using a line fitting method to obtain a fitted line; The line processing module is used to obtain the noise edge segment of the SRAM under test from the fitted line based on the read and write test results of each bit.

[0015] As an optional implementation, in a second aspect of the present invention, the specific operation method by which the straight-line processing module obtains the noise edge segment of the SRAM under test from the fitted line based on the read / write test results of each bit includes: For each bit, if the read / write test result of the bit is that the read / write function is normal, then the weight value of the bit is set to the first value; if the read / write test result of the bit is that at least one read or write operation fails, then the weight value of the bit is set to the second value. Iterate through each target point set on the fitting line. For each target point, obtain a set of points within a preset range around the target point. Determine the target weight corresponding to the target point based on the weight values ​​of all points in the set. For all the target points, a first endpoint and a second endpoint are obtained based on the target weights corresponding to all the target points. The first endpoint and the second endpoint are the inflection points where the target weight values ​​of the target points on the fitted line change. Based on the first endpoint and the second endpoint, the noise edge segment of the SRAM under test is obtained from the fitted line.

[0016] As an optional implementation, in a second aspect of the present invention, the specific operation method by which the line processing module obtains a set of points within a preset range around each target point includes: For each target point, the N surrounding points on the Bit distribution map that are closest to the target point in order of distance are obtained, and the N surrounding points are used as the point set within a preset range around the target point. Furthermore, the line processing module determines the target weight corresponding to the target point based on the weight values ​​corresponding to all points in the point set, including the following specific operation methods: The target weight corresponding to the target point is obtained by summing the weight values ​​of the N surrounding points within the point set.

[0017] As an optional implementation, in a second aspect of the invention, the SRAM under test is manufactured in the following manner: The process parameters corresponding to the circuit structure of each bit in the SRAM under test are obtained. The process parameters include one or more of transistor size, channel doping concentration, and gate oxide thickness. The process parameters are adjusted based on a Gaussian distribution so that each parameter in the process parameters corresponding to all the bit circuit structures satisfies a Gaussian distribution within a preset value range, thereby obtaining the distributed process parameters corresponding to each bit circuit structure. The SRAM under test is manufactured based on the aforementioned distributed process parameters.

[0018] As an optional implementation, in a second aspect of the invention, adjusting the process parameters based on a Gaussian distribution includes: For each process parameter: Based on the current values ​​corresponding to the process parameters, a Gaussian distribution curve with the mean of the current values ​​is generated. Within a preset numerical range, a segment of the Gaussian distribution curve is extracted, and M adjustment values ​​are uniformly obtained on this segment, where M is the number of the Bit circuit structures. The values ​​of the process parameters corresponding to the M bit circuit structures are replaced with M adjustment values ​​so that the process parameters corresponding to the M bit circuit structures satisfy a Gaussian distribution within a preset value range.

[0019] As an optional implementation, in a second aspect of the invention, the apparatus further includes: The parameter setting module is used to set the simulated MOS parameters, which are matched with the process parameters of the SRAM under test. The simulated MOS parameters include one or more of the following: threshold voltage, saturation current, subthreshold swing, drain-induced barrier reduction, gate-induced leakage current, and statistical mismatch parameters. The simulation module is used to simulate the simulated SRAM based on the simulated MOS parameters, and obtain the simulated values ​​of read noise margin and write noise margin corresponding to the simulated SRAM. The feedback adjustment module is used to determine whether the simulated read noise margin value and the simulated write noise margin value are located on the noise edge corresponding to the noise edge segment; if not, the simulation MOS parameters are adjusted and the simulation is repeated until the simulated read noise margin value and the simulated write noise margin value are located on the noise edge, and the simulated read noise margin value and the simulated write noise margin value at this time are determined to be the final simulated read noise margin value and the simulated write noise margin value.

[0020] As an optional implementation, in a second aspect of the present invention, the specific operation method by which the feedback adjustment module determines whether the simulated read noise tolerance value and the simulated write noise tolerance value are located on the noise edge corresponding to the noise edge segment includes: Based on the noise edge segment, calculate the average read noise tolerance and average write noise tolerance corresponding to the noise edge segment; Calculate the difference between the simulated read noise tolerance value and the average read noise tolerance value; calculate the difference between the simulated write noise tolerance value and the average write noise tolerance value. Determine whether the read noise tolerance difference and the write noise tolerance difference are both less than a preset difference threshold, thereby determining whether the simulated read noise tolerance value and the simulated write noise tolerance value are located on the noise edge corresponding to the noise edge segment.

[0021] A third aspect of this invention discloses an SRAM noise edge analysis system, the system comprising: Memory containing executable program code; A processor coupled to the memory; The processor calls the executable program code stored in the memory to execute some or all of the steps in the SRAM noise edge analysis method according to any of the first aspects of the present invention.

[0022] The fourth aspect of the present invention discloses a computer storage medium storing computer instructions, which, when invoked by a processor, are used to execute some or all of the steps in the SRAM noise edge analysis method described in any of the first aspects of the present invention.

[0023] Compared with the prior art, the present invention can produce the following unexpected technical effects: This invention creatively discovers that, on the bit distribution map, points that pass all read and write tests are often distributed around a line segment. Therefore, the noise edge corresponding to the entire SRAM can be defined on a straight line. Thus, this invention first obtains the read and write test results, read noise tolerance, and write noise tolerance of each bit in the SRAM under test. Then, it obtains the bit distribution map and uses a straight line fitting method to fit all points on the bit distribution map, obtaining a fitted line. This fitted line corresponds to the straight line of the noise edge corresponding to the entire SRAM. Finally, based on the read and write test results of each bit, the noise edge segment of the SRAM under test is obtained from the fitted line, thereby reliably analyzing the noise edge corresponding to the SRAM under test.

[0024] Furthermore, the noise edge segment has the following function: (1) The larger the noise edge range, the stronger the ability of the circuit system to maintain normal operation. The noise edge can measure the ability of the circuit system to maintain normal operation, and therefore has guiding significance for the SRAM fabrication process. For example, a larger noise edge range can be used as a process improvement target to optimize the SRAM fabrication process.

[0025] (2) The noise edge segment can indicate a balanced and reliable read noise margin and write noise margin. In the early stages of the research and development process, simulation methods are often used to calculate and analyze the read noise margin and write noise margin. However, since it is difficult to control the parameters in the simulation process to be the same as the actual situation, the analyzed read noise margin and write noise margin often have no guiding significance. Since the noise edge segment in this invention can define a balanced and reliable read noise margin and write noise margin, it can be used to guide the parameter adjustment in the simulation process. When the simulation result is located on the noise edge segment, the obtained simulation value can be considered to have guiding significance. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 It is a 6T SRAM circuit; Figure 2 This is a schematic flowchart of an SRAM noise edge analysis method disclosed in an embodiment of the present invention; Figure 3 This is a schematic diagram of the read noise margin and write noise margin line segments on the bit distribution graph; Figure 4 This is a schematic diagram of the fitted line obtained by fitting all points on the Bit distribution map using a linear fitting method; Figure 5 This is a schematic diagram of the structure of an SRAM noise edge analysis device disclosed in an embodiment of the present invention; Figure 6 This is a schematic diagram of another SRAM noise edge analysis device disclosed in an embodiment of the present invention; Figure 7 This is a schematic diagram of the structure of an SRAM noise edge analysis system disclosed in an embodiment of the present invention. Detailed Implementation

[0028] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0029] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, apparatus, product, or end that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or ends.

[0030] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0031] This invention discloses an SRAM noise edge analysis method, apparatus, system, and storage medium, which provides a relatively reliable solution for analyzing noise edges corresponding to SRAM.

[0032] Example 1 An SRAM consists of multiple 6T or 4T SRAM circuits, each SRAM circuit forming a one-bit storage unit, such as... Figure 1 As shown, Figure 1 It is a 6T SRAM circuit.

[0033] Figure 1 The data reading methods for the 6TSRAM circuit include: (1) SRAM read operation: relying on the voltage signal difference between the two bit lines BL / BLB Assuming the SRAM stores 0 data: SNL=0, SNR=1; Assuming the SRAM stores 1 unit of data: SNL=1, SNR=0; Assuming the SRAM currently stores 0 data, the test conditions are as follows: Given BL=BLB=1 and WL=1, under these conditions, since SNL=0 is at a low potential and SNR=1 is at a high potential, we have: 1. The first pull-up transistor PU1 is turned off, the first pull-down transistor PD1 is turned on, the second pull-down transistor PD2 is turned off, and the second pull-up transistor PU2 is turned on; 2. The potential of the second bit line BLB remains unchanged, but the first pull-down transistor PD1 is turned on, causing current to flow from the first bit line BL to the first power supply point VSS, resulting in a decrease in the potential of the first bit line BL. 3. Initially, BL=BLB=1. After the potential of the first bit line BL drops, a voltage difference will appear between the first bit line BL and the second bit line BLB. This signal will be output through the external amplifier circuit, and the SRAM signal reading is completed.

[0034] (2) SRAM write operation: relying on reversing the potential of the first storage node SNL and the second storage node SNR. Assume the SRAM stores 0 data, SNL=0, SNR=1; the test conditions are as follows: Given BL=1, BLB=0, WL=1, under these conditions: 1. The first pull-up transistor PU1 is turned off, the first pull-down transistor PD1 is turned on, the second pull-down transistor PD2 is turned off, the second pull-up transistor PU2 is turned on. Since BLB=0 and WL=1, the second transmission transistor PG2 is turned on, and the SNR potential of the second storage node gradually decreases. 2. The decrease in the SNR potential of the second storage node causes the first pull-up transistor PU1 to turn on and the first pull-down transistor PD1 to turn off, thus the SNL potential of the first storage node rises. 3. The rise in the SNL potential of the first storage node causes the second pull-down transistor PD2 to turn on and the second pull-up transistor PU2 to turn off, thus completing the data flip.

[0035] An SRAM memory includes numerous 6T or 4T SRAM circuits. This invention proposes a relatively reliable scheme for analyzing the noise edges corresponding to SRAM.

[0036] Please see Figure 2 , Figure 2 This is a flowchart illustrating an SRAM noise edge analysis method disclosed in an embodiment of the present invention. Figure 2 The described SRAM noise edge analysis method can be integrated into an SRAM noise edge analysis device, which can be integrated into a cloud server or a local server. Figure 2 As shown, the SRAM noise edge analysis method may include the following operations: Step 101: Perform read and write tests on each bit in the SRAM under test to obtain the read and write test results for each bit.

[0037] In this embodiment of the invention, the SRAM under test also includes numerous 6T or 4T SRAM circuits. This embodiment aims to perform noise edge analysis on the entire SRAM under test. Each bit in the SRAM under test corresponds to a 6T or 4T SRAM circuit. Read and write tests are performed on the bits. The test principle can be: writing data, reading data, and comparing whether the two are consistent. Specifically, a TSK probe station can be used to perform the read and write tests.

[0038] Step 102: Measure the read noise margin and write noise margin of each bit in the SRAM under test.

[0039] In this embodiment of the invention, the measurement object of read noise margin and write noise margin is a single bit. Specifically, as those skilled in the art will understand, RSNM can be measured using a butterfly curve and WM can be measured using a write current / voltage scan method.

[0040] It should be emphasized that there is no clear order of execution between steps 101 and 102 in the embodiments of the present invention. Step 102 can be executed first, followed by step 101.

[0041] Step 103: Obtain the Bit distribution map.

[0042] In this embodiment of the invention, the horizontal and vertical axes of the Bit distribution graph are the read noise tolerance and the write noise tolerance, respectively, and each point on the Bit distribution graph represents the read noise tolerance and write noise tolerance corresponding to 1 Bit.

[0043] In the embodiments of the present invention, the test objects in steps 101 and 102 are all individual bits. However, in the embodiments of this application, the object to be analyzed for noise edge is the entire SRAM under test. Therefore, the embodiments of the present invention choose to combine the read noise tolerance and write noise tolerance of many bits for analysis: establish a bit distribution map.

[0044] Step 104: Fit all points on the Bit distribution map using a straight line fitting method to obtain the fitted line.

[0045] Inventive discovery of the present invention: It is known that read noise margin is the maximum DC noise voltage that the data nodes stored inside a memory cell can withstand during a read operation. Write noise margin is the minimum bit line voltage difference required to successfully flip the data inside the memory cell during a write operation. This invention has found that, on the bit distribution map, points that pass both read and write tests are often distributed around a line segment. Therefore, this invention defines the noise edge corresponding to the entire SRAM on a straight line, such as... Figure 3 As shown, Figure 3 The read noise margin-write noise margin line segment is divided into three segments. The green sub-segment in the middle of this line segment corresponds to WMmin-WMmax and RSNMmin-RSNMmax. All points on this line segment can satisfy the condition that all read and write tests pass.

[0046] Therefore, as Figure 4 As shown, in this embodiment of the invention, a straight line fitting method is used to fit all points on the bit distribution map to obtain a fitting line. This fitting line corresponds to the definition of the noise edge of the entire SRAM on a straight line in this embodiment of the invention.

[0047] Step 105: Based on the read and write test results of each bit, obtain the noise edge segment of the SRAM under test from the fitted line.

[0048] In this embodiment of the invention, the noise edge corresponding to the entire SRAM is defined on a straight line, and the fitted line is taken as this straight line. Therefore, the noise edge segment of the SRAM under test must lie on this fitted line. Figure 3 As shown. In this embodiment of the invention, the noise edge segment of the SRAM under test corresponds to WMmin-WMmax and RSNMmin-RSNMmax, which are used to represent the appropriate SRAM read / write capability range. This range describes the ability of the circuit system to maintain normal operation in the presence of noise.

[0049] In this embodiment of the invention, the noise edge segment of the SRAM under test can be obtained from the fitting line based on the read and write test results of each bit. For example, the distribution of points corresponding to the bits that passed the read and write test can be analyzed. These points are distributed around the noise edge segment. By analyzing the distribution of points corresponding to the bits that passed the read and write test, the noise edge segment of the SRAM under test can be obtained from the fitting line.

[0050] In summary, the embodiments of the present invention can produce the following unexpected technical effects: This invention creatively discovers that, on the bit distribution map, points that pass all read and write tests are often distributed around a line segment. Therefore, the noise edge corresponding to the entire SRAM can be defined on a straight line. Thus, this invention first obtains the read and write test results, read noise tolerance, and write noise tolerance of each bit in the SRAM under test. Then, it obtains the bit distribution map and uses a straight line fitting method to fit all points on the bit distribution map, obtaining a fitted line. This fitted line corresponds to the straight line of the noise edge corresponding to the entire SRAM. Finally, based on the read and write test results of each bit, the noise edge segment of the SRAM under test is obtained from the fitted line, thereby reliably analyzing the noise edge corresponding to the SRAM under test.

[0051] Furthermore, the noise edge segment has the following function: (1) The larger the noise edge range, the stronger the ability of the circuit system to maintain normal operation. The noise edge can measure the ability of the circuit system to maintain normal operation, and therefore has guiding significance for the SRAM fabrication process. For example, a larger noise edge range can be used as a process improvement target to optimize the SRAM fabrication process.

[0052] (2) The noise edge segment can indicate a balanced and reliable read noise margin and write noise margin. In the early stages of the research and development process, simulation methods are often used to calculate and analyze the read noise margin and write noise margin. However, since it is difficult to control the parameters in the simulation process to be the same as the actual situation, the analyzed read noise margin and write noise margin often have no guiding significance. Since the noise edge segment in the embodiment of the present invention can define a balanced and reliable read noise margin and write noise margin, it can be used to guide the parameter adjustment in the simulation process. When the simulation result is located on the noise edge segment, the obtained simulation value can be considered to have guiding significance.

[0053] In an optional embodiment, obtaining the noise edge segment of the SRAM under test from the fitted line based on the read / write test results of each bit may include: For each bit, if the read / write test result of the bit is that the read / write function is normal, then the weight value of the bit is set to the first value; if the read / write test result of the bit is that at least one read or write operation fails, then the weight value of the bit is set to the second value. For example, if the read / write function of the bit is normal, then its FBC=0; if the bit has at least one read or write operation failed, then its FBC=1.

[0054] Iterate through each target point set on the fitting line. For each target point, obtain the set of points within a preset range around the target point. Determine the target weight corresponding to the target point based on the weight values ​​of all points in the set.

[0055] For the fitted line, multiple target points can be preset on it according to the accuracy requirements. For example, 1000 points can be evenly distributed on the fitted line, and then these 1000 points can be traversed. In each traversal process, the target weight of the traversed point is determined based on the weight values ​​of the points surrounding the traversed point. For example, if the weight values ​​of the points surrounding the traversed point are all 0, then the target weight of the traversed point is also 0; conversely, if the weight values ​​of the points surrounding the traversed point are all 1, then the target weight of the traversed point is also 1; if the weight values ​​of the points surrounding the traversed point are partly 1 and partly 0, then the target weight of the traversed point is determined based on the distribution of 1 and 0.

[0056] In this optional embodiment, the target weight of the target point can reflect the change of the weight value of the points in the preset area around the target point. For example, when traversing from one end of the entire fitting line to the other end, the weight value of the target point will gradually decrease from 1 to 0, and then gradually increase from 0 to 1. Therefore, it is only necessary to find the inflection point of change from 0 to 1 or from 1 to 0 to obtain the two endpoints of the noise edge line segment.

[0057] For all target points, the first endpoint and the second endpoint are obtained based on the target weights corresponding to all target points. The first endpoint and the second endpoint are the inflection points where the target weight values ​​of the target points on the fitted line change.

[0058] Based on the first and second endpoints, the noise edge segment of the SRAM under test is obtained from the fitted line.

[0059] As can be seen, this optional embodiment proposes a fast and efficient method for obtaining noise edge segments. It adopts a traversal scheme of target points, calculates the target weight value corresponding to each target point during the traversal process, and finally finds the inflection point where the target weight value of the target point on the fitting line changes based on the change of the target weight value of the target point, thereby quickly and efficiently obtaining the two endpoints of the noise edge segment.

[0060] Furthermore, for each target point, a set of points within a preset range surrounding that target point is obtained, which may include: For each target point, obtain the N surrounding points on the Bit distribution map that are closest to the target point in order of distance, and use the N surrounding points as the point set within a preset range around the target point; Furthermore, based on the weight values ​​corresponding to all points within the point set, the target weight corresponding to the target point is determined, which may include: The target weight of the target point is obtained by summing the weights of the N surrounding points within the point set.

[0061] In this optional embodiment, the preset range around the target point is not set to a fixed-size area because the density of points around each target point varies. Simply taking points from a fixed area around the target point would not be accurate enough. This optional embodiment uses the N nearest points to the target point as the point set within the preset range around the target point. This ensures that the number of points in the point set corresponding to each target point is the same, improving the accuracy of the target weight calculation.

[0062] In this embodiment of the invention, the noise edge can measure the ability of a circuit system to maintain normal operation, and therefore has guiding significance for the SRAM fabrication process. For example, a larger noise edge range can be used as a process improvement target to optimize the SRAM fabrication process. For such process improvement guidance, it is necessary to know how changes in a specific process parameter will affect the final noise edge.

[0063] Therefore, before SRAM noise edge analysis, the process parameters corresponding to the circuit structure of each bit on the SRAM under test can be fine-tuned. This fine-tuning will make the points on the final bit map more dispersed and able to fit a more accurate fitting line because more dispersed points are more consistent with a linear distribution. Therefore, in another optional embodiment, the SRAM under test is manufactured in the following manner: The process parameters corresponding to each bit circuit structure in the SRAM under test are obtained. The process parameters include at least one or more of the following: transistor size, channel doping concentration, and gate oxide layer thickness. The above process parameters are all parameters that can affect the final noise edge.

[0064] The process parameters are adjusted based on Gaussian distribution so that each parameter in the process parameters corresponding to all bit circuit structures satisfies Gaussian distribution within a preset value range, thus obtaining the distributed process parameters corresponding to each bit circuit structure. Manufacturing the SRAM under test based on distributed process parameters.

[0065] In this optional embodiment, the Gaussian distribution is a common state distribution function in nature. For the distribution of process parameters, each process parameter is deliberately designed to satisfy the Gaussian distribution, so that the points on the final Bit distribution map are more in line with the scatter distribution under the natural deviation state, thereby more naturally amplifying the influence of each process parameter on the noise edge, and finally fitting to a more accurate fitting line.

[0066] Further, optionally, adjusting the process parameters based on a Gaussian distribution may include: For each process parameter: Based on the current values ​​of the process parameters, a Gaussian distribution curve with the mean of the current values ​​is generated. Within a preset numerical range, a segment of the Gaussian distribution curve is extracted, and M adjustment values ​​are uniformly obtained on this segment, where M is the number of bit circuit structures. The values ​​of the process parameters corresponding to the M-bit circuit structure are replaced with M adjustment values ​​so that the process parameters corresponding to the M-bit circuit structure satisfy a Gaussian distribution within a preset value range.

[0067] In this embodiment of the invention, the noise edge segment can define balanced and reliable read noise tolerance and write noise tolerance, thus guiding parameter adjustment in the simulation process. When the simulation result lies on the noise edge segment, the obtained simulation value can be considered to be instructive. Therefore, in another optional embodiment, the method may further include: Set the simulated MOS parameters to match the process parameters of the SRAM under test. The simulated MOS parameters include one or more of the following: threshold voltage, saturation current, subthreshold swing, drain-induced barrier reduction, gate-induced leakage current, and statistical mismatch parameters. The simulated SRAM is simulated based on the simulated MOS parameters to obtain the simulated read noise margin and write noise margin values ​​corresponding to the simulated SRAM. Those skilled in the art will understand that various simulation methods in the field can be used for simulation, such as the common Monte Carlo simulation.

[0068] Determine whether the simulated values ​​of read noise margin and write noise margin are located on the noise edge corresponding to the noise edge segment; if not, adjust the simulation MOS parameters and re-simulate until the simulated values ​​of read noise margin and write noise margin are located on the noise edge, and determine the simulated values ​​of read noise margin and write noise margin at this time as the final simulated values ​​of read noise margin and write noise margin.

[0069] As can be seen, this optional embodiment can overcome the problem of inaccurate simulation caused by the simulation environment not fully conforming to the actual operating environment of SRAM when simulating SRAM circuits in the prior art, making the final simulation value more instructive.

[0070] Further, optionally, determining whether the simulated values ​​of the read noise margin and the write noise margin are located on the noise edge corresponding to the noise edge segment can include: Based on the noise edge segments, calculate the average read noise margin and average write noise margin corresponding to the noise edge segments; Calculate the difference between the simulated read noise margin value and the average read noise margin value; calculate the difference between the simulated write noise margin value and the average write noise margin value. The system determines whether the read noise margin difference and the write noise margin difference are both less than a preset difference threshold, thereby determining whether the simulated read noise margin value and the simulated write noise margin value are located on the noise edge corresponding to the noise edge segment. The difference threshold can be set to 5mV.

[0071] Example 2 Please see Figure 5 , Figure 5 This is a schematic diagram of the structure of an SRAM noise edge analysis device disclosed in an embodiment of the present invention. Figure 5 As shown, the SRAM noise edge analysis device may include: The read / write test module 201 is used to perform read / write tests on each bit in the SRAM under test and obtain the read / write test results for each bit. Noise analysis module 202 is used to measure the read noise margin and write noise margin of each bit in the SRAM under test; Data analysis module 203 is used to obtain a bit distribution map, wherein the horizontal and vertical axes of the bit distribution map are read noise tolerance and write noise tolerance, respectively, and each point on the bit distribution map represents the read noise tolerance and write noise tolerance corresponding to 1 bit; The straight line fitting module 204 is used to fit all points on the Bit distribution map using a straight line fitting method to obtain a fitted line; The line processing module 205 is used to obtain the noise edge segment of the SRAM under test from the fitted line based on the read and write test results of each bit.

[0072] In an optional embodiment, the line processing module 205 obtains the specific operation method of the noise edge segment of the SRAM under test from the fitted line based on the read / write test results of each bit, including: For each bit, if the read / write test result of the bit is that the read / write function is normal, then the weight value of the bit is set to the first value; if the read / write test result of the bit is that at least one read or write operation fails, then the weight value of the bit is set to the second value. Iterate through each target point set on the fitting line. For each target point, obtain a set of points within a preset range around the target point. Determine the target weight corresponding to the target point based on the weight values ​​of all points in the set. For all the target points, a first endpoint and a second endpoint are obtained based on the target weights corresponding to all the target points. The first endpoint and the second endpoint are the inflection points where the target weight values ​​of the target points on the fitted line change. Based on the first endpoint and the second endpoint, the noise edge segment of the SRAM under test is obtained from the fitted line.

[0073] In another optional embodiment, the line processing module 205 obtains a set of points within a preset range around each target point in a specific operation manner, including: For each target point, the N surrounding points on the Bit distribution map that are closest to the target point in order of distance are obtained, and the N surrounding points are used as the point set within a preset range around the target point. And, the line processing module 205 determines the target weight corresponding to the target point based on the weight values ​​corresponding to all points in the point set, including: The target weight corresponding to the target point is obtained by summing the weight values ​​of the N surrounding points within the point set.

[0074] In yet another alternative embodiment, the SRAM under test is manufactured in the following manner: The process parameters corresponding to the circuit structure of each bit in the SRAM under test are obtained. The process parameters include one or more of transistor size, channel doping concentration, and gate oxide thickness. The process parameters are adjusted based on a Gaussian distribution so that each parameter in the process parameters corresponding to all the bit circuit structures satisfies a Gaussian distribution within a preset value range, thereby obtaining the distributed process parameters corresponding to each bit circuit structure. The SRAM under test is manufactured based on the aforementioned distributed process parameters.

[0075] In yet another optional embodiment, adjusting the process parameters based on a Gaussian distribution includes: For each process parameter: Based on the current values ​​corresponding to the process parameters, a Gaussian distribution curve with the mean of the current values ​​is generated. Within a preset numerical range, a segment of the Gaussian distribution curve is extracted, and M adjustment values ​​are uniformly obtained on this segment, where M is the number of the Bit circuit structures. The values ​​of the process parameters corresponding to the M bit circuit structures are replaced with M adjustment values ​​so that the process parameters corresponding to the M bit circuit structures satisfy a Gaussian distribution within a preset value range.

[0076] In yet another alternative embodiment, such as Figure 6 As shown, the device further includes: The parameter setting module 206 is used to set the simulated MOS parameters, which are matched with the process parameters of the SRAM under test. The simulated MOS parameters include one or more of the following: threshold voltage, saturation current, subthreshold swing, drain-induced barrier reduction, gate-induced leakage current, and statistical mismatch parameters. Simulation module 207 is used to simulate the simulated SRAM based on the simulated MOS parameters to obtain the simulated read noise margin simulation value and write noise margin simulation value corresponding to the simulated SRAM. The feedback adjustment module 208 is used to determine whether the simulated read noise tolerance value and the simulated write noise tolerance value are located on the noise edge corresponding to the noise edge segment; if not, the simulation MOS parameters are adjusted and the simulation is repeated until the simulated read noise tolerance value and the simulated write noise tolerance value are located on the noise edge, and the simulated read noise tolerance value and the simulated write noise tolerance value at this time are determined to be the final simulated read noise tolerance value and the simulated write noise tolerance value.

[0077] In another optional embodiment, the specific operation method by which the feedback adjustment module 208 determines whether the simulated read noise tolerance value and the simulated write noise tolerance value are located on the noise edge corresponding to the noise edge segment includes: Based on the noise edge segment, calculate the average read noise tolerance and average write noise tolerance corresponding to the noise edge segment; Calculate the difference between the simulated read noise tolerance value and the average read noise tolerance value; calculate the difference between the simulated write noise tolerance value and the average write noise tolerance value. Determine whether the read noise tolerance difference and the write noise tolerance difference are both less than a preset difference threshold, thereby determining whether the simulated read noise tolerance value and the simulated write noise tolerance value are located on the noise edge corresponding to the noise edge segment.

[0078] Example 3 Please see Figure 7 , Figure 7 This is a schematic diagram of the structure of an SRAM noise edge analysis system disclosed in an embodiment of the present invention. The SRAM noise edge analysis system may include: Memory 301 storing executable program code; Processor 302 coupled to memory 301; The processor 302 calls the executable program code stored in the memory 301 to execute some or all of the steps in any of the SRAM noise edge analysis methods in Embodiment 1 of the present invention.

[0079] Example 4 This invention discloses a computer storage medium storing computer instructions. When these computer instructions are executed by a processor, they implement some or all of the steps in any of the SRAM noise edge analysis methods in this invention.

[0080] The device embodiments described above are merely illustrative. The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules; that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0081] Through the detailed description of the above embodiments, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, including read-only memory (ROM), random access memory (RAM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), one-time programmable read-only memory (OTPROM), electrically-Erasable Programmable Read-Only Memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, disk storage, magnetic tape storage, or any other computer-readable medium that can be used to carry or store data.

[0082] Finally, it should be noted that the above embodiments are merely preferred embodiments of the present invention and are only used to illustrate the technical solutions of the present invention, not to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for SRAM noise edge analysis, characterized in that, The method includes: Perform read and write tests on each bit in the SRAM under test to obtain the read and write test results for each bit; Measure the read noise margin and write noise margin of each bit in the SRAM under test; Obtain a bit distribution map, wherein the horizontal and vertical axes of the bit distribution map are read noise tolerance and write noise tolerance, respectively, and each point on the bit distribution map represents the read noise tolerance and write noise tolerance corresponding to 1 bit; A straight line fitting method is used to fit all points on the Bit distribution map to obtain a fitted line; For each bit, if the read / write test result of the bit is that the read / write function is normal, then the weight value of the bit is set to the first value; if the read / write test result of the bit is that at least one read or write operation fails, then the weight value of the bit is set to the second value. Iterate through each target point set on the fitting line. For each target point, obtain a set of points within a preset range around the target point. Determine the target weight corresponding to the target point based on the weight values ​​of all points in the set. For all the target points, a first endpoint and a second endpoint are obtained based on the target weights corresponding to all the target points. The first endpoint and the second endpoint are the inflection points where the target weight values ​​of the target points on the fitted line change. Based on the first endpoint and the second endpoint, the noise edge segment of the SRAM under test is obtained from the fitted line.

2. The SRAM noise edge analysis method according to claim 1, characterized in that, For each target point, obtaining the set of points within a preset range surrounding that target point includes: For each target point, the N surrounding points on the Bit distribution map that are closest to the target point in order of distance are obtained, and the N surrounding points are used as the point set within a preset range around the target point. And, determining the target weight corresponding to the target point based on the weight values ​​corresponding to all points in the point set includes: The target weight corresponding to the target point is obtained by summing the weight values ​​of the N surrounding points within the point set.

3. The SRAM noise edge analysis method according to claim 1, characterized in that, The SRAM under test is manufactured in the following manner: The process parameters corresponding to the circuit structure of each bit in the SRAM under test are obtained. The process parameters include one or more of transistor size, channel doping concentration, and gate oxide thickness. The process parameters are adjusted based on a Gaussian distribution so that each parameter in the process parameters corresponding to all the bit circuit structures satisfies a Gaussian distribution within a preset value range, thereby obtaining the distributed process parameters corresponding to each bit circuit structure. The SRAM under test is manufactured based on the aforementioned distributed process parameters.

4. The SRAM noise edge analysis method according to claim 3, characterized in that, The adjustment of the process parameters based on the Gaussian distribution includes: For each process parameter: Based on the current values ​​corresponding to the process parameters, a Gaussian distribution curve with the mean of the current values ​​is generated. Within a preset numerical range, a segment of the Gaussian distribution curve is extracted, and M adjustment values ​​are uniformly obtained on this segment, where M is the number of the Bit circuit structures. The values ​​of the process parameters corresponding to the M bit circuit structures are replaced with M adjustment values ​​so that the process parameters corresponding to the M bit circuit structures satisfy a Gaussian distribution within a preset value range.

5. The SRAM noise edge analysis method according to any one of claims 1-4, characterized in that, The method further includes: Set simulated MOS parameters, which are matched with the process parameters of the SRAM under test. The simulated MOS parameters include one or more of the following: threshold voltage, saturation current, subthreshold swing, drain-induced barrier reduction, gate-induced leakage current, and statistical mismatch parameters. The simulated SRAM is simulated based on the simulated MOS parameters to obtain the simulated read noise margin and write noise margin values ​​corresponding to the simulated SRAM. Determine whether the simulated read noise margin value and the simulated write noise margin value are located on the noise edge corresponding to the noise edge segment; if not, adjust the simulated MOS parameters and re-perform the simulation until the simulated read noise margin value and the simulated write noise margin value are located on the noise edge, and determine that the simulated read noise margin value and the simulated write noise margin value at this time are the final simulated read noise margin value and the simulated write noise margin value.

6. The SRAM noise edge analysis method according to claim 5, characterized in that, The step of determining whether the simulated read noise tolerance value and the simulated write noise tolerance value are located on the noise edge corresponding to the noise edge segment includes: Based on the noise edge segment, calculate the average read noise tolerance and average write noise tolerance corresponding to the noise edge segment; Calculate the difference between the simulated read noise tolerance value and the average read noise tolerance value; calculate the difference between the simulated write noise tolerance value and the average write noise tolerance value. Determine whether the read noise tolerance difference and the write noise tolerance difference are both less than a preset difference threshold, thereby determining whether the simulated read noise tolerance value and the simulated write noise tolerance value are located on the noise edge corresponding to the noise edge segment.

7. An SRAM noise edge analysis device, characterized in that, The device includes: The read / write test module is used to perform read / write tests on each bit in the SRAM under test and obtain the read / write test results for each bit. The noise analysis module is used to measure the read noise margin and write noise margin of each bit in the SRAM under test. The data analysis module is used to obtain a bit distribution map, wherein the horizontal and vertical axes of the bit distribution map are read noise tolerance and write noise tolerance, respectively, and each point on the bit distribution map represents the read noise tolerance and write noise tolerance corresponding to 1 bit; The line fitting module is used to fit all points on the Bit distribution map using a line fitting method to obtain a fitted line; The line processing module is used to: for each bit, if the read / write test result of the bit shows that the read / write function is normal, then set the weight value of the bit to a first value; if the read / write test result of the bit shows that at least one read or write operation failed, then set the weight value of the bit to a second value; traverse each target point set on the fitting line, for each target point, obtain a set of points within a preset range around the target point, and determine the target weight corresponding to the target point based on the weight values ​​corresponding to all points in the set; for all target points, obtain a first endpoint and a second endpoint based on the target weights corresponding to all target points, where the first endpoint and the second endpoint are inflection points where the target weight values ​​of the target points on the fitting line change; and obtain the noise edge segment of the SRAM under test from the fitting line based on the first endpoint and the second endpoint.

8. An SRAM noise edge analysis system, characterized in that, The system includes: a memory storing executable program code; a processor coupled to the memory; the processor calling the executable program code stored in the memory to execute the SRAM noise edge analysis method as described in any one of claims 1-6.

9. A computer storage medium, characterized in that, The computer storage medium stores computer instructions, which, when executed by a processor, implement the SRAM noise edge analysis method as described in any one of claims 1-6.

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