Method and system for multi-voltage domain voltage regulation and timing control in integrated circuits

Abstract

The application discloses a multi-power domain voltage regulation and timing control method and system in an integrated circuit, and particularly relates to the technical field of integrated circuit power management. The application captures the instantaneous current change rate and voltage drop amplitude of each power domain in real time, and identifies the load mutation characteristic parameters when any of the two exceeds the corresponding preset threshold. According to the parameters and the current working temperature, the application performs nonlinear correction based on a preset voltage-frequency mapping model to obtain a target voltage. The application monitors the disturbance propagation direction and gain between domains, and executes coupling suppression in combination with the disturbance state of adjacent domains to obtain a single-domain regulation instruction. According to the instruction and the current system state parameters, the application cooperatively generates an inner loop pulse voltage regulation and an outer loop timing alignment driving signal. The application realizes nanosecond-level response by capturing the load mutation in real time, effectively avoids voltage drop, improves the voltage setting precision in the low voltage and wide temperature range by using nonlinear correction, actively suppresses the disturbance propagation of multiple domains and forms a closed-loop feedback, and significantly improves the system stability.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit power management technology, and more specifically, to a method and system for multi-power domain voltage regulation and timing control in integrated circuits. Background Technology

[0002] In multi-power-domain integrated circuits, each power domain independently regulates its voltage, and timing control prevents excessive current or device damage caused by incorrect power-on sequence. Currently, a common approach is Dynamic Voltage and Frequency Scaling (DVFS) combined with the timing configuration of the power management chip. DVFS adjusts voltage and frequency based on the average load over a period of time, balancing power consumption and performance at most operating points.

[0003] However, in some application scenarios, the load changes very rapidly within the chip. For example, a module may suddenly go from almost no operation to full load operation, requiring an instantaneous voltage boost. Existing DVFS (Digital Voltage Regulator) systems, which require software sampling and calculation, take time to respond and often cannot keep up with such rapid load changes. Furthermore, multiple power domains can interfere with each other through power lines or substrates. A rapid change in voltage in one domain can cause fluctuations in adjacent domains, while conventional protection circuits only detect undervoltage or overvoltage in a single domain and do not actively coordinate the mutual influence between multiple domains. Therefore, this invention proposes a method and system for multi-power domain voltage regulation and timing control in integrated circuits to solve the above problems. Summary of the Invention

[0004] To achieve the above objectives, the present invention provides the following technical solution: A multi-power-domain voltage regulation and timing control method for integrated circuits includes the following steps: Real-time capture of instantaneous current change rate and voltage undershoot amplitude of each power domain; comparison of instantaneous current change rate with a preset first current change rate threshold; comparison of voltage undershoot amplitude with a preset first voltage undershoot threshold; identification of load change characteristic parameters when either parameter exceeds the corresponding threshold. Based on the load change characteristic parameters and the current operating temperature, nonlinear correction calculations are performed based on a preset voltage-frequency mapping relationship model to obtain the target voltage setpoint. Monitor the propagation direction and gain of disturbances between power domains, and perform coupling suppression processing based on the target voltage setpoint and the disturbance status of adjacent power domains monitored in real time to obtain single-domain adjustment commands; Based on the single-domain adjustment command and the current system state parameters, the inner loop pulse voltage regulation signal and the outer loop timing alignment signal are calculated in accordance with the preset strategy to generate drive signals for controlling the voltage regulation and timing of each power domain. The drive signal is applied to the voltage regulator corresponding to each power domain, and the actual voltage value fed back by each power domain is compared with the target voltage setting value. When the absolute value of the difference is greater than the preset deviation threshold, the step of real-time capture of instantaneous current change rate and voltage undershoot amplitude is restarted. The preset control period is the time unit used in the method to determine the stable state.

[0005] In a preferred embodiment, the instantaneous current change rate and voltage undershoot amplitude of each power domain are captured in real time. Specifically, a high-side current detection circuit and a voltage comparator array are used. Each power domain is equipped with an independent instantaneous current change rate detection path. This path converts the instantaneous current change rate into a pulse width through a differentiating network composed of resistors and capacitors. The pulse width is inversely proportional to the instantaneous current change rate. The voltage undershoot amplitude is captured by a hysteresis comparator and a digital peak hold circuit. When the hysteresis comparator is triggered, the digital peak hold circuit is activated to record the lowest voltage point.

[0006] In a preferred embodiment, the preset voltage-frequency mapping model is constructed using a piecewise linear interpolation table. This interpolation table is indexed by voltage and temperature values, stores the corresponding reference voltage settings, and calculates the current operating voltage and the preliminary voltage values ​​at the current operating temperature through bilinear interpolation.

[0007] The disturbance propagation direction and gain between each power domain are monitored by periodically injecting a small current pulse with a preset injection amplitude and a preset injection width at the output of the voltage regulator in each power domain, while simultaneously measuring the voltage response amplitude and response delay time of adjacent power domains. The disturbance propagation gain is determined based on the ratio of the voltage response amplitude to the preset injection amplitude, and the disturbance propagation direction is determined based on the response delay time. The disturbance propagation direction is from the source power domain of the injected pulse to the adjacent power domain where the voltage response amplitude is greater than the preset response threshold.

[0008] In a preferred embodiment, the coupling suppression process is performed according to the following rules: When the instantaneous current change rate of any power domain exceeds the preset second change rate threshold, a suppression signal is sent to all adjacent power domains of that power domain and a suppression state is entered. The maximum allowable voltage change slope of the adjacent power domains is temporarily reduced to the maximum allowable voltage change slope specified in the chip datasheet divided by the disturbance propagation gain obtained from the monitoring step. This suppression state continues until the instantaneous current change rate falls back to below the preset second change rate threshold and stabilizes for more than ten preset control cycles.

[0009] In a preferred embodiment, the current system state parameters include the current chip junction temperature, total chip power consumption, cumulative operating time of each power domain since chip power-on, and cumulative voltage stress value of each power domain. The cumulative voltage stress value is obtained by integrating the absolute value of the difference between the actual operating voltage and the rated voltage of each power domain over time, with the integration interval being from the start of this power-on to the current moment.

[0010] In a preferred embodiment, the triggering condition for restarting the step of real-time capture of instantaneous current change rate and voltage undershoot amplitude further includes: If, within three consecutive preset control cycles, the absolute value of the difference between the actual voltage value fed back from each power domain and the target voltage setting value is greater than zero and less than or equal to the preset deviation threshold, and the absolute value of the difference is greater than the value at the end of each cycle than at the end of the previous cycle, the steps are forcibly restarted. Furthermore, based on the ratio of the absolute value of the difference in the last cycle to the preset deviation threshold, the preset first current change rate threshold and the preset first voltage undershoot threshold are adjusted to their original values ​​divided by the ratio, i.e., multiplied by the reciprocal of the ratio.

[0011] In a preferred embodiment, the nonlinear correction calculation specifically employs the following steps: Extract the maximum peak value of the instantaneous current change rate and the maximum depth of the voltage downslope from the load change characteristic parameters; The first dimensionless coefficient is obtained by dividing the maximum peak value of the instantaneous current change rate by the preset reference change rate, and the second dimensionless coefficient is obtained by dividing the maximum depth of the voltage undershoot by the preset reference undershoot depth. The preset temperature compensation curve is queried based on the current operating temperature. This curve is composed of compensation factors corresponding to multiple temperature nodes. The compensation factor at the current temperature is obtained by linear interpolation. The first dimensionless coefficient, the second dimensionless coefficient, and the compensation factor are harmonic averaged. The formula for calculating the harmonic average is the product of the three factors divided by the sum of the pairwise products and then multiplied by three. The first dimensionless coefficient, the second dimensionless coefficient, and the compensation factor are all positive numbers. The harmonic mean is used as the comprehensive disturbance index. Substitute it into the preset error function, which adopts the Lorentz distribution form, to calculate the nonlinear compensation factor. The preset error function is calculated as follows: the nonlinear compensation factor is equal to the sum of the squares of the comprehensive disturbance index and the sum of the squares of the two values ​​in parentheses. Finally, the initial voltage value is multiplied by the square root of the nonlinear compensation factor to obtain the first intermediate value; then the initial voltage value is multiplied by the nonlinear compensation factor to obtain the second intermediate value; the average value of the first intermediate value and the second intermediate value is calculated to obtain the target voltage setpoint.

[0012] In a preferred embodiment, the single-domain adjustment command in the coupling suppression process is calculated through the following steps: Obtain the comprehensive disturbance index and the real-time values ​​of the instantaneous current change rate in adjacent power domains; A piecewise function for the comprehensive disturbance index is constructed. In the first interval, the piecewise function is the sine of the comprehensive disturbance index multiplied by a first coefficient. In the second interval, it is an exponential function with the natural constant as the base, and its exponent is the square of the negative comprehensive disturbance index multiplied by a second coefficient. The boundary between the first and second intervals is determined by a preset piecewise threshold. The first and second coefficients are obtained by offline fitting of the optimal suppression effect under typical disturbance scenarios. The coupling correlation strength is obtained by multiplying the output of the piecewise function with the disturbance propagation gain measured from the adjacent power domain. The difference between the target voltage setpoint and the actual voltage value fed back from the current power domain is used as the original adjustment amplitude. The difference between the original adjustment amplitude and the coupling correlation strength is calculated. Then, this difference is substituted into a saturation function. The saturation function outputs the value of the independent variable when the absolute value of the independent variable is less than the preset saturation threshold, and outputs the sign of the independent variable multiplied by the saturation threshold when the absolute value of the independent variable is greater than or equal to the saturation threshold, to obtain the limited difference. The preset saturation threshold is less than one. Then, the inverse hyperbolic tangent function value of the limited difference is taken to obtain the decoupling attenuation factor. Multiplying the original adjustment amplitude by the decoupling attenuation factor yields the final single-domain adjustment command.

[0013] In a preferred embodiment, the multi-power-domain voltage regulation and timing control system in the integrated circuit includes: The mutation identification module is used to capture the instantaneous current change rate and voltage undershoot amplitude of each power domain in real time, compare the instantaneous current change rate with a preset first current change rate threshold, and compare the voltage undershoot amplitude with a preset first voltage undershoot threshold. When either parameter exceeds the corresponding threshold, the load mutation characteristic parameter is identified. The nonlinear correction module is used to perform nonlinear correction calculations based on a preset voltage-frequency mapping model according to the load change characteristic parameters and the current operating temperature, so as to obtain the target voltage setpoint. The coupling suppression module is used to monitor the propagation direction and gain of disturbances between power domains. Based on the target voltage setpoint and the disturbance status of adjacent power domains monitored in real time, it performs coupling suppression processing to obtain single-domain adjustment commands. The dual-loop coordination module is used to perform coordinated calculations of the inner loop pulse voltage regulation signal and the outer loop timing alignment signal according to a preset strategy based on the single-domain adjustment command and the current system status parameters, thereby generating drive signals for controlling the voltage regulation and timing of each power domain. The closed-loop feedback module is used to apply the drive signal to the voltage regulator corresponding to each power domain, and compare the actual voltage value fed back by each power domain with the target voltage setting value. When the absolute value of the difference is greater than the preset deviation threshold, the sudden change recognition module is triggered to start execution again.

[0014] The technical effects and advantages of this invention are as follows: This invention captures the instantaneous current change rate and voltage undershoot amplitude of each power domain in real time and compares them directly with preset first current change rate thresholds and first voltage undershoot thresholds. Once either parameter exceeds the corresponding threshold, the load surge characteristic parameter is immediately identified. This triggering mechanism uses a hardware comparator instead of software sampling, enabling the detection of load surges within nanoseconds. This allows subsequent nonlinear correction calculations, coupling suppression processing, and drive signal generation to be completed within the same microsecond window. When the central processing unit or AI accelerator in the chip instantly switches from a deep idle state to full load operation, this invention can promptly increase the target voltage setpoint, preventing setup time violations or data errors caused by voltage drops, thereby ensuring the stable operation of high-performance modules under sudden loads.

[0015] This invention explicitly employs nonlinear correction calculations based on a preset voltage-frequency mapping model in the process of obtaining the target voltage setting value according to the load mutation characteristic parameters and the current operating temperature. This model can compensate for voltage-frequency nonlinear distortions that occur in the chip under low voltage regions and extreme high or low temperature conditions. For example, when the power domain operating voltage is close to the transistor threshold voltage, the delay increases exponentially with voltage decrease, and a simple linear mapping cannot accurately reflect this relationship. This invention calculates a more accurate target voltage setting value by comprehensively processing the maximum peak value of the instantaneous current change rate, the maximum depth of the voltage undershoot, and the current operating temperature. This avoids timing errors caused by setting the voltage too low and wasteful power consumption caused by setting the voltage too high. Within a wide temperature range (e.g., -40 degrees Celsius to 125 degrees Celsius), this invention can dynamically adjust the voltage compensation amount to ensure that the chip can operate at a safe and efficient voltage point under different environmental conditions.

[0016] This invention obtains single-domain regulation commands by monitoring the disturbance propagation direction and gain between power domains and performing coupling suppression processing. When any power domain experiences a large instantaneous current change rate due to a sudden load change, this invention sends suppression signals to all adjacent power domains, temporarily reducing the maximum allowable voltage change slope of adjacent domains, thereby cutting off the propagation path of disturbances coupled along the shared power supply network or substrate. Simultaneously, through the coordinated calculation of the inner-loop pulse voltage regulation signal and the outer-loop timing alignment signal, compatibility between fast voltage regulation and multi-domain timing requirements is ensured. Finally, after applying the drive signal to the voltage regulator, the actual voltage values ​​fed back from each power domain are continuously compared with the target voltage setpoint. Once the absolute value of the difference exceeds a preset deviation threshold, the entire process restarts, forming a closed-loop feedback control, significantly improving the robustness of the integrated circuit under complex dynamic loads. Attached Figure Description

[0017] To facilitate understanding by those skilled in the art, the present invention will be further described below with reference to the accompanying drawings; Figure 1 This is a schematic diagram of the multi-power domain voltage regulation and timing control method in the integrated circuit of the present invention.

[0018] Figure 2 This is a schematic diagram of the multi-power domain voltage regulation and timing control system in the integrated circuit of the present invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] Reference Figure 1 - Figure 2 The following examples were obtained: Example 1: A method for voltage regulation and timing control in multiple power supply domains of an integrated circuit, comprising the following steps: Real-time capture of instantaneous current change rate and voltage undershoot amplitude of each power domain; comparison of instantaneous current change rate with a preset first current change rate threshold; comparison of voltage undershoot amplitude with a preset first voltage undershoot threshold; identification of load change characteristic parameters when either parameter exceeds the corresponding threshold. Based on the load change characteristic parameters and the current operating temperature, nonlinear correction calculations are performed based on a preset voltage-frequency mapping relationship model to obtain the target voltage setpoint. Monitor the propagation direction and gain of disturbances between power domains, and perform coupling suppression processing based on the target voltage setpoint and the disturbance status of adjacent power domains monitored in real time to obtain single-domain adjustment commands; Based on the single-domain adjustment command and the current system state parameters, the inner loop pulse voltage regulation signal and the outer loop timing alignment signal are calculated in accordance with the preset strategy to generate drive signals for controlling the voltage regulation and timing of each power domain. The drive signal is applied to the voltage regulator corresponding to each power domain, and the actual voltage value fed back by each power domain is compared with the target voltage setting value. When the absolute value of the difference is greater than the preset deviation threshold, the step of real-time capture of instantaneous current change rate and voltage undershoot amplitude is restarted. The preset control period is the time unit used in the method to determine the stable state.

[0021] Real-time capture of instantaneous current change rate and voltage undershoot amplitude in each power domain is achieved using a high-side current detection circuit and a voltage comparator array. The high-side current detection circuit uses a model with a bandwidth of at least 10 MHz, determined based on the typical load transient rise time (e.g., 100 nanoseconds), ensuring distortion-free acquisition of the instantaneous current change rate. Each power domain is equipped with an independent instantaneous current change rate detection path, which converts the instantaneous current change rate into a pulse width through a differentiating network composed of resistors and capacitors. The resistor in the differentiating network is 100 ohms, and the capacitor is 22 picofarads; the time constant of this combination is 2.2 nanoseconds, set empirically to match the chip's maximum internal current change rate (e.g., 50 mA per nanosecond). The pulse width is inversely proportional to the instantaneous current change rate; for example, when the instantaneous current change rate is 10 mA per nanosecond, the pulse width is 2 microseconds; when the change rate increases to 50 mA per nanosecond, the pulse width decreases to 0.4 microseconds. The voltage undershoot amplitude is captured by a combination of a hysteresis comparator and a digital peak hold circuit.

[0022] The hysteresis comparator's hysteresis width is set to 50 mV, a value derived from the noise margin recommended in the power management chip's datasheet. When the hysteresis comparator is triggered, its reference voltage is preset to 90% of the target voltage (e.g., 0.9 V when the target voltage is 1.0 V). When the voltage undershoots below the reference voltage, the comparator outputs a high level. This high-level signal activates a digital peak hold circuit, which records the voltage minimum at a 500 MHz sampling clock. The sampling clock frequency is determined by the Nyquist theorem based on the maximum possible undershoot duration (e.g., 2 nanoseconds) on the power rail. The digital peak hold circuit internally contains a high-speed comparator and a digital register. When the input voltage falls below the register's stored value, the register value is updated, thereby capturing the minimum magnitude of the voltage undershoot; for example, in experiments, this circuit captured a minimum of 0.85 V. All threshold parameters (such as the 50 mV hysteresis width and the 90% reference voltage ratio) were obtained through Monte Carlo simulations of a batch of chips, with typical values ​​ranging from 30 to 70 mV and 85% to 95%.

[0023] The instantaneous current change rate is compared with a preset first current change rate threshold, which is set according to the maximum safe transient current change rate specified in the chip design datasheet, typically ranging from 30 mA to 80 mA per nanosecond, for example, 50 mA per nanosecond. The voltage undershoot is compared with a preset first voltage undershoot threshold, which is set according to the voltage sag tolerance given in the power management chip datasheet, typically ranging from 8% to 15% of the nominal voltage, for example, 120 mV for a nominal voltage of 1.2 V. Load mutation characteristic parameters are identified when the instantaneous current change rate exceeds the first current change rate threshold, or when the voltage undershoot exceeds the first voltage undershoot threshold.

[0024] For example, if the instantaneous current change rate of a power domain reaches 65 mA per nanosecond (exceeding 50 mA per nanosecond) and the voltage downsampling amplitude is 150 mV (exceeding 120 mV), identification is triggered. At this time, the load change characteristic parameters include the identifier of the power domain, the timestamp of exceeding the threshold, and the specific value exceeded.

[0025] When any parameter exceeds its corresponding threshold, load transient characteristic parameters are identified. These parameters include the maximum peak value of the instantaneous current change rate and the maximum depth of the voltage undershoot during the transient event. The maximum peak value of the instantaneous current change rate is obtained by measuring the minimum pulse width of the differential network output, as the pulse width is inversely proportional to the instantaneous current change rate. For example, if the minimum pulse width is measured to be 0.4 microseconds, the corresponding maximum peak value of the instantaneous current change rate is 50 mA per nanosecond. The maximum depth of the voltage undershoot is obtained by the difference between the lowest voltage value recorded by the digital peak hold circuit and the target voltage setting. For example, if the target voltage setting is 1.0 V and the recorded lowest voltage is 0.85 V, the maximum depth is 150 mV. The load transient characteristic parameters also include the current operating temperature, which is read by an on-chip temperature sensor with a typical accuracy of ±1 degree Celsius.

[0026] Based on the load transient characteristic parameters and the current operating temperature, a nonlinear correction calculation is performed using a preset voltage-frequency mapping model to obtain the target voltage setpoint. This nonlinear correction calculation requires two inputs: the first is the load transient characteristic parameters (including the maximum peak value of the instantaneous current change rate and the maximum depth of the voltage undershoot), and the second is the current operating temperature. Additionally, the current operating voltage is needed as an index for interpolation queries. This current operating voltage is obtained in real-time from the actual voltage values ​​fed back from each power domain, such as reading the voltage sample value at the voltage regulator output, with a typical sampling accuracy of 10 millivolts and a sampling frequency of 1 MHz.

[0027] The preset voltage-frequency mapping model is constructed using a piecewise linear interpolation table. This table uses voltage and temperature values ​​as indices to store the corresponding reference voltage settings. The reference voltage settings are defined as the minimum safe voltage value that ensures the chip's normal operation, measured offline at specific voltage and temperature index points. For example, at a voltage index point of 0.8 volts and a temperature index point of 25 degrees Celsius, the experimentally measured reference voltage setting is 0.82 volts, and this value is stored in the table. The voltage index range of the interpolation table covers 0.6 volts to 1.4 volts with a step size of 20 millivolts; the temperature index range covers -40 degrees Celsius to 125 degrees Celsius with a step size of 10 degrees Celsius.

[0028] Preliminary voltage values ​​at the current operating voltage and temperature are calculated using bilinear interpolation. Specifically, using the current operating voltage (e.g., 0.85 volts) and current operating temperature (e.g., 85 degrees Celsius) as lookup points, two adjacent voltage index points (0.84 volts and 0.86 volts) and two temperature index points (80 degrees Celsius and 90 degrees Celsius) are located in the interpolation table. The four reference voltage settings corresponding to these four index points are read. First, linear interpolation is performed along the voltage direction to obtain the intermediate values ​​for 0.85 volts at 80 degrees Celsius and 0.85 volts at 90 degrees Celsius. Then, linear interpolation is performed along the temperature direction to obtain the final preliminary voltage value. For example, if the four reference voltage settings are 0.83 volts, 0.85 volts, 0.84 volts, and 0.86 volts, the calculated preliminary voltage value is 0.845 volts. This preliminary voltage value is the reference voltage setting value without nonlinear compensation and will be used as input for subsequent nonlinear compensation factor calculations.

[0029] The propagation direction and gain of disturbances between power domains are monitored by periodically injecting a small current pulse with a preset injection amplitude and width at the output of the voltage regulator in each power domain. The preset injection amplitude is 5% to 15% of the nominal load current, for example, 10%. This percentage is set empirically to ensure that the disturbance is measurable and does not affect normal operation. A typical nominal load current of 2 amps results in an injection amplitude of 200 mA. The preset injection width is 500 nanoseconds to 2 microseconds, for example, 1 microsecond. This width is determined based on the charging time constant of the power domain's output capacitor (approximately 0.5 microseconds) to ensure that the pulse can be detected by adjacent domains. The injection period is 100 microseconds to 1 millisecond, for example, 500 microseconds. This period is set empirically based on the system response speed to avoid excessive injection affecting voltage regulation.

[0030] Simultaneously, the voltage response amplitude and response delay time of adjacent power domains are measured. Voltage response amplitude refers to the peak change in voltage of adjacent power domains after the injection pulse, measured using a high-speed analog-to-digital converter with a sampling rate of at least 100 MHz. Response delay time refers to the time difference between the rising edge of the injection pulse and the first significant change in voltage of the adjacent power domain (e.g., exceeding three standard deviations of static noise). This time difference is recorded using a digital counter with a clock frequency of 500 MHz.

[0031] The disturbance propagation gain is determined based on the ratio of the voltage response amplitude to the preset injection amplitude. For example, if the preset injection amplitude is 200 mA, the measured voltage response amplitude of the adjacent domain is 40 mV, and the output impedance of the adjacent domain is known to be 0.2 ohms, then the equivalent current disturbance propagation gain is 40 mV divided by 0.2 ohms and then divided by 200 mA, resulting in a gain of 1.0. More directly, if the preset injection amplitude is 200 mA and the transimpedance characteristic of the voltage regulator in the adjacent domain is known, then the disturbance propagation gain is the voltage response amplitude divided by the product of the preset injection amplitude and the output impedance of the adjacent domain. For simplicity, this method directly uses the ratio of the voltage response amplitude to the preset injection amplitude as the gain; for example, 40 mV divided by 200 mA yields 0.2 V / A, which is used as the relative gain for subsequent coupling suppression. The disturbance propagation direction is determined based on the response delay time. If the response delay time is less than a preset propagation time threshold (e.g., 100 nanoseconds), then the disturbance is determined to have propagated from the injection source to the adjacent domain. The propagation time threshold is calculated based on the parasitic parameters of the on-chip traces (approximately 0.1 ohms per millimeter of resistance and approximately 1 nanohenry per millimeter of inductance) and the spacing between adjacent domains (typically 1 millimeter), with an empirical value of 50 to 150 nanoseconds.

[0032] The perturbation propagation direction is from the source power domain of the injected pulse to the adjacent power domain where the voltage response amplitude is greater than a preset response threshold. The preset response threshold is three times the standard deviation of the static voltage fluctuation. For example, when the static voltage fluctuation is 5 mV, the threshold is set to 15 mV. This threshold is determined based on experimental data (voltage values ​​were continuously collected for 100,000 cycles, and the standard deviation was calculated). For instance, if after injecting a pulse into source power domain A, the voltage response amplitude measured in adjacent power domain B is 20 mV (greater than 15 mV), and the response delay time is 80 nanoseconds (less than 100 nanoseconds), then the perturbation propagation direction is determined to be from A to B. If the response amplitude measured in adjacent power domain C is only 10 mV, then direct perturbation propagation is not considered to exist. For each source power domain, the above injection and measurement are performed sequentially on all its adjacent domains, ultimately establishing a directed graph of perturbation propagation for the entire chip. The perturbation propagation gain is recorded on each directed edge.

[0033] Coupling suppression is performed according to the following rules: When the instantaneous current change rate of any power domain exceeds a preset second change rate threshold, a suppression signal is sent to all adjacent power domains. The preset second change rate threshold is set according to the critical change rate that may cause disturbances in neighboring power domains, as specified in the chip datasheet. A typical value ranges from 20 mA / s to 40 mA / s, for example, 30 mA / s. This threshold is determined by statistically analyzing the disturbance initiation points in multiple load switching experiments. When the instantaneous current change rate exceeds 30 mA / s, the experimentally measured voltage fluctuation in adjacent domains exceeds 10 mV.

[0034] For example, if the instantaneous current change rate of a power domain (called the source domain) reaches 45 mA per nanosecond (more than 30 mA per nanosecond), then an suppression signal is immediately sent to all physically adjacent power domains (e.g., adjacent domain A, adjacent domain B) and the domain enters a suppression state. The suppression signal is a pulse flag with a width of 100 nanoseconds.

[0035] The maximum permissible voltage change slope of the adjacent power domain is temporarily reduced to the maximum permissible voltage change slope specified in the chip datasheet divided by the disturbance propagation gain obtained from the monitoring step. The maximum permissible voltage change slope specified in the chip datasheet is the upper limit of the voltage change rate that the power domain can tolerate when operating independently. For example, for a 1.2V power domain, this value is typically 100 millivolts per microsecond, derived from chip reliability test data (such as 1000-hour high-temperature operating life test). The disturbance propagation gain is the directed gain from the source domain to the adjacent domain. For example, if the gain from source domain A to adjacent domain B is 0.5, then the maximum permissible voltage change slope of adjacent domain B is temporarily reduced to 100 millivolts per microsecond divided by 0.5, resulting in 200 millivolts per microsecond.

[0036] It's important to note that reducing the value actually increases the overall value, meaning that adjacent domains are more sensitive to voltage changes. Therefore, their voltage regulators will respond at a slower rate to suppress coupled oscillations. If the disturbance propagation gain is greater than 1, the reduced value becomes smaller, indicating a more stringent limitation. For example, if the gain is 1.2, then 100 divided by 1.2 is approximately 83.3 millivolts per microsecond. The allowed slope of change in adjacent domains decreases, thereby reducing the feedback effect on the source domain.

[0037] If the suppression state continues until the instantaneous current change rate falls below a preset second change rate threshold and remains stable for more than ten preset control cycles, the system begins counting stable cycles after the instantaneous current change rate falls below the second change rate threshold. A typical control cycle is 10 microseconds, a value set based on the voltage regulator's response time (approximately 5 microseconds) and the system stability margin (twice). An empirical range is 5 to 20 microseconds, and ten control cycles equal 100 microseconds. For example, if the instantaneous current change rate in the source domain decreases from 45 mA / s to 25 mA / s (below 30 mA / s), and for the subsequent ten consecutive control cycles (e.g., 100 microseconds), the instantaneous current change rate remains below 30 mA / s, the suppression state is lifted, and the maximum allowable voltage change slope of the adjacent domain is restored to the original value specified in the chip datasheet. If the threshold is exceeded again during the stable counting period, the stable counter is reset, and the suppression state continues. This mechanism prevents frequent switching of the suppression state, ensuring the dynamic stability of the system.

[0038] Current system status parameters include the current chip junction temperature, total chip power consumption, cumulative operating time of each power domain since chip power-on, and cumulative voltage stress value of each power domain. The current chip junction temperature is read by an on-chip temperature sensor with an accuracy of ±1 degree Celsius and a sampling period of 100 microseconds. This period is set based on an empirical value of the thermal time constant (typically 1 millisecond) to ensure timely capture of temperature changes. Total chip power consumption is obtained by summing the product of the actual operating voltage and instantaneous current of each power domain. The instantaneous current is provided by the high-side current detection circuitry of each domain, with an accumulation period of 1 millisecond, determined based on the power meter data update rate. The typical range of total power consumption is 0.5 watts to 5 watts. The cumulative running time of each power domain since the chip was powered on is recorded by a low-frequency timer inside the chip. The timer clock is 1 Hz (i.e., counts once per second). This frequency is determined based on the time constant of threshold voltage drift in the aging test data (typically 1000 hours). 1 Hz sampling is sufficient to capture aging trends. The maximum timing interval covers 10 years, corresponding to a counter bit width of 28 bits. For example, if the chip runs for 2 years, the reading is 63,072,000 seconds. This design takes into account both aging compensation requirements and hardware resource consumption.

[0039] The accumulated voltage stress value is obtained by integrating the absolute value of the difference between the actual operating voltage and the rated voltage for each power domain over time, with the integration interval from the start of the current power-on to the current moment. The rated voltage is the maximum recommended operating voltage for that power domain as stated in the chip datasheet; for example, the rated voltage for the 1.2V domain is 1.32V. The absolute value of the difference between the actual operating voltage and the rated voltage is calculated; if the actual voltage is 1.4V, the difference is 0.08V. The integration step is 1 millisecond, and this difference is multiplied by the time step.

[0040] For example, if a power domain experiences an actual voltage of 1.3 volts for the first 500 seconds (difference of 0.02 volts) and 1.4 volts for the next 500 seconds (difference of 0.08 volts), then the cumulative voltage stress value is (0.02 × 500 + 0.08 × 500) = 50 volts per second. This stress value is used for aging compensation in the dual-loop collaborative module. When the stress value exceeds a preset stress threshold (e.g., 1000 volts per second, determined based on accelerated life test data), the inner loop pulse voltage regulation signal will add an additional bias voltage (typically 5 millivolts) to compensate for the threshold voltage drift.

[0041] The triggering conditions for restarting the step of real-time capture of instantaneous current change rate and voltage undershoot also include the following: If, within three consecutive preset control cycles, the absolute value of the difference between the actual voltage value fed back from each power domain and the target voltage setting value is greater than zero and less than or equal to the preset deviation threshold, and the absolute value of this difference is greater than the value at the end of each cycle than at the end of the previous cycle, the step of real-time capture of instantaneous current change rate and voltage undershoot amplitude is forcibly restarted. The preset control cycle is 10 microseconds, which is determined based on the voltage regulator closed-loop response time (approximately 5 microseconds) and the system stability margin (twice), with a typical range of 5 to 20 microseconds. The preset deviation threshold is 5% of the nominal voltage; for example, when the target voltage setting value is 1.0 volt, the deviation threshold is 50 millivolts. This threshold is set according to the transient response accuracy (±5%) specified in the power management chip datasheet.

[0042] Three consecutive cycles are used to filter out single random noise interference. This number is determined to be 3 based on experimental statistics (the probability of a single-cycle false trigger is less than 1% in 1000 disturbance tests). The condition that the absolute value of the difference is greater than zero excludes a completely stable state (i.e., the difference is zero), while being less than or equal to the deviation threshold indicates that the master control condition has not yet been triggered (i.e., the absolute value is greater than the deviation threshold). The absolute value of the difference at the end of each cycle is greater than the value at the end of the previous cycle. For example, the absolute value at the end of the first cycle is 10 mV, the end of the second cycle is 20 mV, and the end of the third cycle is 30 mV, which shows an increasing trend. This indicates that the system is diverging towards the over-limit direction but has not yet exceeded the threshold, which is a precursor to chain oscillation.

[0043] After forcibly restarting this step, based on the ratio of the absolute value of the difference in the last cycle to the preset deviation threshold, the preset first current change rate threshold and the preset first voltage undershoot threshold are increased proportionally, with the ratio equal to the value of the preset deviation threshold. At the end of the last cycle (the third cycle), the absolute value of the difference is 30 millivolts, the preset deviation threshold is 50 millivolts, and the ratio is 0.6. The original value of the preset first current change rate threshold is 50 milliamps per nanosecond, adjusted to the original value divided by this ratio, i.e., 50 ÷ 0.6 ≈ 83.3 milliamps per nanosecond; the original value of the preset first voltage undershoot threshold is 120 millivolts, adjusted to the original value divided by this ratio, i.e., 120 ÷ 0.6 = 200 millivolts. The upper limit of the ratio is limited to 1 because the absolute value of the difference will not exceed the deviation threshold (otherwise the master control condition will be triggered), so the ratio range is between (0,1]. This increase mechanism is set based on empirical values, and its purpose is to increase the threshold sensitivity reduction when oscillations diverge but have not yet exceeded the limit, allowing the system to adjust itself without frequent intervention, and avoiding repeated triggering due to an overly tight threshold.

[0044] It should be noted that if the system stabilizes afterward, the threshold will return to its original value in the next power-on cycle or through software reset. Alternatively, the threshold may remain at its increased value until the chip is powered on again or receives an external reset command. For example, if the absolute value of the difference between three consecutive cycles is 8 mV, 15 mV, and 22 mV (all less than 50 mV and increasing), a forced restart will be triggered. The two thresholds will be multiplied by the ratio 22 / 50 = 0.44, meaning the first current change rate threshold will be reduced to 22 mA per nanosecond and the first voltage undershoot threshold will be reduced to 52.8 mV. This adjusts the sensitivity to subsequent sudden changes. This triggering condition complements the previous condition of "absolute difference greater than deviation threshold," together covering all fault modes from incremental divergence to exceeding limits.

[0045] The nonlinear correction calculation specifically adopts the following steps: First, extract the maximum peak value of the instantaneous current change rate and the maximum depth of the voltage downslope from the load change characteristic parameters. Divide the maximum peak value of the instantaneous current change rate by a preset reference change rate to obtain the first dimensionless coefficient. The preset reference change rate is set according to the upper limit of the typical transient current change rate specified in the chip design manual, and is set to 40 mA per nanosecond. This value is derived from the statistical average of 100 chips under maximum load jump conditions, with an empirical range of 30 to 50 mA per nanosecond. If the maximum peak value is 50 mA per nanosecond, then the first dimensionless coefficient is 50 divided by 40, which equals 1.25. Divide the maximum depth of voltage undershoot by the preset reference undershoot depth to obtain the second dimensionless coefficient. The preset reference undershoot depth is 8% of the nominal voltage. For example, when the nominal voltage is 1.0 volt, it is 80 millivolts. This ratio is determined by taking the median of 8% of the typical transient response values ​​(5% to 10%) in the power module datasheet. If the maximum depth is 70 millivolts, then the second dimensionless coefficient is 70 divided by 80, which is 0.875.

[0046] Next, the preset temperature compensation curve is retrieved based on the current operating temperature. This curve consists of compensation factors corresponding to multiple temperature nodes. Five temperature nodes are selected: -40°C, 0°C, 25°C, 85°C, and 125°C. The compensation factor for each node is determined experimentally: a standard load mutation (instantaneous current change rate of 40 mA per nanosecond and voltage downscaling depth of 80 mV) is applied at the corresponding temperature, the voltage is adjusted to allow the chip to operate normally, and the percentage of additional voltage required is recorded as the compensation factor. For example, the compensation factor is 1.2 at -40°C, 1.05 at 0°C, 1.0 at 25°C, 0.95 at 85°C, and 0.9 at 125°C. These compensation factors are statistically derived from aging test data, with an empirical range of 0.8 to 1.3. Aging tests are a well-known and mature technique in this field, and will not be elaborated upon here. The compensation factor at the current temperature is obtained through linear interpolation. For example, if the current temperature is 60 degrees Celsius, the factor is between 25 and 85. The interpolated compensation factor is 1.0 - (60 - 25) / (85 - 25) × (1.0 - 0.95) = 0.97.

[0047] The harmonic mean is calculated by multiplying the first dimensionless coefficient, the second dimensionless coefficient, and the compensation factor. The formula for the harmonic mean is: product of the three coefficients divided by the sum of their pairwise products, then multiplied by three. For example, if the first dimensionless coefficient is 1.25, the second dimensionless coefficient is 0.875, and the compensation factor is 0.97, then the product of the three coefficients is 1.25 × 0.875 × 0.97 ≈ 1.061; the sum of their pairwise products is 1.25 × 0.875 + 1.25 × 0.97 + 0.875 × 0.97 = 1.09375 + 1.2125 + 0.84875 = 3.155; and the harmonic mean is 3 × 1.061 / 3.155 ≈ 1.009. This harmonic mean is used as the comprehensive disturbance index.

[0048] Substituting the comprehensive disturbance index into a preset error function, which adopts a Lorentz distribution, the function value is one times the square of the comprehensive disturbance index. The Lorentz distribution formula is 1 / (1+x^2), where x is the comprehensive disturbance index. For example, if the comprehensive disturbance index is 1.009, its square is 1.018, then the function value is 1 / (1+1.018)=0.495, which is the nonlinear compensation factor. The Lorentz distribution function is chosen because it is sensitive to medium-amplitude disturbances but tends to saturate for large disturbances, which meets the nonlinear suppression requirements for overshoot and undershoot in voltage regulation.

[0049] Finally, the initial voltage value is multiplied by the sum of the square root of the nonlinear compensation factor (within parentheses) and the nonlinear compensation factor, and then divided by two to obtain the target voltage setpoint. This calculation method is expressed by the formula: Vtarget = V0 × (sqrt(k) + k) / 2, where V0 is the initial voltage value, k is the nonlinear compensation factor, sqrt(k) represents the square root of k, and Vtarget is the target voltage setpoint. The initial voltage value is calculated through bilinear interpolation. It should be noted that in practice, if the comprehensive disturbance index is greater than 1, the voltage after compensation is significantly reduced; if the comprehensive disturbance index is less than 1, the compensation factor is close to 1, and the target voltage is close to the initial voltage value. This calculation method, combining square root and mean operations, can balance transient response and steady-state accuracy. Experimental data shows that this method can reduce voltage overshoot by approximately 30% in 100 tests.

[0050] The single-domain adjustment command in coupling suppression processing is calculated through the following steps: First, obtain the real-time values ​​of the comprehensive disturbance index and the instantaneous current change rate of adjacent power domains. Construct a piecewise function for the comprehensive disturbance index. In the first interval, this piecewise function is the sine of the comprehensive disturbance index multiplied by a first coefficient. In the second interval, it is an exponential function with the natural constant as its base, where the exponent is the square of the negative comprehensive disturbance index multiplied by a second coefficient. The boundary between the first and second intervals is determined by a preset piecewise threshold. The preset piecewise threshold is set to 1.0, a value determined based on the physical meaning of the comprehensive disturbance index (greater than 1 indicates the disturbance exceeds the reference level), with an empirical range of 0.8 to 1.2. In the first interval, the comprehensive disturbance index is less than or equal to the piecewise threshold, and the function is a sine multiplied by the first coefficient. The sine function monotonically increases within the interval; for example, when the comprehensive disturbance index is 0.8, the sine value is approximately 0.717. The first and second coefficients are obtained by offline fitting of the optimal suppression effect under typical disturbance scenarios.

[0051] During offline fitting, data from 100 different load-change experiments were collected. With the goal of minimizing output oscillation amplitude, the least squares method was used for fitting, resulting in a first coefficient of 0.8 and a second coefficient of 0.5. The typical ranges for these two coefficients are 0.5 to 1.2 and 0.3 to 0.8, respectively. For example, if the overall disturbance index is 0.9 (less than 1), the piecewise function output is sin(0.9) × 0.8 ≈ 0.783 × 0.8 = 0.626. If the overall disturbance index is 1.2 (greater than 1), it enters the second interval, and the exponential function is calculated: negative 1.2 squared is -1.44, the exponential value ≈ 0.237, multiplied by the second coefficient 0.5, yielding 0.1185. This piecewise function design is based on the gain scheduling principle in control theory, employing sinusoidal soft suppression for small disturbances (exponent < 1) and exponential fast decay for large disturbances.

[0052] The coupling correlation strength is obtained by multiplying the output of the piecewise function by the disturbance propagation gain measured from the adjacent power domain. The disturbance propagation gain is obtained from the monitoring steps described above; for example, the gain from source domain A to adjacent domain B is 0.5. If the piecewise function output is 0.626, the coupling correlation strength is 0.626 × 0.5 = 0.313; if the piecewise function output is 0.1185, the coupling correlation strength is 0.05925. This coupling correlation strength represents the degree of influence of the adjacent domain disturbance on the current domain regulation command.

[0053] The difference between the target voltage setpoint and the actual voltage value fed back from the current power domain is used as the initial adjustment range. The target voltage setpoint is obtained from the aforementioned nonlinear correction calculation, for example, 0.551 volts. The actual voltage value fed back from the current power domain is obtained by sampling the output of the voltage regulator in that domain, for example, 0.550 volts, so the initial adjustment range is 0.001 volts. The difference between the initial adjustment range and the coupling correlation strength is calculated, and then this difference is substituted into a saturation function. This saturation function outputs the value of the independent variable when the absolute value of the independent variable is less than a preset saturation threshold, and outputs the sign of the independent variable multiplied by the preset saturation threshold when the absolute value of the independent variable is greater than or equal to the preset saturation threshold. The preset saturation threshold is less than one and is set to 0.9. This value is determined according to the domain requirement of the inverse hyperbolic tangent function (absolute value less than 1), with a 10% safety margin, and an empirical range of 0.8 to 0.99.

[0054] For example: if the absolute value of the independent variable is 0.5 and less than 0.9, then the output is 0.5; if the independent variable is -1.2, and its absolute value 1.2 is greater than 0.9, then the output is the sign (negative sign) of the independent variable multiplied by 0.9, i.e., -0.9. Here, the difference before constraint is -0.292, and its absolute value 0.292 is less than 0.9, so the saturation function output is still -0.292, obtaining the difference after constraint. Taking the inverse hyperbolic tangent function value of the difference after constraint, we obtain the decoupling attenuation factor. The formula for the inverse hyperbolic tangent function is arctanh(y), and its domain requires |y|<1. After the saturation function, the input is constrained within (-0.9, 0.9), satisfying the domain. Calculating arctanh(-0.292)≈-0.301, this negative value indicates that reverse attenuation is needed to decouple the coupled oscillations between adjacent domains.

[0055] Finally, the original adjustment amplitude is multiplied by the decoupling attenuation factor to obtain the final single-domain adjustment command. A negative value indicates that the target voltage needs to be reduced or the adjustment amplitude needs to be decreased. The single-domain adjustment command is -0.0003 volts. This command is sent to the digital control interface of the voltage regulator and converted into a duty cycle adjustment amount of a pulse width modulation signal. For example, each millivolt corresponds to a 0.1% duty cycle change, so -0.0003 volts corresponds to a -0.03% duty cycle. This command works in conjunction with the dual-loop coordinating module to achieve stable control of multiple power domains.

[0056] Example 2: A multi-power-domain voltage regulation and timing control system in an integrated circuit, comprising: The mutation identification module is used to capture the instantaneous current change rate and voltage undershoot amplitude of each power domain in real time, compare the instantaneous current change rate with a preset first current change rate threshold, and compare the voltage undershoot amplitude with a preset first voltage undershoot threshold. When either parameter exceeds the corresponding threshold, the load mutation characteristic parameter is identified. The nonlinear correction module is used to perform nonlinear correction calculations based on a preset voltage-frequency mapping model according to the load change characteristic parameters and the current operating temperature, so as to obtain the target voltage setpoint. The coupling suppression module is used to monitor the propagation direction and gain of disturbances between power domains. Based on the target voltage setpoint and the disturbance status of adjacent power domains monitored in real time, it performs coupling suppression processing to obtain single-domain adjustment commands. The dual-loop coordination module is used to perform coordinated calculations of the inner loop pulse voltage regulation signal and the outer loop timing alignment signal according to a preset strategy based on the single-domain adjustment command and the current system status parameters, thereby generating drive signals for controlling the voltage regulation and timing of each power domain. The closed-loop feedback module is used to apply the drive signal to the voltage regulator corresponding to each power domain, and compare the actual voltage value fed back by each power domain with the target voltage setting value. When the absolute value of the difference is greater than the preset deviation threshold, the sudden change recognition module is triggered to start execution again.

[0057] In a specific implementation, performing the collaborative calculation of the inner loop pulse voltage regulation signal and the outer loop timing alignment signal according to a preset strategy refers to: First, the single-domain adjustment command is converted into an inner-loop pulse voltage regulation signal. The inner-loop pulse voltage regulation signal is a pulse sequence with a variable width, the pulse width of which is proportional to the absolute value of the single-domain adjustment command. For example, when the single-domain adjustment command is -0.0063 volts, the pulse width is set to 63 nanoseconds, with a proportionality coefficient of 1 nanosecond for every 0.0001 volts. The inner-loop pulse voltage regulation signal is directly applied to the power switch driver terminal of the voltage regulator in this power domain to quickly pull down or raise the output voltage.

[0058] Simultaneously, an outer-loop timing alignment signal is generated based on the current system state parameters. The outer-loop timing alignment signal is a multi-channel synchronous control pulse, with each channel corresponding to a power domain. The outer loop reads the current chip junction temperature. If the junction temperature is between 85°C and 105°C, the rising edge of the outer-loop timing alignment signal is delayed relative to the system master clock by an adjustment step. The delay time is calculated using the formula: Delay step (nanoseconds) = (cumulative voltage stress value / 1000) rounded down and multiplied by 2. For example, if the cumulative voltage stress value is 50 volts per second, the delay step is 0 nanoseconds; if the cumulative voltage stress value is 1200 volts per second, the delay step is 2 nanoseconds. This delay is used to compensate for aging differences caused by stress.

[0059] Co-operation refers to performing a logical AND operation between the inner-loop pulse voltage regulation signal and the outer-loop timing alignment signal: the inner-loop pulse voltage regulation signal is allowed to pass during the high-level period of the outer-loop timing alignment signal, and is prohibited during the low-level period, thus ensuring that voltage regulation only occurs within the time window of timing alignment. When generating drive signals for controlling voltage regulation and timing in each power domain, the result of the logical AND operation between the inner-loop pulse voltage regulation signal and the outer-loop timing alignment signal is amplified and output. For example, if a power domain needs to perform a -0.0063V regulation, the inner-loop pulse voltage regulation signal generates a 63-nanosecond pulse. The outer-loop timing alignment signal provides a 100-nanosecond high-level window within the current cycle, starting 5 nanoseconds after the rising edge of the system master clock. The 63-nanosecond pulse falls entirely within the 100-nanosecond window, so the drive signal outputs this pulse. If the outer-loop window is not aligned with the inner-loop pulse, the drive signal does not output and waits for the next outer-loop window, thus achieving coordination between timing and voltage regulation.

[0060] The above formulas are all dimensionless calculations. The formulas are derived from software simulations based on a large amount of collected data to obtain the most recent real-world results. The preset parameters in the formulas are set by those skilled in the art according to the actual situation.

[0061] It should be understood that in the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0062] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0063] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0064] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for multi-power-domain voltage regulation and timing control in integrated circuits, characterized in that, Includes the following steps: Real-time capture of instantaneous current change rate and voltage undershoot amplitude of each power domain; comparison of instantaneous current change rate with a preset first current change rate threshold; comparison of voltage undershoot amplitude with a preset first voltage undershoot threshold; identification of load change characteristic parameters when either parameter exceeds the corresponding threshold. Based on the load change characteristic parameters and the current operating temperature, nonlinear correction calculations are performed based on a preset voltage-frequency mapping relationship model to obtain the target voltage setpoint. Monitor the propagation direction and gain of disturbances between power domains, and perform coupling suppression processing based on the target voltage setpoint and the disturbance status of adjacent power domains monitored in real time to obtain single-domain adjustment commands; Based on the single-domain adjustment command and the current system state parameters, the inner loop pulse voltage regulation signal and the outer loop timing alignment signal are calculated in accordance with the preset strategy to generate drive signals for controlling the voltage regulation and timing of each power domain. The drive signal is applied to the voltage regulator corresponding to each power domain, and the actual voltage value fed back by each power domain is compared with the target voltage setting value. When the absolute value of the difference is greater than the preset deviation threshold, the step of real-time capture of instantaneous current change rate and voltage undershoot amplitude is restarted. When capturing the instantaneous current change rate and voltage undershoot amplitude of each power domain in real time, each power domain is equipped with an independent instantaneous current change rate detection path. This path converts the instantaneous current change rate into pulse width through a differentiating network composed of resistors and capacitors. The pulse width is inversely proportional to the instantaneous current change rate. The voltage undershoot amplitude is captured by a combination of a hysteresis comparator and a digital peak hold circuit. When the hysteresis comparator is triggered, the digital peak hold circuit is activated to record the lowest voltage point. The disturbance propagation direction and gain between each power domain are monitored by periodically injecting a small current pulse with a preset injection amplitude and a preset injection width at the output of the voltage regulator in each power domain, while simultaneously measuring the voltage response amplitude and response delay time of adjacent power domains. The disturbance propagation gain is determined based on the ratio of the voltage response amplitude to the preset injection amplitude, and the disturbance propagation direction is determined based on the response delay time. The disturbance propagation direction is from the source power domain of the injected pulse to the adjacent power domain where the voltage response amplitude is greater than the preset response threshold.

2. The multi-power-domain voltage regulation and timing control method in an integrated circuit according to claim 1, characterized in that, The preset voltage-frequency mapping model is constructed using a piecewise linear interpolation table. This interpolation table is indexed by voltage and temperature values ​​and stores the corresponding reference voltage settings. The current operating voltage and the preliminary voltage values ​​at the current operating temperature are calculated through bilinear interpolation.

3. The multi-power-domain voltage regulation and timing control method in an integrated circuit according to claim 1, characterized in that, Coupling suppression is performed according to the following rules: When the instantaneous current change rate of any power domain exceeds the preset second change rate threshold, a suppression signal is sent to all adjacent power domains of that power domain, temporarily reducing the maximum allowable voltage change slope of the adjacent power domains to the maximum allowable voltage change slope specified in the chip datasheet divided by the disturbance propagation gain obtained from the monitoring step. This suppression state continues until the instantaneous current change rate falls back to below the preset second change rate threshold and stabilizes for more than ten preset control cycles.

4. The multi-power-domain voltage regulation and timing control method in an integrated circuit according to claim 1, characterized in that, The current system status parameters include the current chip junction temperature, total chip power consumption, cumulative operating time of each power domain since chip power-on, and cumulative voltage stress value of each power domain. The cumulative voltage stress value is obtained by integrating the absolute value of the difference between the actual operating voltage and the rated voltage of each power domain over time, with the integration interval from the start of this power-on to the current moment.

5. The multi-power-domain voltage regulation and timing control method in an integrated circuit according to claim 1, characterized in that, The triggering conditions for restarting the step of real-time capture of instantaneous current change rate and voltage undershoot amplitude also include: If, within three consecutive preset control cycles, the absolute value of the difference between the actual voltage value fed back from each power domain and the target voltage setting value is greater than zero and less than or equal to the preset deviation threshold, and the absolute value of the difference is greater than the value at the end of each cycle than at the end of the previous cycle, the steps are forcibly restarted. Furthermore, based on the ratio of the absolute value of the difference in the last cycle to the preset deviation threshold, the preset first current change rate threshold and the preset first voltage undershoot threshold are adjusted to their original values ​​divided by the ratio, i.e., multiplied by the reciprocal of the ratio.

6. The multi-power-domain voltage regulation and timing control method in an integrated circuit according to claim 2, characterized in that, The nonlinear correction calculation specifically adopts the following steps: Extract the maximum peak value of the instantaneous current change rate and the maximum depth of the voltage downslope from the load change characteristic parameters; The first dimensionless coefficient is obtained by dividing the maximum peak value of the instantaneous current change rate by the preset reference change rate, and the second dimensionless coefficient is obtained by dividing the maximum depth of the voltage undershoot by the preset reference undershoot depth. The preset temperature compensation curve is queried based on the current operating temperature. This curve is composed of compensation factors corresponding to multiple temperature nodes. The compensation factor at the current temperature is obtained by linear interpolation. The first dimensionless coefficient, the second dimensionless coefficient, and the compensation factor are harmonic averaged. The formula for calculating the harmonic average is the product of the three factors divided by the sum of the pairwise products and then multiplied by three. The first dimensionless coefficient, the second dimensionless coefficient, and the compensation factor are all positive numbers. The harmonic mean is used as the comprehensive disturbance index. Substitute it into the preset error function, which adopts the Lorentz distribution form, to calculate the nonlinear compensation factor. The preset error function is calculated as follows: the nonlinear compensation factor is equal to the sum of the squares of the comprehensive disturbance index and the sum of the squares of the two values ​​in parentheses. Finally, the initial voltage value is multiplied by the square root of the nonlinear compensation factor to obtain the first intermediate value; The initial voltage value is then multiplied by the nonlinear compensation factor to obtain the second intermediate value; the average value of the first intermediate value and the second intermediate value is then calculated to obtain the target voltage setpoint.

7. The multi-power-domain voltage regulation and timing control method in an integrated circuit according to claim 6, characterized in that, The single-domain adjustment command in coupling suppression processing is calculated through the following steps: Obtain the comprehensive disturbance index and the real-time values ​​of the instantaneous current change rate in adjacent power domains; A piecewise function for the comprehensive disturbance index is constructed. In the first interval, the piecewise function is the sine of the comprehensive disturbance index multiplied by a first coefficient. In the second interval, it is an exponential function with the natural constant as the base, and its exponent is the square of the negative comprehensive disturbance index multiplied by a second coefficient. The boundary between the first and second intervals is determined by a preset piecewise threshold. The first and second coefficients are obtained by offline fitting of the optimal suppression effect under typical disturbance scenarios. The coupling correlation strength is obtained by multiplying the output of the piecewise function with the disturbance propagation gain measured from the adjacent power domain. The difference between the target voltage setpoint and the actual voltage value fed back from the current power domain is used as the original adjustment amplitude. The difference between the original adjustment amplitude and the coupling correlation strength is calculated. Then, this difference is substituted into a saturation function. The saturation function outputs the value of the independent variable when the absolute value of the independent variable is less than the preset saturation threshold, and outputs the sign of the independent variable multiplied by the saturation threshold when the absolute value of the independent variable is greater than or equal to the saturation threshold, to obtain the limited difference. The preset saturation threshold is less than one. Then, the inverse hyperbolic tangent function value of the limited difference is taken to obtain the decoupling attenuation factor. Multiplying the original adjustment amplitude by the decoupling attenuation factor yields the final single-domain adjustment command.

8. A multi-power-domain voltage regulation and timing control system in an integrated circuit, used to implement the multi-power-domain voltage regulation and timing control method in an integrated circuit as described in any one of claims 1-7, characterized in that, include: The mutation identification module is used to capture the instantaneous current change rate and voltage undershoot amplitude of each power domain in real time, compare the instantaneous current change rate with a preset first current change rate threshold, and compare the voltage undershoot amplitude with a preset first voltage undershoot threshold. When either parameter exceeds the corresponding threshold, the load mutation characteristic parameter is identified. The nonlinear correction module is used to perform nonlinear correction calculations based on a preset voltage-frequency mapping model according to the load change characteristic parameters and the current operating temperature, so as to obtain the target voltage setpoint. The coupling suppression module is used to monitor the propagation direction and gain of disturbances between power domains. Based on the target voltage setpoint and the disturbance status of adjacent power domains monitored in real time, it performs coupling suppression processing to obtain single-domain adjustment commands. The dual-loop coordination module is used to perform coordinated calculations of the inner loop pulse voltage regulation signal and the outer loop timing alignment signal according to a preset strategy based on the single-domain adjustment command and the current system status parameters, thereby generating drive signals for controlling the voltage regulation and timing of each power domain. The closed-loop feedback module is used to apply the drive signal to the voltage regulator corresponding to each power domain, and compare the actual voltage value fed back by each power domain with the target voltage setting value. When the absolute value of the difference is greater than the preset deviation threshold, the sudden change recognition module is triggered to start execution again.

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