An output voltage stabilizing circuit and method based on closed-loop dynamic clamping during startup of a switching power supply chip

Abstract

The application provides an output voltage stabilizing circuit and method based on closed-loop dynamic clamping during starting of a switching power supply chip, a closed-loop dynamic clamping loop is added in a traditional current mode control architecture, including voltage dividing and sampling resistors R3 and R4, a soft start level amplifier and a voltage clamping module, a sampling voltage Vc_sns is compared with a soft start level Vsoft by voltage dividing and sampling of an error level Vc; when Vc_sns is greater than Vsoft, the voltage clamping module is triggered to act, and Vc is clamped in a dynamic threshold value Vc_c range. In the initial stage of soft start, Vc is clamped in a dynamic low level range, inductive current IL and output voltage Vo are prevented from being sharply fluctuated due to instant high Vc, output voltage is safely started, key elements such as a power switch tube and an output capacitor are effectively protected, and the service life of the chip is prolonged.

Description

Technical Field

[0001] This invention relates to the field of switching power supply control technology, specifically to a circuit structure for stabilizing the output voltage of a switching power supply chip during the soft-start phase, and particularly to a switching power supply chip output voltage stabilization circuit based on closed-loop dynamic clamping of the error amplifier output voltage Vc. Background Technology

[0002] In today's electronics and automation equipment fields, such as computers, communication equipment, medical equipment, and automotive electronic systems, switching power supply chips serve as core power supply components, and their reliability directly impacts the operational stability of the entire system. In these applications, the requirements for switching power supply chips are increasingly stringent: they need to prevent damage to components such as capacitors and inductors during startup to extend equipment lifespan; they need to reduce the impact of sudden current surges on circuits to improve system stability; and they need to suppress high-frequency noise during startup to reduce electromagnetic interference. Therefore, the output voltage stability of switching power supply chips has become a key indicator for evaluating their performance.

[0003] However, existing switching power supply chips have a significant technical problem during startup. For example... Figure 1 As shown, existing switching power supply chips typically consist of an error amplifier, a current comparator, a current detection module, a clock module, a PWM controller, feedback resistors R1 and R2, a soft-start current source I1, a soft-start capacitor C1, a power transistor Q1, a power transistor Q2, and external inductors L and output capacitor Co. Its working principle is as follows: the output voltage Vo generates a feedback voltage Vfb via feedback resistors R1 and R2, which is compared and amplified with the soft-start level Vsoft to generate an error level Vc; the inductor current IL is sampled to generate a sampling voltage Vsns, which is compared with Vc to generate a signal Vcmp. When Vcmp goes high, the duty cycle signal Duty goes low, controlling Q1 to turn off and Q2 to turn on. During the soft-start phase after the chip is powered on, the current source I1 charges the capacitor C1, and the soft-start level Vsoft gradually increases. At this time, the rising edge of the clock signal CLK determines that the duty cycle signal Duty changes from low to high, thereby controlling Q1 to turn on and Q2 to turn off. When the inductor current crosses zero in each cycle, the current zero-crossing detection module outputs a high level Vzc to turn off Q1 and Q2 simultaneously, and the switching frequency remains fixed with the clock frequency CLK.

[0004] like Figure 2As shown in the waveform timing diagram, at the very beginning of soft-start, due to the initial voltage difference between the soft-start level Vsoft and the feedback voltage Vfb, the error level Vc output by the error amplifier surges instantaneously to an excessively high voltage value. This excessively high Vc value directly causes a huge peak fluctuation in the inductor current IL, which in turn leads to a drastic fluctuation in the output voltage Vo. This abnormal fluctuation brings a series of serious technical problems: it affects the normal soft-start process of the chip's output voltage, resulting in inaccurate soft-start time; it causes system instability, affecting the overall power supply reliability; the excessively large inductor current peak may damage electronic components such as power switches and output capacitors, seriously affecting the chip's lifespan and reliability; more seriously, this drastic fluctuation in output voltage may also pose a significant risk of downtime and damage to downstream load circuits.

[0005] To address the aforementioned technical issues, the industry urgently needs a low-cost, high-reliability technical solution that can eliminate abnormal output voltage fluctuations in switching power supply chips during the soft-start phase through a dynamic clamping mechanism, thereby improving the overall performance and reliability of switching power supply chips. Summary of the Invention

[0006] The purpose of this invention is to solve the technical problem of abnormal output voltage fluctuation caused by error level Vc overshoot during the soft start-up phase of existing switching power supply chips, and to propose an output voltage stabilization circuit based on closed-loop dynamic clamping during the startup of switching power supply chips.

[0007] The technical solution of this invention is: In a first aspect, the present invention provides an output voltage stabilization circuit based on closed-loop dynamic clamping during the startup of a switching power supply chip, comprising an error amplifier, a current comparator, a current detection module, a clock module, an SR flip-flop, a PWM controller, feedback resistors R1 and R2, a soft-start current source I1, a soft-start capacitor C1, a power transistor Q1, a power transistor Q2, an inductor L, and an output capacitor Co; the output voltage Vo is amplified by comparing the feedback voltage Vfb generated by the feedback resistors R1 and R2 with the soft-start level Vsoft to generate an error level Vc; the inductor current IL of the inductor L is sampled by the current detection module to generate a sampling voltage Vsns, which is compared with the error level Vc by the current comparator to generate a comparison signal Vcmp. When the comparison signal Vcmp goes high, the duty cycle signal Duty of the SR flip-flop goes low to control the power transistor Q1 to turn off and the power transistor Q2 to turn on; It also includes a closed-loop dynamic clamping circuit; the closed-loop dynamic clamping circuit includes voltage divider sampling resistors R3 and R4, a soft-start level amplifier, and a voltage clamping module; one end of the voltage divider sampling resistor R3 is connected to the output terminal of the error amplifier to receive the error level Vc, and the other end is connected in series with the voltage divider sampling resistor R4 and then grounded; the connection point of the voltage divider sampling resistors R3 and R4 outputs the clamping sampling voltage Vc_sns to the non-inverting input terminal of the soft-start level amplifier; the inverting input terminal of the soft-start level amplifier is connected to the soft-start level Vsoft; the output terminal of the soft-start level amplifier is connected to the input terminal of the voltage clamping module; and the output terminal of the voltage clamping module is connected to the output terminal of the error amplifier to limit the maximum voltage value of the error level Vc output by the error amplifier.

[0008] Furthermore, the upper power transistor Q1, the lower power transistor Q2, the inductor L, and the output capacitor Co constitute the main power circuit; the input terminal of the upper power transistor Q1 is connected to the input voltage terminal Vin, the output terminal of the upper power transistor Q1 is connected to one end of the inductor L and the input terminal of the lower power transistor Q2, the output terminal of the lower power transistor Q2 is grounded, the other end of the inductor L is connected to the output voltage terminal Vo and the positive terminal of the output capacitor Co, and the negative terminal of the output capacitor Co is grounded; The clock module, SR flip-flop, PWM controller, current detection module, and current comparator constitute a PWM control and current-mode control loop. The clock module generates a clock signal CLK, which is output to the set terminal S of the SR flip-flop. The output terminal Q of the SR flip-flop outputs a duty cycle signal Duty to the PWM controller. The PWM controller outputs drive signals to control the on and off states of the upper power transistor Q1 and the lower power transistor Q2, respectively. The current detection module is connected to an inductor L and generates a sampling voltage Vsns, which is output to the inverting input terminal of the current comparator. The non-inverting input terminal of the current comparator receives the error level Vc, and its output terminal generates a comparison signal Vcmp. The comparison signal Vcmp is connected to the reset terminal R of the SR flip-flop. The feedback resistors R1 and R2, the soft-start current source I1, the soft-start capacitor C1, and the error amplifier constitute an error amplification and soft-start circuit. The feedback resistors R1 and R2 are connected in series between the output voltage terminal Vo and ground. The connection point of the feedback resistors R1 and R2 generates a feedback voltage Vfb, which is connected to the inverting input terminal of the error amplifier. The soft-start current source I1 is connected in series with the soft-start capacitor C1 and then grounded. It is used to charge the soft-start capacitor C1, generating a gradually increasing soft-start level Vsoft, which is output to the non-inverting input terminal of the error amplifier. The output terminal of the error amplifier generates an error level Vc, which is output to the non-inverting input terminal of the current comparator.

[0009] Further, the soft-start level amplifier compares the clamping sampling voltage Vc_sns with the soft-start level Vsoft; When the clamping sampling voltage Vc_sns is greater than the soft-start level Vsoft, the soft-start level amplifier outputs a control signal to trigger the voltage clamping module to clamp the maximum value of the error level Vc within the range of the dynamic threshold Vc_c determined by the soft-start level Vsoft.

[0010] Furthermore, the dynamic threshold Vc_c gradually increases following the soft-start level Vsoft. When the dynamic threshold Vc_c rises to exceed the normal operating range of the error level Vc, the voltage clamping module releases the clamp on the error level Vc.

[0011] Furthermore, the voltage clamping module is implemented using an emitter follower, source follower, or dedicated clamping circuit composed of transistors.

[0012] This invention provides a method for stabilizing the output voltage of a switching power supply chip during startup based on closed-loop dynamic clamping, the circuit comprising: S1. Obtain the output voltage Vo and generate the feedback voltage Vfb through the feedback resistors R1 and R2. Compare and amplify the feedback voltage with the soft start level Vsoft to generate the error level Vc. S2. A sampling voltage Vsns is generated by sampling the current IL of the inductor L, and compared with the error level Vc to generate a comparison signal Vcmp to control the switching state of the power transistor Q1 and the power transistor Q2. S3. The maximum value of the error level Vc is dynamically limited by a closed-loop dynamic clamping circuit, and the error level Vc is clamped within the dynamic threshold Vc_c range determined by the soft start level Vsoft, so as to eliminate output voltage fluctuations.

[0013] Furthermore, S3 includes: S31. The closed-loop dynamic clamping circuit performs voltage division sampling on the error level Vc through voltage divider sampling resistors R3 and R4 to generate clamping sampling voltage Vc_sns. S32. Compare the clamping sampling voltage Vc_sns with the soft-start level Vsoft input soft-start level amplifier; If the clamping sampling voltage Vc_sns is greater than the soft-start level Vsoft, the voltage clamping module is triggered to clamp the maximum value of the error level Vc within the range of the dynamic threshold Vc_c.

[0014] Furthermore, S32 specifically refers to: The clamping sampling voltage Vc_sns is input to the non-inverting input of the soft-start level amplifier, and the soft-start level Vsoft is input to the inverting input of the soft-start level amplifier. The soft-start level amplifier compares the clamping sampling voltage Vc_sns with the soft-start level Vsoft and outputs a control signal to the voltage clamping module. When Vc_sns > Vsoft, the soft-start level amplifier outputs a high-level control signal to the voltage clamping module, and the voltage clamping module is turned on, clamping the error level Vc output by the error amplifier within the range of the dynamic threshold Vc_c. The dynamic threshold Vc_c and the soft start level Vsoft satisfy the following relationship: Vc_c = Vsoft × (1 +R3 / R4).

[0015] Furthermore, S3 also includes: S33. As the soft-start phase progresses, the soft-start level Vsoft gradually increases, and the dynamic threshold Vc_c increases accordingly. If the dynamic threshold Vc_c rises to a level exceeding the normal operating range of the error level Vc, the clamping sampling voltage Vc_sns is less than the soft-start level Vsoft. The soft-start level amplifier outputs a low-level control signal, the voltage clamping module is turned off, the clamping of the error level Vc is released, and the circuit enters normal operating state.

[0016] Compared with the prior art, the present invention has the following significant advantages and beneficial effects: First, it effectively solves the problem of abnormal output voltage fluctuations during the soft-start phase of switching power supply chips. This invention, through a designed closed-loop dynamic clamping circuit, forcibly clamps the error voltage Vc within a dynamically low level range that varies with the soft-start level Vsoft during the initial soft-start phase. This avoids the drastic fluctuations in inductor current IL and output voltage Vo caused by the instantaneous surge of Vc in traditional circuits, achieving a smooth and safe start-up of the output voltage.

[0017] Secondly, it significantly improves the reliability of the chip and the performance of the system. By limiting the peak fluctuations of the inductor current, this invention effectively protects key electronic components such as the power switch and output capacitor from overcurrent surges, extending the lifespan of the chip and the entire power supply system. Simultaneously, the stable output voltage reduces interference and damage risks to downstream load circuits, improving the overall system's operational stability.

[0018] Third, it reduces costs while ensuring versatility and compatibility. This invention requires no additional digital or analog interfaces, nor external compensation components. It achieves its purpose by adding only a few analog circuit modules such as voltage divider sampling resistors, soft-start amplifiers, and voltage clamps within the chip, significantly reducing manufacturing costs. Furthermore, this solution requires minimal modification to the design architecture of existing switching power supply chips, exhibiting good versatility and compatibility, making it easy to promote and apply in actual products.

[0019] Other features and advantages of the present invention will be described in detail in the following detailed description section. Attached Figure Description

[0020] The above and other objects, features and advantages of the present invention will become more apparent from the more detailed description of exemplary embodiments of the invention in conjunction with the accompanying drawings, wherein the same reference numerals generally represent the same components in the exemplary embodiments of the invention.

[0021] Figure 1 A schematic diagram of a switching power supply chip in the prior art is shown.

[0022] Figure 2 The waveform timing diagram of soft-start of a switching power supply chip in the prior art is shown.

[0023] Figure 3 The circuit diagram shows the output voltage stabilization circuit based on closed-loop dynamic clamping during the startup of the switching power supply chip.

[0024] Figure 4 The waveform timing diagram shows the output voltage stabilization circuit diagram based on closed-loop dynamic clamping when the switching power supply chip starts up.

[0025] Figure 2 In the initial stage of startup, the error level Vc oscillates, the peak value of the inductor current IL changes too much, and the soft-start output voltage Vo rises with abnormal fluctuations. Figure 4 In the process, the dynamic threshold Vc_c follows the soft-start level Vsoft, gradually limiting the error level Vc in the early stage of startup, stabilizing the peak value of the inductor current IL, and ensuring that the soft-start output voltage Vo rises at a constant speed. Detailed Implementation

[0026] Preferred embodiments of the invention will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein.

[0027] like Figure 3As shown, the output voltage stabilization circuit based on closed-loop dynamic clamping for startup of the switching power supply chip provided by the present invention mainly includes four core parts: main power circuit, PWM control and current mode control circuit, error amplification and soft start circuit, and closed-loop dynamic clamping circuit.

[0028] The main power circuit consists of an input voltage terminal Vin, a high-side power transistor Q1, a low-side power transistor Q2, an inductor L, and an output capacitor Co. The input voltage terminal Vin is connected to the input of the high-side power transistor Q1. The output of the high-side power transistor Q1 is connected to one end of the inductor L and the input of the low-side power transistor Q2. The output of the low-side power transistor Q2 is grounded. The other end of the inductor L is connected to the output voltage terminal Vo and the positive terminal of the output capacitor Co. The negative terminal of the output capacitor Co is grounded. This main power circuit constitutes a typical buck switching power supply topology. When the high-side power transistor Q1 is turned on, the input voltage Vin charges the inductor L through Q1 and provides energy to the output, while simultaneously charging the output capacitor Co. When the high-side power transistor Q1 is turned off and the low-side power transistor Q2 is turned on, the inductor L releases energy through Q2, maintaining a stable output voltage.

[0029] The PWM control and current-mode control loop consists of a clock module, an SR flip-flop, a PWM controller, a current sensing module, and a current comparator. The clock module generates a clock signal CLK and outputs it to the set terminal S of the SR flip-flop. The frequency of the clock signal CLK determines the operating frequency of the switching power supply. The output Q of the SR flip-flop outputs a duty cycle signal Duty to the PWM controller. The PWM controller outputs drive signals based on the duty cycle signal Duty to control the on / off state of the upper power transistor Q1 and the lower power transistor Q2. The current sensing module is connected to inductor L and samples the inductor current IL, generating a sampling voltage Vsns, which is output to the inverting input of the current comparator. The non-inverting input of the current comparator receives the error level Vc, and the output of the current comparator generates a comparison signal Vcmp, which is connected to the reset terminal R of the SR flip-flop. When the sampling voltage Vsns generated by the inductor current IL rises above the error level Vc, the current comparator outputs a high-level comparison signal Vcmp, which resets the SR flip-flop and flips the duty cycle signal Duty from high to low, thereby turning off the upper power transistor Q1 and turning on the lower power transistor Q2, realizing closed-loop control in peak current mode.

[0030] The error amplification and soft-start circuit consists of feedback resistors R1 and R2, a soft-start current source I1, a soft-start capacitor C1, and an error amplifier. Feedback resistors R1 and R2 are connected in series between the output voltage terminal Vo and ground. The connection point of feedback resistors R1 and R2 generates a feedback voltage Vfb, which is connected to the inverting input of the error amplifier. The feedback voltage Vfb and the output voltage Vo satisfy the following relationship: Vfb = Vo × R2 / (R1+R2). The soft-start current source I1 is connected in series with the soft-start capacitor C1 and then grounded. The soft-start current source I1 charges the soft-start capacitor C1, generating a gradually increasing soft-start level Vsoft. The soft-start level Vsoft is output to the non-inverting input of the error amplifier. The output of the error amplifier generates an error level Vc and outputs it to the non-inverting input of the current comparator. The soft-start level Vsoft starts from zero and gradually increases as the soft-start capacitor C1 is charged. The rate of increase is determined by the current value of the soft-start current source I1 and the capacitance value of the soft-start capacitor C1.

[0031] The closed-loop dynamic clamping circuit consists of voltage divider sampling resistors R3 and R4, a soft-start level amplifier, and a voltage clamping module. This is the core innovation of this invention. One end of the voltage divider sampling resistor R3 is connected to the output of the error amplifier and receives the error level Vc. The other end of R3 is connected in series with voltage divider sampling resistor R4 and then grounded. The connection point of voltage divider sampling resistors R3 and R4 outputs the clamping sampling voltage Vc_sns to the non-inverting input of the soft-start level amplifier. The inverting input of the soft-start level amplifier is connected to the soft-start level Vsoft, and the output of the soft-start level amplifier is connected to the input of the voltage clamping module. The output of the voltage clamping module is connected to the output of the error amplifier to limit the maximum voltage value of the error level Vc output by the error amplifier.

[0032] The dynamic threshold Vc_c gradually increases following the soft-start level Vsoft. During the soft-start phase, the soft-start level Vsoft gradually increases from zero, and the dynamic threshold Vc_c increases accordingly. If the dynamic threshold Vc_c rises to a level exceeding the normal operating range of the error level Vc, the clamping sampling voltage Vc_sns becomes less than the soft-start level Vsoft. The soft-start level amplifier outputs a low-level control signal to cut off the voltage clamping module, thereby releasing the clamping on the error level Vc, and the circuit enters normal closed-loop regulation.

[0033] The voltage clamping module is implemented using an emitter follower circuit composed of transistors. The emitter follower circuit includes an NPN transistor. The base of the NPN transistor receives the control signal output from a soft-start amplifier, the emitter of the NPN transistor is connected to the output of an error amplifier, and the collector of the NPN transistor is connected to the power supply. When the soft-start amplifier outputs a high-level control signal, the NPN transistor turns on, and its emitter output voltage follows the base voltage change, thereby clamping the error level Vc output by the error amplifier within the dynamic threshold Vc_c range. Emitter followers have characteristics such as high input impedance, low output impedance, and voltage gain close to 1, making them very suitable for voltage clamping applications. The voltage clamping module can also be implemented using a source follower circuit or a dedicated clamping circuit; the scope of protection of this invention is not limited to a specific circuit implementation.

[0034] from Figure 4 As can be seen from the waveform timing diagram, under the closed-loop dynamic clamping effect of this invention, the error level Vc is limited to the range of the dynamic threshold Vc_c (shown by the solid line) within the range shown by the dashed line, without the instantaneous surge of Vc to excessive levels seen in traditional technologies. The inductor current IL exhibits a triangular wave shape with its peak value effectively limited, without drastic fluctuations. The output voltage Vo rises steadily in a stepped manner without drastic fluctuations. This smooth and safe startup process effectively protects key electronic components such as the power switch and output capacitor from overcurrent surges, extends the lifespan of the chip and the entire power supply system, reduces interference and damage risks to downstream load circuits, and improves the overall system stability.

[0035] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.

Claims

1. A closed-loop dynamic clamping-based output voltage stabilization circuit for a switching power supply chip during startup, comprising: The system comprises an error amplifier, a current comparator, a current detection module, a clock module, an SR flip-flop, a PWM controller, feedback resistors R1 and R2, a soft-start current source I1, a soft-start capacitor C1, a power transistor Q1, a power transistor Q2, an inductor L, and an output capacitor Co. The output voltage Vo is amplified by comparing the feedback voltage Vfb generated by the feedback resistors R1 and R2 with the soft-start level Vsoft to generate an error level Vc. The inductor current IL of inductor L is sampled by the current detection module to generate a sampling voltage Vsns. The current comparator compares the sampling voltage Vsns with the error level Vc to generate a comparison signal Vcmp. When the comparison signal Vcmp goes high, it causes the duty cycle signal Duty of the SR flip-flop to go low, thereby controlling the power transistor Q1 to turn off and the power transistor Q2 to turn on. Its key feature is that… It also includes a closed-loop dynamic clamping circuit; The closed-loop dynamic clamping circuit includes voltage divider sampling resistors R3 and R4, a soft-start level amplifier, and a voltage clamping module. One end of the voltage divider sampling resistor R3 is connected to the output of the error amplifier to receive the error level Vc, and the other end is connected in series with the voltage divider sampling resistor R4 and then grounded. The connection point of the voltage divider sampling resistors R3 and R4 outputs the clamping sampling voltage Vc_sns to the non-inverting input of the soft-start level amplifier. The inverting input of the soft-start level amplifier is connected to the soft-start level Vsoft. The output of the soft-start level amplifier is connected to the input of the voltage clamping module. The output of the voltage clamping module is connected to the output of the error amplifier to limit the maximum voltage value of the error level Vc output by the error amplifier. The upper power transistor Q1, the lower power transistor Q2, the inductor L, and the output capacitor Co constitute the main power circuit. The input terminal of the upper power transistor Q1 is connected to the input voltage terminal Vin. The output terminal of the upper power transistor Q1 is connected to one end of the inductor L and the input terminal of the lower power transistor Q2. The output terminal of the lower power transistor Q2 is grounded. The other end of the inductor L is connected to the output voltage terminal Vo and the positive terminal of the output capacitor Co. The negative terminal of the output capacitor Co is grounded. The clock module, SR flip-flop, PWM controller, current detection module, and current comparator constitute a PWM control and current-mode control loop. The clock module generates a clock signal CLK, which is output to the set terminal S of the SR flip-flop. The output terminal Q of the SR flip-flop outputs a duty cycle signal Duty to the PWM controller. The PWM controller outputs drive signals to control the on and off states of the upper power transistor Q1 and the lower power transistor Q2, respectively. The current detection module is connected to an inductor L and generates a sampling voltage Vsns, which is output to the inverting input terminal of the current comparator. The non-inverting input terminal of the current comparator receives the error level Vc, and its output terminal generates a comparison signal Vcmp. The comparison signal Vcmp is connected to the reset terminal R of the SR flip-flop. The feedback resistors R1 and R2, the soft-start current source I1, the soft-start capacitor C1, and the error amplifier constitute an error amplification and soft-start circuit. The feedback resistors R1 and R2 are connected in series between the output voltage terminal Vo and ground. The connection point of the feedback resistors R1 and R2 generates a feedback voltage Vfb, which is connected to the inverting input terminal of the error amplifier. The soft-start current source I1 is connected in series with the soft-start capacitor C1 and then grounded. It is used to charge the soft-start capacitor C1, generating a gradually increasing soft-start level Vsoft, which is output to the non-inverting input terminal of the error amplifier. The output terminal of the error amplifier generates an error level Vc, which is output to the non-inverting input terminal of the current comparator.

2. The output voltage stabilization circuit based on closed-loop dynamic clamping during startup of the switching power supply chip according to claim 1, characterized in that, The soft-start level amplifier compares the clamping sampling voltage Vc_sns with the soft-start level Vsoft. When the clamping sampling voltage Vc_sns is greater than the soft-start level Vsoft, the soft-start level amplifier outputs a control signal to trigger the voltage clamping module to clamp the maximum value of the error level Vc within the range of the dynamic threshold Vc_c determined by the soft-start level Vsoft.

3. The output voltage stabilization circuit based on closed-loop dynamic clamping during startup of the switching power supply chip according to claim 2, characterized in that, The dynamic threshold Vc_c gradually increases following the soft-start level Vsoft. When the dynamic threshold Vc_c rises to exceed the normal operating range of the error level Vc, the voltage clamping module releases the clamp on the error level Vc.

4. The output voltage stabilization circuit based on closed-loop dynamic clamping during startup of the switching power supply chip according to claim 1, characterized in that, The voltage clamping module is implemented using an emitter follower, source follower, or dedicated clamping circuit composed of transistors.

5. A method for stabilizing the output voltage of a switching power supply chip during startup based on closed-loop dynamic clamping, based on the circuit described in any one of claims 1-4, comprising: S1. Obtain the output voltage Vo and generate the feedback voltage Vfb through the feedback resistors R1 and R2. Compare and amplify the feedback voltage with the soft start level Vsoft to generate the error level Vc. S2. A sampling voltage Vsns is generated by sampling the current IL of the inductor L, and compared with the error level Vc to generate a comparison signal Vcmp to control the switching state of the power transistor Q1 and the power transistor Q2. S3. The maximum value of the error level Vc is dynamically limited by a closed-loop dynamic clamping circuit, and the error level Vc is clamped within the dynamic threshold Vc_c range determined by the soft start level Vsoft, so as to eliminate output voltage fluctuations.

6. The method according to claim 5, characterized in that, S3 include: S31. The closed-loop dynamic clamping circuit performs voltage division sampling on the error level Vc through voltage divider sampling resistors R3 and R4 to generate clamping sampling voltage Vc_sns. S32. Compare the clamping sampling voltage Vc_sns with the soft-start level Vsoft input soft-start level amplifier; If the clamping sampling voltage Vc_sns is greater than the soft-start level Vsoft, the voltage clamping module is triggered to clamp the maximum value of the error level Vc within the range of the dynamic threshold Vc_c.

7. The method according to claim 6, characterized in that, S32 specifically refers to: The clamping sampling voltage Vc_sns is input to the non-inverting input of the soft-start level amplifier, and the soft-start level Vsoft is input to the inverting input of the soft-start level amplifier. The soft-start level amplifier compares the clamping sampling voltage Vc_sns with the soft-start level Vsoft and outputs a control signal to the voltage clamping module. When Vc_sns > Vsoft, the soft-start level amplifier outputs a high-level control signal to the voltage clamping module, and the voltage clamping module is turned on, clamping the error level Vc output by the error amplifier within the range of the dynamic threshold Vc_c. The dynamic threshold Vc_c and the soft start level Vsoft satisfy the following relationship: Vc_c = Vsoft × (1 + R3 / R4).

8. The method according to claim 5, characterized in that, S3 also includes: S33. As the soft-start phase progresses, the soft-start level Vsoft gradually increases, and the dynamic threshold Vc_c increases accordingly. If the dynamic threshold Vc_c rises to a level exceeding the normal operating range of the error level Vc, the clamping sampling voltage Vc_sns is less than the soft-start level Vsoft. The soft-start level amplifier outputs a low-level control signal, the voltage clamping module is turned off, the clamping of the error level Vc is released, and the circuit enters normal operating state.

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