A multi-phase non-overlapping clock generation circuit

Abstract

The application provides a multi-phase non-overlapping clock generation circuit, which comprises a triangular wave generation module, a clock generation module, a reference voltage generation module, a triangular wave intercepting module and a signal combination logic processing module. The triangular wave generation module generates a periodic triangular wave signal. The clock generation module receives the periodic triangular wave signal and outputs a multi-phase non-overlapping clock signal. The reference voltage generation module generates a plurality of reference voltages, and the plurality of reference voltages sequentially intercept the triangular wave signal, so that the period of the triangular wave is divided into a plurality of equal parts. The triangular wave intercepting module compares the reference voltage with the periodic triangular wave signal and outputs a plurality of comparison signals. The signal combination logic processing module comprises an exclusive OR gate and a NOR gate. The exclusive OR gate receives the comparison signals and performs logic operation, and outputs a first part of the multi-phase non-overlapping clock. The NOR gate receives the output of the exclusive OR gate and a first comparison signal, and outputs a second part of the multi-phase non-overlapping clock signal. The first comparison signal is output as a third part of the multi-phase non-overlapping clock signal. The application further comprises an electronic device.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design, and more particularly to a multiphase non-overlapping clock generation circuit. Background Technology

[0002] Different circuits require different functions and therefore have different requirements for clock signals. Multiphase clocks are widely used in time-interleaved analog-to-digital converters, clock data recovery circuits, phase-locked loops (PLLs), delay-locked loops (DLLs), and systems-on-a-chip (SoCs). Current methods for generating multiphase clocks have certain shortcomings. For example, multiphase clocks generated using inverter delays suffer from insufficient accuracy. While multiphase non-overlapping clocks generated using frequency dividers can precisely control phase magnitude, they lack flexibility and require the output clock frequency to be a multiple of the input clock frequency.

[0003] Therefore, there is an urgent need for a circuit with a simple structure that can flexibly generate any number of non-overlapping multi-phase clocks that meet the required accuracy. Summary of the Invention

[0004] This application proposes a multiphase non-overlapping clock generation circuit, including a triangular wave generation module configured to generate a periodic triangular wave signal; a clock generation module configured to receive the periodic triangular wave signal and output a multiphase non-overlapping clock signal, including a reference voltage generation module configured to generate multiple reference signals, wherein the multiple reference signals sequentially truncate the triangular wave signal to divide the period of the triangular wave into multiple equal parts; a triangular wave truncation module configured to compare the multiple reference signals and the periodic triangular wave signal and output M comparison signals, where M is an integer greater than or equal to 2; and a signal combinational logic processing module, including at least N XOR gates and NOR gates. Where N equals M-1, each of the XOR gates is configured to receive two comparison signals for logical operation, and at least one of the comparison signals received by different XOR gates is different. The outputs of the plurality of XOR gates serve as the first part of the multiphase non-overlapping clock signal. The NOR gate is configured to receive the output of the XOR gate and the first comparison signal among the plurality of comparison signals, wherein the first comparison signal is the comparison result of the periodic triangular wave signal and the reference signal with the largest absolute value among the plurality of reference signals. The output of the NOR gate serves as the second part of the multiphase non-overlapping clock signal. The first comparison signal output serves as the third part of the multiphase non-overlapping clock signal.

[0005] Specifically, the multiphase non-overlapping clock generation circuit proposed in this application includes a triangular wave interception module comprising a comparator. The comparator includes a positive input terminal and multiple negative input terminals. The positive terminal receives a periodic triangular wave signal, and the negative terminal receives a reference signal.

[0006] Specifically, the multiphase non-overlapping clock generation circuit proposed in this application includes a first reference signal, a second reference signal, and a third reference signal as the plurality of reference signals. The first reference signal is greater than the second reference signal, and the second reference signal is greater than the third reference signal. The first reference signal, the second reference signal, and the third reference signal respectively truncate the triangular wave at 1 / 4, 2 / 4, and 3 / 4 of the period of the periodic triangular wave signal to obtain the first comparison signal, the second comparison signal, and the third comparison signal in sequence.

[0007] Specifically, the multiphase non-overlapping clock generation circuit proposed in this application includes a signal combination logic processing module comprising a first XOR gate, a second XOR gate, and a NOR gate. The first comparison signal is low-pass filtered and delayed to obtain a first clock signal. The second and third comparison signals are XORed, low-pass filtered, and delayed to obtain a second clock signal. The second and third comparison signals are XORed, low-pass filtered, and delayed to obtain a third clock signal. The first comparison signal, the second clock signal, and the third clock signal are NORed, low-pass filtered, and delayed to obtain a fourth clock signal.

[0008] Specifically, in the multiphase non-overlapping clock generation circuit proposed in this application, the signal combination logic processing module further includes a low-pass filter, which includes a resistor and a capacitor. The XOR gate output, the NOR gate output, and the first comparison signal output are connected in series with the low-pass filter. The first end of the resistor serves as the input end of the low-pass filter, and its second end is electrically connected to the first end of the capacitor. The second end of the capacitor is grounded.

[0009] In particular, the multiphase non-overlapping clock generation circuit proposed in this application further includes a buffer in the signal combination logic processing module, wherein the XOR gate output, the NOR gate output and the first comparison signal output are each connected in series with at least one buffer.

[0010] In particular, in the multiphase non-overlapping clock generation circuit proposed in this application, the rising speed of the periodic triangular wave signal is much greater than the falling speed, wherein the rising speed is less than the nanosecond level, or the falling speed is much greater than the rising speed, wherein the falling speed is less than the nanosecond level.

[0011] This application also proposes an electronic device including any of the described multiphase non-overlapping clock generation circuits.

[0012] This application uses a comparator to simultaneously compare the magnitudes of multiple reference voltages and triangular waves, and performs digital logic processing on the resulting signals to generate a multi-phase non-overlapping clock, which can improve the problems of insufficient accuracy and flexibility of existing clock signals. Attached Figure Description

[0013] Figure 1 This is a logic diagram of a multiphase non-overlapping clock generation circuit according to an embodiment of this application; Figure 2 This is a schematic diagram of a multiphase non-overlapping clock generation circuit according to an embodiment of this application; Figure 3 for Figure 2 A circuit example diagram of a comparator used in a multiphase non-overlapping clock generation circuit according to an embodiment of this application; Figure 4 for Figure 2 Input-output waveform diagram of a comparator in a multiphase non-overlapping clock generation circuit according to an embodiment of this application; Figure 5 for Figure 2 A clock waveform diagram generated in a multiphase non-overlapping clock generation circuit according to an embodiment of this application; Figure 6 This is a schematic diagram of an n-phase non-overlapping clock generation circuit according to an embodiment of this application; Figure 7 for Figure 6 A circuit example diagram of the comparator used in an n-phase non-overlapping clock generation circuit according to an embodiment of this application. Detailed Implementation

[0014] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0015] In the following detailed description, reference can be made to the accompanying drawings, which form part of this application and illustrate specific embodiments of the present application. In the drawings, similar reference numerals describe substantially similar components in different figures. Specific embodiments of the present application are described in sufficient detail below to enable those skilled in the art to implement the technical solutions of the present application. It should be understood that other embodiments may also be utilized, or structural, logical, or electrical changes may be made to the embodiments of the present application.

[0016] Techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and apparatus should be considered part of the specification. The lines connecting the units in the accompanying drawings are merely for illustrative purposes, indicating that at least the units at both ends of the line are communicating with each other, and are not intended to prevent unconnected units from communicating. Furthermore, the number of lines between two units is intended to indicate at least the number of signals involved in communication between the two units or at least the number of output terminals, and is not intended to limit communication between the two units to only the signals shown in the figures.

[0017] A transistor can refer to any type of transistor, such as a field-effect transistor (FET) or a bipolar junction transistor (BJT). When a transistor is a field-effect transistor, depending on the channel material, it can be hydrogenated amorphous silicon, metal oxide, low-temperature polycrystalline silicon, organic transistors, etc. Based on whether the charge carriers are electrons or holes, they can be divided into N-type transistors and P-type transistors. The gate of a field-effect transistor is its control electrode; the first electrode can be the drain or source, and the corresponding second electrode can be the source or drain. The gate or control electrode can be the control electrode. When a transistor is a bipolar junction transistor (BJT), the base is its control electrode; the first electrode can be the collector or emitter, and the corresponding second electrode can be the emitter or collector. The base or control electrode can be the control electrode. Transistors can be manufactured using amorphous silicon, polycrystalline silicon, oxide semiconductor, organic semiconductor, NMOS / PMOS, or CMOS processes.

[0018] This application compares a periodic triangular wave signal with multiple reference signals to obtain comparison signals with different duty cycles, and then generates a multi-phase non-overlapping clock by performing digital logic processing on the generated comparison signals. This solution improves upon the shortcomings of existing clock signal generators in terms of accuracy and flexibility.

[0019] Figure 1 This is a logic diagram of a multiphase non-overlapping clock generation circuit according to an embodiment of this application.

[0020] According to one embodiment, the triangular wave generation module 101 and the clock generation module 102 are electrically connected. According to another embodiment, the clock generation module 102 may include a reference voltage generation module 1021, a triangular wave truncation module 1022, and a signal combination logic processing module 1023. The output terminals of the reference voltage generation module 1021 and the triangular wave generation module 101 are electrically connected to the first and second input terminals of the triangular wave truncation module 1022, respectively. The output terminal of the triangular wave truncation module 1022 is electrically connected to the input terminal of the signal combination logic processing module 1023. The output terminal of the signal combination logic processing module 1023 outputs a multiphase non-overlapping clock signal.

[0021] The triangular wave generation module 101 is configured to generate a triangular wave signal, and the triangular wave interception module 1022 is configured to intercept the triangular wave generated by the triangular wave generation module 101 using the reference signal generated by the reference voltage generation module 1021 to obtain comparison signals with different duty cycles. The comparison signals are processed by the signal combination logic processing module 1023 to obtain a multiphase non-overlapping clock signal and output it.

[0022] Figure 2 This is a schematic diagram of a multiphase non-overlapping clock generation circuit according to an embodiment of this application.

[0023] like Figure 2 As shown, the triangular wave generation module 201 can generate a periodic triangular wave signal clk0 with a short falling edge.

[0024] According to one embodiment, in the triangular wave generation module 201, the positive input terminal of operational amplifier OA is electrically connected to the first terminals of resistors R1, R2, and R3, and the negative input terminal is electrically connected to the first terminals of capacitor C1, R4, and switch TG. The voltage at the connection point is used as the output of the periodic triangular wave signal clk0 generated by the triangular wave generation module 201. The output terminal of operational amplifier OA is electrically connected to the second terminals of resistors R3 and R4, and the first terminal of inverter INV1. The second terminal of resistor R1 is connected to voltage level VDD, and the second terminals of resistor R2, capacitor C1, and switch TG are all grounded. The second terminal of inverter INV1 is electrically connected to the first terminal of inverter INV2, the second terminal of inverter INV2 is electrically connected to the first terminal of inverter INV3, the second terminal of inverter INV3 is electrically connected to the third terminal of switch TG, and the fourth terminal of switch TG is electrically connected to the second terminal of inverter INV2. According to one embodiment, switch TG is a transmission gate switch, jointly controlled by NOMS and PMOS, and can transmit either a high or low level. Introducing a switch TG between the two ends of capacitor C1 can accelerate the discharge speed of capacitor C1. The discharge of the charge of capacitor C1 from TG to ground can greatly accelerate the discharge speed and avoid additional phase overlap when comparing at the falling edge of the triangular wave.

[0025] like Figure 2 As shown, the clock generation module 202 can generate four-phase non-overlapping clock signals Ф1~Ф4.

[0026] According to one embodiment, the reference voltage generation circuit in the reference voltage generation module 2021 generates reference signals Vref0, Vref1, and Vref2. The reference signals Vref0 to Vref2 are independent of power supply voltage, temperature, and process angle.

[0027] According to one embodiment, the periodic triangular wave signal clk0 output by the triangular wave generation module 201 is input to the positive input terminal of the comparator COMP in the triangular wave interception module 2022. The negative input terminal of the comparator COMP receives reference signals Vref0, Vref1, and Vref2 respectively. The reference signal Vref0 is compared with clk0 at the positive terminal of the comparator COMP, and a comparison signal Q1 is output through the output terminal VO1. The reference signal Vref1 is compared with clk0 at the positive terminal of the comparator COMP, and a comparison signal Q2 is output through the output terminal VO2. The reference signal Vref1 is compared with clk0 at the positive terminal of the comparator COMP, and a comparison signal Q3 is output through the output terminal VO3.

[0028] According to one embodiment, in the signal combination logic processing module 2023, the first end of resistor R5 is electrically connected to the output terminal VO1, the second end of resistor R5 is electrically connected to the first end of capacitor C2 and the first end of buffer A1, the second end of capacitor C2 is grounded, the second end of buffer A1 is electrically connected to the first end of buffer A2, and the second end of buffer A2 outputs a clock signal Ф1, wherein resistor R5 and capacitor C2 constitute a low-pass filter.

[0029] According to one embodiment, in the signal combinational logic processing module 2023, the input terminal of the XOR gate XOR1 is electrically connected to the output terminals VO1 and VO2 of the comparator COMP, respectively, and receives the comparison signals Q1 and Q2. The output terminal of the XOR gate XOR1 is electrically connected to the first terminal of the resistor R6. The second terminal of the resistor R6 is electrically connected to the first terminal of the capacitor C3 and the first terminal of the buffer A3. The second terminal of the capacitor C3 is grounded. The second terminal of the buffer A3 is electrically connected to the first terminal of the buffer A4. The second terminal of the buffer A4 serves as the output terminal of the clock signal Ф2. The resistor R6 and the capacitor C3 constitute a low-pass filter.

[0030] According to one embodiment, in the signal combinational logic processing module 2023, the input terminal of the XOR gate XOR2 is electrically connected to the output terminals VO2 and VO3 respectively, and receives the comparison signal Q2 and the comparison signal Q3. The output terminal of the XOR gate XOR2 is electrically connected to the first terminal of the resistor R7. The second terminal of the resistor R7 is electrically connected to the first terminal of the capacitor C4 and the first terminal of the buffer A5. The second terminal of the capacitor C4 is grounded. The second terminal of the buffer A5 is electrically connected to the first terminal of the buffer A6. The second terminal of the buffer A6 serves as the output terminal of the clock signal Ф3. The resistor R7 and the capacitor C4 constitute a low-pass filter.

[0031] According to one embodiment, in the signal combinational logic processing module 2023, the three input terminals of the OR gate are electrically connected to the output terminal VO1 of the comparator COMP, the second terminal of buffer A4, and the second terminal of buffer A6, respectively, and receive the comparison signal Q1, clock signal Ф2, and clock signal Ф3. Its output terminal outputs the comparison signal Q4. According to another embodiment, the output terminal of the OR gate is electrically connected to the first terminal of resistor R8, the second terminal of resistor R8 is electrically connected to the first terminal of capacitor C5 and the first terminal of buffer A7, the second terminal of buffer A7 is electrically connected to the first terminal of buffer A8, the second terminal of buffer A8 outputs the clock signal Ф4, and the second terminal of capacitor C5 is grounded. Resistor R8 and capacitor C5 constitute a low-pass filter.

[0032] In practical applications, the falling edge of the periodic triangular wave signal clk0 does not fall without any delay. Therefore, the reference signals Vref0~Vref2 may slightly overlap when capturing the falling edge of the periodic triangular wave signal clk0. This overlap may produce glitches or unwanted high levels during logic operations. To avoid these unwanted glitches or high levels, a low-pass filter is introduced in the branches corresponding to the clock signals Φ1~Φ4 to filter out glitches or high levels. Since the low-pass filter has a capacitor, it will reduce the driving capability of the circuit. Therefore, a buffer is added after the filter to maintain the driving capability.

[0033] According to one embodiment, such as Figure 2 The triangular wave generation module 201 shown can use other circuits that can generate periodic triangular waves, but the rising or falling edge speed of the generated triangular wave signal must be fast. For higher precision requirements, a triangular wave waveform with a linear rising edge and a rapid falling edge can be used, where the falling speed can be less than the nanosecond level, or a triangular wave waveform with a rapid rising edge and a linear falling edge, where the rising speed can be less than the nanosecond level.

[0034] According to one embodiment, the voltage magnitude relationship of the reference signals Vref0~Vref2 must satisfy Vref0>Vref1>Vref2, and the amplitude of the reference signals Vref0~Vref2 must be able to equally divide one period of the periodic triangular wave signal clk0 when compared with the periodic triangular wave signal clk0.

[0035] Figure 3 for Figure 2 A circuit example diagram of the comparator used in a multiphase non-overlapping clock generation circuit according to an embodiment of this application.

[0036] In the clock generation module 202, comparison signals Q1~Q3 need to be generated simultaneously, therefore three comparators are required. Since the positive terminal of each comparator is the periodic triangular wave signal clk0 from the triangular wave generation module 201, this application multiplexes the positive terminals of the three comparators to obtain the following result: Figure 3 The comparator shown saves a significant amount of area and power consumption.

[0037] According to one embodiment, signal Vinp is used as the positive input signal of the comparator, and signals Vinn_1, Vinn_2, and Vinn_3 are used as the negative input signals of the comparator. The output signals of the comparator are signals Vout1, Vout2, and Vout3. According to one embodiment, when the comparator is used in the triangular wave truncation module 2022, signal Vinn_1 is compared with signal Vinp to output signal Vout1, signal Vinn_2 is compared with signal Vinp to output signal Vout2, and signal Vinn_3 is compared with signal Vinp to output signal Vout3.

[0038] According to one embodiment, the gates of transistors P1, P2, P3, and P4, the drain of transistor P1, and the drain of transistor N1 are electrically connected; the drain of transistor P2 is electrically connected to the gate of transistor P5 and the drain of transistor N2; the drain of transistor P3 is electrically connected to the gate of transistor P6 and the drain of transistor N3; and the drain of transistor P4 is electrically connected to the gate of transistor P7 and the drain of transistor N4. The sources of transistors P1, P2, P3, P4, P5, P6, and P7 receive a power supply signal vdd. The sources of transistors N2, N3, and N4 are electrically connected to the drain of transistor N5. The gates of transistors N1, N2, N3, and N4 receive signals Vinp, Vinn_1, Vinn_2, and Vinn_3, respectively. Transistor N5 receives a bias signal Vbias1. The gates of transistors N6, N7, and N8 are electrically connected and receive a bias signal Vbias2. Bias signals Vbias1 and Vbias2 turn on transistors N5, N6, N7, and N8. The sources of transistors N5, N6, N7, and N8 are electrically connected and grounded. The drains of transistors P5 and N6 are electrically connected, resulting in a node voltage signal Vout1. The drains of transistors P6 and N7 are electrically connected, resulting in a node voltage signal Vout2. The drains of transistors P7 and N8 are electrically connected, resulting in a node voltage signal Vout3.

[0039] According to one embodiment, to meet matching requirements, the dimensions of transistors P1, P2, P3, and P4 must be consistent, and the dimensions of transistors N1, N2, N3, and N4 must be consistent. According to another embodiment, the dimensions of transistors P5, P6, and P7 must be consistent, and the dimensions of transistors N6, N7, and N8 must be consistent.

[0040] Figure 4 for Figure 2 Input-output waveform diagram of a comparator in a multiphase non-overlapping clock generation circuit according to an embodiment of this application. Figure 5 for Figure 2 A clock waveform diagram generated in a multiphase non-overlapping clock generation circuit according to an embodiment of this application.

[0041] The inputs of the comparator COMP are a periodic triangular wave signal clk0 and reference signals Vref0~Vref2.

[0042] The periodic triangular wave signal clk0 is generated by the triangular wave generation module 201, which can generate a periodic triangular wave signal clk0 with a steep falling edge.

[0043] According to one embodiment, during the charging phase of capacitor C1, in the actual circuit, due to offset voltage and other factors, the output voltage VOUT of operational amplifier OA is initially not 0 when the circuit is powered on. Due to the positive feedback branch containing resistor R3, the output voltage VOUT of operational amplifier OA increases, and its output terminal charges capacitor C1 through resistor R4 until it reaches the maximum voltage achievable across capacitor C1. When the output voltage VOUT reaches its maximum, the output signal VOUT of operational amplifier OA is approximately connected to the level VDD, and resistors R1 and R3 are essentially connected in parallel. According to the virtual short principle, the maximum voltage Vc1max reached by capacitor C1 is VDD. (R2 / [(R1 / / R3)+R2]).

[0044] According to one embodiment, during the discharge phase of capacitor C1, an overcharge voltage is generated when capacitor C1 is fully charged, causing the voltage at the negative input terminal of operational amplifier OA to be greater than the voltage at the positive input terminal. Therefore, the output voltage of operational amplifier OA begins to decrease. When the voltage at the second terminal of resistor R4 is lower than the voltage at its first terminal, capacitor C1 begins to discharge through resistor R4. When the output terminal of operational amplifier OA is at a low level, its output terminal is approximately grounded. Therefore, resistors R2 and R3 can be considered as connected in parallel. Thus, the minimum voltage Vc1min reached by capacitor C1 is VDD. ((R2 / / R3) / [(R2 / / R3)+R1]).

[0045] A periodic triangular wave signal clk0 is generated by periodically charging and discharging capacitor C1, and output through the first terminal of capacitor C1. The comparator compares the magnitudes of two analog voltage signals and outputs a digital (high / low level) result. This application limits the magnitudes of reference signals Vref0~Vref2, and outputs a digital signal with a fixed duty cycle when compared with the periodic triangular wave signal clk0.

[0046] like Figure 4 As shown, according to one embodiment, a periodic triangular wave signal clk0 is input to the positive terminal of the comparator COMP and compared with three reference signals Vref0~Vref2 input to the negative terminal of the comparator COMP. Within one period T of the periodic triangular wave signal clk0, reference signal Vref0 is compared with the periodic triangular wave signal clk0 to obtain a comparison signal Q1 with a duty cycle of T / 4; reference signal Vref1 is compared with the periodic triangular wave signal clk0 to obtain a comparison signal Q2 with a duty cycle of T / 2; and reference signal Vref2 is compared with the periodic triangular wave signal clk0 to obtain a comparison signal Q3 with a duty cycle of 3T / 4. That is, the triangular wave is truncated at 1 / 4, 2 / 4, and 3 / 4 of the period T of the periodic triangular wave signal clk0, dividing the period of the periodic triangular wave signal clk0 into four equal parts, resulting in comparison signals Q1~Q3 with different duty cycles. The output waveform is shown below. Figure 4 As shown. Since the reference signals Vref0~Vref2 are all compared with the periodic triangular wave signal clk0, the resulting comparison signals Q1~Q3 have the same frequency. At the same time, it can be seen that the duty cycle of the comparison signals Q1~Q3 increases by T / 4 in sequence, which makes it possible to generate non-overlapping clocks.

[0047] like Figure 4 As shown, the duty cycles of the comparison signals Q1~Q3 increase by T / 4 sequentially, and the overlap also increases sequentially. To obtain a non-overlapping clock, the overlap needs to be removed. The XOR gate works by outputting a low level when the two signals are the same and a high level only when the two signals are different. Therefore, the overlap between the comparison signals can be removed. The NOR gate works by outputting a low level as long as one input is high. Therefore, by performing a NOR operation on the output signal of the first comparator and all the non-overlapping signals obtained by the XOR gates, the signal that does not overlap with any of the non-overlapping signals obtained by the XOR gates can be extracted.

[0048] like Figure 5As shown, according to one embodiment, clock signal Φ1 is obtained by delaying comparison signal Q1; clock signal Φ2 is obtained by XORing comparison signals Q1 and Q2 and then low-pass filtering and delaying; clock signal Φ3 is obtained by XORing comparison signals Q2 and Q3 and then low-pass filtering and delaying. According to another embodiment, clock signal Φ4 is obtained by performing NOR operations on comparison signals Q1, clock signal Φ2, and clock signal Φ3, followed by low-pass filtering and delaying.

[0049] Figure 6 This is a schematic diagram of an n-phase non-overlapping clock generation circuit according to an embodiment of this application. Figure 7 for Figure 6 A circuit example diagram of the comparator used in an n-phase non-overlapping clock generation circuit according to an embodiment of this application.

[0050] According to one embodiment, it can be based on, as follows: Figure 6 and Figure 7 The structure shown generates an n-phase non-overlapping clock. To generate an n-phase non-overlapping clock, only the number of reference voltages, XOR gates, low-pass filters, and comparator branches need to be changed, where n is an integer greater than or equal to 3.

[0051] The method implemented in this application achieves the interception of different positions of the periodic triangular wave signal by simultaneously comparing the magnitudes of multiple reference signals and the periodic triangular wave signal, thereby obtaining a multi-phase clock. After digital logic processing of the multi-phase clock, a multi-phase non-overlapping clock is generated. The structure is simple and can flexibly change the magnitude of the reference signals to generate a multi-phase non-overlapping clock according to the requirements.

[0052] The above embodiments are for illustrative purposes only and are not intended to limit the scope of this application. Those skilled in the art can make various changes and modifications without departing from the scope of this application. Therefore, all equivalent technical solutions should also fall within the scope of this application.

Claims

1. A multiphase non-overlapping clock generation circuit, characterized in that, include: The triangular wave generation module is configured to generate periodic triangular wave signals; A clock generation module, configured to receive the periodic triangular wave signal and output a multi-phase non-overlapping clock signal, includes: A reference voltage generation module is configured to generate multiple reference signals, wherein the multiple reference signals sequentially extract periodic triangular wave signals and divide the periodic triangular wave signals into multiple equal parts; The triangular wave interception module is configured to compare the plurality of reference signals with the periodic triangular wave signal and output M comparison signals, where M is an integer greater than or equal to 2; The signal combination logic processing module includes at least N XOR gates and NOR gates, where N equals M-1. Each XOR gate is configured to receive two comparison signals for logical operation. At least one of the comparison signals received by different XOR gates is different. The outputs of the multiple XOR gates serve as the first part of a multiphase non-overlapping clock signal. The NOR gates are configured to receive the outputs of the XOR gates and a first comparison signal from the multiple comparison signals. The first comparison signal is the comparison result of the periodic triangular wave signal and the reference signal with the largest absolute value among the multiple reference signals. The outputs of the NOR gates serve as the second part of a multiphase non-overlapping clock signal. The output of the first comparison signal serves as the third part of a multiphase non-overlapping clock signal.

2. The multiphase non-overlapping clock generation circuit as described in claim 1, characterized in that, The triangular wave interception module includes a comparator with one positive input and multiple negative inputs. The positive input receives a periodic triangular wave signal, and the negative input receives a reference signal.

3. The multiphase non-overlapping clock generation circuit as described in claim 2, characterized in that, The plurality of reference signals include a first reference signal, a second reference signal, and a third reference signal. The first reference signal is greater than the second reference signal, and the second reference signal is greater than the third reference signal. The first reference signal, the second reference signal, and the third reference signal respectively intercept the triangular wave at 1 / 4, 2 / 4, and 3 / 4 of the period of the periodic triangular wave signal to obtain the first comparison signal, the second comparison signal, and the third comparison signal in sequence.

4. The multiphase non-overlapping clock generation circuit as described in claim 3, characterized in that, The signal combination logic processing module includes a first XOR gate, a second XOR gate, and a NOR gate. The first comparison signal is low-pass filtered and delayed to obtain a first clock signal. The second and third comparison signals are XORed, low-pass filtered, and delayed to obtain a second clock signal. The second and third comparison signals are XORed, low-pass filtered, and delayed to obtain a third clock signal. The first comparison signal, the second clock signal, and the third clock signal are NORed, low-pass filtered, and delayed to obtain a fourth clock signal.

5. The multiphase non-overlapping clock generation circuit as described in claim 1, characterized in that, The signal combination logic processing module further includes a low-pass filter, which includes a resistor and a capacitor. The XOR gate output, the NOR gate output, and the first comparison signal output are connected in series with the low-pass filter. The first end of the resistor serves as the input of the low-pass filter, and its second end is electrically connected to the first end of the capacitor. The second end of the capacitor is grounded.

6. The multiphase non-overlapping clock generation circuit as described in claim 1, characterized in that, The signal combination logic processing module further includes a buffer, and the XOR gate output, NOR gate output and the first comparison signal output are each connected in series with at least one buffer.

7. The multiphase non-overlapping clock generation circuit as described in claim 1, characterized in that, The periodic triangular wave signal has a rising speed much greater than its falling speed, where the rising speed is below the nanosecond level, or a falling speed much greater than its rising speed, where the falling speed is below the nanosecond level.

8. An electronic device, characterized in that, Includes the multiphase non-overlapping clock generation circuit as described in any one of claims 1-7.

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