A low-power mixed analog-digital converter with prediction and edge extraction functions

Abstract

The application discloses a low-power consumption hybrid analog-digital converter with a prediction and edge extraction function, comprising a slope generator and a running main body module; the running main body module comprises a first switch, a capacitor DAC array unit, a dynamic comparator and a logic unit; the first switch is used for sampling an input signal; the dynamic comparator is used for comparing a signal output by the capacitor DAC array unit with the sampled input signal and outputting a comparison result; the logic unit is used for generating a feedback signal according to an output signal of the dynamic comparator and outputting a final data signal; the capacitor DAC array unit is used for outputting a prediction signal and an SS signal and / or a SAR signal to an inverting input end of the dynamic comparator according to the feedback signal; and the slope generator is used for outputting a slope signal to regulate the size of the SS signal. The embodiment of the application combines a SAR-SS hybrid quantization architecture with a prediction mechanism, thereby providing an efficient solution for the application of a low-power consumption image sensor in the field of machine vision.

Description

Technical Field

[0001] This invention belongs to the field of image sensors, and specifically relates to a low-power hybrid analog-to-digital converter with prediction and edge extraction functions. Background Technology

[0002] Image sensors are widely used in consumer electronics, security monitoring, autonomous driving, and industrial inspection. The on-chip analog-to-digital converter (ADC), as a key module for converting analog pixel signals into digital signals, accounts for a significant proportion of the total system power consumption. With the continuous increase in pixel array size and frame rate, the ADC needs to complete more conversions per unit time, leading to a near-linear increase in dynamic power consumption, becoming a major bottleneck restricting sensor energy efficiency. Simultaneously, the increase in resolution and frame rate causes a dramatic expansion in output data volume, placing a heavy burden on transmission bandwidth and back-end processing, further increasing system power consumption.

[0003] In machine vision applications, algorithms typically only need to extract sparse features such as edges and corners, rather than complete pixel-level information. However, traditional sensors generally employ a "full readout-post-processing" working mode, where all signals must first be converted into a complete digital image by an ADC before feature extraction. In this process, a large amount of redundant data participates in high-power analog-to-digital conversion and transmission, which not only wastes ADC power but also increases processing latency, making it difficult to meet the demanding requirements of low-power, real-time machine vision perception front-ends.

[0004] Therefore, how to effectively reduce the conversion power consumption of on-chip ADCs and reduce redundant data output has become a key issue that needs to be addressed in the development of sensors towards low power consumption and machine vision. Summary of the Invention

[0005] The technical problem this invention aims to solve is that existing analog-to-digital converters (ADCs) consume significantly more power and output a large amount of redundant data under conditions of large-area arrays and high frame rates, making it difficult to meet the requirements of low power consumption and machine vision applications. Therefore, this invention provides a low-power hybrid ADC with prediction and edge extraction functions.

[0006] To address the aforementioned technical problems, embodiments of the present invention provide a low-power hybrid analog-to-digital converter with prediction and edge extraction functions, comprising: a ramp generator and a main operating module;

[0007] The main operating module includes: a first switch, a capacitor array unit, a dynamic comparator, and a logic unit;

[0008] The first switch is used to sample the input signal;

[0009] The dynamic comparator is used to compare the signal output by the capacitor DAC array unit with the sampled input signal, and latch the comparison result and output it.

[0010] The logic unit is used to generate a feedback signal based on the output signal of the dynamic comparator and output the final data signal.

[0011] The capacitor array unit is used to output a prediction signal and an SS signal and / or a SAR signal to the inverting input of the dynamic comparator based on the feedback signal.

[0012] The ramp generator is used to output a ramp signal to adjust the magnitude of the SS signal;

[0013] The non-inverting input of the dynamic comparator is connected to the first switch; the inverting input of the dynamic comparator is connected to the first reference voltage signal and the capacitor DAC array unit; the inverting input of the dynamic comparator initially receives the prediction signal and performs the prediction process; when the prediction is successful, the inverting input of the dynamic comparator receives the SS signal and performs SS quantization; when the prediction fails, the inverting input of the dynamic comparator sequentially receives the first reference voltage signal, the SAR signal, and the SS signal, and performs SAR quantization and SS quantization sequentially.

[0014] Preferably, the capacitor DAC array unit includes a capacitor array and a selection switch group; the feedback signal includes a prediction control signal and a SAR control signal;

[0015] The capacitor array includes an SS quantization capacitor, a prediction capacitor group, and a SAR quantization capacitor group. The upper plates of the SS quantization capacitor, the prediction capacitor group, and the SAR quantization capacitor group are all connected to the inverting input of the dynamic comparator. The lower plate of the SS quantization capacitor is connected to the ramp signal. The switches in the selection switch group are connected one-to-one with the lower plates of the prediction capacitor group and the SAR quantization capacitor group. The other end of the switch in the selection switch group is used to select the first reference voltage signal, the second reference voltage signal, and the third reference voltage signal. The switch control terminal of the selection switch group is connected to the SAR control signal and the prediction control signal output by the logic unit.

[0016] Preferably, the prediction capacitor group includes at least one prediction capacitor; the SS quantization capacitor has the same structure as the capacitors in the prediction capacitor group and the capacitors in the SAR quantization capacitor group.

[0017] Preferably, the magnitudes of the second reference voltage signal and the third reference voltage signal are symmetrical relative to the first reference voltage signal.

[0018] Preferably, the predictive control signal is used to control the voltage of the lower plate of the capacitor in the predictive capacitor bank.

[0019] Preferably, the SAR control signal is used to control the voltage of the lower plate of the SAR quantization capacitor bank.

[0020] Preferably, the main operating module further includes: a second switch; the second switch is used to sample the first reference voltage signal; the second switch is connected to the inverting input terminal of the dynamic comparator.

[0021] Preferably, the logic unit includes a SAR-SS logic circuit and an arithmetic logic circuit; the SAR-SS logic circuit is used to output a prediction control signal and a SAR control signal, and to output digital code values ​​during SAR and SS quantization; the arithmetic logic circuit is used to generate pixel-level edge information; the digital code values ​​during SAR and SS quantization and the pixel-level edge information constitute the final data signal.

[0022] Preferably, there are multiple operating main modules; the ramp generator outputs a single ascending ramp signal or descending ramp signal to multiple operating main modules.

[0023] Preferably, both ends of the ascending ramp signal or descending ramp signal are provided with multiple steps.

[0024] Implementing the embodiments of the present invention has the following beneficial effects:

[0025] (1) The present invention introduces the prediction mechanism into the SAR-SS hybrid quantization architecture, and skips the SAR quantization stage directly when the prediction is successful, and only retains the necessary SS quantization operation, thereby significantly reducing the power consumption in the analog-to-digital conversion process, which is beneficial to the application of image sensors in low-power scenarios.

[0026] (2) According to the prediction results and the SAR quantization results of the adjacent column analog-to-digital converters, the edge features are directly extracted on the chip. Pixel-level edge information can be obtained synchronously during the quantization process without waiting for the complete image to be generated. This reduces the computational overhead of backend data handling and feature extraction, which is conducive to realizing a high-efficiency perception front-end for machine vision. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 A schematic diagram of a low-power hybrid analog-to-digital converter with prediction and edge extraction functions provided for the implementation of this invention;

[0029] Figure 2 The figure shows the transient simulation results of a low-power hybrid analog-to-digital converter with prediction and edge extraction functions that failed to predict and was SS quantized using a rising ramp signal, provided for the implementation of this invention. Detailed Implementation

[0030] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0031] like Figure 1 As shown, this embodiment discloses a low-power hybrid analog-to-digital converter (ADC) with prediction and edge extraction functions. The low-power hybrid ADC with prediction and edge extraction functions includes a ramp generator 10 and an operating main module. The operating main module includes a first switch 20, a second switch 30, a capacitor-to-analog converter (DAC) array unit 40, a dynamic comparator 50, and a logic unit 60. The first switch 20 is used to control the input signal V. IN Sampling is performed. The second switch 30 is used to sample the first reference voltage signal V. CM Sampling is performed. The dynamic comparator 50 is used to sample the signal V output by the capacitor DAC array unit 40. DAC With the sampled input signal V INP The comparison is performed, and the comparison result is latched and output. The logic unit 60 generates a feedback signal based on the output signal of the dynamic comparator, and outputs the digital code value corresponding to the quantization result and pixel-level edge information. The digital code value corresponding to the quantization result and the pixel-level edge information together constitute the final data signal. The capacitor DAC array unit 40 is used to adjust the capacitor DAC array unit mode according to the feedback signal, and outputs the prediction signal required for the prediction process, the SAR signal required for the Successive Approximation Register (SAR) quantization process, and the SS signal required for the Single-Slope (SS) quantization process to the inverting input terminal of the dynamic comparator 50. Not all SAR signals are necessarily output to the inverting input terminal of the dynamic comparator, but are determined according to the specific content of the feedback signal. The capacitor DAC array unit 40 modes include prediction mode, SAR quantization mode, and SS quantization mode. The ramp generator 10 is used to output a ramp signal to adjust the magnitude of the SS signal.

[0032] Specifically, the non-inverting input of the dynamic comparator 50 is connected to the first switch, thereby receiving the sampled input signal V. INP The inverting input of the dynamic comparator 50 is connected to the output of the second switch 30 and the capacitor DAC array unit 40, thereby receiving the first reference voltage signal V. CM and signal V DAC The output of the dynamic comparator 50 is connected to the input of the logic unit 60. The output of the logic unit 60 outputs the final data signal. The other output of the logic unit 60 is connected to the input of the capacitor DAC array unit 40, thereby transmitting the feedback signal to the capacitor DAC array unit 40. The output of the ramp generator 10 is connected to the other input of the capacitor DAC array unit 40, thereby outputting a ramp signal to adjust the magnitude of the SS signal. The capacitor DAC array unit 40 outputs a prediction signal and / or a SAR signal and / or an SS signal to the inverting input of the dynamic comparator based on the feedback signal.

[0033] The signal at the non-inverting input of the dynamic comparator 50 is always the initial signal V. INP The inverting input of the dynamic comparator 50 initially receives a prediction signal and performs a prediction process. When the prediction is successful, the inverting input of the dynamic comparator 50 receives the SS signal and performs SS quantization. When the prediction fails, the inverting input of the dynamic comparator 50 sequentially receives the first reference voltage signal, the SAR signal, and the SS signal, and sequentially performs SAR quantization and SS quantization. Specifically, the prediction process involves: based on the signal V from the non-inverting input of the dynamic comparator 50... INP With the inverting input signal V DAC Predict the size of V. INP Less than V DAC Then V DAC Switch downwards, and vice versa. If V... INP With V DAC If there is an intersection, the prediction is successful; otherwise, the prediction fails.

[0034] In some embodiments, the signal V DAC The downward switching occurs twice. The signal V... DAC The number of switching operations is determined by actual needs.

[0035] The capacitor DAC array unit 40 includes a capacitor array 401 and a selection switch group 402. The feedback signal includes a prediction control signal and a SAR control signal. The capacitor array 401 includes an SS quantization capacitor C0, a prediction capacitor group, and a SAR quantization capacitor group (C1-C2). M-1The upper plates of the SS quantization capacitor, the prediction capacitor bank, and the SAR quantization capacitor bank are all connected to the inverting input of the dynamic comparator 50. The lower plate of the SS quantization capacitor is connected to the ramp signal V. RAMP The switches in the selection switch group 402 are connected one-to-one with the lower plates of the prediction capacitor group and the SAR quantization capacitor group. Specifically, the total number of capacitors in the prediction capacitor group and the SAR quantization capacitor group is the same as the number of switches in the selection switch group 402, and they are connected one-to-one. The other end of the switch in the selection switch group 402 is used to select the first reference voltage signal V. CM Second reference voltage signal V REFN Third reference voltage signal V REFP The switch control terminal of the selection switch group 402 is connected to the SAR control signal and prediction control signal output by the logic unit 60.

[0036] The prediction capacitor bank may contain one or more prediction capacitors. In this embodiment, the prediction capacitor bank contains two prediction capacitors C. R0 and C R1 The number of prediction capacitors is related to the range of the prediction signal; a larger number results in a wider range, but also increases the number of clock cycles required for the prediction process and the area of ​​the capacitor DAC array unit 40. Typically, the number of prediction capacitors can be 1-8. The size of the prediction capacitors is consistent with that of the SS quantization capacitors. The capacitor structures in the SS quantization capacitors, prediction capacitor group, and SAR quantization capacitor group are identical, all using unit capacitors.

[0037] The number of unit capacitors is related to the segmented structure of the SAR-SS hybrid ADC. In some embodiments, the 12-bit precision SAR-SS hybrid ADC with prediction and edge extraction functions employs a segmented structure of two prediction capacitors, 6-bit SAR quantization, and 6-bit SS quantization, i.e., the capacitor C with the highest weight in the SAR quantization capacitor group. M-1 The weight is 2 M-1 =2 5 M=6. The total number of unit capacitors is 2+2. 6 =66, far less than the 2 required by traditional SAR ADCs. 12 =4096 unit capacitors, greatly reducing the area of ​​the capacitor DAC array unit 40. If the capacitor DAC array unit 40 adopts V CM The -based structure can further reduce the number of unit capacitors; the number of unit capacitors required for 6-bit SAR quantization is only 2+2. 5 =34.

[0038] In some embodiments, the magnitudes of the second reference voltage signal and the third reference voltage signal are symmetrical relative to the first reference voltage signal.

[0039] The prediction control signal is used to control the voltage of the lower plate of the prediction capacitor. The prediction control signal is also used to ensure that the signal at the inverting input of the dynamic comparator 50 is greater than or less than the signal at the non-inverting input when SAR quantization ends. If the signal at the inverting input of the dynamic comparator is greater than the signal at the non-inverting input, the ramp generator 10 outputs a descending ramp signal. If the signal at the inverting input of the dynamic comparator is less than the signal at the non-inverting input, the ramp generator outputs a ascending ramp signal.

[0040] The dynamic comparator 50 includes a static pre-amplification module and a dynamic latch module. The static pre-amplification module is used to amplify the signal at the input terminal of the dynamic comparator 50, and the dynamic latch module is used to output the comparison result and provide drive.

[0041] The logic unit 60 includes a SAR-SS logic circuit 601 and an arithmetic logic circuit 602. The SAR-SS logic circuit 601 outputs prediction control signals and SAR control signals, and outputs the digital code values ​​during SAR and SS quantization. The arithmetic logic circuit 602 generates pixel-level edge information. Pixel-level edge information includes row edge information obtained from the prediction result and column edge information obtained from the SAR quantization code values ​​of adjacent columns. If the prediction fails, it indicates that the code values ​​of adjacent rows exceed a preset threshold range, and is judged as a row edge. The corresponding row edge information output by the arithmetic logic circuit 602 is logic high, otherwise logic low. If the SAR quantization code values ​​of adjacent columns are not completely consistent, it also indicates that they exceed the preset threshold range, and is judged as a column edge. The corresponding column edge information output by the arithmetic logic circuit 602 is logic high, otherwise logic low.

[0042] In some embodiments, the number of operating main modules is multiple, and the ramp generator 10 outputs a single rising ramp signal or falling ramp signal to multiple operating main modules. To reduce the impact of non-ideal factors such as noise, reference level mismatch, and offset on the switching between SAR quantization and SS quantization, multiple steps are added to both ends of the rising ramp signal or falling ramp signal. In some embodiments, the number of added steps can be 1-32. This design ensures that the hybrid analog-to-digital converter maintains V during the SS quantization stage. DAC Signal and V INP The existence of intersections in the signals ensures the robustness of the quantization process.

[0043] like Figure 2The figure shows the transient simulation results of a low-power hybrid analog-to-digital converter with prediction and edge extraction functions, employing a segmented structure with two prediction capacitors, 6-bit SAR quantization and 6-bit SS quantization, and using a rising ramp signal for SS quantization. During the sampling phase, the first switch 20 is used to sample the input signal V. IN Sampling is performed, and the value is maintained at V after sampling. INP Subsequently, based on the non-inverting input signal V of the dynamic comparator 50... INP With the inverting input signal V DAC Predict the size of V. INP Less than V DAC Then V DAC Switch downwards twice, or upwards twice. INP With V DAC The presence of an intersection point indicates a successful prediction, while the absence of an intersection point indicates a failed prediction. Based on the characteristic that adjacent pixel code values ​​are typically close in the shooting scene, the prediction mechanism of this invention has a high success rate. When a prediction is successful, SAR quantization is skipped to save power; when a prediction fails, full SAR-SS quantization is performed. The additional overhead introduced is far less than the power saved by a successful prediction, thereby significantly reducing the overall energy consumption of the system.

[0044] In summary, this invention significantly reduces analog-to-digital conversion power consumption while achieving pixel-level edge extraction by introducing a prediction mechanism into the SAR-SS hybrid quantization architecture. This structure skips the SAR quantization stage directly upon successful prediction, retaining only the necessary SS quantization operations. This substantially reduces dynamic power consumption during analog-to-digital conversion, solving the problem of excessive power consumption in traditional full-readout modes and facilitating the application of image sensors in low-power scenarios. Simultaneously, this structure utilizes the prediction results and the SAR quantization results of adjacent column analog-to-digital converters to simultaneously complete on-chip extraction of pixel-level edge information during quantization, eliminating the need to wait for complete image generation. This reduces the computational overhead of backend data handling and feature extraction, solving the problems of high processing latency and redundant computation in traditional architectures, and contributing to the realization of high-efficiency perception front-ends for machine vision.

[0045] The above description discloses only one preferred embodiment of the present invention, and should not be construed as limiting the scope of the present invention. Those skilled in the art will understand that all or part of the processes of the above embodiments can be implemented, and equivalent changes made in accordance with the claims of the present invention are still within the scope of the invention.

Claims

1. A low-power hybrid analog-to-digital converter with prediction and edge detection functions, characterized in that, include: Incline generator and main operating module; The main operating module includes: a first switch, a capacitor array unit, a dynamic comparator, and a logic unit; The first switch is used to sample the input signal; The dynamic comparator is used to compare the signal output by the capacitor DAC array unit with the sampled input signal, and latch the comparison result and output it. The logic unit is used to generate a feedback signal based on the output signal of the dynamic comparator and output the final data signal. The capacitor array unit is used to output a prediction signal and an SS signal and / or a SAR signal to the inverting input of the dynamic comparator based on the feedback signal. The ramp generator is used to output a ramp signal to adjust the magnitude of the SS signal; The non-inverting input of the dynamic comparator is connected to the first switch; the inverting input of the dynamic comparator is connected to the first reference voltage signal and the capacitor DAC array unit; the inverting input of the dynamic comparator initially receives a prediction signal and performs a prediction process; when the prediction is successful, the inverting input of the dynamic comparator receives the SS signal and performs SS quantization; when the prediction fails, the inverting input of the dynamic comparator sequentially receives the first reference voltage signal, the SAR signal, and the SS signal, and sequentially performs SAR quantization and SS quantization. The capacitor DAC array unit includes a capacitor array and a selection switch group; the feedback signal includes a prediction control signal and a SAR control signal. The capacitor array includes an SS quantization capacitor, a prediction capacitor group, and a SAR quantization capacitor group. The upper plates of the SS quantization capacitor, the prediction capacitor group, and the SAR quantization capacitor group are all connected to the inverting input of the dynamic comparator. The lower plate of the SS quantization capacitor is connected to the ramp signal. The switches in the selection switch group are connected one-to-one with the lower plates of the prediction capacitor group and the SAR quantization capacitor group. The other end of the switch in the selection switch group is used to select the first reference voltage signal, the second reference voltage signal, and the third reference voltage signal. The switch control terminal of the selection switch group is connected to the SAR control signal and the prediction control signal output by the logic unit.

2. The low-power hybrid analog-to-digital converter with prediction and edge extraction functions according to claim 1, characterized in that, The prediction capacitor group includes at least one prediction capacitor; the SS quantization capacitor has the same structure as the capacitors in the prediction capacitor group and the capacitors in the SAR quantization capacitor group.

3. The low-power hybrid analog-to-digital converter with prediction and edge extraction functions according to claim 1, characterized in that, The magnitudes of the second and third reference voltage signals are symmetrical relative to the first reference voltage signal.

4. The low-power hybrid analog-to-digital converter with prediction and edge extraction functions according to claim 1, characterized in that, The predictive control signal is used to control the voltage of the lower plate of the capacitor in the predictive capacitor bank.

5. The low-power hybrid analog-to-digital converter with prediction and edge extraction functions according to claim 1, characterized in that, The SAR control signal is used to control the voltage of the lower plate of the SAR quantization capacitor bank.

6. The low-power hybrid analog-to-digital converter with prediction and edge extraction functions according to claim 1, characterized in that, The main operating module further includes: a second switch; the second switch is used to sample the first reference voltage signal; the second switch is connected to the inverting input terminal of the dynamic comparator.

7. The low-power hybrid analog-to-digital converter with prediction and edge extraction functions according to claim 1, characterized in that, The logic unit includes a SAR-SS logic circuit and an arithmetic logic circuit; the SAR-SS logic circuit is used to output a prediction control signal and a SAR control signal, and to output digital code values ​​during SAR and SS quantization; the arithmetic logic circuit is used to generate pixel-level edge information; the digital code values ​​during SAR and SS quantization and the pixel-level edge information constitute the final data signal.

8. The low-power hybrid analog-to-digital converter with prediction and edge extraction functions according to claim 1, characterized in that, The number of operating main modules is multiple; the ramp generator outputs a single ascending ramp signal or descending ramp signal to multiple operating main modules.

9. The low-power hybrid analog-to-digital converter with prediction and edge extraction functions according to claim 8, characterized in that, Both ends of the ascending ramp signal or descending ramp signal are equipped with multiple steps.

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