Dram module and method of manufacturing same, manufacturing apparatus

Abstract

This invention discloses a DIMM module and its manufacturing method and equipment, relating to the field of DIMM modules. The manufacturing method of the DIMM module includes: obtaining the weight of command type in a predetermined application scenario based on usage frequency; obtaining temperature zone data and operating current data of memory chips; determining the temperature zone distribution weight of different temperature zones based on the temperature zone data; determining the sample number corresponding to each temperature zone based on the temperature zone distribution weight and the number of memory chips; traversing the temperature zones in ascending order of temperature based on the sorted memory chips and the sample number corresponding to each temperature zone; selecting the memory chip with the same sample number as the currently traversed temperature zone and the highest weighted total current from the unselected memory chips; and obtaining the memory chip installation decision result. This invention is beneficial for improving the working stability and system reliability of the entire memory module.

Description

Technical Field

[0001] This invention relates to the technical field of DIMM modules, and more particularly to DIMM modules and their manufacturing methods and equipment. Background Technology

[0002] Currently, the industry generally treats DRAM chips as ideal, uniform components, failing to consider the coupling effect between individual performance differences and internal heat distribution during mounting. This leads to the possibility that lower-performing, temperature-sensitive DRAM chips may be randomly placed in high-heat-load areas near the PMIC, becoming potential sources of early module failure. Related technologies simply divide temperature zones into high-temperature and low-temperature zones and use power consumption and / or data retention capabilities for screening and decision-making; therefore, DIMM modules still face the risk of failure. Summary of the Invention

[0003] The main objective of this invention is to provide a DIMM module and its manufacturing method and equipment, which aims to improve the working stability and system reliability of the entire memory module and ensure the reliable operation of the DIMM module.

[0004] To achieve the above objectives, the present invention proposes a method for manufacturing a DIMM module, the method comprising: Run a predetermined application to enter a predetermined application scenario. In the predetermined application scenario, obtain a sequence of commands sent to memory granules, sample the command sequence, obtain the usage frequency of different command types in the command sequence, and obtain the weight of the command type in the predetermined application scenario based on the usage frequency. The predetermined application scenario includes a read-heavy, write-light application scenario and a write-heavy, read-light application scenario. Obtain temperature zone data and operating current data of memory chips; Based on the weight and the current value corresponding to the command type in the operating current data, the weighted total current of the memory chip in the predetermined application scenario is obtained, and the memory chips are sorted based on the weighted total current. Based on the temperature zone data, determine the temperature zone distribution weights for different temperature zones, and determine the sample size corresponding to each temperature zone based on the temperature zone distribution weights and the number of memory chips. Based on the sorted memory chips and the number of samples corresponding to the temperature zones, the temperature zones are traversed in order from low to high. Among the unfiltered memory chips, the memory chip with the same number of samples as the currently traversed temperature zone and the highest weighted total current is selected. The selected memory chip is assigned to the installation area corresponding to the currently traversed temperature zone to obtain the installation decision result of the memory chip. Prepare the PCB board, and based on the installation decision, mount the memory chips to the corresponding areas on the PCB board.

[0005] In one embodiment, the temperature average distribution rule includes: Based on the operating current data, multiple memory chips are sequentially installed into their corresponding regions.

[0006] In one embodiment, the method for manufacturing the DIMM module further includes: The memory chip weights of the lowest heat load zone are determined based on the temperature zone data, and the number of samples in the lowest heat load zone is calculated based on the memory chip weights. Based on the average temperature distribution rule, memory chips with high total power consumption, equal to the number of samples mentioned above, are selected from the remaining unselected memory chip samples. After the screening is completed, the temperature zone level is increased, and the screening continues in the next temperature zone level until the installation location decision of the memory chips in all temperature zones is completed, and the corresponding installation decision results are output.

[0007] In one embodiment, obtaining the usage frequency of different command types in the command sequence includes: Divide the sampling time period of the logic analyzer into multiple consecutive sampling windows; Count the frequency of window usage for the command type within different sampling windows; The average frequency of window usage of the command type within multiple sampling windows is obtained, and the average value is used as the actual frequency of use of the command type in the predetermined application scenario.

[0008] In one embodiment, the current value corresponding to the command type in the operating current data is determined in the following way: For each command type, the current sampling values ​​of the memory chip are collected multiple times under the command type using an ADC acquisition device based on the operating current test device. The average current sampled values ​​from the multiple operations are averaged to obtain the average operating current of the memory chip under the command type. The average operating current under the command type is normalized so that the normalized average operating current of each command type is determined as the current value corresponding to the command type in the operating current data.

[0009] In one embodiment, before sequentially traversing the temperature zones in ascending order of temperature, the method further includes: The weighted total current of the memory chip is compared with a preset current threshold. Memory chips with a weighted total current greater than or equal to the current threshold are marked as high-power category, and memory chips with a weighted total current less than the current threshold are marked as low-power category. In the step of traversing the temperature range and selecting the memory chip with the highest weighted total current from the remaining unscreened memory chips that has the same number of samples as the current traversed temperature range, memory chips belonging to the high power consumption category are preferentially selected.

[0010] In one embodiment, acquiring the temperature zone data of the memory chip specifically includes: During the operation of the predetermined application scenario, temperature data of the memory chip is collected at preset time intervals to obtain temperature time-series data; The temperature time series data is divided into multiple temperature windows according to the temperature change stages; Calculate the average temperature within each of the temperature windows; The temperature zone data of the memory chip is determined based on the temperature range of the average temperature of the window within the temperature window.

[0011] In one embodiment, the step of obtaining the commands sent to the memory granules and calculating the weights of the commands specifically includes: In one embodiment, a mode register is integrated within the memory chip, and the step of acquiring the temperature zone data of the memory chip specifically includes: Send a mode register read command to the memory chip to obtain the actual value of the mode register returned by the memory chip, and obtain the temperature zone data of the memory chip; And / or, read the temperature zone data of the memory chip through a contact temperature sensor; And / or, read the temperature data of the memory chips using a thermal imager.

[0012] In one embodiment, the step of obtaining the operating current data of the memory chip specifically includes: For each type of command sent to the memory chip, the total current of the memory chip's core logic and memory array during operation, the current consumed by the memory chip's output driver during state switching or in a terminated state, and the current consumed by the memory chip's word line boost circuit are collected to obtain the memory chip's operating current data.

[0013] In one embodiment, the PCB board has a first side surface and a second side surface disposed opposite to each other; the step of preparing the PCB board specifically includes: Circuit routing is performed on the first side surface of the PCB board to create a central region on the PCB board and a memory mounting area extending outward from the central region. A heat dissipation layer is provided on the second side surface at a position corresponding to the central region.

[0014] In one embodiment, the circuit wiring layer thickness in the central region of the PCB board is greater than the circuit wiring layer thickness in the memory mounting region.

[0015] The present invention also proposes a manufacturing apparatus for a DIMM module, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the manufacturing method of the DIMM module as described above.

[0016] The present invention also proposes a DIMM module, which is manufactured using the DIMM module manufacturing method described above; the DIMM module includes: A PCB board having a first side surface and a second side surface disposed opposite to each other, circuit wiring being formed on the first side surface of the PCB board, the circuit wiring forming a central region on the PCB board and a memory mounting area extending outward from the central region; A power management chip and a register clock driver are disposed in the central region; and, Multiple memory chips are mounted onto corresponding areas of the PCB board according to the mounting decision results obtained from the manufacturing method of the DIMM module as described above.

[0017] This invention initiates specific application scenarios, uses a DRAM command capture device to capture DRAM commands, and calculates the weight of each DRAM command. Each scenario may have different command weights. By obtaining the DRAM command weights for specific application scenarios, these weights are used as reference indicators for memory module placement decisions when producing memory modules for a particular scenario. This allows for the selection of more suitable DRAM chips and better allocation of DRAM chips with different performance characteristics. Initiating specific application scenarios also collects temperature data of the DRAM chips to determine their temperature distribution. This helps avoid high-current-consuming DRAM chips from high-heat-load areas, preventing the heat from the power management chip or RCD from being conducted into the DRAM chip itself, thus avoiding instability caused by the combined heat from the DRAM chip and its own heat. Finally, a working current measuring device measures the working current data of the DRAM chip under test. This data, obtained according to DRAM current testing standards, reflects the normal current consumption of the DRAM chip. Combined with the DRAM command weights for specific application scenarios, the total current consumption of the DRAM chip in a specific scenario can be predicted, providing direct data for DRAM chip placement decisions. The aforementioned DRAM command weights, DRAM chip temperature data, and DRAM chip operating current data serve as input conditions for the selection decision-maker. Combined with temperature average distribution rules, this determines the installation location of the memory chips and outputs the corresponding installation decision results. Then, based on these results, the memory chips are mounted onto the PCB board, thus providing favorable conditions for the long-term operation of the DRAM chips. This invention suppresses the weakest link from the design stage, contributing to a systematic improvement in the reliability of memory modules. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic flowchart of an embodiment of the manufacturing method of the DIMM module of the present invention; Figure 2 This is a schematic flowchart illustrating another embodiment of the manufacturing method of the DIMM module of the present invention; Figure 3This is a detailed flowchart illustrating an embodiment of step S100 in Figure 1; Figure 4 This is a detailed flowchart illustrating an embodiment of step S200 in Figure 1; Figure 5 This is a detailed flowchart illustrating an embodiment of step S600 in Figure 1; Figure 6 This is a detailed flowchart illustrating another embodiment of step S200 in Figure 1; Figure 7 This is a schematic diagram of the hardware structure involved in the manufacturing method of the DIMM module of the present invention; Figure 8 This is a schematic diagram of the signal flow for obtaining DRAM command weights in the manufacturing method of the DIMM module of the present invention; Figure 9 This is a schematic diagram of the signal flow in the manufacturing method of the DIMM module of the present invention, which obtains temperature zone data by reading the actual value of the mode register. Figure 10 This is a schematic diagram of the signal flow in the manufacturing method of the DIMM module of the present invention, which acquires temperature zone data by means of a contact temperature sensor. Figure 11 This is a schematic diagram of the signal flow path in the manufacturing method of the DIMM module of the present invention, which acquires temperature zone data by means of a thermal imager. Figure 12 This is a schematic diagram of the circuit structure of the working current testing device in the hardware structure involved in the DIMM module method of the present invention. Figure 13 This is a schematic diagram of the DRAM temperature distribution of the DIMM module of the present invention under a preset application scenario; Figure 14 A schematic diagram of the structure of a DIMM module mounted according to the installation decision results obtained by the manufacturing method of the DIMM module according to the present invention; Figure 15 This is a schematic diagram of the hardware operating environment involved in the manufacturing method of the DIMM module in this embodiment of the invention.

[0021] The objectives, functional characteristics, and optimal time periods of this invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0022] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of the present invention and are not intended to limit the present invention.

[0023] To better understand the technical solution of the present invention, a detailed description will be provided below in conjunction with the accompanying drawings and specific embodiments.

[0024] A DIMM (Dual In-line Memory Module) consists of a PCB (Printed Circuit Board), memory chips mounted on the PCB, and a power management chip mounted on the PCB to supply power to the memory chips. The DIMM module may also include a register clock driver, which communicates with an external memory controller. The register clock driver outputs corresponding control signals based on access commands from the external memory controller. Each memory module can have a different number of memory chips, which can be DRAM (Dynamic Random Access Memory) chips. DRAM chips are the core component of the DIMM module. With the continuous miniaturization of manufacturing processes and the continuous increase in storage density, DIMM modules face increasingly severe reliability challenges, mainly manifested in the following issues: Individual performance differences in DRAM chips: Due to inherent process fluctuations in semiconductor manufacturing (such as non-uniformity in photolithography, etching, and doping), even DRAM chips from the same wafer and batch can exhibit significant differences in key performance parameters such as power consumption, access speed, temperature sensitivity, and refresh rate. This inconsistency is amplified under harsh operating conditions such as high load and high temperature, causing some chips to become the "weakest link" in the entire module and affecting system stability.

[0025] Uneven thermal environment within DIMM modules: The power management chip supplying power to the DRAM chips is one of the main heat sources in DIMM modules. DRAM chips located near the power management chip have significantly higher operating temperatures than those further away. Excessive temperatures accelerate the degradation of transistor performance within the DRAM, increase leakage current, reduce data retention time, and may induce bit errors, seriously threatening data integrity.

[0026] Currently, the industry generally treats DRAM chips as ideal, uniform components, failing to consider the coupling effect between their individual performance differences and the heat distribution within the module during mounting. This leads to the possibility that lower-performing, temperature-sensitive DRAM chips may be randomly placed near the high-heat-load area of ​​the PMIC, thus becoming potential sources of early module failure. Related technologies simply divide the temperature zone into high-heat-load and low-heat-load areas based on the heat generated by the PMIC and RCD, lacking consideration for specific application scenarios. They fail to account for the impact of matching DRAM command weights with actual DRAM command current consumption in specific application scenarios, and do not further consider the influence of temperature distribution in specific application scenarios on the DRAM chip's position within the module.

[0027] To solve the above problems, refer to Figure 15 This invention proposes a method for manufacturing a DIMM module. The hardware structure for executing the DIMM module manufacturing method may include, but is not limited to: The system includes a processor, memory controller, logic analyzer, DRAM temperature sensor, operating current measuring device, and pick-and-place machine. The processor runs a predetermined application program to bring the device into a predetermined application scenario. Within this scenario, the processor continuously operates the memory controller to obtain the data needed for decision-making. A filtering decision-maker is integrated into the processor. (See reference...) Figure 1 , Figure 7 and Figure 8 In one embodiment of the present invention, the manufacturing method of the DIMM module includes: Step S100: Run a predetermined application to enter a predetermined application scenario. In the predetermined application scenario, obtain a sequence of commands sent to the memory granules, sample the command sequence, obtain the usage frequency of different command types in the command sequence, and obtain the weight of the command type in the predetermined application scenario based on the usage frequency. The predetermined application scenario includes a read-heavy, write-light application scenario and a write-heavy, read-light application scenario. Step S200: Obtain the temperature range data and operating current data of the memory chip; Step S300: Based on the weight and the current value corresponding to the command type in the working current data, obtain the weighted total current of the memory chip in the predetermined application scenario, and sort the memory chips based on the weighted total current; Step S400: Determine the temperature distribution weight of different temperature zones based on the temperature zone data, and determine the number of samples corresponding to each temperature zone based on the temperature distribution weight and the number of memory chips; Step S500: Based on the sorted memory chips and the number of samples corresponding to the temperature zones, the temperature zones are traversed in order from low to high. Among the unscreened memory chips, the memory chip with the same number of samples as the currently traversed temperature zone and the highest weighted total current is selected. The selected memory chip is assigned to the installation area corresponding to the currently traversed temperature zone to obtain the installation decision result of the memory chip. Step S600: Prepare the PCB board and, based on the installation decision result, mount the memory chips to the corresponding areas of the PCB board.

[0028] The intended application scenarios can be read-heavy and write-light scenarios, such as large model training, which requires data-intensive computation and is a read-dominant, write-secondary scenario. Its memory access pattern can be seen as a coexistence of heavy reads and strategic writes. Large model training typically requires repeatedly reading massive amounts of data for training. Since training is an iterative process, the entire training dataset needs to be read repeatedly.

[0029] The intended application scenario can also be a write-heavy, read-light scenario, such as the operation of a high-frequency trading system. This system processes massive, continuous streams of market tick data. This data contains precise timestamps and needs to be recorded rapidly. The system needs to handle 50,000 to 100,000 writes per second, or even higher. The core characteristics of this data are extremely high write frequency and it is usually immutable. High-frequency trading systems primarily write time-series data, including the latest transaction price, volume, and order book for each stock, as well as the complete lifecycle record of each order, including creation, modification, execution, and cancellation.

[0030] In this embodiment, considering the current lack of specific scenario-based DRAM chip selection, placing low-performance DRAM chips in high-temperature module locations could lead to decreased DRAM chip stability. Furthermore, different application scenarios have varying weight requirements for different command types. Scenarios with high command type weights should use DRAM chips with low command type current consumption. For example, in a certain application scenario with high write command weight requirements, a DRAM chip with low write command current consumption should be selected, not one with high write command current consumption. Matching a scenario with high write command weight requirements with a DRAM chip with high write command current consumption will accelerate DRAM chip wear, and prolonged high current consumption can easily damage the DRAM chip. Therefore, this embodiment can activate specific application scenarios and use a DRAM chip logic analyzer as a command capturer to capture DRAM commands, calculate the weight of DRAM chip commands, and incorporate the weight of DRAM chip commands into the memory chip installation location decision.

[0031] The specific steps for calculating the weight of the commands include: The command sequence sent to the memory chips is obtained, and the command truth table is consulted to calculate the weight of each command. Optionally, during application scenarios, the processor continuously operates the memory controller according to the application. A logic analyzer is connected between the memory controller and the memory module to obtain the command sequence of the memory controller through signal sampling. The command sequence is combined with the DRAM command truth table to calculate the weight of each command type. When the DIMM module is normally reading and writing data, there are 5 command types that are always active and have a large proportion: Active, Pre Charge, Write, Read, and Refresh. Therefore, calculating the weight of Active, Pre Charge, Write, Read, and Refresh is one of the criteria for chip selection. Specifically, the command type weight can be calculated by connecting a logic analyzer between the memory controller and the memory module or memory chip, capturing commands under specific application scenarios through the logic analyzer, and finally obtaining the command type and command weight, as shown in Table 1.

[0032] Table 1

[0033] Furthermore, a logic analyzer samples the command channel between the memory controller and the memory chips. The analyzer then parses the sampled signals, classifying and statistically analyzing each command type according to its occurrence within the sampling period to determine the usage frequency of each command type. Based on the proportion of each command type's usage frequency to the total number of commands, the weight of each command type in a predetermined application scenario is determined. For example, if 1000 commands are collected in a predetermined application scenario, and the Read command appears 400 times, then the usage frequency of the Read command is 400, and its weight is 400 / 1000 = 40%. Since the weight is based on the usage frequency statistically derived from the actual command data collected in the predetermined application scenario, it accurately reflects the memory access characteristics of that application scenario.

[0034] Among them, reference Figure 3 The step of obtaining the usage frequency of different command types in the command sequence specifically includes: Step S110: Divide the sampling time period of the logic analyzer into multiple consecutive sampling windows; Step S120: Count the frequency of window usage of the command type within different sampling windows; Step S130: Obtain the average frequency of window usage of the command type in multiple sampling windows, and use the average value as the actual frequency of use of the command type in the predetermined application scenario.

[0035] Understandably, to improve the stability of command weight statistics and avoid the impact of abnormal command distribution in a certain period on the overall weight, the sampling time period of the logic analyzer is divided into multiple consecutive sampling windows. For example, if the total runtime of the predetermined application scenario is T, the sampling time period is divided into N equal sampling windows, each with a duration of T / N. The window usage frequency of each command type within each sampling window is counted, i.e., the number of times each command type appears in each sampling window. Then, for each command type, the arithmetic mean of its window usage frequency across all N sampling windows is calculated. This arithmetic mean is taken as the usage frequency of that command type in the predetermined application scenario, thereby determining the weight of that command type. By using window-based statistics and then taking the average, the temporal fluctuations in command distribution can be effectively smoothed, improving the reliability of the weight data.

[0036] During the application scenario, the processor periodically acquires the temperature data of the DRAM chips to determine the temperature distribution of the DRAM chips in the physical space of the memory module. Methods for acquiring the DRAM chip temperature can include, but are not limited to: (1) obtaining the DRAM chip temperature by reading the actual value in the MR4 (Mode Register 4) register; (2) reading the DRAM chip temperature using a thermal imager; and (3) reading the DRAM chip temperature using a contact temperature sensor. After the application scenario has been running for a period of time, the temperature of each DRAM chip will fluctuate around a certain threshold. The temperature distribution corresponding to the DRAM chip positions in the memory module is recorded, ultimately obtaining the distribution of the DRAM chip positions in the memory module.

[0037] Among them, reference Figure 6 The acquisition of temperature zone data for memory chips specifically includes: Step S221: During the operation of the predetermined application scenario, the temperature data of the memory chip is collected at preset time intervals to obtain temperature time-series data; Step S222: Divide the temperature time series data into multiple temperature windows according to the temperature change stages; Step S223: Calculate the average window temperature within the temperature window, and determine the temperature zone data of the memory chip based on the temperature range of the average window temperature within the temperature window.

[0038] In this embodiment, to more accurately reflect the temperature characteristics of memory chips in actual working scenarios, time-domain window analysis is performed on the temperature zone data. During the operation of the predetermined application scenario, the processor periodically collects temperature data from each memory chip at preset time intervals, recording the temperature values ​​of each memory chip at different times to form temperature time-series data. The temperature time-series data is divided into multiple temperature windows according to the temperature change stages, including an early response window, a mid-term response window, and a stable response window, corresponding to the rapid temperature rise stage, the temperature stabilization stage, and the temperature fluctuation stage near the steady-state threshold, respectively. The average temperature within each temperature window is calculated, that is, the arithmetic mean of all temperature data collected within that temperature window is calculated. Based on the temperature range of the average temperature within the stable response window, the temperature zone data of each memory chip is determined. For example, if the average temperature of a memory chip within the stable response window is 82°C, then the memory chip belongs to the 80-85°C temperature zone. By sampling at multiple time periods and performing window-based analysis, the random errors of single sampling are avoided, making the temperature zone data more reflective of the true temperature level of the memory chips in actual working scenarios.

[0039] When obtaining the operating current of memory chips, an operating current testing device can be used. Specifically, the DRAM chip under test is mounted on the device, and then a Per-Device IDD test is performed to collect the current value of each DRAM chip under commands such as Active, Pre-Charge, Write, Read, and Refresh. The operating current testing device can collect the current consumed by the DRAM through three channels: IDD, IDDQ, and IPP, using an ADC acquisition unit. Each command type used in the test yields the corresponding current sample value. By performing Per-Device IDD tests on all the DRAM chips under test, the operating current of each DRAM chip under Active, Pre-Charge, Write, Read, and Refresh commands can be obtained, thus acquiring the operating current data of the memory chip.

[0040] In this embodiment, when a specific application scenario is initiated, a DRAM command capture device is used to capture DRAM commands and calculate their weights; a DRAM temperature zone collector is used to collect temperature zone data of the DRAM chip; and a working current measuring device is used to measure the working current data of the DRAM chip under test. The weights of the DRAM commands, the temperature zone data of the DRAM chip, and the working current data of the DRAM chip are used as input conditions for a screening decision-maker. Combined with a temperature average distribution rule, the module placement decision for the specific application scenario is completed. Specifically, the temperature average distribution rule involves sequentially installing multiple memory chips into corresponding areas based on the working current data. That is, DRAM chips with high total current consumption are placed in the low heat load area, and DRAM chips with low total current consumption are placed in the high heat load area. This decision result can be output to a placement machine, which then places each DRAM chip into its corresponding position based on the decision result.

[0041] Furthermore, referring to Figure 5 Before screening memory chips by sequentially traversing each temperature zone from low to high, a threshold classification is performed on the weighted total current of each memory chip: Step S610: Compare the weighted total current of the memory chip with a preset current threshold. Step S620: Mark memory chips with a weighted total current greater than or equal to the current threshold as high-power category, and mark memory chips with a weighted total current less than the current threshold as low-power category; Step S630: In the step of traversing the temperature range and selecting the memory chip with the highest weighted total current from the remaining unscreened memory chips that has the same number of samples as the current traversed temperature range, memory chips belonging to the high power consumption category are selected first.

[0042] In this embodiment, a preset current threshold I_th is set. The current threshold I_th can be determined based on the statistical distribution of the weighted total current of all memory chips under test, such as the median or average of the weighted total current. The weighted total current I_weight of each memory chip is compared with the current threshold I_th one by one: if the weighted total current I_weight of a memory chip is greater than or equal to the current threshold I_th, the memory chip is marked as a high-power category; if the weighted total current I_weight of a memory chip is less than the current threshold I_th, the memory chip is marked as a low-power category. When subsequently traversing each temperature zone in ascending order for screening, if it is necessary to select memory chips from the remaining unscreened memory chips with a sample size equal to that of the currently traversed temperature zone, memory chips belonging to the high-power category are prioritized. Through threshold classification, memory chips are divided into high-power and low-power categories, providing a priority basis for temperature zone traversal screening and ensuring that memory chips with higher power consumption are preferentially allocated to installation areas with lower temperatures.

[0043] In this embodiment, the PCB board has a first side surface and a second side surface arranged opposite to each other. Circuit wiring can be performed on the first side surface of the PCB board to generate a central region and a memory mounting area extending outwards from the central region. The central region of the PCB board can be used to mount a power management chip and a register clock driver, along with their peripheral circuitry. Since the power management chip and register clock driver are power-consuming devices, they generate a significant amount of heat. After the power management chip and register clock driver are mounted in the central region, a heat dissipation structure can be provided on the side of the power management chip and register clock driver away from the PCB board. This heat dissipation structure can be thermal grease with a graphene heat dissipation pad, etc. After mounting the power management chip and register clock driver in the central region, high-performance thermal grease can be applied to the power management chip and register clock driver, and a graphene heat dissipation pad can be pressed onto them. By attaching heat dissipation structures to the surfaces of the power management chip and the register clock driver, heat can be radiated into the air through the heat dissipation structures. This helps to radiate the heat generated during the operation of the power management chip and the register clock driver outward, increases the contact area between the heat and the air, and thus improves the heat dissipation rate of the power management chip and the register clock driver. It can also prevent heat from being conducted to the memory chips through the PCB board, thereby reducing the temperature of the hot area from the source.

[0044] To reduce the performance degradation of memory chips due to temperature fluctuations, the PCB board can be divided into different zones. For example, with the power management chip and the register clock driver as the center, the area within a first preset range from the power management chip and the register clock driver is defined as a high-heat-load zone, where memory chips with low total current consumption are soldered. The area beyond a second preset range from the power management chip and the register clock driver is defined as a low-heat-load zone, where memory chips with high total current consumption can be soldered. The first preset range is smaller than the second preset range. Furthermore, memory chips with different total current consumption are installed in different zones. For example, the power management chip and the register clock driver are installed in the central area, and the memory chips are distributed on both sides. Memory chips with low total current consumption are placed in the high-heat-load zone closer to the center, while memory chips with high total current consumption are placed in the low-heat-load zone farther from the center. Since the memory chips that consume high total current are located far from the central area where heat is concentrated, the instability caused by the heat generated by the power management chip and the register clock driver during operation and the heat of the memory chips themselves can be reduced. This can improve the working stability and system reliability of the entire memory module.

[0045] In practical applications, the number of memory chips arranged on the PCB board of a memory module is usually 8, 16, 32, or 40, etc., and they are mounted using a pick-and-place machine. The memory chips are usually mounted on both sides of the power management chip and the register clock driver. Taking a memory module PCB board with 40 memory chips as an example, the 40 memory chips are divided into two areas, with 20 memory chips in each area. One area contains the power management chip, and the other area contains the register clock driver. The 20 memory chips are located on both sides of the register clock driver, and the other 20 are located on both sides of the register clock driver. Furthermore, the 20 memory chips can be arranged side by side in pairs along the width of the memory module.

[0046] This invention initiates specific application scenarios, uses a DRAM command capture device to capture DRAM commands, and calculates the weight of each DRAM command. Each scenario may have different command weights. By obtaining the DRAM command weights for specific application scenarios, these weights are used as reference indicators for memory module placement decisions when producing memory modules for a particular scenario. This allows for the selection of more suitable DRAM chips and better allocation of DRAM chips with different performance characteristics. Initiating specific application scenarios also allows for the collection of DRAM chip temperature data to determine the temperature distribution of the DRAM chips. This helps to better avoid high-heat-load areas for DRAM chips with high current consumption, thus preventing the heat from the power management chip or RCD conducted from high-heat-load areas from accumulating with the DRAM chip's own heat and causing instability. Finally, a working current measuring device is used to measure the working current data of the DRAM chip under test. This working current data, obtained through standard testing, reflects the normal current consumption of the DRAM chip. Combined with the DRAM command weights for specific application scenarios, the total current consumption of the DRAM chip in a specific scenario can be predicted, providing direct data for DRAM chip placement decisions. The weights of the DRAM commands, the temperature data of the DRAM chip, and the operating current data of the DRAM chip are used as input conditions for the screening decision-maker. Combined with the temperature average distribution rule, the installation position of the memory chip is determined and the corresponding installation decision result is output. Then, the memory chip is mounted on the PCB board according to the installation decision result, thereby providing good conditions for the long-term operation of the DRAM chip.

[0047] Reference Figure 2 In one embodiment, the method for manufacturing the DIMM module further includes: Step S310: Determine the memory chip weight of the lowest heat load zone based on the temperature zone data, and calculate the number of samples occupied by the lowest heat load zone based on the memory chip weight. Step S320: According to the temperature average distribution rule, select memory chips with high total power consumption from the remaining unselected memory chip samples. Step S330: After the screening is completed, the temperature zone level is increased, and the screening continues in the next temperature zone level until the installation location decision of the memory chips in all temperature zones is completed, and the corresponding installation decision result is output.

[0048] In this embodiment, the DRAM chip is taken as DDR5 (Double Data Rate 5 Synchronous Dynamic Random-Access Memory). The DDR5 standard specifies two types of temperature zones: wide-temperature and non-wide-temperature. The non-wide-temperature zone has 5 temperature zones, and the wide-temperature zone has 7 temperature zones, such as... Figure 13 As shown. The difference between the two lies in the upper and lower limits. For non-wide temperature ranges, the upper limit is >95℃, and the lower limit is <80℃. This case uses a wide temperature range as an example. The screening decision-maker starts its decision from the low-temperature range (<75℃) of DRAM chips. First, it obtains the weight of DRAM chips in the low-temperature range. Then, it multiplies the total number of DRAM chip samples by the weight of DRAM chips in the low-temperature range to calculate the number of samples in the low-temperature range. Then, according to the temperature average distribution rule, it screens DRAM chips with high total power consumption from the remaining unscreened DRAM chip samples. The number of these chips is the same as the number of samples in the low-heat load range. After screening, the temperature range level is upgraded, and screening continues in the next level. For example, it transitions from the <75℃ low-temperature range to the 75-80℃ temperature range, and then screens the 75-80℃ temperature range until all temperature ranges have been traversed, finally completing the screening decision. DRAM chips that are screened into the same temperature range according to the temperature average distribution rule do not need to be screened again. In specific application scenarios, the temperature range distribution of DRAM chips can be referred to Figure 14 The temperature zone distribution weights can be found in Table 2. Based on the above "DRAM temperature zone distribution in application scenarios" and "statistics on the number of temperature zones for DRAM chips," we can obtain the actual situation of specific application scenarios, which has very high reference value for surface mount decisions. Combining Table 2 "statistics on the number of DRAM chips in temperature zones" with Table 1 "captured DRAM command weights" provides a reliable parameter basis for adapting different DRAM chips to different temperature zones.

[0049] Table 2

[0050] Reference Figure 13 Taking the example of setting 40 DRAM chips on the PCB board of each DIMM module, the 40 DRAM chips are selected by the selection decision-maker based on the command weight, the temperature range data, and the operating current data, and the installation decision result is obtained, as follows: Temperature range (<75℃): 40×17.5%=7. Therefore, select the 7 DRAM chips with the highest total current consumption from the 40 samples, namely U07, U30, U21, U29, U23, U05, and U35. Temperature range (75-80℃): 40×15%=6. Therefore, select the 6 DRAM chips with the highest total current consumption from the remaining samples, namely U08, U03, U15, U16, U37, and U01. Temperature range (80-85℃): 40×15%=6. Therefore, select the 6 DRAM chips with the highest total current consumption from the remaining samples, namely U32, U20, U39, U36, U40, and U10. Temperature range (85-90℃): 40×20%=8. Therefore, select the 8 DRAM chips with the highest total current consumption from the remaining samples, namely U25, U18, U31, U11, U17, U13, U22, and U34. Temperature range (90-95℃): 40×22.5%=9. Therefore, select the 9 DRAM chips with the highest total current consumption from the remaining samples, namely U09, U02, U33, U38, U04, U12, U27, U06, and U26. Temperature range (95-100℃): 40×10%=4. Therefore, select the 4 DRAM chips with the highest total current consumption from the remaining samples, namely U28, U14, U19, and U24. Temperature range (>100℃): 40×0=0, no corresponding DRAM chip.

[0051] In one embodiment, a mode register is integrated within the memory chip, and the step of acquiring the temperature zone data of the memory chip specifically includes: Send a mode register read command to the memory chip to obtain the actual value of the mode register returned by the memory chip, and obtain the temperature zone data of the memory chip; And / or, read the temperature zone data of the memory chip through a contact temperature sensor; And / or, read the temperature data of the memory chips using a thermal imager.

[0052] Reference Figure 9 In this embodiment, when obtaining the temperature range by reading the MR4 register of the DRAM chip, the relevant registers of the memory controller can be configured. After arbitration, the memory controller initiates an MR4 read command to the DRAM chip. The memory chip returns the actual MR4 value to the memory controller, which then returns the actual MR4 value to the processor. In this way, by performing the MR4 register read operation on all DRAM chips, the processor obtains the temperature range of multiple memory chips.

[0053] Reference Figure 10In the method of reading the temperature zone of DRAM chip through contact temperature sensor, the temperature of DRAM chip gradually rises during the operation of application scenario. The contact temperature sensor converts the physical signal into an analog signal, which is then converted into a digital signal by ADC acquisition unit. The digital signal is input to processor for processing, and the temperature zone of memory chip is obtained.

[0054] Reference Figure 11 In the method of reading the temperature zone of DRAM chips using a thermal imager, during application operation, the processor activates the thermal imager to monitor the temperature of all memory chips. The temperature data of the memory chips is transmitted to the processor via the data channel, and the processor obtains the temperature zone of the memory chips. This can be achieved using any one or a combination of three methods: MR4 reading, contact temperature sensor acquisition, and thermal imager. In this embodiment, the actual MR4 values ​​of the DRAM chips can be read to obtain the temperature zone data. Combining the actual temperature zone distribution of the specific application scenario with the performance level ranking of the DRAM chips, and selecting and mounting them according to the temperature average distribution rule helps to ensure a more uniform temperature of the storage module.

[0055] Reference Figure 12 In one embodiment, the step of obtaining the operating current data of the memory chip specifically includes: For each type of command sent to the memory chip, the total current of the memory chip's core logic and memory array during operation, the current consumed by the memory chip's output driver when switching states or in a specific termination state, and the current consumed by the memory chip's word line boost circuit are collected to obtain the memory chip's operating current data.

[0056] In this embodiment, a working current testing device can be used, which includes ADC acquisition units (ADC0, ADC1, ADC2) to collect three currents consumed by the DRAM: IDD (total current of the core logic and memory array during operation), IDDQ (current consumed by the output driver of the memory chip during state switching or in a terminated state), and IPP (current consumed by the word line boost circuit of the memory chip). Furthermore, the command types sent to the memory chip can include, but are not limited to: Active, Pre Charge, Write, Read, and Refresh. Each command type used in the test yields a corresponding current sampling value.

[0057] Specifically, the average current consumed by the memory chip under the Active command is calculated as the sum of the sampled values ​​of current values ​​IDU0, IDDQ0, and IPP0 divided by the number of samples, denoted as [missing information]. ; The average current consumed by the memory chips under the Pre Charge command is calculated as the sum of the sampled values ​​of current values ​​IDU2N, IDDQ2N, and IPP2N, divided by the number of samples. ; The average current consumed by the memory chip under the Read command is calculated as the sum of the sampled values ​​of current values ​​IDD4R, IDDQ4R, and IPP4R, divided by the number of samples. ; The average current consumed by the memory chips under the Write command is calculated as the sum of the sampled values ​​of current values ​​IDD4W, IDDQ4W, and IPP4W, divided by the number of samples. ; The average current consumed by the memory chips under the Refresh command is calculated as the sum of the sampled values ​​of current values ​​IDD5B, IDDQ5B, and IPP5B, divided by the number of samples. ; The above method can obtain the average current consumption value of different commands in DRAM. Then, the filtering decision-maker, combined with the command weight distribution in Table 1, calculates the total current consumed by the DRAM chip in this specific scenario. The formula is as follows: = + + + +

[0058] As shown in Tables 3 and 4, Table 3 shows the current values ​​collected by the sample through the operating current testing device, and includes the total current consumed by each DRAM chip calculated by the DRAM command weights for a specific application scenario. Table 4 shows the total current consumed by the DRAM chip samples. The chips are sorted in ascending order. Data from Table 2, "Statistics on the Number of DRAM Chips in Each Temperature Zone," and Table 4, "Ranking of Operating Current of DRAM Chip Samples," are used as input to the screening decision-maker. The decision-maker combines the average temperature distribution rule (DRAM chips with high total current consumption are placed in the low heat load zone, and DRAM chips with low total current consumption are placed in the high heat load zone) to screen and place the chips. The performance level of the DRAM chips is ranked by combining the command weights for specific application scenarios and the IDD, IDDQ, and IPP current values ​​of the DRAM chips after standard testing, which better meets the needs of the application scenarios.

[0059] Reference Figure 4 In one embodiment, since the operating current range may differ under different command types, the average operating current under each command type is normalized before calculating the weighted total current: Step S211: For each command type, based on the operating current testing device, the current sampling value of the memory chip is collected multiple times under the command type by the ADC acquisition unit. Step S212: Average the current sampling values ​​from the multiple operations to obtain the average operating current of the memory chip under the command type; Step S213: Normalize the average operating current under the command type, so as to determine the normalized average operating current of each command type as the current value corresponding to the command type in the operating current data.

[0060] The normalization process employs the Min-Max normalization method. For each command type, the maximum and minimum values ​​of the average operating current of all tested memory chips under that command type are determined. The average operating current of each memory chip under that command type is then linearly mapped to the [0,1] interval. The normalized current value is calculated as (average operating current - minimum value) / (maximum value - minimum value). This average operating current is the current value corresponding to each command type. This dimensional normalization process eliminates the influence of current value differences between different command types on the weighted calculation, ensuring that the weights of each command type participate fairly in the calculation of the total weighted current.

[0061] Table 3

[0062] Table 4

[0063] In one embodiment, the PCB has a first side surface and a second side surface disposed opposite to each other; the step of preparing the PCB specifically includes: Circuit routing is performed on the first side surface of the PCB to create a central region on the PCB and a memory mounting area extending outward from the central region. A heat dissipation layer is provided on the second side surface at a position corresponding to the central region.

[0064] In this embodiment, the first surface of the PCB board where the components are located is referred to as the front side, and the opposite second surface is referred to as the back side. The heat dissipation layer can be a graphene thermal pad, a vapor chamber, etc. A heat dissipation layer made of a high thermal conductivity material is added to the corresponding back area of ​​the PCB board. The heat generated by the power management chip and the register clock driver is conducted through the PCB board to the heat dissipation layer on the side of the PCB board away from the power management chip and the register clock driver. The heat can be radiated into the air through the heat dissipation layer, which is beneficial for radiating the heat generated by the power management chip and the register clock driver during operation. It increases the contact area between the heat and the air, thereby improving the heat dissipation rate of the power management chip and the register clock driver. It can also prevent heat from being conducted to the memory chips through the PCB board, thus reducing the temperature of the hot area from the source.

[0065] The central area of ​​the PCB board can be used to mount the power management chip and the register clock driver, along with their peripheral circuitry. As power-consuming devices, the power management chip and register clock driver generate significant heat. To reduce the performance degradation of memory chips due to temperature fluctuations, different areas can be designated on the PCB board. For example, the area within a first preset range centered on the power management chip and register clock driver is defined as a high-heat-load zone, where DRAM memory chips soldered are tested and certified to have low total current consumption. The area beyond a second preset range is defined as a low-heat-load zone, where memory chips with high total current consumption can be soldered. The first preset range is smaller than the second preset range. Furthermore, memory chips with different temperature zones and current distributions are installed in different areas. For instance, the power management chip and register clock driver are mounted in the central area. After mounting them in the central area, high-performance thermal grease can be applied to the power management chip and register clock driver, and a graphene heatsink can be pressed onto them. By attaching heat dissipation structures to the surfaces of the power management chip and the register clock driver, heat can be radiated into the air through the heat dissipation structures. This helps to radiate the heat generated during the operation of the power management chip and the register clock driver outward, increases the contact area between heat and air, and thus improves the heat dissipation rate of the power management chip and the register clock driver. It can also prevent heat from being conducted to the memory chips through the PCB board, thereby reducing the temperature of high heat load areas from the source.

[0066] The memory chips are positioned on both sides of the module, with the lower-current-consuming chips placed in the high-heat-load area closer to the center, and the higher-current-consuming chips placed in the low-heat-load area further away from the center. Since the higher-current-consuming chips, which generate more heat themselves, are located away from the heat-concentrated central area, the combined effect of the heat generated by the power management chip and register clock driver on these chips is reduced, thereby improving the overall stability and reliability of the memory module and the system.

[0067] In some embodiments, silver plating may also be applied to the device mounting area and the power supply traces.

[0068] In this embodiment, the silver layer, as a highly conductive metal, can reduce the resistance of the pads and power supply traces, making it easier for heat to be conducted to the heat dissipation path. By plating the pads and power supply traces of the power management chip and the register clock driver with silver, contact resistance can be reduced, thereby reducing Joule heating. Simultaneously, the uniform silver plating layer reduces wire resistance, resulting in a more even current distribution and preventing the power management chip, register clock driver, and power supply traces from overheating due to excessive current, thus improving overall heat dissipation efficiency. The bright silver surface has good infrared emissivity, which helps to radiate the heat generated by the power management chip and register clock driver into the surrounding environment in the form of electromagnetic waves.

[0069] In one embodiment, the circuit wiring layer thickness in the central region of the PCB is greater than the circuit wiring layer thickness in the memory mounting region.

[0070] In this embodiment, during the PCB manufacturing process, corresponding circuits and mounting positions (pads) for various electronic components such as memory chips, power management chips, and register clock drivers can be formed on the PCB board. The memory chips, power management chips, and register clock drivers are respectively positioned on the mounting positions of the circuit routing layer and electrically connected to the circuit routing layer through conductive materials such as solder and conductive adhesive, forming a current loop. Specifically, after copper plating is applied to the PCB board, copper foil is etched according to a preset circuit design to form the circuit routing layer. The copper foil layer applied in the central area where the power management chip and register clock driver are installed, and on the corresponding power lines, can be larger than the copper foil layer of the memory chips, for example, it can be 1, 1.5, or 2 times larger. In this way, the heat generated by the power management chip and the register clock driver is conducted to the PCB board through the copper foil layer. Because the thickness of the area containing the power management chip and register clock driver is increased, the cross-sectional area for heat conduction becomes larger. According to the law of thermal conductivity, thermal resistance decreases. Simultaneously, the increased thickness further reduces the resistance of the copper foil layer. According to the law of resistance, increased thickness leads to decreased resistance. Under the same current, the power management chip and register clock driver generate less Joule heat, thus reducing their own heat generation. Furthermore, the thicker copper foil can store and absorb more heat, resulting in a more gradual temperature rise and acting as a buffer. This reduces the thermal impact of the power management chip and register clock driver on the memory chips.

[0071] This invention also proposes a DIMM module, which is manufactured using the DIMM module manufacturing method described above; see reference. Figure 13 The DIMM module includes: A PCB board having a first side surface and a second side surface disposed opposite to each other, circuit wiring being formed on the first side surface of the PCB board, the circuit wiring forming a central region on the PCB board and a memory mounting area extending outward from the central region; A power management chip and a register clock driver are located in the central area; Multiple memory chips are mounted onto corresponding areas of the PCB board according to the mounting decision results obtained from the manufacturing method of the DIMM module as described above.

[0072] In this embodiment, circuit wiring is performed on the first side surface of the PCB board to generate a central region, a high heat load region near the central region, and a low heat load region away from the central region on the PCB board; a heat dissipation layer is provided in the central region. The first side surface of the PCB board where the components are located is called the front side, and the opposite second side surface is called the back side. The heat dissipation layer can be a graphene thermal pad, a vapor chamber, etc. A heat dissipation layer made of a high thermal conductivity material is added to the corresponding back area of ​​the PCB board. The heat generated by the power management chip and the register clock driver is conducted through the PCB board to the heat dissipation layer on the side of the PCB board away from the power management chip and the register clock driver. The heat can be radiated into the air through the heat dissipation layer, which is beneficial for radiating the heat generated during the operation of the power management chip and the register clock driver outward, increasing the contact area between heat and air, thereby improving the heat dissipation rate of the power management chip and the register clock driver, and preventing heat from being conducted to the memory chips through the PCB board, thus reducing the temperature of the hot area at the source.

[0073] In some embodiments, the thickness of the circuit wiring layer in the central region of the PCB board is greater than the thickness of the circuit wiring layer in the high heat load region and the low heat load region.

[0074] In this embodiment, during the PCB manufacturing process, corresponding circuits and mounting positions (pads) for various electronic components such as memory chips, power management chips, and register clock drivers can be formed on the PCB board. The memory chips, power management chips, and register clock drivers are respectively positioned on the mounting positions of the circuit routing layer and electrically connected to the circuit routing layer through conductive materials such as solder and conductive adhesive, forming a current loop. Specifically, after copper plating is applied to the PCB board, copper foil is etched according to a preset circuit design to form the circuit routing layer. The copper foil layer applied in the central area where the power management chip and register clock driver are installed, and on the corresponding power lines, can be larger than the copper foil layer of the memory chips, for example, it can be 1, 1.5, or 2 times larger. In this way, the heat generated by the power management chip and the register clock driver is conducted to the PCB board through the copper foil layer. Because the thickness of the area containing the power management chip and register clock driver is increased, the cross-sectional area for heat conduction becomes larger. According to the law of thermal conductivity, thermal resistance decreases. Simultaneously, the increased thickness further reduces the resistance of the copper foil layer. According to the law of resistance, increased thickness leads to decreased resistance. Under the same current, the power management chip and register clock driver generate less Joule heat, thus reducing their own heat generation. Furthermore, the thicker copper foil can store and absorb more heat, resulting in a more gradual temperature rise and acting as a buffer. This reduces the thermal impact of the power management chip and register clock driver on the memory chips.

[0075] In some embodiments, a heat dissipation structure is provided on the side of the power management chip and the register clock driver away from the PCB board.

[0076] In this embodiment, the heat dissipation structure can be thermally conductive silicone grease with a graphene heat dissipation pad attached, etc. After the power management chip and the register clock driver are mounted to the central area, high-performance thermally conductive silicone grease can be applied to the power management chip and the register clock driver, and a graphene heat dissipation pad can be attached. Attaching a heat dissipation structure to the surface of the power management chip and the register clock driver allows heat to be radiated into the air, which is beneficial for radiating the heat generated during the operation of the power management chip and the register clock driver outward. This increases the contact area between heat and air, thereby improving the heat dissipation rate of the power management chip and the register clock driver. It can also prevent heat from being conducted to the memory chips through the PCB board, thus reducing the temperature of the hot area at the source.

[0077] In some embodiments, the PCB board has a device mounting area formed in the central region and power supply traces formed in the high heat load area and the low heat load area through circuit wiring; a silver plating layer is provided on the surface of the device mounting area and the power supply traces.

[0078] In this embodiment, the silver layer, as a highly conductive metal, can reduce the resistance of the pads and power supply traces, making it easier for heat to be conducted to the heat dissipation path. By plating the pads and power supply traces of the power management chip and the register clock driver with silver, contact resistance can be reduced, thereby reducing Joule heating. Simultaneously, the uniform silver plating layer reduces wire resistance, resulting in a more even current distribution and preventing the power management chip, register clock driver, and power supply traces from overheating due to excessive current, thus improving overall heat dissipation efficiency. The bright silver surface has good infrared emissivity, which helps to radiate the heat generated by the power management chip and register clock driver into the surrounding environment in the form of electromagnetic waves.

[0079] This invention implements enhanced heat dissipation measures in the PCB design and manufacturing of DIMM modules, specifically targeting the areas where the power management chip and register clock driver are located. These measures include: increasing the copper foil thickness of the power / ground layers on the PCB below and around the power management chip and register clock driver to improve lateral heat dissipation; silver plating the pads and critical power traces of the power management chip and register clock driver to reduce resistance and improve thermal conductivity; and adding high thermal conductivity materials, such as graphene thermal pads or vapor chambers, to the surface of the power management chip and register clock driver or the corresponding back surface area of ​​the PCB. This reduces the temperature of the hot zones at the source, providing more favorable conditions for optimizing the memory module layout. The memory module of this invention can be widely used in servers, data centers, high-performance computing, workstations, and other fields requiring high-reliability DIMM modules, and is particularly suitable for mission-critical systems with extreme requirements for memory stability.

[0080] The present invention also proposes a manufacturing apparatus for a DIMM module, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the manufacturing method of the DIMM module as described above.

[0081] The following is for reference. Figure 15 The diagram illustrates a structural schematic of a manufacturing apparatus suitable for implementing DIMM modules in embodiments of the present invention. The manufacturing apparatus for DIMM modules in embodiments of the present invention may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Description), PMPs (Portable Media Players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 15 The manufacturing equipment for the DIMM module shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of the present invention.

[0082] like Figure 15As shown, the manufacturing equipment for DIMM modules may include a processing unit 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1002 or a program loaded from a storage device 1003 into a random access memory (RAM) 1004. The RAM 1004 also stores various programs and data required for the operation of the DIMM module manufacturing equipment. The processing unit 1001, ROM 1002, and RAM 1004 are interconnected via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems can be connected to the I / O interface 1006: input devices 1007 including, for example, a touchscreen, touchpad, keyboard, mouse, image sensor, microphone, accelerometer, gyroscope, etc.; output devices 1008 including, for example, a liquid crystal display (LCD), speaker, vibrator, etc.; storage devices 1003 including, for example, magnetic tape, hard disk, etc.; and communication devices 1009. Communication device 1009 allows the DIMM module manufacturing equipment to communicate wirelessly or wiredly with other devices to exchange data. Although the figure shows DIMM module manufacturing equipment with various systems, it should be understood that implementation or possession of all the systems shown is not required. More or fewer systems may be implemented alternatively.

[0083] In particular, according to the embodiments disclosed in this invention, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this invention include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from ROM 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this invention.

[0084] The DIMM module manufacturing equipment provided by this invention, employing the DIMM module manufacturing method described in the above embodiments, can solve the technical problems in DIMM module manufacturing. Compared with the prior art, the beneficial effects of the DIMM module manufacturing equipment provided by this invention are the same as those of the DIMM module manufacturing method provided in the above embodiments, and other technical features of this DIMM module manufacturing equipment are the same as those disclosed in the previous embodiment method, and will not be repeated here.

[0085] It should be understood that the various parts disclosed in this invention can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or specific time periods can be combined in any suitable manner in one or more embodiments or examples.

[0086] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

[0087] The above description is only a part of the embodiments of the present invention and does not limit the patent scope of the present invention. All equivalent structural transformations made under the technical concept of the present invention using the contents of the present invention specification and drawings, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. A method for manufacturing a DIMM module, characterized in that, The manufacturing method of the DIMM module includes: Run a predetermined application to enter a predetermined application scenario. In the predetermined application scenario, obtain a sequence of commands sent to memory granules, sample the command sequence, obtain the usage frequency of different command types in the command sequence, and obtain the weight of the command type in the predetermined application scenario based on the usage frequency. The predetermined application scenario includes a read-heavy, write-light application scenario and a write-heavy, read-light application scenario. Obtain temperature zone data and operating current data of memory chips; Based on the weight and the current value corresponding to the command type in the operating current data, the weighted total current of the memory chip in the predetermined application scenario is obtained, and the memory chips are sorted based on the weighted total current. Based on the temperature zone data, determine the temperature zone distribution weights for different temperature zones, and determine the sample size corresponding to each temperature zone based on the temperature zone distribution weights and the number of memory chips. Based on the sorted memory chips and the number of samples corresponding to the temperature zones, the temperature zones are traversed in order from low to high. Among the unfiltered memory chips, the memory chip with the same number of samples as the currently traversed temperature zone and the highest weighted total current is selected. The selected memory chip is assigned to the installation area corresponding to the currently traversed temperature zone to obtain the installation decision result of the memory chip. Prepare the PCB board, and based on the installation decision, mount the memory chips to the corresponding areas on the PCB board.

2. The method for manufacturing a DIMM module as described in claim 1, characterized in that, The manufacturing method of the DIMM module further includes: The memory chip weights of the lowest heat load zone are determined based on the temperature zone data, and the number of samples in the lowest heat load zone is calculated based on the memory chip weights. Based on the average temperature distribution rule, memory chips with high total power consumption, equal to the number of samples mentioned above, are selected from the remaining unselected memory chip samples. After the screening is completed, the temperature zone level is increased, and the screening continues in the next temperature zone level until the installation location decision of the memory chips in all temperature zones is completed, and the corresponding installation decision results are output.

3. The method for manufacturing a DIMM module as described in claim 1, characterized in that, The step of obtaining the usage frequency of different command types in the command sequence includes: Divide the sampling time period of the logic analyzer into multiple consecutive sampling windows; Count the frequency of window usage for the command type within different sampling windows; The average frequency of window usage of the command type within multiple sampling windows is obtained, and the average value is used as the actual frequency of use of the command type in the predetermined application scenario.

4. The method for manufacturing a DIMM module as described in claim 1, characterized in that, The current value corresponding to the command type in the operating current data is determined in the following way: For each command type, the current sampling values ​​of the memory chip are collected multiple times under the command type using an ADC acquisition device based on the operating current test device. The average current sampled values ​​from the multiple operations are averaged to obtain the average operating current of the memory chip under the command type. The average operating current under the command type is normalized so that the normalized average operating current of each command type is determined as the current value corresponding to the command type in the operating current data.

5. The method for manufacturing a DIMM module as described in claim 1, characterized in that, Before sequentially traversing the temperature zones from low to high, the method further includes: The weighted total current of the memory chip is compared with a preset current threshold. Memory chips with a weighted total current greater than or equal to the current threshold are marked as high-power category, and memory chips with a weighted total current less than the current threshold are marked as low-power category. In the step of traversing the temperature range and selecting the memory chip with the highest weighted total current from the remaining unscreened memory chips that has the same number of samples as the current traversed temperature range, memory chips belonging to the high power consumption category are preferentially selected.

6. The method for manufacturing a DIMM module as described in claim 1, characterized in that, The acquisition of temperature zone data for memory chips specifically includes: During the operation of the predetermined application scenario, temperature data of the memory chip is collected at preset time intervals to obtain temperature time-series data; The temperature time series data is divided into multiple temperature windows according to the temperature change stages; Calculate the average temperature within each of the temperature windows; The temperature zone data of the memory chip is determined based on the temperature range of the average temperature of the window within the temperature window.

7. The method for manufacturing a DIMM module as described in claim 1, characterized in that, The memory chip integrates a mode register, and the step of obtaining the temperature zone data of the memory chip specifically includes: Send a mode register read command to the memory chip to obtain the actual value of the mode register returned by the memory chip, and obtain the temperature zone data of the memory chip. And / or, read the temperature zone data of the memory chip through a contact temperature sensor; And / or, read the temperature data of the memory chips using a thermal imager.

8. The method for manufacturing a DIMM module as described in claim 1, characterized in that, The specific steps for obtaining the operating current data of memory chips include: For each type of command sent to the memory chip, the total current of the memory chip's core logic and memory array during operation, the current consumed by the memory chip's output driver during state switching or in a terminated state, and the current consumed by the memory chip's word line boost circuit are collected to obtain the memory chip's operating current data.

9. The method for manufacturing a DIMM module as described in claim 1, characterized in that, The PCB board has a first side surface and a second side surface that are disposed opposite to each other; the steps for preparing the PCB board specifically include: Circuit routing is performed on the first side surface of the PCB board to create a central region on the PCB board and a memory mounting area extending outward from the central region. A heat dissipation layer is provided on the second side surface at a position corresponding to the central region.

10. The method for manufacturing a DIMM module as described in claim 9, characterized in that, The thickness of the circuit wiring layer in the central area of ​​the PCB board is greater than the thickness of the circuit wiring layer in the memory mounting area.

11. A manufacturing apparatus for DIMM modules, characterized in that, It includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement a method for manufacturing a DIMM module as described in any one of claims 1 to 10.

12. A DIMM module, characterized in that, The DIMM module is manufactured using the manufacturing method of a DIMM module as described in any one of claims 1 to 10; the DIMM module comprises: A PCB board having a first side surface and a second side surface disposed opposite to each other, circuit wiring being formed on the first side surface of the PCB board, the circuit wiring forming a central region on the PCB board and a memory mounting area extending outward from the central region; A power management chip and a register clock driver are disposed in the central region; and, Multiple memory chips are mounted onto corresponding areas of a PCB board according to mounting decision results obtained from the manufacturing method of a DIMM module as described in any one of claims 1 to 10.

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