Packaging structure and manufacturing method of ultra-thin wafer CSP power device

Abstract

The application discloses a kind of ultra-thin wafer CSP power device packaging structure and manufacturing method, including semiconductor device layer, re-wiring layer, conductive interconnection structure and stress adjustment structure;Semiconductor device layer front surface is provided with active region and source metal layer;Re-wiring layer includes current spreading / thermal diffusion layer and electrical connection metal layer, conductive interconnection structure is connected with current spreading / thermal diffusion layer, forms the composite heat dissipation structure that plane direction is coupled with vertical direction;Stress adjustment structure includes crack suppression structure and stress buffer structure, crack suppression structure is set in the edge dicing lane area of semiconductor device layer one side close to chip effective area, stress buffer structure is set between semiconductor device layer and conductive interconnection structure and forms elastic modulus transition area.The application can improve the thermal diffusion performance in ultra-thin packaging, stress distribution uniformity and mechanical reliability, and reduce packaging warping, interface stress concentration, crack propagation and thermal cycle failure risk.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor power device packaging technology, and specifically relates to a packaging structure and manufacturing method for an ultra-thin wafer CSP power device. Background Technology

[0002] With the development of mobile terminals, fast charging systems, and high-power-density electronic devices, power devices are evolving towards miniaturization, high current density, and high power density. To reduce device on-resistance (Rdson), decrease parasitic parameters, and reduce package size, ultra-thin wafer chip-scale packaging (CSP) structures have gradually become an important development direction for power devices.

[0003] However, when the wafer thickness is reduced to tens of micrometers or even thinner, the overall structural rigidity of ultra-thin wafers decreases significantly. Under packaging manufacturing, reflow soldering, thermal cycling and board bending conditions, problems such as package warping, thermomechanical stress concentration, fatigue failure of conductive interconnect structure, edge crack propagation and interface peeling are likely to occur, thus affecting the long-term reliability of the device.

[0004] On the other hand, under high power and high current operating conditions, local current congestion and heat flux density concentration are likely to occur inside the device, which further leads to increased temperature rise of local hot spots and exacerbates the accumulation of thermal stress inside the package and the risk of interface fatigue failure.

[0005] Existing ultrathin wafer CSP packaging structures typically focus primarily on optimizing conductive interconnect structures or package dimensions, while lacking coordinated optimization of planar thermal diffusion channels, vertical thermal conduction paths, and thermomechanical stress distribution. Therefore, it is difficult to simultaneously achieve thermal diffusion performance, mechanical reliability, and long-term thermal cycling stability in ultrathin packages. Summary of the Invention

[0006] The purpose of this invention is to provide a packaging structure and manufacturing method for ultrathin wafer CSP power devices, so as to solve the problems of packaging warpage, thermomechanical stress concentration, crack propagation, interface fatigue failure and decreased thermal cycling reliability of existing ultrathin wafer packaging under high power density and high current operating conditions.

[0007] The main technical solution adopted in this invention is as follows: A packaging structure for an ultrathin wafer CSP power device includes: The semiconductor device layer is an ultra-thin wafer structure. The front side of the semiconductor device layer has an active region and a source metal layer located above the active region, and the back side has a back metal layer. A redistribution layer is disposed on the active region side of the semiconductor device layer, including a current diffusion / heat diffusion layer and a plurality of electrically connected metal layers, wherein the plurality of electrically connected metal layers are disposed on the source metal layer of the active region; the current diffusion / heat diffusion layer is disposed on the electrically connected metal layers and is used to form a current diffusion path and a heat diffusion channel in the planar direction; A conductive interconnect structure is disposed on the redistribution layer to form an electrical connection between the semiconductor device layer and the external circuit board, as well as a vertical heat conduction path; the conductive interconnect structure is connected to the current amplification / heat diffusion layer to form a composite heat dissipation structure coupled in the planar and vertical directions; and A stress-regulating structure includes a crack-suppressing structure and a stress-buffering structure, wherein the crack-suppressing structure is disposed on one side of the edge scribe line region of the semiconductor device layer near the effective region of the chip; the stress-buffering structure is disposed between the semiconductor device layer and the conductive interconnect structure, for forming an elastic modulus transition region between the semiconductor device layer and the conductive interconnect structure.

[0008] Preferably, the horizontal projected area of ​​the current amplification / heat diffusion layer covers more than 70% of the area of ​​the active region.

[0009] Preferably, the electroplating thickness of the current diffusion / thermal diffusion layer is 5μm to 20μm, and its electroplating thickness is greater than the thickness of the electrically connected metal layer in the redistribution layer.

[0010] Preferably, the stress buffer structure includes one or more of the following: a low-modulus buffer structure, an edge stress relief structure, a modulus transition structure, or a flexible dielectric layer.

[0011] Preferably, the stress buffer structure is a flexible dielectric layer, which is disposed in the redistribution layer and at least wraps around the peripheral area of ​​the current amplification / heat diffusion layer.

[0012] Preferably, the edge morphology of the flexible dielectric layer has a continuously varying thickness structure, and the thickness gradually decreases from the chip center to the outer scribe line direction.

[0013] Preferably, the crack suppression structure includes at least one pre-embedded crack termination groove in a closed loop shape. The pre-embedded crack termination groove is disposed on one side of the chip effective area within the dicing channel, and the pre-embedded crack termination groove extends longitudinally from the front side of the semiconductor device layer inward to block the crack propagation path.

[0014] Preferably, the conductive interconnect structure includes one or more of copper pillars, microbumps, solder balls, or copper clips.

[0015] Preferably, the conductive interconnect structure is arranged in an array on the surface of the redistribution layer to form a multi-path vertical heat conduction path.

[0016] A method for manufacturing a packaging structure for an ultrathin wafer CSP power device includes the following steps: S1: Provide a power semiconductor wafer with an active region and a source metal layer on the front side, and then form a pre-embedded crack termination groove on the side of the dicing area on the front side of the power semiconductor wafer near the effective chip area, and fill the pre-embedded crack termination groove with a low modulus material to form a crack suppression structure. S2: The active region and source metal layer of the power semiconductor wafer are oriented toward the temporary carrier, and are fixedly connected to the temporary carrier through a temporary bonding layer disposed between the two. S3: Thin the back side of the power semiconductor wafer to form an ultra-thin wafer structure, and form a back metal layer on the thinned back side. S4: Remove the temporary carrier and temporary bonding layer, and flip the ultrathin wafer structure so that the back metal layer faces down, exposing the active region and source metal layer on the front side; S5: A redistribution layer is formed on the front side of the ultrathin wafer structure, the redistribution pattern is defined by photolithography, and an electrical connection metal layer and a current diffusion / thermal diffusion layer are formed by electroplating. S6: A flexible dielectric layer is formed on the redistribution layer. Through exposure, development and thermal curing processes, the edge of the flexible dielectric layer forms a continuous gradient thickness structure that gradually thins from the chip center to the outside, so as to form an elastic modulus transition region. S7: Within the open area defined by the flexible dielectric layer, a conductive interconnect structure is formed by electroplating. S8: The ultrathin wafer structure is cut along the dicing area where the pre-embedded crack termination groove is set to form a discrete ultrathin wafer CSP power device package structure.

[0017] Beneficial effects: This invention provides a packaging structure and manufacturing method for an ultra-thin wafer CSP power device, which has the following advantages: (1) The present invention improves the thermal diffusion performance, mechanical reliability and thermal cycling stability of the ultrathin package structure by setting a current-expanding / thermal diffusion layer, a conductive interconnect structure and a stress adjustment structure in the packaging structure of the ultrathin wafer CSP power device, thereby co-optimizing the thermal diffusion channel in the planar direction, the thermal conduction path in the vertical direction and the mechanical stress distribution.

[0018] (2) The present invention uses a stress buffer structure in combination with a crack suppression structure to reduce the local heat concentration effect, interface stress concentration effect and package warpage risk, and suppress the extension of edge cracks to the active area, thereby improving the structural stability and manufacturing reliability of ultra-thin wafer packaging under thermal cycling, board bending and mechanical conditions.

[0019] (3) By setting a pre-embedded crack termination groove in the dicing area and combining it with the ultra-thin wafer temporary bonding thinning process, the present invention can reduce the risk of edge chipping and mechanical damage during the processing and cutting of ultra-thin wafers, thereby improving the manufacturing yield and long-term reliability of ultra-thin wafer packaging structures. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the ultra-thin wafer CSP power device packaging structure in Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of the composite heat dissipation structure in Embodiment 1 of the present invention; Figure 3 This is a schematic cross-sectional view of the stress adjustment structure in Embodiment 1 of the present invention; Figure 4 This is a schematic diagram of the temporary bonding support and thinning process structure for ultrathin wafers provided in Embodiment 2 of the present invention; The reference numerals in the attached figures are explained as follows: Semiconductor device layer 100, active region 110, source metal layer 120, back metal layer 130, redistribution layer 200, current diffusion / thermal diffusion layer 210, electrical connection metal layer 220, conductive interconnect structure 300, copper pillar 310, solder ball 320, stress adjustment structure 400, crack suppression structure 410, embedded crack termination groove 420, flexible dielectric layer 430, temporary carrier 600, temporary bonding layer 610, printed circuit board 700. Detailed Implementation

[0021] To enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application are clearly and completely described below. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this application. Example 1

[0022] like Figure 1 As shown, this embodiment discloses a packaging structure for an ultra-thin wafer CSP power device, which is suitable for mobile terminal fast charging systems or high-density power systems. Specifically, it includes a semiconductor device layer 100, a redistribution layer 200, a conductive interconnect structure 300, and a stress adjustment structure 400.

[0023] like Figure 1As shown, the semiconductor device layer 100 is an ultrathin wafer structure. An active region 110 and a source metal layer 120 are disposed on its front side, and a back metal layer 130 is disposed on its back side. In this embodiment, the thickness of the semiconductor device layer 100 is 15 μm to 40 μm. The back metal layer 130 adopts a multilayer metal composite structure of Ti / Ni / Ag or Ti / Ni / Cu, used to form a drain electrical connection layer and a back heat-conducting layer, and to improve the overall structural stability of the ultrathin wafer.

[0024] A redistribution layer 200 is disposed on the active region side of the semiconductor device layer 100, and includes a current diffusion / heat diffusion layer 210 and a plurality of electrically connected metal layers 220. The plurality of electrically connected metal layers 220 are disposed on the source metal layer 120 of the active region 110 and are used to form an electrical connection path between the active region 110 and the current diffusion / heat diffusion layer 210; the current diffusion / heat diffusion layer 210 is disposed on the electrically connected metal layers 220 and is used to form a current diffusion path and a planar heat diffusion channel.

[0025] In this embodiment, the current diffusion / heat diffusion layer 210 is a copper current diffusion / heat diffusion layer, formed by electroplating. Its electroplating thickness is 5μm to 20μm, and the electroplating thickness of the current diffusion / heat diffusion layer 210 is greater than the thickness of other electrically connected metal layers 220 in the same layer. In addition, the horizontal projected area of ​​the current diffusion / heat diffusion layer 210 covers more than 70% of the area of ​​the active region 110, thereby forming a low-impedance current diffusion path and a planar heat diffusion channel to improve the uniformity of current distribution inside the device and reduce local hot spot effects.

[0026] A conductive interconnect structure 300 is disposed on the redistribution layer 200 to form an electrical connection between the semiconductor device layer 100 and the external circuit board, as well as a vertical heat conduction path. In this embodiment, as shown... Figure 1 As shown, the conductive interconnect structure 300 adopts a copper pillar 310 structure. The height of the copper pillar 310 is 30μm to 80μm, and a SnAg solder cap or solder ball 320 is formed on the top of the copper pillar 310 for electrical and thermal connection with external system circuit boards (such as PCBs). The copper pillars 310 are arranged in an array on the surface of the redistribution layer 200 to form multiple vertical heat conduction paths, improving the heat conduction capability to external system circuit boards.

[0027] In other embodiments, the conductive interconnect structure 300 may also be at least one of microbumps, solder balls, or copper clips.

[0028] like Figure 2 As shown, the conductive interconnect structure 300 is connected to the current diffusion / heat diffusion layer 210 to form a composite heat dissipation structure that is coupled in the planar and vertical directions.

[0029] like Figure 3As shown, the stress adjustment structure 400 includes a crack suppression structure 410 and a stress buffer structure. The crack suppression structure 410 is disposed on the side of the edge scribe line region of the semiconductor device layer 100 near the effective region of the chip. The stress buffer structure is disposed between the semiconductor device layer 100 and the conductive interconnect structure 300 to form an elastic modulus transition region between the semiconductor device layer 100 and the conductive interconnect structure 300.

[0030] In this embodiment, the stress buffer structure is a flexible dielectric layer 430, which at least wraps around the periphery of the current diffusion / heat diffusion layer 210 (e.g., Figure 1 As shown, it also encapsulates other electrically connected metal layers 220. The edge morphology of the flexible dielectric layer 430 has a continuously varying thickness structure, and the thickness gradually decreases from the chip center outwards along the scribe line direction, thereby forming a progressively decreasing elastic modulus gradient between the semiconductor device layer 100, the current diffusion / thermal diffusion layer 210, and the flexible dielectric layer 430. Figure 3 As shown, an elastic modulus transition region (Si (approximately 130 GPa) - Cu (approximately 110 GPa) - PI (approximately 3 GPa)) is formed in the edge region, thereby alleviating the thermomechanical stress concentration caused by the mismatch of thermal expansion coefficients between heterogeneous material interfaces.

[0031] The flexible dielectric layer 430 can be made of at least one of polyimide (PI), polybenzoxazole (PBO), or low-modulus organic dielectric material. The coefficient of thermal expansion (CTE) of the cured flexible dielectric layer 430 is 20ppm / ℃ to 80ppm / ℃.

[0032] In other embodiments, the stress buffer structure may include one or more of the following: a low-modulus buffer structure, an edge stress relief structure, a modulus transition structure, or a flexible dielectric layer.

[0033] like Figure 3 As shown, the crack suppression structure 410 includes at least one pre-embedded crack termination groove 420 in a closed loop shape. The pre-embedded crack termination groove 420 is disposed on one side of the scribe line near the effective area of ​​the chip, and the pre-embedded crack termination groove 420 extends longitudinally from the front side of the semiconductor device layer 100 inward to block the crack propagation path.

[0034] In this embodiment, the pre-embedded crack termination groove 420 is arranged in a closed loop along the outer non-working area (inside the dicing track) of the semiconductor device layer 100 and longitudinally cuts into the interior of the semiconductor device layer 100, with a cutting depth of 2μm to 10μm. The interior of the pre-embedded crack termination groove 420 is filled with a low-modulus flexible buffer material, thereby forming a crack propagation blocking region, inhibiting edge chipping or microcracks from propagating into the internal active region 110, and reducing the mechanical stress concentration effect generated during the physical dicing of ultrathin wafers.

[0035] In this embodiment, the flexible dielectric layer 430, the crack suppression structure 410, the current diffusion / heat diffusion layer 210, and the conductive interconnect structure 300 work together to improve the heat diffusion performance, stress distribution uniformity, and current diffusion capability in the ultra-thin package, thereby improving the thermal stability and mechanical reliability of the ultra-thin package structure. Example 2

[0036] Based on the packaging structure described in Example 1, this example provides a method for fabricating a packaging structure for an ultrathin wafer CSP power device, specifically including the following steps: S1: As Figure 4 As shown, a power semiconductor wafer with an active region 110 and a source metal layer 120 on its front side is provided. The surface of the wafer is cleaned and passivated. Then, on the side of the dicing area near the effective chip area on the front side of the power semiconductor wafer, a pre-embedded crack termination groove 420 with a depth of 2μm to 10μm is formed by photolithography and dry etching. A low-modulus material (such as photosensitive polyimide) is then filled into the pre-embedded crack termination groove 420 using a spin-coating process, followed by pre-baking to form a crack suppression structure 410. In some embodiments, the total surface thickness variation (TTV) of the power semiconductor wafer is less than 2μm.

[0037] S2: As Figure 4 As shown, the active region 110 and source metal layer 120 on the front side of the power semiconductor wafer are oriented towards the temporary carrier 600 and fixedly connected to the temporary carrier 600 by a temporary bonding layer 610. In this embodiment, the temporary carrier 600 is selected from at least one of a glass carrier, a silicon carrier, or a ceramic carrier, and the temporary bonding layer 610 is formed using a detachable organic bonding material with a thickness of 5 μm to 50 μm.

[0038] S3: As Figure 4 As shown, after temporary bonding is completed, the back side of the power semiconductor wafer is thinned to form an ultrathin wafer structure. Subsequently, the back side of the thinned ultrathin wafer structure undergoes plasma surface activation treatment, and a back metal layer 130 is formed on the back side through sputtering and electroplating processes. In this embodiment, the thinning treatment includes at least one of back side rough grinding, fine grinding, chemical mechanical polishing (CMP), or plasma polishing, thinning the entire power semiconductor wafer to 15μm to 40μm. In some embodiments, the surface roughness Ra of the back side of the thinned wafer is less than 0.5nm. The back metal layer 130 adopts a Ti / Ni / Ag structure or a Ti / Ni / Cu structure to form a back electrical connection layer and a back thermal conductive layer.

[0039] S4: As Figure 4As shown, after the back metal layer 130 is fabricated, the temporary carrier 600 and the temporary bonding layer 610 are removed by at least one of laser debonding, thermal slip debonding, mechanical exfoliation debonding, or chemical debonding, and residual bonding material is cleaned away. Subsequently, the ultrathin wafer structure is flipped so that the back metal layer 130 faces downward, exposing the active region 110, the source metal layer 120, and the surrounding crack suppression structure 410 on the front side.

[0040] S5: A redistribution layer 200 is formed on the front side of the ultra-thin wafer structure. Specifically, a Ti / Cu seed layer is first formed using a sputtering process, then the redistribution pattern is defined using a photolithography process, and finally a thick copper conductive structure is formed using an electroplating process to form an electrical connection metal layer 220 and a current diffusion / heat diffusion layer 210. The horizontal projected area of ​​the current diffusion / heat diffusion layer 210 covers more than 70% of the area of ​​the active region 110, and is used to form a low-impedance current diffusion path and a planar heat diffusion channel.

[0041] S6: A flexible dielectric layer 430 is formed on the redistribution layer 200. Through exposure, development, and thermal curing processes, the edges of the flexible dielectric layer 430 form a continuously tapered thickness structure that gradually thins from the chip center outwards, thereby forming an elastic modulus transition region. In this embodiment, the flexible dielectric layer 430 is formed using at least one of photosensitive polyimide (PI), polybenzoxazole (PBO), or a low-modulus organic dielectric material. In some embodiments, the thermal curing temperature is 250°C to 350°C, and the coefficient of thermal expansion of the cured flexible dielectric layer 430 is 20ppm / °C to 80ppm / °C. The flexible dielectric layer 430 works in conjunction with the crack suppression structure 410 to alleviate thermomechanical stress concentration in the ultra-thin package.

[0042] S7: Within the open area defined by the flexible dielectric layer 430, a conductive interconnect structure 300 is formed by electroplating. In this embodiment, the conductive interconnect structure 300 includes copper pillars 310 with a height of 30μm to 80μm, and SnAg solder caps or solder balls 320 are formed on the top of the copper pillars 310. The copper pillars 310 are arranged in an array on the surface of the redistribution layer 200 and are connected to the current diffusion / heat diffusion layer 210 to form a composite heat dissipation structure in which a planar heat diffusion channel and a vertical heat conduction path are coupled.

[0043] S8: Along the dicing area with a pre-set pre-embedded crack termination groove 420, the ultrathin wafer structure is mechanically cut, laser cut, or combined cut to form multiple discrete ultrathin wafer CSP power devices.

[0044] During the cutting process, the pre-embedded crack termination groove 420 and the flexible buffer material filled therein are used to reduce the local mechanical stress concentration in the dicing area and inhibit the edge crack from spreading into the active area, thereby improving the edge reliability and manufacturing yield of the ultra-thin packaging structure. Example 3

[0045] Based on the packaging structure of the ultra-thin wafer CSP power device proposed in Example 1, this example provides a variety of packaging heat dissipation topologies based on the packaging structure described in Example 1 to suit different system board-level assembly conditions.

[0046] In the first embodiment, the package structure adopts a source-down configuration. In this structure, the source metal layer 120 of the power device faces the bottom of the package and forms an electrical and thermal connection with the printed circuit board (PCB) 700 through an array of copper pillars 310 and solder balls 320. During device operation, the heat generated in the active region 110 can form a vertical heat conduction path through the source metal layer 120, copper pillars 310, and PCB 700 to shorten the heat conduction distance and reduce the package thermal resistance. Furthermore, the copper pillars 310 are arranged in an array on the surface of the redistribution layer 200 to improve the heat conduction capability to the external system and improve the local heat flux density distribution.

[0047] In the second embodiment, the package structure adopts a drain-down configuration. In this structure, the back metal layer 130 of the semiconductor device layer 100 faces the underside of the package and forms an electrical and thermal connection with the printed circuit board 700 through the conductive interconnect structure 300. The heat generated during device operation can be conducted to the external system through the semiconductor device layer 100, the back metal layer 130, and the conductive interconnect structure 300 to improve the longitudinal heat conduction efficiency.

[0048] In the third embodiment, the packaging structure employs a double-sided heat conduction structure. In this structure, a front heat conduction path is formed on the front side of the device through a current-diffusing / heat-diffusion layer 210 and copper pillars 310, while a back heat conduction path is formed on the back side of the device through a back metal layer 130 and an external heat-conducting structure. The external heat-conducting structure includes at least one of copper clips, metal heat sinks, or other high thermal conductivity metal structures. By simultaneously forming heat conduction paths on both the front and back sides of the device, the overall heat diffusion performance can be improved, the local hot spot effect can be reduced, and the uniformity of heat flux density distribution can be improved.

[0049] Comparative Example 1 This embodiment provides a conventional ultrathin packaging structure. The difference from Embodiment 1 is that it does not include the crack suppression structure 410, and the front side adopts a conventional uniform thickness insulating dielectric layer structure with a vertical edge morphology and does not form a continuous gradient thickness structure. The rest is the same as Embodiment 1.

[0050] Comparative Test Under the same conditions of electrical trace structure, package size and ultra-thin wafer thickness (20μm), the following package reliability and thermomechanical stability tests were performed on Example 1 and this comparative example respectively.

[0051] (1) In the package warpage test, the comparative package structure, lacking the crack suppression structure 410 and employing a conventional uniform thickness insulating dielectric layer structure, struggled to form a continuous elastic modulus transition region, resulting in reduced stress buffering capacity and increased thermomechanical stress concentration within the package, thus significantly increasing package warpage. Test results showed that the maximum package warpage of the comparative example was significantly higher than that of Example 1; in some test samples, the maximum package warpage of the comparative example reached approximately 80 μm, while the maximum package warpage of Example 1 was less than 20 μm. These results indicate that the crack suppression structure 410 and flexible dielectric layer 430 in Example 1 can optimize the structural rigidity distribution and thermomechanical stress distribution in ultra-thin packages, thereby reducing the risk of package warpage.

[0052] (2) In the board bending and drop reliability tests, the comparative example showed edge crack propagation and packaging structure failure when the board bending displacement reached about 0.8 mm; while in Example 1, due to the inclusion of crack suppression structure 410 and flexible dielectric layer 430, no obvious crack propagation was observed even when the board bending displacement reached 3.5 mm. The results show that Example 1 can effectively reduce the stress concentration effect in the edge region of the ultra-thin chip and improve the board bending reliability and mechanical shock reliability of the device.

[0053] (3) In the thermal cycling reliability test (-55℃ to +150℃), after approximately 150 cycles, the comparative example showed obvious fatigue cracking and interface peeling in the root region of the conductive interconnect structure 300. The cracking rate at the copper pillar root and the interface peeling rate both exceeded 85%, resulting in a significant decrease in electrical connection reliability. In contrast, after 1000 thermal cycles, the conductive interconnect structure 300 and the interface region in Example 1 maintained a good bonding state, and no obvious cracking or peeling was observed. These results indicate that Example 1, through the synergistic cooperation of the flexible dielectric layer 430, the current-diffusing / thermal diffusion layer 210, and the conductive interconnect structure 300, can effectively alleviate the interface shear stress and fatigue accumulation effect generated during thermal cycling, thereby improving the long-term thermal cycling reliability of the ultra-thin packaging structure.

[0054] In summary, compared to conventional ultra-thin packaging structures, Example 1, through the synergistic cooperation of the flexible dielectric layer 430, the current diffusion / thermal diffusion layer 210, the conductive interconnect structure 300, and the crack suppression structure 410, can improve the thermal diffusion performance, stress distribution uniformity, and structural mechanical reliability of ultra-thin packaging, and reduce the risk of packaging warpage, crack propagation, and interface fatigue failure.

[0055] The above are merely preferred embodiments of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A packaging structure for an ultrathin wafer CSP power device, characterized in that, include: The semiconductor device layer (100) is an ultra-thin wafer structure. The front side of the semiconductor device layer is provided with an active region (110) and a source metal layer (120) located above the active region (110), and the back side is provided with a back metal layer (130). A redistribution layer (200) is disposed on the active region side of the semiconductor device layer (100), including a current diffusion / heat diffusion layer (210) and a plurality of electrically connected metal layers (220), wherein the plurality of electrically connected metal layers (220) are disposed on the source metal layer (120) of the active region (110); the current diffusion / heat diffusion layer (210) is disposed on the electrically connected metal layers (220) for forming a current diffusion path and a heat diffusion channel in the planar direction; A conductive interconnect structure (300) is disposed on the redistribution layer (200) to form an electrical connection between the semiconductor device layer (100) and an external circuit board, as well as a vertical heat conduction path; the conductive interconnect structure (300) is connected to the current diffusion / heat diffusion layer (210) to form a composite heat dissipation structure coupled in the planar and vertical directions; and The stress adjustment structure (400) includes a crack suppression structure (410) and a stress buffer structure, wherein the crack suppression structure (410) is disposed on one side of the edge scribe line region of the semiconductor device layer (100) near the effective region of the chip; the stress buffer structure is disposed between the semiconductor device layer (100) and the conductive interconnect structure (300) for forming an elastic modulus transition region between the semiconductor device layer (100) and the conductive interconnect structure (300).

2. The packaging structure of the ultra-thin wafer CSP power device according to claim 1, characterized in that, The horizontal projected area of ​​the flow amplification / heat diffusion layer (210) covers more than 70% of the area of ​​the active region (110).

3. The packaging structure of the ultra-thin wafer CSP power device according to claim 1, characterized in that, The electroplating thickness of the current diffusion / thermal diffusion layer (210) is 5μm to 20μm, and its electroplating thickness is greater than the thickness of the electrically connected metal layer (220) in the redistribution layer (200).

4. The packaging structure of the ultra-thin wafer CSP power device according to claim 1, characterized in that, The stress buffer structure includes one or more of the following: a low-modulus buffer structure, an edge stress relief structure, a modulus transition structure, or a flexible dielectric layer (430).

5. The packaging structure of the ultra-thin wafer CSP power device according to claim 4, characterized in that, The stress buffer structure is a flexible dielectric layer (430), which is disposed in the redistribution layer (200) and at least covers the peripheral area of ​​the current diffusion / heat diffusion layer (210).

6. The packaging structure of the ultra-thin wafer CSP power device according to claim 5, characterized in that, The edge morphology of the flexible dielectric layer (430) has a continuously varying thickness structure, and the thickness gradually decreases from the chip center to the outer scribe line direction.

7. The packaging structure of the ultra-thin wafer CSP power device according to claim 1, characterized in that, The crack suppression structure (410) includes at least one pre-embedded crack termination groove (420) in the form of a closed ring. The pre-embedded crack termination groove (420) is disposed on one side of the chip effective area within the dicing channel, and the pre-embedded crack termination groove (420) extends longitudinally from the front of the semiconductor device layer (100) inward to block the crack propagation path.

8. The packaging structure of the ultra-thin wafer CSP power device according to claim 1, characterized in that, The conductive interconnect structure (300) includes one or more of copper pillars (310), microbumps, solder balls (320), or copper clips.

9. The packaging structure of the ultra-thin wafer CSP power device according to claim 1, characterized in that, The conductive interconnect structure (300) is arranged in an array on the surface of the redistribution layer (200) to form a multi-path vertical heat conduction path.

10. A method for manufacturing a packaging structure for an ultrathin wafer CSP power device as described in any one of claims 1-9, characterized in that, Includes the following steps: S1: Provide a power semiconductor wafer with an active region (110) and a source metal layer (120) on the front side, and then form a pre-embedded crack termination groove (420) on the side of the dicing area on the front side of the power semiconductor wafer near the effective chip area, and fill the pre-embedded crack termination groove (420) with a low modulus material to form a crack suppression structure (410). S2: The active region (110) and source metal layer (120) of the power semiconductor wafer are oriented toward the temporary carrier (600), and are fixedly connected to the temporary carrier (600) through a temporary bonding layer (610) disposed between the two. S3: The back side of the power semiconductor wafer is thinned to form an ultra-thin wafer structure, and a back metal layer (130) is formed on the thinned back side. S4: Remove the temporary carrier (600) and temporary bonding layer (610), and flip the ultrathin wafer structure so that the back metal layer (130) faces down, exposing the active region (110) and source metal layer (120) on the front side. S5: A redistribution layer (200) is formed on the front side of the ultrathin wafer structure, the redistribution pattern is defined by photolithography, and an electrical connection metal layer (220) and a current diffusion / heat diffusion layer (210) are formed by electroplating. S6: A flexible dielectric layer (430) is formed on the redistribution layer (200). Through exposure, development and thermal curing processes, the edge of the flexible dielectric layer (430) forms a continuous gradient thickness structure that gradually thins from the center of the chip to the outside, so as to form an elastic modulus transition region. S7: Within the open area defined by the flexible dielectric layer (430), a conductive interconnect structure (300) is formed by electroplating. S8: The ultrathin wafer structure is cut along the dicing area where the pre-embedded crack termination groove (420) is provided to form a discrete ultrathin wafer CSP power device packaging structure.

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