Chip packaging structure and sensor module

Abstract

The application provides a chip packaging structure and a sensor module, comprising: a substrate; a shell arranged on one side of the substrate and having an opening; and a first chip and a first carrier located in the shell; the first chip and the first carrier are arranged in a stacking manner in the thickness direction of the substrate, the first chip is used at least to obtain a pressure signal and convert the obtained pressure signal into an electrical signal output; a first bonding layer is arranged between the first chip and the first carrier, a second bonding layer is arranged between the substrate and the first carrier, and the viscosity of the second bonding layer is greater than that of the first bonding layer; the application adds the first carrier, and uses the first bonding layer to connect the chip and the first carrier and the second bonding layer to connect the first carrier and the substrate, thereby enhancing the connection strength and anti-interference ability of the first chip, reducing the risk of falling off, and blocking the stress of the second bonding layer to ensure the measurement sensitivity and accuracy of the first chip to external stress.

Description

Technical Field

[0001] This application relates to the field of chip packaging technology, and in particular to a chip packaging structure and a sensor module. Background Technology

[0002] MEMS (Micro Electro Mechanical Systems Pressure Sensor) devices typically consist of a MEMS chip and an ASIC (Application Specific Integrated Circuit) chip. Because MEMS chips are highly sensitive to stress, low-viscosity adhesives are usually used for fixation to prevent excessive stress in the bonding area between the adhesive and the MEMS chip, which could affect the measurement accuracy of the MEMS device. However, the weak adhesion of low-viscosity adhesives makes the MEMS chip less resistant to vibration and other interference factors, resulting in a higher risk of chip detachment, which in turn affects product quality and customer acceptance. Summary of the Invention

[0003] In view of this, the purpose of this application is to propose a chip packaging structure and a sensor module to solve at least some of the technical problems mentioned above.

[0004] To achieve the above objectives, this application provides a chip packaging structure, comprising:

[0005] substrate;

[0006] A housing, disposed on one side of the substrate and having an opening; and

[0007] A first chip and a first carrier are located inside the housing; the first chip and the first carrier are stacked in the thickness direction of the substrate, and the first chip is used at least to acquire pressure signals and convert the acquired pressure signals into electrical signals for output;

[0008] A first adhesive layer is disposed between the first chip and the first carrier, and a second adhesive layer is disposed between the substrate and the first carrier, wherein the viscosity of the second adhesive layer is greater than the viscosity of the first adhesive layer.

[0009] Based on the same inventive concept, a second aspect of this disclosure also provides a sensor module, including the chip packaging structure described in the first aspect.

[0010] As can be seen from the above, the chip packaging structure and sensor module provided in this application enhance the connection strength of the first chip by adding a first carrier between the substrate and the first chip, connecting the first chip and the first carrier with a first adhesive layer formed by a low-viscosity adhesive, and connecting the substrate and the first carrier with a second adhesive layer with a viscosity greater than that of the first adhesive layer. This improves the chip packaging structure's resistance to interference factors and reduces the risk of the first chip falling off. At the same time, the first carrier can prevent the stress generated in the connection area between the second adhesive layer and the first carrier from diffusing towards the first chip, ensuring the first chip's sensitivity and accuracy in measuring external stress, thereby optimizing the packaging reliability and functionality. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic diagram of the first chip packaging structure in the embodiments of this application;

[0013] Figure 2 This is a schematic diagram of the second chip packaging structure in the embodiments of this application;

[0014] Figure 3 This is a schematic diagram of the third chip packaging structure in the embodiments of this application;

[0015] Figure 4 This is a schematic diagram of the first carrier in the embodiments of this application;

[0016] Figure 5 This is a schematic diagram of the second type of first carrier in the embodiments of this application;

[0017] Figure 6 This is a schematic diagram of the fourth chip packaging structure in the embodiments of this application;

[0018] Figure 7 This is a top view of the second chip in an embodiment of this application;

[0019] Figure 8 This is a schematic diagram of the fifth chip packaging structure in the embodiments of this application;

[0020] Figure 9 This is a schematic diagram of the sixth chip packaging structure in the embodiments of this application;

[0021] Figure 10 This is a schematic diagram of the seventh chip packaging structure in the embodiments of this application;

[0022] Figure 11 This is a schematic diagram of the eighth chip packaging structure in the embodiments of this application;

[0023] Figure 12 This is a schematic diagram of the first type of second carrier in the embodiments of this application;

[0024] Figure 13 This is a schematic diagram of the second type of second carrier in the embodiments of this application;

[0025] Figure 14 This is a schematic diagram of the third type of second carrier in the embodiments of this application.

[0026] Explanation of reference numerals in the attached figures:

[0027] 1. Substrate;

[0028] 2. Housing; 201. Opening;

[0029] 3. First chip;

[0030] 4. First carrier; 401. First blind hole; 402. First through hole;

[0031] 501, First adhesive layer; 502, Second adhesive layer; 503, Third adhesive layer; 504, Fourth adhesive layer; 505, Fifth adhesive layer; 506, Sixth adhesive layer;

[0032] 6. Second chip; 601. Functional area; 602. Non-functional area;

[0033] 7. Second carrier; 701. Second blind hole; 702. Second through hole. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0035] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in the embodiments of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0036] MEMS devices are common pressure sensors widely used in various fields and have broad development prospects. The core structure of a MEMS device is a MEMS chip, which has a highly sensitive silicon-based thin film. This silicon-based thin film can sense external pressure. Specifically, when external pressure causes deformation of the silicon-based thin film, it causes a change in the resistance of the piezoresistive element inside the MEMS chip. The change in resistance is converted into an electrical signal by a Wheatstone bridge inside the MEMS chip, and then output through the printed circuit of the PCB (Printed Circuit Board) or data lines and other data transmission channels.

[0037] Therefore, in some embodiments, a chip packaging structure is provided; specifically as follows: Figure 1 As shown, the chip packaging structure includes a MEMS packaging assembly, which includes a substrate 1, a housing 2 disposed on one side of the substrate 1, and a first chip 3 located within the housing 2. Specifically, the substrate 1 can be a PCB, providing a mounting position and data transmission channel for the first chip 3; the housing 2 can effectively protect the first chip 3 and can sense external pressure through openings 201 on its sidewalls; the first chip 3 can be a MEMS chip, which can be electrically connected to the PCB and adhered to the surface of the substrate 1 through a first adhesive layer 501. More specifically, since MEMS chips are extremely sensitive to stress, a low-stress adhesive is required to fix and connect the MEMS chip. For adhesives, the viscosity is proportional to the stress. Therefore, when the MEMS chip is connected by the first adhesive layer 501 formed by the low-viscosity adhesive, the stress generated in the connection area is relatively small, thus fixing the first chip 3 to the substrate 1 without interfering with the overall performance of the MEMS chip.

[0038] Furthermore, MEMS chips in MEMS devices can be used in conjunction with ASIC chips. Specifically, during application, the ASIC chip establishes an electrical connection with the MEMS chip and receives the converted electrical signal output by the MEMS chip. After receiving the converted electrical signal, the ASIC chip amplifies and performs accuracy compensation, then converts the compensated electrical signal into a corresponding digital signal for output, enabling users to accurately obtain the pressure data measured by the MEMS device.

[0039] Therefore, some embodiments also disclose a chip packaging structure, such as Figure 2 As shown, in addition to the MEMS packaging components in the above embodiments, the chip packaging structure also includes an ASIC packaging component. The ASIC packaging component mainly includes a second chip 6. Specifically, the second chip 6 can be an ASIC chip. The second chip 6 is electrically connected to the substrate 1 and establishes an electrical connection with the first chip 3 through a portion of the printed circuit on the substrate 1. This ensures that the pressure signal acquired by the MEMS chip can be received, converted, processed, and output by the ASIC chip, thereby obtaining relatively accurate pressure data.

[0040] Based on the above embodiments, the stress generated when the first adhesive layer 501, formed with a low-viscosity adhesive, is connected to the MEMS chip on the PCB surface is relatively small, thus the interference to the MEMS chip is also relatively low. However, the applicant has discovered that the aforementioned embodiments also introduce a new technical problem: although the stress generated after the low-viscosity adhesive is connected is small, its viscosity is relatively poor, and therefore its adhesion ability is relatively weak. Therefore, when the MEMS chip is adhered to the substrate board through the first adhesive layer 501, the connection strength of the MEMS chip is low, making it susceptible to interference factors such as vibration, which may cause the MEMS chip to detach, thereby affecting product quality and customer acceptance.

[0041] In view of this, the first aspect of this application provides a chip packaging structure, combined with Figures 3-14 The content shown provides a detailed explanation of the chip's packaging structure.

[0042] A chip packaging structure includes a substrate 1, a housing 2, a first chip 3, and a first carrier 4; wherein the housing 2 is disposed on one side of the substrate 1 and has an opening 201; the first chip 3 and the first carrier 4 are located inside the housing 2; the first chip 3 and the first carrier 4 are stacked in the thickness direction of the substrate 1, the first chip 3 is used at least to acquire a pressure signal and convert the acquired pressure signal into an electrical signal for output; a first adhesive layer 501 is disposed between the first chip 3 and the first carrier 4, and a second adhesive layer 502 is disposed between the substrate 1 and the first carrier 4, the viscosity of the second adhesive layer 502 being greater than the viscosity of the first adhesive layer 501.

[0043] Specifically, such as Figure 3 , Figure 6 as well as Figures 8-11 As shown, the substrate 1 can serve as the main carrier of the chip packaging structure, supporting the housing 2, the first chip 3 and the first carrier 4, and providing corresponding mounting positions.

[0044] For example, the substrate 1 can be a PCB, which, in addition to supporting and protecting the first chip 3, can also establish an electrical connection with the first chip 3 to transmit the electrical signals output by the first chip 3.

[0045] Specifically, such as Figure 3 , Figure 6 as well as Figures 8-11 As shown, the housing 2 is fixedly connected to one side of the substrate 1, and the housing 2 covers the first chip 3 and the first carrier 4, thereby providing effective protection for the first chip 3. More specifically, the side wall of the housing 2 has an opening 201, through which the first chip 3 can obtain the pressure signal acting on its surface, thereby realizing the acquisition and acquisition of the pressure signal.

[0046] Specifically, such as Figure 3 , Figure 6 as well as Figures 8-11 As shown, in the chip packaging structure, both the first chip 3 and the first carrier 4 are located inside the housing 2. In this case, the housing 2 not only provides effective protection for both but also offers a stable detection environment with minimal interference. More specifically, the first chip 3 can be used to acquire and process external pressure signals, that is, to obtain pressure signals and convert them into electrical signals for output.

[0047] More specifically, such as Figure 3 , Figure 6 as well as Figures 8-11 As shown, the first chip 3 and the first carrier 4 are stacked in the thickness direction of the substrate 1. The first chip 3 and the first carrier 4 can be connected by the first adhesive layer 501. At this time, the first adhesive layer 501 can be formed with a low-stress adhesive, so that while fixing the first chip 3 to the side of the first carrier 4 away from the substrate 1, it can reduce the stress of the first adhesive layer 501 on the connection area between the first chips 3, reduce the stress interference on the first chip 3, and ensure the measurement effect and measurement accuracy of the first chip 3 to external stress.

[0048] More specifically, the substrate 1 and the first carrier 4 are connected by a second adhesive layer 502, and the viscosity of the second adhesive layer 502 is greater than that of the first adhesive layer 501. In this case, the second adhesive layer 502 can be formed by a high-viscosity adhesive to fix the first carrier 4 to the surface of the substrate 1, thereby improving the connection strength of the first carrier 4 on the substrate 1, and thus improving the resistance of the first carrier 4 and even the first chip 3 to interference factors, thereby reducing the probability of the first chip 3 falling off, thereby improving the product quality of the chip packaging structure and customer acceptance.

[0049] Furthermore, since the substrate 1 and the first carrier 4 are connected by a second adhesive layer 502 with a viscosity greater than that of the first adhesive layer 501, the stress generated in the connection area between the second adhesive layer 502 and the substrate 1, and in the connection area between the second adhesive layer 502 and the first carrier 4, is relatively large. Because the first carrier 4 is located between the second adhesive layer 502 and the first chip 3, the second carrier 7 can block the stress of the second adhesive layer 502, thereby preventing the stress of the second adhesive layer 502 from spreading to the first chip 3 and causing stress interference, thus ensuring the accuracy of the first chip 3 in measuring external stress.

[0050] For example, the first carrier 4 may be formed of a material with a low coefficient of thermal expansion, such as a glass carrier.

[0051] For example, the first adhesive layer 501 may be formed using a silicon-based low-viscosity adhesive, and the second adhesive layer 502 may be formed using a silicon-based high-viscosity adhesive, so as to ensure the bonding effect between the two and the first carrier 4.

[0052] For example, the first chip 3 can be a MEMS chip. The MEMS chip can sense external pressure through the opening 201 on the housing 2, thereby obtaining the external pressure signal. Subsequently, the MEMS chip can convert the obtained pressure signal into an electrical signal and output it to achieve the purpose of pressure measurement.

[0053] In some embodiments, the first carrier 4 is provided with a plurality of first blind holes 401 and / or a plurality of first through holes 402; wherein, along the thickness direction of the substrate 1, the first blind holes 401 are recessed at least on the side of the first carrier 4 away from the substrate 1; the first through holes 402 penetrate the first carrier 4 in the thickness direction of the substrate 1.

[0054] Specifically, such as Figures 3-5As shown, for the chip packaging structure, the first chip 3 and the first carrier 4 can be fixedly connected by the first adhesive layer 501. By opening multiple first blind holes 401 and / or multiple first through holes 402 on the first carrier 4, the connection area between the first adhesive layer 501 and the first carrier 4 can be increased, the connection strength between the two can be enhanced, and the risk of the first chip 3 falling off can be reduced. At the same time, the first adhesive layer 501 is in contact with the multiple first blind holes 401 and / or first through holes 402 on the surface of the first carrier 4. Therefore, when the first chip 3 and the first carrier 4 are connected by the first adhesive layer 501, the first adhesive layer 501 can generate strain toward the first blind holes 401 and / or first through holes 402, so that the stress on the surface of the first adhesive layer 501 is concentrated toward the first blind holes 401 and / or first through holes 402, which helps to reduce the stress interference of the first adhesive layer 501 on the first chip 3.

[0055] For example, when the first carrier 4 has a plurality of first blind holes 401, the plurality of first blind holes 401 can be recessed on the side of the first carrier 4 away from the substrate 1; since the first chip 3 and the first carrier 4 are connected by the first adhesive layer 501, the first adhesive layer 501 can concentrate its surface stress in the first blind hole 401, thereby reducing the stress interference of the first adhesive layer 501 on the first chip 3.

[0056] For example, when the first carrier 4 has multiple first through holes 402, the multiple first through holes 402 can penetrate the first carrier 4 in the thickness direction of the substrate 1. Since the first chip 3 and the first carrier 4 are connected by the first adhesive layer 501, the first adhesive layer 501 can concentrate its surface stress in the first through holes 402, thereby reducing the stress interference of the first adhesive layer 501 on the first chip 3. In addition, the substrate 1 and the first carrier 4 are connected by the second adhesive layer 502. At this time, the second adhesive layer 502 can also concentrate the surface stress towards the first through holes 402 to reduce the degree of compression of the surface of the first carrier 4 by the second adhesive layer 502. At the same time, opening the first through holes 402 can enhance the contact area of ​​the connection area between the second adhesive layer 502 and the first carrier 4, improve the connection strength between the substrate 1 and the second carrier 7, and reduce the risk of the first carrier 4 and even the first chip 3 falling off.

[0057] In some embodiments, the coefficient of thermal expansion of the first carrier 4 is less than the coefficient of thermal expansion of the second adhesive layer 502.

[0058] Specifically, for the first carrier 4, the first carrier 4 is located between the second adhesive layer 502 and the first chip 3, and the first carrier 4 is connected to the surface of the substrate 1 by the second adhesive layer 502 with a viscosity greater than the first viscosity; therefore, the stress generated in the connection area between the second adhesive layer 502 and the substrate 1, and the connection area between the second adhesive layer 502 and the first carrier 4 is relatively large, that is, the stress of the second adhesive layer 502 is relatively large; at this time, by using a first carrier 4 with a relatively small expansion coefficient (such as a glass carrier) with a smaller expansion coefficient than the expansion coefficient of the first carrier 4, the stress of the second adhesive layer 502 can be blocked, and the stress of the second adhesive layer can be prevented from spreading to the first chip 3 and causing stress interference to it.

[0059] In addition, since the chip packaging structure generates heat during operation and is prone to heat accumulation, the expansion coefficient of the first carrier 4 is less than that of the second adhesive layer 502, which can reduce the deformation of the first carrier 4, thereby reducing the stress generated during deformation and further reducing its interference with the first chip 3.

[0060] In some embodiments, the ratio of the coefficient of thermal expansion of the first carrier 4 to the coefficient of thermal expansion of the first adhesive layer 501 ranges from 0.8 to 1.2.

[0061] Specifically, for the chip packaging structure, when the temperature changes, the volume of the first carrier 4 and the first adhesive layer 501 will change with the temperature. If the deformation difference between the first carrier 4 and the second adhesive layer 502 is large, it will cause a corresponding stress difference between the two, thereby causing stress interference to the first chip 3. Therefore, by controlling the ratio of the expansion coefficient of the first carrier 4 to the expansion coefficient of the first adhesive layer 501 within the range of 0.8-1.2, so that the expansion coefficients of the two are close, the deformation difference between the two at different temperatures can be reduced, thereby reducing the stress difference generated during the deformation process and preventing significant interference to the first chip 3.

[0062] For example, when the ratio of the expansion coefficient of the first carrier 4 to the expansion coefficient of the first adhesive layer 501 is 1:1, the two will have basically the same degree of deformation under the same temperature difference, and the resulting stress difference will be relatively small, so the interference to the first chip 3 will also be relatively low.

[0063] In some embodiments, the ratio of the coefficient of thermal expansion of the first adhesive layer 501 to the coefficient of thermal expansion of the first chip 3 is in the range of 0.8-1.2.

[0064] Specifically, for the chip packaging structure, when the temperature changes, the volume of the first chip 3 and the first adhesive layer 501 will change with the temperature. If the deformation difference between the first chip 3 and the first adhesive layer 501 is large, it will cause a corresponding stress difference between the two, thereby causing stress interference to the first chip 3. Therefore, by controlling the ratio of the expansion coefficient of the first adhesive layer 501 to the expansion coefficient of the first chip 3 within the range of 0.8-1.2, so that their expansion coefficients are close, the deformation difference between the two at different temperatures can be reduced, thereby reducing the stress difference generated during the deformation process and preventing significant interference to the first chip 3.

[0065] For example, when the ratio of the coefficient of thermal expansion of the first chip 3 to the coefficient of thermal expansion of the first adhesive layer 501 is 1:1, the two will have basically the same degree of deformation under the same temperature difference, and the resulting stress difference will be relatively small, so the degree of interference to the first chip 3 will also be relatively low.

[0066] In some embodiments, the first chip 3 is electrically connected to the substrate 1 and is also used to compensate the converted electrical signal and convert the compensated electrical signal into a digital signal for output.

[0067] Specifically, such as Figure 6 As shown, for chip packaging structure, when the chip packaging structure is a MEMS device, the first chip 3 in this embodiment can integrate the functions of MEMS chip and ASIC chip into one, forming a single chip structure. In addition to accurately measuring external pressure, the chip has a relatively small package size and relatively low cost, which is conducive to promoting the miniaturization design of MEMS devices.

[0068] For example, when the chip packaging structure provided in this embodiment is used, the first chip 3 can sense the external pressure through the opening 201 of the housing 2 to obtain the corresponding pressure signal, and after obtaining the pressure signal, convert the pressure signal into an electrical signal, and at the same time perform precise compensation on the electrical signal to obtain the compensated electrical signal. Then, the first chip 3 can convert the compensated electrical signal into a digital signal and output it, thereby accurately measuring the external pressure data.

[0069] In some embodiments, the first carrier 4 includes a second chip 6; the second chip 6 is located between the substrate 1 and the first chip 3, and both the second chip 6 and the first chip 3 are electrically connected to the substrate 1; the second chip 6 is used to receive and compensate the electrical signal output by the first chip 3, and convert the compensated electrical signal into a digital signal for output; a first adhesive layer 501 is provided between the second chip 6 and the first chip 3, and a second adhesive layer 502 is provided between the second chip 6 and the substrate 1.

[0070] Specifically, such as Figure 6As shown, the first carrier 4 includes a second chip 6 stacked with the first chip 3 in the thickness direction of the substrate 1, which can reduce the space occupied by the first chip 3 and the second chip 6 inside the housing 2. Both the first chip 3 and the second chip 6 are electrically connected to the substrate 1. Therefore, when the first chip 3 obtains an external pressure signal, it can convert the obtained pressure signal into an electrical signal and then transmit it to the second chip 6 through components such as the printed circuit on the substrate 1. When the second chip 6 receives the electrical signal output by the first chip 3, it can amplify and compensate the received electrical signal, convert the compensated electrical signal into a digital signal, and output it through the printed circuit on the substrate 1, thereby obtaining the pressure data of the external pressure.

[0071] More specifically, such as Figure 6 As shown, when the first carrier 4 includes the second chip 6, the first chip 3 and the second chip 6 are stacked on one side of the substrate 1 so that the first chip 3 is disposed away from the substrate 1 relative to the second chip 6. At this time, the first chip 3 and the second chip 6 can be fixedly connected by a first adhesive layer 501 formed by a low viscosity adhesive to reduce the stress interference of the first adhesive layer 501 on the first chip 3.

[0072] More specifically, the substrate 1 and the second chip 6 can be formed by a second adhesive with a viscosity greater than that of the first adhesive layer 501, such as a high-viscosity adhesive; when a high-viscosity adhesive is used, the second adhesive layer 502 can enhance the connection strength between the substrate 1 and the second chip 6, reducing the risk of the first chip 3 and the second chip 6 falling off the substrate 1.

[0073] Furthermore, since the second chip 6 is located between the second adhesive layer 502 and the first chip 3, and the second adhesive layer 502 is formed with a high-viscosity adhesive, the stress generated on the surface of the second adhesive layer 502 is relatively large, that is, the stress acting on the second chip 6 is relatively large. Since the second chip 6 can be an ASIC chip, its own coefficient of expansion is relatively small, which can prevent the stress of the second adhesive from spreading towards the first chip 3, and therefore will not cause stress interference to the first chip 3.

[0074] Furthermore, when the second chip 6 is used as the second carrier 7, the glass carrier of the chip packaging structure can be replaced or omitted, thereby simplifying the packaging structure, reducing cost investment, and also reducing the packaging volume, which helps to achieve miniaturization and lightweight design of the chip packaging structure.

[0075] In some embodiments, the second chip 6 has a functional area 601 and a non-functional area 602. The non-functional area 602 has a plurality of first blind holes 401 and / or a plurality of first through holes 402. The first blind holes 401 are recessed at least on the side of the second chip 6 away from the substrate 1 along the thickness direction of the substrate 1. The first through holes 402 penetrate the non-functional area 602 along the thickness direction of the substrate 1.

[0076] Specifically, such as Figure 7 As shown, taking the second chip 6 as an ASIC chip as an example, the second chip 6 has a functional area 601 and a non-functional area 602 surrounding the functional area 601. The functional area 601 is the main area of ​​the second chip 6, used to receive and compensate the electrical signals output by the first chip 3, and convert the compensated electrical signals into digital signals for output. The non-functional area 602 is used for encapsulation and heat dissipation of the functional area 601. More specifically, by opening multiple first blind vias 401 or multiple first through-holes 402 in the non-functional area 602, the contact area between the first adhesive layer 501 and the second chip 6 can be increased, thereby improving the connection strength between the first chip 3 and the second chip 6.

[0077] More specifically, by opening multiple first blind holes 401 and / or multiple first through holes 402 in the non-functional area 602, the stress distribution in the connection area between the first adhesive layer 501 and the second chip 6 can be changed, so that the stress on the surface of the first adhesive layer 501 is concentrated in the first blind holes 401 or the first through holes 402, thereby reducing the stress diffusion and stress interference of the first adhesive layer 501 on the first chip 3.

[0078] In some embodiments, the chip packaging structure further includes a second chip 6; the second chip 6 is located between the substrate 1 and the first carrier 4; both the second chip 6 and the first chip 3 are electrically connected to the substrate 1, the second chip 6 is used to receive and compensate the electrical signal output by the first chip 3, and convert the compensated electrical signal into a digital signal for output; a second adhesive layer 502 is provided between the substrate 1 and the second chip 6, and a third adhesive layer 503 is provided between the second chip 6 and the first carrier 4, the viscosity of the third adhesive layer 503 being greater than the viscosity of the first adhesive layer 501.

[0079] Specifically, such as Figure 8As shown, the chip packaging structure in this embodiment includes a second chip 6, which is located between the substrate 1 and the first carrier 4, so that the first chip 3, the first carrier 4, and the second chip 6 are stacked sequentially. The first chip 3 is used to acquire pressure signals and convert the acquired pressure signals into electrical signals for output. Therefore, the first chip 3 is positioned away from the substrate 1 relative to the first carrier 4 and is electrically connected to the substrate 1 to realize the acquisition of pressure signals and the output of electrical signals. In addition, the first chip 3 and the first carrier 4 are connected by a first adhesive layer 501 formed by a low-viscosity adhesive, which can reduce interference to the first chip 3, thereby ensuring that the first chip 3 has good sensitivity and excellent measurement performance.

[0080] More specifically, such as Figure 8 As shown, the substrate 1 and the second chip 6 can be connected by a second adhesive layer 502 with a viscosity greater than that of the first adhesive layer 501, which can enhance the connection strength between the substrate 1 and the second chip 6 to prevent the second chip 6 from falling off the surface of the substrate 1; and since the second chip 6 has a small coefficient of thermal expansion, the stress generated by the second adhesive layer 502 formed by the high viscosity adhesive will not diffuse toward the other side of the second chip 6, and therefore will not diffuse to the area where the first chip 3 is located, so as not to cause stress interference to the first chip 3.

[0081] Similarly, a third adhesive layer 503 is provided between the second chip 6 and the first carrier 4, and the viscosity of both the second adhesive layer 502 and the third adhesive layer 503 is greater than that of the first adhesive layer 501. That is, the third adhesive layer 503 is also formed with a high-viscosity adhesive, which can enhance the connection strength between the second chip 6 and the substrate 1. Furthermore, the expansion coefficient of the first carrier 4 located between the third adhesive layer 503 and the first adhesive layer 501 is relatively small, which can prevent the stress generated on the surface of the third adhesive layer 503 from spreading toward the first chip 3, so as to prevent stress interference to the first chip 3.

[0082] For example, the third adhesive layer 503 and the second adhesive layer 502 can be formed using the same high-viscosity adhesive to ensure that the formed adhesive layer has good adhesion, while also reducing the cost of the chip packaging structure.

[0083] In some embodiments, the chip packaging structure further includes a second carrier 7, which is located between the substrate 1 and the second chip 6; a second adhesive layer 502 is disposed between the substrate 1 and the second carrier 7, and a fourth adhesive layer 504 is disposed between the second chip 6 and the second carrier 7, wherein the viscosity of the fourth adhesive layer 504 is greater than the viscosity of the first adhesive layer 501.

[0084] Specifically, such as Figure 9As shown, for the chip packaging structure, a second carrier 7 is also provided between the substrate 1 and the second chip 6. The substrate 1 and the second carrier 7 can be connected by forming a second adhesive layer 502 with a high-viscosity adhesive to ensure the connection strength between the substrate 1 and the second carrier 7. Similarly, the second carrier 7 and the second chip 6 can be connected by forming a fourth adhesive layer 504 with a high-viscosity adhesive to ensure that the second carrier 7 and the second chip 6 also have good connection strength.

[0085] For example, the fourth adhesive layer 504 and the second adhesive layer 502 can be formed using the same high-viscosity adhesive to ensure good adhesion of the corresponding adhesive layers, while also reducing the cost of the chip packaging structure.

[0086] In some embodiments, the second carrier 7 is provided with a plurality of second blind holes 701 and / or a plurality of second through holes 702; wherein, along the thickness direction of the substrate 1, the second blind holes 701 are recessed on at least one side of the second carrier 7; and the second through holes 702 penetrate the second carrier 7 along the thickness direction of the substrate 1.

[0087] Specifically, such as Figure 9 , Figures 12-14 As shown, in the thickness direction of the substrate 1, one of the opposite sides of the second carrier 7 is connected to the substrate 1 through the second adhesive layer 502, and the other is connected to the second chip 6 through the fourth adhesive layer 504. At this time, by providing a plurality of second blind holes 701 and / or a plurality of second through holes 702 on the second carrier 7, the connection area between the second adhesive layer 502 and the second carrier 7, and / or between the second carrier 7 and the fourth adhesive layer 504 can be increased, thereby improving the connection strength between the substrate 1 and the second carrier 7, and / or between the second carrier 7 and the second chip 6.

[0088] For example, such as Figure 12 and Figure 13 As shown, when the second carrier 7 has multiple second blind holes 701, the multiple second blind holes 701 can be opened on the side of the second carrier 7 close to the substrate 1, or on the side of the second carrier 7 away from the substrate 1, or on opposite sides, depending on the actual needs of the product.

[0089] For example, such as Figure 14 As shown, when the second carrier 7 has multiple second through holes 702, the second through holes 702 penetrate the second carrier 7 in the thickness direction of the substrate 1, which can simultaneously increase the connection strength between the second adhesive layer 502 and the fourth adhesive layer 504 and the second carrier 7.

[0090] In some embodiments, the chip packaging structure further includes a second chip 6, which is disposed side by side with the first chip 3 on the same side of the substrate 1. The second chip 6 is electrically connected to the substrate 1 and the first chip 3 respectively. The second chip 6 is used to receive and compensate the electrical signal output by the first chip 3, and convert the compensated electrical signal into a digital signal for output. A fifth adhesive layer 505 is disposed between the second chip 6 and the substrate 1. The viscosity of the fifth adhesive layer 505 is greater than that of the first adhesive layer 501.

[0091] Specifically, such as Figure 10 As shown, the second chip 6 in the chip packaging structure can also be arranged side by side with the first chip 3 on the same side of the substrate 1, so that the first chip 3 and the second chip 6 are independent of each other on the surface of the substrate 1. This not only improves the heat dissipation effect of the chip packaging structure, but also reduces the interference between the first chip 3 and the second chip 6 and the assembly difficulty. The second chip 6 is electrically connected to the substrate 1 and the first chip 3 respectively. The first chip 3 can acquire pressure signals and convert the acquired pressure signals into electrical signals and transmit them to the second chip 6. When the second chip 6 receives the electrical signals sent by the first chip 3, it can perform precision compensation on the received electrical signals, and then convert the compensated electrical signals into digital signals and transmit the converted digital signals to the substrate 1 for further transmission through the printed circuit on the substrate 1, thereby obtaining the corresponding pressure data.

[0092] For example, the fifth adhesive layer 505 and the second adhesive layer 502 can be formed using the same high-viscosity adhesive to ensure good adhesion of the corresponding adhesive layers, while also reducing the cost of the chip packaging structure.

[0093] Furthermore, such as Figure 10 As shown, the second chip 6 and the substrate 1 are connected by a fifth adhesive layer 505 formed by an adhesive with a viscosity greater than that of the first adhesive layer 501. Therefore, a high-viscosity adhesive can be used to form the fifth adhesive layer 505 to improve the connection strength of the second chip 6 on the surface of the substrate 1 and to improve the resistance of the second chip 6 to interference factors.

[0094] In some embodiments, the chip packaging structure further includes a second carrier 7 located between the substrate 1 and the second chip 6; a fifth adhesive layer 505 is disposed between the second carrier 7 and the substrate 1, and a sixth adhesive layer 506 is disposed between the second carrier 7 and the second chip 6, wherein the viscosity of the sixth adhesive layer 506 is greater than the viscosity of the first adhesive layer 501.

[0095] Specifically, such as Figure 11As shown, for the chip packaging structure, a second carrier 7 can also be provided between the substrate 1 and the second chip 6; wherein, the substrate 1 and the second carrier 7 can be connected by forming a fifth adhesive layer 505 with a high viscosity adhesive to ensure the connection strength between the substrate 1 and the second carrier 7; similarly, the second carrier 7 and the second chip 6 can be connected by forming a sixth adhesive layer 506 with an adhesive with a viscosity greater than that of the first adhesive layer 501, that is, the sixth adhesive layer 506 is formed with a high viscosity adhesive, thereby ensuring the connection strength between the second carrier 7 and the second chip 6.

[0096] For example, the sixth adhesive layer 506 and the second adhesive layer 502 can be formed using the same high-viscosity adhesive to ensure good adhesion of the corresponding adhesive layers, while also reducing the cost of the chip packaging structure.

[0097] In some embodiments, the second carrier 7 is provided with a plurality of second blind holes 701 and / or a plurality of second through holes 702; wherein, along the thickness direction of the substrate 1, the second blind holes 701 are recessed on at least one side of the second carrier 7; and the second through holes 702 penetrate the second carrier 7 along the thickness direction of the substrate 1.

[0098] Specifically, such as Figures 11-14 As shown, in the thickness direction of the substrate 1, one of the opposite sides of the second carrier 7 is connected to the substrate 1 through the second adhesive layer 502, and the other is connected to the second chip 6 through the sixth adhesive layer 506. Therefore, by providing a plurality of second blind holes 701 and / or a plurality of second through holes 702 on the second carrier 7, the connection area between the second adhesive layer 502 and the second carrier 7, and / or between the second carrier 7 and the sixth adhesive layer 506 can be increased, thereby improving the connection strength between the substrate 1 and the second carrier 7, and / or between the second carrier 7 and the second chip 6.

[0099] For example, such as Figure 12 and Figure 13 As shown, when the second carrier 7 has multiple second blind holes 701, the multiple second blind holes 701 can be opened on the side of the second carrier 7 close to the substrate 1, or on the side of the second carrier 7 away from the substrate 1, or on opposite sides, depending on the actual needs of the product.

[0100] For example, such as Figure 14 As shown, when the second carrier 7 has multiple second through holes 702, the second through holes 702 penetrate the second carrier 7 in the thickness direction of the substrate 1, which can simultaneously increase the connection strength between the second adhesive layer 502 and the sixth adhesive layer 506 and the second carrier 7.

[0101] In a second aspect, this application provides a sensor module including a chip packaging structure as described in any embodiment of the first aspect. Therefore, the sensor module possesses all the advantages and beneficial effects of the chip packaging structure disclosed in the first aspect. Furthermore, the sensor module can be used in devices such as mobile terminals, aircraft, display devices, transportation vehicles, altimeters, and barometers, which will not be elaborated further here.

[0102] It should be noted that the above description describes some embodiments of this application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in a different order than that shown in the above embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0103] The various embodiments in this application are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0104] The description in this application is given for illustrative purposes and is not intended to be exhaustive or to limit the application to the forms disclosed. Many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described to better illustrate the principles and practical application of this application and to enable those skilled in the art to understand this application and design various embodiments with various modifications suitable for a particular purpose.

[0105] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this application (including the claims) is limited to these examples; within the framework of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the embodiments of this application as described above, which are not provided in the details for the sake of brevity.

[0106] Although this application has been described in conjunction with specific embodiments thereof, many substitutions, modifications and variations of these embodiments will be apparent to those skilled in the art from the foregoing description.

[0107] The embodiments of this application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the embodiments of this application should be included within the protection scope of this application.

Claims

1. A chip packaging structure, characterized in that, include: substrate; A housing is disposed on one side of the substrate and has an opening; as well as A first chip and a first carrier are located inside the housing; the first chip and the first carrier are stacked in the thickness direction of the substrate, and the first chip is used at least to acquire pressure signals and convert the acquired pressure signals into electrical signals for output; A first adhesive layer is disposed between the first chip and the first carrier, and a second adhesive layer is disposed between the substrate and the first carrier, wherein the viscosity of the second adhesive layer is greater than the viscosity of the first adhesive layer.

2. The chip packaging structure according to claim 1, characterized in that, The first carrier has multiple first blind holes and / or multiple first through holes; wherein, Along the thickness direction of the substrate, the first blind hole is recessed at least on the side of the first carrier away from the substrate; The first through hole penetrates the first carrier in the thickness direction of the substrate.

3. The chip packaging structure according to claim 1, characterized in that, The ratio of the expansion coefficients between the first carrier and the first adhesive layer ranges from 0.8 to 1.

2.

4. The chip packaging structure according to claim 1, characterized in that, The first chip is electrically connected to the substrate and is also used to compensate the converted electrical signal and convert the compensated electrical signal into a digital signal for output.

5. The chip packaging structure according to claim 1, characterized in that, The first carrier includes: The second chip is located between the substrate and the first chip, and both the second chip and the first chip are electrically connected to the substrate; the second chip is used to receive and compensate the electrical signal output by the first chip, and convert the compensated electrical signal into a digital signal for output. The first adhesive layer is disposed between the second chip and the first chip, and the second adhesive layer is disposed between the second chip and the substrate.

6. The chip packaging structure according to claim 5, characterized in that, The second chip has functional and non-functional areas, wherein the non-functional area has multiple first blind vias and / or multiple first through-holes; wherein, Along the thickness direction of the substrate, the first blind via is recessed at least on the side of the second chip away from the substrate; The first through-hole penetrates the non-functional area along the thickness direction of the substrate.

7. The chip packaging structure according to claim 1, characterized in that, Also includes: The second chip is located between the substrate and the first carrier; both the second chip and the first chip are electrically connected to the substrate. The second chip is used to receive and compensate the electrical signal output by the first chip, and convert the compensated electrical signal into a digital signal for output. The substrate and the second chip are provided with a second adhesive layer, and the second chip and the first carrier are provided with a third adhesive layer, the viscosity of the third adhesive layer being greater than the viscosity of the first adhesive layer.

8. The chip packaging structure according to claim 7, characterized in that, Also includes: The second carrier is located between the substrate and the second chip; A second adhesive layer is disposed between the substrate and the second carrier, and a fourth adhesive layer is disposed between the second chip and the second carrier, wherein the viscosity of the fourth adhesive layer is greater than that of the first adhesive layer.

9. The chip packaging structure according to claim 8, characterized in that, The second carrier has multiple second blind holes and / or multiple second through holes; wherein, Along the thickness direction of the substrate, the second blind hole is recessed on at least one side of the second carrier; The second through hole penetrates the second carrier along the thickness direction of the substrate.

10. The chip packaging structure according to claim 1, characterized in that, Also includes: The second chip is disposed side by side with the first chip on the same side of the substrate, and the second chip is electrically connected to both the substrate and the first chip. The second chip is used to receive and compensate the electrical signal output by the first chip, and convert the compensated electrical signal into a digital signal for output. A fifth adhesive layer is provided between the second chip and the substrate, and the viscosity of the fifth adhesive layer is greater than that of the first adhesive layer.

11. The chip packaging structure according to claim 10, characterized in that, Also includes: The second carrier is located between the substrate and the second chip; A fifth adhesive layer is disposed between the second carrier and the substrate, and a sixth adhesive layer is disposed between the second carrier and the second chip. The viscosity of the sixth adhesive layer is greater than that of the first adhesive layer.

12. The chip packaging structure according to claim 11, characterized in that, The second carrier has multiple second blind holes and / or multiple second through holes; wherein, Along the thickness direction of the substrate, the second blind hole is recessed on at least one side of the second carrier; The second through hole penetrates the second carrier along the thickness direction of the substrate.

13. A sensor module, characterized in that, Includes the chip packaging structure as described in any one of claims 1-12.

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