Substrate assembly, MEMS device, electronic device, and manufacturing method

Abstract

The application provides a substrate assembly, a MEMS device, an electronic device and a manufacturing method, and belongs to the technical field of micro-electro-mechanical systems. The substrate comprises a support layer, an insulating layer and a substrate. The substrate comprises a functional layer and an isolated island in an integrated structure. The support layer has a first through hole. The insulating layer comprises a first insulating part, a second insulating part and a second through hole, the functional layer, the first insulating part and the support layer are sequentially stacked in the thickness direction of the substrate assembly, the second insulating part is located inside the first through hole and is fixedly connected with the first insulating part, the second through hole penetrates through the first insulating part and the second insulating part, and the isolated island is filled in the inside of the second through hole and is electrically isolated from the support layer through the insulating layer. In this way, the substrate is a straight-through substrate with an isolated island, the manufacturing process of the isolated island is simple, and the preparation efficiency is high.

Description

Technical Field

[0001] This application relates to the field of microelectromechanical systems (MEMS) technology, and in particular to a substrate assembly, MEMS device, electronic device, and fabrication method. Background Technology

[0002] Currently, MEMS (microelectromechanical system) devices include a substrate, a vibrating component, and a conductive structure. The vibrating component is movably connected to the substrate, and the conductive structure penetrates the substrate and is electrically connected to the vibrating component. In related technologies, the fabrication process of the isolated island of the conductive structure involves first performing deep silicon etching on the silicon substrate layer to form annular grooves, and then filling the annular grooves with an insulating layer to obtain an isolated island electrically isolated from the silicon substrate. Therefore, the fabrication process for the isolated island involves numerous steps and is time-consuming, resulting in low fabrication efficiency. Summary of the Invention

[0003] This application provides a substrate assembly, a MEMS device, an electronic device, and a fabrication method. The substrate of the substrate assembly is a through-type substrate with self-contained isolation islands. The fabrication process of the isolation islands is simple and has high fabrication efficiency.

[0004] In a first aspect, embodiments of this application provide a substrate assembly, which includes a substrate, an insulating layer, and a support layer. The substrate includes a functional layer and an isolation island of an integral structure. The support layer has a first through-hole. The insulating layer includes a first insulating portion, a second insulating portion, and a second through-hole. The functional layer, the first insulating portion, and the support layer are sequentially stacked along the thickness direction of the substrate assembly. The second insulating portion is located inside the first through-hole and is fixedly connected to the first insulating portion. The second through-hole penetrates both the first and second insulating portions. The isolation island fills the interior of the second through-hole and is electrically isolated from the support layer by the insulating layer.

[0005] In existing technologies, to form small-sized conductive structures, top vias penetrating the top silicon layer and buried insulating layer are required on an SOI (silicon-on-insulator) substrate. Conductive material is then filled into these vias to form anchor points. Next, isolation islands for conduction are fabricated on the substrate silicon of the SOI substrate, forming a vertically connected electrical interconnect structure with the anchor points. The fabrication process for these isolation islands involves deep silicon etching of the substrate silicon layer to form annular trenches, followed by filling the trenches with an insulating layer to obtain an isolation island electrically isolated from the silicon substrate. This process involves numerous steps and is time-consuming, resulting in low fabrication efficiency. Furthermore, when the depth-to-width ratio of the annular trench is high, the trenching efficiency is low, requiring multiple fillings of the insulating layer, which further reduces filling efficiency. Therefore, high aspect ratio annular trenches lead to low trenching efficiency and low insulating layer filling efficiency, further reducing fabrication efficiency and increasing cost, making it difficult to fabricate isolation islands for high-density interconnect scenarios.

[0006] In this embodiment, the substrate manufacturing process can involve first providing a substrate, then etching the substrate to form an integrated isolation island and functional layer. The isolation island and the functional layer above it constitute an electrical interconnect structure, which is part of the substrate. Therefore, the isolation island fabrication process is simple and improves the fabrication efficiency. Furthermore, compared to existing technologies, it eliminates the need for top vias to form anchor points, saving process steps, improving the fabrication efficiency of the electrical interconnect structure, facilitating the realization of high-density electrical interconnect structures, reducing the cost of MEMS devices, and improving the yield and consistency of MEMS devices.

[0007] Furthermore, by forming an insulating structure on the surface of the substrate, covering the surface of the isolation island and the exposed area of ​​the side of the functional layer connected to the isolation island, an epitaxial layer is then formed on the side of the insulating structure away from the substrate. Finally, the epitaxial layer and the insulating layer are thinned sequentially until the isolation island is exposed, resulting in an insulating layer and a support layer. Therefore, forming an insulating layer on the surface of a substrate with isolation islands is a simple, low-cost process that improves yield and consistency, and is easy to fabricate isolation islands for high-density interconnect scenarios.

[0008] In some possible implementations, the functional layer is made of the same material as the isolated island.

[0009] This reduces the difficulty of integrating the functional layer and the isolation islands into a single structure and helps improve the substrate fabrication efficiency.

[0010] In some possible implementations, both the isolation islands and the functional layers are made of monocrystalline silicon.

[0011] In this implementation, since single-crystal silicon has the characteristics of high purity and uniformity, good mechanical properties and elastic modulus, and good thermal stability, the isolation islands and functional layers are supported by single-crystal silicon, which can realize high-performance MEMS devices.

[0012] In some possible implementations, the lattice constants of the functional layer and the isolation island are consistent. This allows for lattice matching between the functional layer and the isolation island, both of which are continuous monocrystalline silicon with no internal lattice dislocations, further enhancing the performance of MEMS devices.

[0013] In some possible implementations, the support layer is made of polycrystalline silicon.

[0014] Typically, the substrate material is silicon. In this implementation, both the support layer and the substrate are made of silicon, which can further improve the performance, reliability, and manufacturing efficiency of MEMS devices, and help to realize high-performance, low-cost MEMS devices.

[0015] In some possible implementations, the ratio of the depth of the second insulating portion in the thickness direction of the substrate assembly to the width of the second insulating portion in the radial direction of the second through hole is greater than or equal to 10.

[0016] In this implementation, since the isolation island and the functional layer are an integral structure, the fabrication efficiency of the insulating layer is improved by directly growing the insulating layer on the surface of the substrate. This enables the realization of a second insulating part with a high aspect ratio, while reducing the size of the conductive structure and achieving high-density interconnection.

[0017] In some possible implementations, the ratio of the depth to the width of the second insulating portion is greater than or equal to 20, and the ratio of the depth to the width of the second insulating portion is less than or equal to 50.

[0018] In this implementation, limiting the depth-to-width ratio of the second insulating portion to between 20 and 50 enables further high-density interconnection.

[0019] In some possible implementations, the insulating layer is made of silicon dioxide, silicon nitride, or silicon oxynitride.

[0020] Typically, the support layer and substrate are made of silicon. In this implementation, the insulating layer is made of silicon-containing material, which can further improve the performance, reliability and manufacturing efficiency of MEMS devices, and help to realize high-performance, low-cost MEMS devices.

[0021] In some possible implementations, the first insulating part and the second insulating part are an integral structure.

[0022] In this implementation, an insulating layer can be formed on the surface of the substrate by deposition, which reduces the difficulty of connecting the substrate and the insulating layer and improves the fabrication efficiency of the insulating layer.

[0023] In some possible implementations, the first insulating portion includes a plurality of insulator layers stacked along the thickness direction of the substrate assembly.

[0024] In this implementation, the first insulating part is a multi-layer structure, which can provide better electrical isolation, enhance mechanical strength, reduce stress concentration, and help improve device performance and reliability.

[0025] Secondly, embodiments of this application provide a MEMS device, which includes a substrate assembly as described in any of the first aspects. The substrate assembly further includes a third through-hole that penetrates a first insulating portion of an insulating layer along the thickness direction of the substrate assembly and exposes a portion of the surface of a support layer.

[0026] In some possible implementations, the MEMS device also includes a cover plate located on the side of the functional layer of the substrate away from the support layer. The functional layer includes anchor points, a movable support structure, and an anchor point electrically connected to an isolation island, forming an electrical interconnect with the island. The movable structure is electrically connected to the anchor point, and both the anchor point and the movable structure are electrically isolated from the support structure. The support structure is fixedly connected to the cover plate and serves to support the cover plate. The orthographic projection of the movable structure onto the cover plate lies inside the orthographic projection of the third via onto the cover plate, thus suspending the movable structure above the insulating layer.

[0027] In the fabrication process of MEMS devices, a movable structure is first fabricated on a substrate assembly with isolated islands. Then, the insulating layer beneath the movable structure is etched away to suspend the movable structure above the insulating layer. Finally, a cover plate and a functional layer are bonded together. This demonstrates that the fabrication steps for MEMS devices are simple. Compared to existing technologies that fabricate MEMS devices on SOI substrate assemblies, this reduces the number of process steps, improves fabrication efficiency, lowers production costs, and increases production efficiency and yield.

[0028] In addition, the anchor point is located between the supporting structure and the movable structure, and there is an isolation groove between the anchor point and the supporting structure to separate the movable structure from the supporting structure, thereby achieving electrical isolation between the supporting structure and the anchor point and the movable structure. Furthermore, the third through hole is used to avoid the movable structure, allowing the movable structure to be separated from the insulating layer, ensuring that the movable structure is suspended and can move relative to the insulating layer to realize the device function.

[0029] In some possible implementations, a groove is provided on the side of the cover plate near the functional layer, and the functional layer and the inner wall of the groove form an airtight chamber, with the movable structure suspended in the airtight chamber.

[0030] In this implementation, a groove is provided on the cover plate, which allows the movable structure to be suspended above the cover plate, ensuring that the movable structure can move relative to the cover plate and realize the function of the device.

[0031] In some possible implementations, the MEMS device further includes a passivation layer and substrate electrode leads. The passivation layer is located on the side of the substrate assembly away from the cover plate and has a window exposing the isolation island. At least a portion of the substrate electrode leads is disposed within the window, and the substrate electrode leads are electrically connected to the isolation island.

[0032] In this implementation, the substrate electrode leads, electrical interconnect structure, and movable structure form a vertical electrical connection to enable the MEMS device to be electrically connected to other circuit structures, such as the MEMS device being electrically connected to the circuit board via the electrode leads.

[0033] In some possible implementations, the MEMS device is a high-density interconnect device, which includes multiple MEMS device microstructures arranged in an array. Each MEMS device microstructure includes a movable structure and multiple electrical interconnect structures. Any two electrical interconnect structures are electrically isolated, and the isolation islands of each electrical interconnect structure are electrically isolated from the support layer through an insulating layer.

[0034] In the embodiments of this application, since the isolation island and the functional layer are an integral structure, the size of the electrical interconnect structure can be made small enough, the fabrication efficiency of the electrical interconnect structure and the isolation island is high, it can be applied to high-density interconnect devices, and the fabrication efficiency and production cost of high-density interconnect devices are high.

[0035] Thirdly, embodiments of this application provide an electronic device, which includes a circuit board and a MEMS device as described in any of the second aspects, wherein the MEMS device is electrically connected to the circuit board.

[0036] Fourthly, embodiments of this application provide a method for fabricating a MEMS device, the method comprising:

[0037] Fabricating a substrate assembly, the substrate assembly including a support layer, an insulating layer, and a substrate; wherein, fabricating the substrate assembly includes:

[0038] Fabricate a substrate, which includes a functional layer and isolation islands;

[0039] An insulating structure is formed, which covers the surface of the isolated island and the exposed area of ​​the side surface where the functional layer connects to the isolated island;

[0040] An epitaxial layer is grown on the surface of the insulating structure away from the substrate;

[0041] The epitaxial layer and the insulating structure are thinned sequentially until the isolation islands are exposed to form the support layer and the insulating layer.

[0042] In some possible implementations, the substrate is fabricated, including:

[0043] Provide substrate;

[0044] The substrate is etched to form a substrate.

[0045] In some possible implementations, forming the insulating structure includes:

[0046] Insulating structures are formed through chemical vapor deposition, physical vapor deposition, or thermal growth.

[0047] In some possible implementations, after the substrate assembly is fabricated, the fabrication method also includes:

[0048] The functional layer of the substrate is etched to form a movable structure;

[0049] A third through-hole is formed through the insulating layer to suspend the movable structure in the insulating layer, thus obtaining a MEMS structure.

[0050] The functional layer of the MEMS structure is bonded to a cover plate with grooves, and the functional layer and the inner wall of the grooves form an airtight cavity, so that the movable structure is suspended in the cover plate.

[0051] In some possible implementations, after forming the airtight chamber, the fabrication method also includes:

[0052] A passivation layer with a window is formed on the side of the support layer away from the substrate, with the window exposing the isolation island of the substrate;

[0053] Substrate electrode leads that are electrically connected to the isolated island are formed within the window. Attached Figure Description

[0054] Figure 1 An exploded view of an electronic device provided in an embodiment of this application;

[0055] Figure 2 This is a cross-sectional schematic diagram of a MEMS device in related technologies;

[0056] Figure 3 A cross-sectional schematic diagram of a MEMS device provided in an embodiment of this application;

[0057] Figure 4a A top view schematic diagram of a substrate assembly provided in an embodiment of this application;

[0058] Figure 4b for Figure 4a A cross-sectional view along the AA direction;

[0059] Figure 5 for Figure 3A cross-sectional schematic diagram of the substrate assembly and cover plate fitting together;

[0060] Figure 6 A cross-sectional schematic diagram of the microstructure of another MEMS device provided in this application embodiment;

[0061] Figure 7 This is a schematic diagram of step one of the fabrication process of a substrate assembly provided in an embodiment of this application;

[0062] Figure 8 This is a schematic diagram of step two in the fabrication process of a substrate assembly provided in an embodiment of this application;

[0063] Figure 9 This is a schematic diagram of step three in the fabrication process of a substrate assembly provided in an embodiment of this application;

[0064] Figure 10 This is a schematic diagram of step four in the fabrication process of a substrate assembly provided in an embodiment of this application;

[0065] Figure 11 This is a schematic diagram of step five in the fabrication process of a substrate assembly provided in an embodiment of this application;

[0066] Figure 12 This is a schematic diagram of step one of the fabrication processes of a MEMS device provided in an embodiment of this application;

[0067] Figure 13 This is a schematic diagram of step two in the fabrication process of a MEMS device provided in an embodiment of this application;

[0068] Figure 14 This is a schematic diagram of step three in the fabrication process of a MEMS device provided in an embodiment of this application;

[0069] Figure 15 This is a schematic diagram of step four in the fabrication process of a MEMS device provided in an embodiment of this application.

[0070] Explanation of reference numerals in the attached figures:

[0071] 100. Display screen;

[0072] 200, Mid-frame;

[0073] 300. Circuit board assembly;

[0074] 310. Circuit board;

[0075] 320. MEMS devices;

[0076] 400, battery;

[0077] 500, back cover;

[0078] 10. Cover plate; 11. Groove;

[0079] 20. Substrate assembly;

[0080] 21. Support layer; 211. First through hole;

[0081] 22. Insulating layer; 221. First insulating portion; 222. Second insulating portion; 223. Second through hole;

[0082] 23. Substrate; 23a. Electrical interconnect structure;

[0083] 231. Functional layer; 231a. Anchor point; 231b. Movable structure; 231c. Supporting structure;

[0084] 241. First movable comb tooth; 242. Second movable comb tooth; 243. First fixed comb tooth; 244. Second fixed comb tooth; 245. Reflector; 246. First cantilever beam; 247. Second cantilever beam;

[0085] 232. Isolated island;

[0086] 25. Third through hole;

[0087] 30. Passivation layer;

[0088] 40. Substrate electrode leads;

[0089] 50. Airtight chamber. Detailed Implementation

[0090] The terminology used in the implementation section of this application is for the purpose of explaining specific embodiments of this application only, and is not intended to limit this application.

[0091] This application provides an electronic device, which may include, but is not limited to, mobile phones, tablet computers, laptop computers, personal computers, laptops, drones, game controllers, base stations, true wireless stereo (TWS) headphones, and other smart devices. This application does not impose any special limitations on the specific form of the aforementioned electronic device. For ease of explanation, the following description uses a mobile phone as an example.

[0092] Figure 1 An exploded view of an electronic device provided in an embodiment of this application.

[0093] like Figure 1As shown, the electronic device may include a display screen 100, a middle frame 200, a back cover 500, a battery 400, and a circuit board assembly 300. The back cover 500 and the display screen 100 are located on opposite sides of the middle frame 200 and are fixedly connected to the middle frame 200. The back cover 500 and the middle frame 200 can form an accommodating space for accommodating components such as the circuit board assembly 300, the battery 400, and the camera module.

[0094] Understandable Figure 1 The electronic device is shown only schematically, and the actual shape, size, location, and construction of these components are not subject to change. Figure 1 The limitations. In some other examples, the electronic device may also not include a display screen 100.

[0095] like Figure 1 As shown, the circuit board assembly 300 includes a circuit board 310 and electronic devices. There are multiple electronic devices, each disposed on the circuit board 310, and at least one electronic device is a MEMS (micro electro-mechanical system) device.

[0096] MEMS devices 320 may include, but are not limited to, MEMS resonators, MEMS gyroscopes, MEMS accelerometers, MEMS array devices (such as optical micromirror array devices), MEMS oscillators, MEMS OXC (micro-electro-mechanical systems optical cross connect), MEMS crystal oscillators (micro-electro-mechanical systems crystal oscillators), etc.

[0097] Many high-precision MEMS devices, such as MEMS resonators, MEMS gyroscopes, and MEMS accelerometers, require operation in a high-vacuum, low-stress environment. MEMS vacuum packaging can meet these requirements, and it includes device-level packaging and wafer-level packaging. In these vacuum packaging solutions, the internal and external electrical connections of MEMS devices can easily affect the reliability of the vacuum packaging structure. Therefore, the way the substrate electrode leads of the vacuum packaging structure are led out is very important.

[0098] Figure 2 This is a cross-sectional schematic diagram of a MEMS device in related technologies.

[0099] In related technologies, such as Figure 2As shown, the MEMS device 600 includes an SOI (silicon on insulator) substrate, anchor points 620, an annular groove 630, a top via 640, an insulating layer 650, isolation islands 660, a passivation layer 670, a cover plate 680, and substrate electrode leads 690. The SOI substrate 610 is located between the cover plate 680 and the passivation layer 670. SOI substrate 610 includes a top silicon layer 611, a buried oxide layer 612, and a substrate silicon layer 613 stacked together. The top silicon layer 611 has a comb-like structure. An annular groove 630 is an annular via penetrating the substrate silicon layer 613. An insulating layer 650 is disposed inside the annular groove 630. An isolation island 660 is located inside the insulating layer 650 and is electrically isolated from the substrate silicon layer 613 through the insulating layer 650. A top via 640 penetrates the top silicon layer 611 and the buried oxide layer 612 and exposes the isolation island 660. An anchor point 620 fills the annular groove 630 and is electrically in contact with the isolation island 660. A passivation layer 670 has a window exposing the isolation island 660. A substrate electrode lead 690 is located on the side of the isolation island 660 away from the anchor point 620 and is electrically connected to the isolation island 660 through the window. Thus, the anchor point 620 and the isolation island 660 form an electrical interconnect structure electrically connected to the substrate electrode lead 690, realizing electrode lead-out.

[0100] In one implementation, Figure 2 The fabrication method of the MEMS device 600 shown includes the following specific steps:

[0101] Step 1: Provide an SOI silicon wafer, which includes a top silicon layer 611, a buried oxide layer 612, and a substrate silicon layer 613. Deeply etch the top silicon layer 611 and the buried oxide layer 612 using a deep reactive-ion etching (DRIE) process to form a top via 640. During the fabrication of the top via 640, an oxide layer will grow on the hole walls of the top via 640.

[0102] Step 2: After removing the excess oxide layer on the wall of the top via 640, deposit conductive material on the surface of the top silicon 611 and fill the top via 640.

[0103] Step 3: Remove excess conductive material from the surface of the top silicon 611 by chemical mechanical polishing (CMP) to achieve planarization and form anchor points 620 in the top via 640.

[0104] Step 4: The top silicon 611 between anchor points 620 is deeply etched using the DRIE process to form a comb structure. Then, the buried oxide layer 612 below the comb structure is etched away using a hydrofluoric acid (HF) vapor phase etching process to release the comb structure and obtain a wafer-level MEMS structure.

[0105] Step 5: Etch grooves on the lower surface of the cover plate 680 wafer to obtain the wafer cover plate 680.

[0106] Step 6: Perform high-vacuum bonding between the wafer-level MEMS structure and the wafer cover plate 680.

[0107] Step 7: Deeply etch the lower surface of the substrate silicon 613 on both sides of any anchor point 620 using the DRIE process to form multiple annular grooves 630. Grow an insulating layer 650 in the annular grooves 630. The portion of the substrate silicon 613 whose sidewalls are covered by the insulating layer 650 forms an isolation island 660. The isolation island 660 is electrically isolated from the surrounding substrate silicon 613 through the insulating layer 650. The isolation island 660 forms a vertical electrical connection with the anchor point 620.

[0108] Step 8: Form a passivation layer 670 located below the isolation island 660, open a window at the passivation layer 670 on the lower surface of the isolation island 660, and then fabricate a substrate electrode lead 690 electrically connected to the isolation island 660 in the window.

[0109] As can be seen from the fabrication process of MEMS device 600, the process of fabricating MEMS devices on SOI substrates is complex, with low production efficiency and high production cost.

[0110] Furthermore, the fabrication process of the isolation island 660 involves first creating a high aspect ratio annular trench 630 on the silicon substrate 613, and then filling the annular trench 630 with an insulating layer 650 to form an isolation island 660 electrically isolated from the silicon substrate 613. Due to the high aspect ratio of the annular trench 630 (e.g., if the silicon substrate 613 is 200µm thick and the annular trench 630 is 10µm wide, resulting in an aspect ratio of 20:1), the trenching time for the annular trench 630 is long, leading to low trenching efficiency and high cost. Additionally, the high aspect ratio of the annular trench 630 necessitates multiple filling stages for the insulating layer 650, resulting in a long filling time and low filling efficiency for the insulating layer 650. Therefore, it can be seen that due to the low grooving efficiency of the annular groove 630 and the low filling efficiency of the insulating layer 650, the fabrication efficiency of the isolation island 660 is low, the production cost is high, and it is difficult to fabricate the isolation island 660 for high-density interconnect devices (such as MEMS micromirrors).

[0111] Furthermore, the fabrication process of the electrical interconnect structure is as follows: first, the top silicon layer 611 and the buried oxide layer 612 are etched; then, the oxide layer on the wall of the top via 640 is removed; next, conductive material is filled into the top via 640; finally, excess conductive material on the surface of the top silicon layer 611 is removed, and anchor points 620 are formed in the top via 640. The anchor points 620 are electrically connected to the isolation islands 660 to form the electrical interconnect structure. Therefore, the fabrication process of the electrical interconnect structure involves many steps, resulting in low fabrication efficiency and high production costs, making it impossible to fabricate high-density electrical interconnect structures.

[0112] Figure 3 This is a cross-sectional schematic diagram of a MEMS device provided in an embodiment of this application. Figure 4a This is a top view schematic diagram of a substrate provided in an embodiment of this application. Figure 4b for Figure 4a A cross-sectional view along the AA direction. Wherein, Figure 4a This is used to illustrate the relationship between the isolation island 232 and the second insulating portion 222 and the first through hole 211 and the second through hole 223, and does not constitute a limitation on the specific structure of the substrate assembly 20.

[0113] In view of this, such as Figure 3 and Figure 4b As shown in the embodiments of this application, a substrate assembly 20, a MEMS device 320, and a fabrication method are also provided. The substrate assembly 20 includes a substrate 23, which includes an integrally structured functional layer 231 and an isolation island 232. That is, the functional layer 231 and the isolation island 232 are integrally formed, and the isolation island 232 and the functional layer 231 are electrically interconnected. The isolation island 232 and the portion of the functional layer 231 above it constitute an electrical interconnection structure 23a. The electrical interconnection structure 23a is part of the substrate 23. Therefore, in the fabrication process of the electrical interconnection structure 23a, it is not necessary to open through-holes and annular grooves through the functional layer 231 and the insulating layer 22 to fabricate the electrical interconnection structure, which saves process steps, reduces the fabrication cost of the electrical interconnection structure 23a, and improves the fabrication efficiency, yield, and consistency of the electrical interconnection structure 23a, thereby reducing the cost of the MEMS device 320. In addition, the process of forming an insulating layer 22 on the surface of a substrate 23 with isolation islands 232 is simple, low-cost, improves yield and consistency, and makes it easy to fabricate isolation islands 232 for high-density interconnect scenarios (such as optical micromirror array devices).

[0114] The substrate assembly 20, MEMS device 320, and fabrication method provided in the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0115] like Figure 3As shown, the MEMS device 320 includes a cover plate 10, a substrate assembly 20, a passivation layer 30, and substrate electrode leads 40. The passivation layer 30 and the substrate electrode leads 40 are both located on the side of the substrate assembly 20 away from the cover plate 10. That is, the passivation layer 30 and the cover plate 10 are located on opposite sides of the substrate assembly 20 and are fixedly connected to it. The substrate assembly 20 includes an electrically interconnected structure 23a and a movable structure 231b. The passivation layer 30 has a window exposing the electrically interconnected structure 23a. At least a portion of the substrate electrode leads 40 is disposed within the window and is electrically connected to the electrically interconnected structure 23a. The movable structure 231b, the electrically interconnected structure 23a, and the substrate electrode leads 40 form a vertical electrical connection, enabling the MEMS device 320 to be electrically connected to other circuit structures, such as a circuit board 310 connected to the substrate electrode leads 40.

[0116] The substrate electrode lead 40 can be made of conductive materials such as metals or metal composites, such as aluminum, or other materials such as copper.

[0117] The passivation layer 30 is mainly used to protect the internal structure from the influence of the external environment and to ensure the long-term reliability and performance stability of the device. The material of the passivation layer 30 may include one or more of silicon nitride, silicon oxide, silicon oxynitride, and silicon dioxide.

[0118] See Figure 4b As shown, the substrate assembly 20 includes a support layer 21, an insulating layer 22, and a substrate 23. Among them, combined with... Figure 4a and Figure 4b It is known that the support layer 21 has a first through-hole 211. The insulating layer 22 includes a first insulating portion 221, a second insulating portion 222, and a second through-hole 223. The first insulating portion 221 and the second insulating portion 222 are along the thickness direction of the substrate assembly 20 (e.g., ...). Figure 4b The substrate assembly 20 is stacked in the Z-direction, with the second insulating portion 222 located inside the first through-hole 211 and fixedly connected to the first insulating portion 221. The second through-hole 223 is along the thickness direction of the substrate assembly 20 (e.g., in the Z-direction). Figure 4b (in the Z direction) penetrating the first insulating part 221 and the second insulating part 222.

[0119] See Figure 4bAs shown, substrate 23 includes a functional layer 231 and isolated islands 232 of a monolithic structure. It should be noted that in the semiconductor field, a monolithic structure typically refers to the integration of multiple components or functional units of a semiconductor device into an indivisible integral structure through specific processes and technologies to achieve specific electrical functions and performance advantages. From a materials and process perspective: through specific growth or etching processes, a monolithic structure with specific structures and functions is formed on a single semiconductor substrate.

[0120] See Figure 4b As shown, the functional layer 231 is located between the cover plate 10 and the first insulating portion 221 and is fixedly connected to the cover plate 10. The functional layer 231, the first insulating portion 221 and the support layer 21 are along the thickness direction of the substrate assembly 20 (e.g., Figure 4b The isolation island 232 is fixedly connected to the functional layer 231 in the Z-direction. The isolation island 232 fills the interior of the second through-hole 223. The isolation island 232 is electrically isolated from the support layer 21 through the insulating layer 22. The isolation island 232 and part of the functional layer 231 above it form an electrical interconnection structure 23a. Figure 3 As shown, the window of the passivation layer 30 exposes the isolation island 232, so that the substrate electrode lead 40 is electrically connected to the isolation island 232, thereby realizing the electrical interconnection structure 23a and the substrate electrode lead 40 being electrically connected.

[0121] In existing technologies, to form small-sized conductive structures, top vias penetrating the top silicon layer and buried insulating layer are required on an SOI (silicon-on-insulator) substrate. Conductive material is then filled into these vias to form anchor points. Next, isolation islands for conduction are fabricated on the substrate silicon of the SOI substrate, forming a vertically connected electrical interconnect structure with the anchor points. The fabrication process for these isolation islands involves deep silicon etching of the substrate silicon layer to form annular trenches, followed by filling the trenches with an insulating layer to obtain an isolation island electrically isolated from the silicon substrate. This process involves numerous steps and is time-consuming, resulting in low fabrication efficiency. Furthermore, when the depth-to-width ratio of the annular trench is high, the trenching efficiency is low, requiring multiple fillings of the insulating layer, which further reduces filling efficiency. Therefore, high aspect ratio annular trenches lead to low trenching efficiency and low insulating layer filling efficiency, further reducing fabrication efficiency and increasing cost, making it difficult to fabricate isolation islands for high-density interconnect scenarios.

[0122] In this embodiment, the substrate 23 can be manufactured by first providing a substrate and then etching it to form an integral isolation island 232 and a functional layer 231. The isolation island 232 and the portion of the functional layer 231 above it constitute an electrical interconnect structure 23a, which is part of the substrate 23. Therefore, the fabrication process of the isolation island 232 is simple, improving its fabrication efficiency. Furthermore, compared to existing technologies, it eliminates the need for top vias to form anchor points and annular grooves to form the isolation island 232, saving process steps, improving the fabrication efficiency of the electrical interconnect structure 23a, and facilitating the realization of high-density electrical interconnect structures 23a. This reduces the cost of the MEMS device 320 and improves its yield and consistency.

[0123] Furthermore, by forming an insulating structure on the surface of substrate 23, covering the surface of isolation island 232 and the exposed area of ​​the side surface where functional layer 231 connects to isolation island 232, an epitaxial layer is then formed on the side surface of the insulating structure away from substrate 23. Finally, the epitaxial layer and insulating layer 22 are thinned sequentially until isolation island 232 is exposed, resulting in insulating layer 22 and support layer 21. Therefore, the process of forming insulating layer 22 on the surface of substrate 23 with isolation island 232 is simple, low-cost, improves yield and consistency, and facilitates the fabrication of isolation island 232 for high-density interconnect scenarios.

[0124] Figure 5 for Figure 3 A cross-sectional schematic diagram of the substrate assembly and cover plate in operation.

[0125] See Figure 5 As shown, the functional layer 231 includes an anchor point 231a, a movable structure 231b, and a support structure 231c. The orthographic projections of any two parts of the anchor point 231a, the movable structure 231b, and the support structure 231c onto the cover plate 10 do not coincide. Along a direction perpendicular to the thickness direction of the substrate assembly 20, the anchor point 231a is located between the support structure 231c and the movable structure 231b. Along the thickness direction of the functional layer 231 (e.g., along the thickness direction of the substrate assembly 20), the anchor point 231a is located between the support structure 231c and the movable structure 231b. Figure 5 (In the Z-direction), anchor point 231a is located directly above isolation island 232. Anchor point 231a and the orthographic projection of isolation island 232 on cover plate 10 coincide. Anchor point 231a is fixedly connected to isolation island 232 and electrically connected, forming an electrical interconnection structure 23a. Movable structure 231b is electrically connected to anchor point 231a, thereby connecting movable structure 231b to electrical interconnection structure 23a. Both anchor point 231a and movable structure 231b are electrically isolated from support structure 231c. Support structure 231c is fixedly connected to cover plate 10 and supports cover plate 10.

[0126] Among them, such as Figure 5 As shown, by providing an isolation groove between the support structure 231c and the anchor point 231a, both the anchor point 231a and the movable structure 231b are electrically isolated from the support structure 231c. Of course, in some embodiments, the isolation groove between the support structure 231c and the anchor point 231a can also be filled with an insulating material, such as silicon dioxide, to achieve electrical isolation.

[0127] The specific structure of the movable structure 231b is not limited here. In some embodiments, the MEMS device 320 is a MEMS accelerometer, and the movable structure 231b includes an acceleration measurement component, such as... Figure 5 As shown, the acceleration measurement component includes a first fixed comb tooth 243, a second fixed comb tooth 244, a first movable comb tooth 241, and a second movable comb tooth 242. The first fixed comb tooth 243 and the second fixed comb tooth 244 are located between the first movable comb tooth 241 and the second movable comb tooth 242. There is an isolation groove (e.g., between the first fixed comb tooth 243 and the second fixed comb tooth 244) between them. Figure 5 (As shown in G) is isolated. The first movable comb tooth 241 and the second fixed comb tooth 244 form a set of comb teeth and are isolated together. Figure 5 The electrical interconnection structure 23a on the left side is connected, and the second movable comb tooth 242 and the first fixed comb tooth 243 form another set of comb teeth and are connected with it. Figure 5 The electrical interconnect structure 23a on the right side of the middle is connected, and the two sets of comb teeth detect the change in capacitance by changing the distance between them, thus realizing the function of the device.

[0128] Figure 6 This is a cross-sectional schematic diagram of the microstructure of another MEMS device provided in an embodiment of this application.

[0129] In other embodiments, the MEMS device 320 may also be a high-density interconnect device, such as a MEMS array device. Exemplarily, the MEMS array device is an optical micro-mirror array device, also commonly referred to as a micromirror array or MEMS micromirror array. The optical micromirror array device includes multiple interconnected MEMS device microstructures, each including a movable structure 231b and multiple electrical interconnect structures 23a. Any two electrical interconnect structures 23a are electrically isolated, and the isolation islands 232 of each electrical interconnect structure 23a are electrically isolated from the support layer 21 through an insulating layer 22.

[0130] Typically, MEMS devices contain a large number of microstructures, such as 200 microstructures within a 2*2mm area, each including 4 to 5 electrical interconnect structures 23a, totaling over 1000 electrical interconnect structures 23a. In existing technologies, the fabrication process for electrical interconnect structures on SOI substrates is complex and inefficient, making it difficult to fabricate high-density electrical interconnect structures and thus high-density interconnect devices. In this embodiment, a substrate 23 with electrical interconnect structures 23a is obtained by etching the substrate to form isolation islands 232 and a functional layer 231. The fabrication process for the electrical interconnect structures 23a is simple, easily achieving high-density electrical interconnect structures 23a, thus reducing the difficulty of fabricating high-density interconnect devices. Furthermore, the fabrication process of the isolation islands 232 does not require creating high aspect ratio annular grooves, resulting in high efficiency and enabling the fabrication of isolation islands 232 suitable for high-density interconnect devices.

[0131] For example, such as Figure 6 As shown, the MEMS device microstructure includes a movable structure 231b and four electrical interconnect structures 23a. An isolation groove is provided between any two electrical interconnect structures 23a for electrical isolation. The isolation islands 232 of each electrical interconnect structure 23a are electrically isolated from the support layer 21 by an insulating layer 22. The four electrical interconnect structures 23a are arranged in an array with the movable structure 231b as the center. The movable structure 231b includes a reflector 245 and a first cantilever beam 246 and a second cantilever beam 247 located on both sides of the reflector 245. The first cantilever beam 246 and... Figure 6 The anchor point 231a of the first electrical interconnect structure 23a on the left side is an integral structure, and the second cantilever beam 247 and Figure 6 The anchor point 231a of the first electrical interconnect structure 23a on the right side is an integral structure.

[0132] In this embodiment, no specific limitations are placed on the specific structure and size of the isolation island 232. For example, the shape of the orthographic projection of the isolation island 232 onto the functional layer 231 can be circular or square, and the isolation island 232 can be a cylindrical, square, or other columnar structure. Furthermore, if dry etching is used, the angle between the sidewall of the isolation island 232 and the functional layer 231 is approximately 90°; that is, the angle between the sidewall of the isolation island 232 and the functional layer 231 can be greater than or less than 90°. In addition, the aspect ratio of the isolation island 232 can be greater than or equal to 1, and the depth of the isolation island 232 is in the thickness direction of the substrate assembly 20 (e.g., ...). Figure 4b The dimension in the Z-direction, the width of the isolation island 232 is in the direction perpendicular to the thickness direction of the substrate assembly 20 (e.g., in the Z-direction), Figure 4b The dimension in the X direction.

[0133] The substrate 23 can be made of semiconductor materials such as silicon, germanium, or germanium-silicon. In some embodiments, the substrate 23 can be made of polycrystalline semiconductors, such as polycrystalline silicon. In other embodiments, the substrate 23 can be made of monocrystalline semiconductors, such as monocrystalline silicon. The substrate 23 is formed by a functional layer 231 and an isolation island 232; therefore, either the isolation island 232 or the functional layer 231 can be a monocrystalline semiconductor or a polycrystalline semiconductor.

[0134] It should be noted that single-crystal semiconductors have several significant advantages over polycrystalline semiconductors, making them the preferred material for applications. The main advantages of single-crystal semiconductors over polycrystalline semiconductors are: superior electrical performance, better uniformity and consistency, excellent optical performance, higher mechanical strength, better thermal stability, and better durability. Furthermore, when the single-crystal semiconductor is single-crystal silicon, its high purity and uniformity, good mechanical properties and elastic modulus, and good thermal stability enable the realization of high-performance MEMS devices.

[0135] In some embodiments, the functional layer 231 and the isolation island 232 are made of the same material, which reduces the difficulty of forming an integral structure of the functional layer 231 and the isolation island 232 and helps to improve the fabrication efficiency of the substrate 23. Of course, in other embodiments, the functional layer 231 and the isolation island 232 may be made of different materials.

[0136] For example, the functional layer 231 and the isolation island 232 are both made of single-crystal silicon. Since single-crystal silicon has the characteristics of high purity and uniformity, good mechanical properties and elastic modulus, and good thermal stability, the isolation island and the functional layer are supported by single-crystal silicon, which can realize high-performance MEMS device 320.

[0137] In some embodiments, the lattice constants of the functional layer 231 and the isolation island 232 are consistent, so that the lattice of the functional layer 231 and the isolation island 232 are matched. For example, the materials of the functional layer 231 and the isolation island 232 are both continuous monocrystalline silicon with no internal lattice misalignment, which can further improve the performance of the MEMS device 320.

[0138] The term "consistent lattice constant" is typically used in the field of crystallography. The lattice constant is a fundamental parameter describing crystal structure, representing the size and shape of the unit cell (the smallest repeating unit that makes up a crystal). In its most intuitive sense, consistent lattice constants mean that parameters such as edge lengths or angles of the unit cell are the same. For example, in the cubic crystal system, there are simple cubic, body-centered cubic, and face-centered cubic structures. If two cubic crystal systems have the same lattice constant, it means that their unit cells have the same edge length. This is crucial in applications such as epitaxial growth of materials. In semiconductor material growth, for instance, if a thin film of another material is to be grown on a substrate of another material, consistent or similar lattice constants can result in a better film structure and fewer defects. This is because it allows for a more regular atomic arrangement, avoiding problems such as stress and dislocations caused by lattice mismatch.

[0139] Lattice matching is a concept in semiconductor physics. In semiconductor device manufacturing, a heterostructure refers to a multilayer structure formed by growing one semiconductor material on top of another, creating layers with different lattice constants. The purpose of lattice matching is to reduce lattice distortion and defects caused by lattice constant mismatch, thereby improving device performance and reliability.

[0140] The types of lattice matching include: 1. Perfect lattice matching, which is the ideal case, where the lattice constants of the two materials are exactly the same, and no lattice distortion occurs at the interface. 2. Partial lattice matching, in which the lattice constants of the two materials are not exactly the same, but the difference is very small, and lattice distortion can be reduced by specific epitaxial techniques (such as buffer layer techniques). 3. Quasi-lattice matching, even if the lattice constants are not matched, quasi-lattice matching can be achieved by designing specific superlattice structures, so that the lattice distortion is within an acceptable range.

[0141] The importance of lattice matching can be reflected in the following aspects: 1. Improving device performance: Lattice matching can reduce lattice distortion, thereby reducing the scattering of electrons and holes, increasing carrier mobility, and increasing the device's response speed and frequency. 2. Improving device reliability: Reducing lattice defects can improve device stability and lifetime, and reduce leakage current caused by lattice distortion.

[0142] In some embodiments, the method for achieving lattice matching is to select a suitable material, for example, to select a material with a similar lattice constant for epitaxial growth.

[0143] The support layer 21 primarily serves a supporting function, ensuring the mechanical strength and stability of the entire MEMS device 320. The material of the support layer 21 can be silicon, glass, sapphire, silicon carbide, etc., for example... Figure 4bAs shown, the material of the support layer 21 can be polycrystalline silicon. When both the support layer 21 and the substrate 23 are made of silicon, the performance, reliability and manufacturing efficiency of the MEMS device 320 can be further improved, which helps to realize a high-performance, low-cost MEMS device 320.

[0144] The main function of the insulating layer 22 is to serve as an electrical isolation layer between the substrate 23 and the support layer 21, thereby reducing parasitic capacitance and improving the performance and reliability of the device. Furthermore, the material of the insulating layer 22 can be silicon dioxide, silicon nitride, or silicon oxynitride, etc.

[0145] In some embodiments, such as Figure 4b As shown, the first insulating portion 221 and the second insulating portion 222 are integrally formed structures. The insulating layer 22 can be formed on the surface of the substrate 23 by chemical vapor deposition (CVD), physical vapor deposition (PVD), or thermal growth. This simplifies the preparation of the insulating layer 22, improves the preparation efficiency of the insulating layer 22, and reduces the difficulty of electrically isolating the isolation island 232 from the support layer 21.

[0146] In some embodiments, the first insulating portion 221 includes a plurality of insulator layers stacked along the thickness direction of the substrate assembly 20, such that the first insulating portion 221 is a multilayer structure, which can provide better electrical isolation, enhance mechanical strength, reduce stress concentration, and help improve device performance and reliability. Of course, in other embodiments, the first insulating portion 221 may also be a single-layer structure.

[0147] In this embodiment, the thickness of the first insulating portion 221 is not specifically limited. In some embodiments, such as Figure 4b As shown, the first insulating portion 221 is in the thickness direction of the substrate assembly 20 (e.g., Figure 4b A thickness of 10 μm or more in the Z-direction can further improve the electrical isolation between the substrate 23 and the support layer 21.

[0148] In some possible implementations, the second insulating portion is in the thickness direction of the substrate assembly 20 (e.g., Figure 4b The depth of the second insulating portion 222 in the Z direction and the radial direction of the second through hole 223 (e.g., Figure 4bThe ratio of the width in the X direction is greater than or equal to 10. Since the isolation island 232 and the functional layer 231 are an integral structure, by directly growing the insulating layer 22 on the surface of the substrate 23, a second insulating portion 222 with a high aspect ratio can be achieved. This helps to improve the electrical isolation effect between the isolation island 232 and the support layer 21 while reducing the size of the conductive structure and achieving high-density interconnection.

[0149] The specific ratio of the depth to the width of the second insulating portion 222 is not limited here. In some embodiments, the ratio of the depth to the width of the second insulating portion 222 is greater than or equal to 20, and less than or equal to 50. In this way, it is possible to increase the electrical isolation effect between the isolation island 232 and the support layer 21 while reducing the size of the conductive structure, thereby achieving high-density interconnection.

[0150] Of course, the ratio of the depth to the width of the second insulating portion 222 can also be between 10 and 20, or the ratio of the depth to the width of the second insulating portion 222 can be greater than 50.

[0151] In this embodiment, the specific value of the width of the second insulating portion 222 is not limited. For example, the width of the second insulating portion 222 can be greater than 1 μm, such as 2 μm.

[0152] The cover plate 10 can be made of silicon, glass, or other materials. Furthermore, the cover plate 10 can be connected to the substrate assembly 20 via wafer bonding, which may include, but is not limited to, silicon-silicon hermetic bonding, silicon-silicon vacuum bonding, anodic bonding, and eutectic bonding. In some embodiments, when the cover plate 10 is made of silicon, the cover plate 10 and the substrate assembly 20 can be connected via silicon-silicon hermetic bonding or silicon-silicon vacuum bonding. In some embodiments, when the cover plate 10 is made of glass, the cover plate 10 and the substrate assembly 20 are anodicly bonded.

[0153] like Figure 3 As shown, a groove 11 is provided on the side of the cover plate 10 near the functional layer 231. The functional layer 231 and the inner wall of the groove 11 form an airtight chamber 50. At this time, the orthographic projection of the movable structure 231b on the cover plate 10 is located inside the groove 11, so that the movable structure 231b is suspended in the airtight chamber 50. The movable structure 231b can move relative to the cover plate 10 to realize the device function.

[0154] The depth of the groove 11 is not limited here. For example, the depth of the groove 11 in the thickness direction of the cover plate 10 can be 3~5μm.

[0155] In some embodiments, the edge of the groove 11 may be aligned with the edge of the anchor point 231a. In other embodiments, such as Figure 5 As shown, the edge of the groove 11 can also be aligned with the edge of the anchor point 231a in a direction perpendicular to the thickness direction of the cover plate 10 (e.g., Figure 5 (In the X direction) the spacing is set. When the edge of the groove 11 is aligned with the edge of the anchor point 231a, the area occupied by the hermetic device can be further reduced.

[0156] like Figure 3 As shown, the substrate assembly 20 also includes a third through hole 25. The third through hole penetrates the first insulating portion 221 of the insulating layer 22 along the thickness direction of the substrate assembly 20 and exposes a portion of the surface of the support layer 21. The functional layer 231, the inner wall of the third through hole 25, and the support layer 21 together form a cavity. The orthographic projection of the movable structure 231b on the cover plate 10 is located inside the orthographic projection of the third through hole 25 on the cover plate 10, so that the movable structure 231b is suspended above the insulating layer 22, allowing the movable structure 231b to move relative to the insulating layer 22 and realize the device function.

[0157] Figure 7 This is a schematic diagram of step one of the fabrication processes of a substrate assembly provided in an embodiment of this application. Figure 8 This is a schematic diagram illustrating step two of the fabrication process of a substrate assembly provided in an embodiment of this application. Figure 9 This is a schematic diagram of step three in the fabrication process of a substrate assembly provided in an embodiment of this application. Figure 10 This is a schematic diagram of step four in the fabrication process of a substrate assembly provided in an embodiment of this application. Figure 11 This is a schematic diagram of step five in the fabrication process of a substrate assembly provided in an embodiment of this application.

[0158] This application embodiment also provides a method for manufacturing a substrate assembly 20, the method comprising the following steps:

[0159] S1. Prepare substrate 23, which includes functional layer 231 and isolation island 232.

[0160] In some embodiments, the specific method for preparing the substrate 23 includes the following steps:

[0161] S11, Provide a substrate, such as Figure 7 As shown.

[0162] For example, the substrate material is silicon, such as monocrystalline silicon. In this case, the substrate is a monocrystalline silicon substrate. Of course, the substrate material can also be other materials. The material of substrate 23 has been described above, so it will not be repeated here.

[0163] S12. Etch the substrate to form substrate 23, such as... Figure 8As shown.

[0164] Specifically, in combination Figure 7 and Figure 8 It is known that the region in the substrate where the electrical interconnect structure 23a is pre-fabricated is formed using dry etching or wet etching to create isolation islands 232. Dry etching includes at least reactive ion etching (RIE) or inductively coupled plasma (ICP). Wet etching includes at least the use of a potassium hydroxide solution.

[0165] The isolation island 232 can be circular or square, or other shapes such as elliptical. The width of the isolation island 232 is 80-150 μm, and its aspect ratio ranges from 5 to 1. However, the width and / or aspect ratio can also be other values; for example, the width could be 70 μm, and the aspect ratio could be 6. Furthermore, if dry etching is used, the angle between the sidewall of the isolation island 232 and the monocrystalline silicon substrate assembly 20 is approximately 90 degrees.

[0166] The depth of the isolation island 232 refers to the dimension along the thickness direction of the substrate assembly 20, and the width of the isolation island 232 refers to the dimension along the direction perpendicular to the thickness direction of the substrate assembly 20.

[0167] For example, two isolation islands 232 are formed at the electrical interconnect structure 23a in a single-crystal silicon substrate using reactive ion etching (RIE) as an illustration. The isolation islands 232 are square in shape, with a width of 100 μm and a height of 200 μm. The aspect ratio of the isolation islands 232 is 2:1.

[0168] It should be noted that, in addition to etching the substrate to form the substrate 23, in some embodiments, the substrate 23 can also be obtained by depositing isolation islands 232 on the functional layer 231, or by forming an integral isolation island 232 and functional layer 231.

[0169] S2, forming an insulating structure, such as Figure 9 As shown, the insulating structure covers the surface of the isolation island 232 and the exposed area of ​​the side surface where the functional layer 231 is connected to the isolation island 232.

[0170] Specifically, in combination Figure 8 and Figure 9It is known that an insulating structure is formed on the surface of the isolation island 232 and on the exposed area of ​​the functional layer 231 on the side surface near the isolation island 232 by chemical vapor deposition (CVD), physical vapor deposition (PVD), or thermal growth. The material of the insulating structure can be silicon dioxide, silicon nitride, or silicon oxynitride, etc.

[0171] The insulating structure includes a first insulating portion 221, a second insulating portion 222, and a third insulating layer, with the third insulating layer covering the end face of the isolation island 232 away from the functional layer 231. For example, the thickness of the first insulating portion 221 can be 10 μm; however, the thickness of the first insulating portion 221 can also be greater than or less than 10 μm. The ratio of the depth to the width of the second insulating portion 222 is greater than or equal to 10; for example, the width of the second insulating portion 222 is 2 μm, and the depth of the second insulating portion 222 is 200 μm.

[0172] S3. An epitaxial layer (e.g., ...) is grown on the surface of the insulating structure away from the substrate 23. Figure 10 As shown in the middle (W).

[0173] Specifically, in combination Figure 9 and Figure 10 It can be seen that an epitaxial layer is grown on the surface of the insulating layer 22 away from the substrate 23 while being doped (e.g., ...). Figure 10 As shown in Figure W), the material of the epitaxial layer is polycrystalline silicon. The surface of the epitaxial layer away from the functional layer 231 is higher than the surface of the insulating layer 22 away from the functional layer 231. In other words, the insulating layer 22 is located between the epitaxial layer and the substrate 23.

[0174] S4. The epitaxial layer and the insulating structure are thinned sequentially until the isolation island 232 is exposed to form the support layer 21 and the insulating layer 22.

[0175] Specifically, in combination Figure 10 and Figure 11 It can be seen that by sequentially thinning the epitaxial layer and the insulating structure, for example by using a chemical mechanical polishing process to sequentially thin the epitaxial layer and the insulating structure until the surface of the isolation island 232 is exposed, the desired result is obtained. Figure 11 The support layer 21 and the insulating layer 22 are shown.

[0176] Figure 12 This is a schematic diagram of step one of the fabrication processes of a MEMS device provided in an embodiment of this application. Figure 13 This is a schematic diagram of step two in the fabrication process of a MEMS device provided in an embodiment of this application. Figure 14 This is a schematic diagram of step three in the fabrication process of a MEMS device provided in an embodiment of this application. Figure 15 This is a schematic diagram of step four in the fabrication process of a MEMS device provided in an embodiment of this application.

[0177] This application embodiment also provides a method for fabricating a MEMS device 320, which includes the following steps:

[0178] S101. Prepare substrate assembly 20, which includes a support layer 21, an insulating layer 22 and a substrate 23.

[0179] Specifically, the fabrication method of the substrate assembly 20 is described in detail above and will not be described in detail here. In addition, a temporary carrier can be provided, on which the prepared substrate assembly 20 is placed, with the support layer 21 in contact with the temporary carrier. The substrate assembly 20 is then inverted, with the support layer 21 serving as the support substrate for the MEMS device 320, with the substrate 23 facing upwards, to facilitate subsequent steps.

[0180] In some embodiments, the functional layer 231 may be provided with an isolation zone (such as...). Figure 4b As shown in Figure H), this provides electrical isolation for each movable structure 231b when the MEMS device 320 has multiple movable structures 231b. The isolation region can be fabricated before the movable structures 231b are fabricated.

[0181] S102, the functional layer 231 of the substrate 23 is etched to form a movable structure 231b.

[0182] Specifically, after the substrate assembly 20 is fabricated, a movable structure 231b is formed by deep etching of the portion of the functional layer 231 located between the two electrical interconnect structures 23a using the DRIE process. The movable structure 231b is provided with a release hole (e.g., Figure 12 As shown in Figure S), the result is as follows: Figure 12 The structure shown.

[0183] S103. A third through-hole 25 is formed through the insulating layer 22 so that the movable structure 231b is suspended in the insulating layer 22, thus obtaining a MEMS structure.

[0184] Specifically, a portion of the insulating layer 22 below the movable structure 231b is etched away from the opening of the release hole using either a hydrofluoric acid (HF) vapor-phase etching process or a hydrofluoric acid (HF) liquid-phase etching process to form a third through-hole 25. The third through-hole 25 exposes the support layer 21. The functional layer 231, the third through-hole 25, and the insulating layer 22 together form a cavity, and the movable structure 231b is suspended above the insulating layer 22, resulting in… Figure 13 The MEMS structure shown.

[0185] S104. The functional layer 231 of the MEMS structure is bonded to the cover plate 10 with the groove 11. The functional layer 231 and the inner wall of the groove 11 form an airtight cavity 50, so that the movable structure 231b is suspended in the cover plate 10.

[0186] Specifically, a cover plate 10 is provided, and the side of the cover plate 10 facing the comb structure has a groove 11. The depth of the groove 11 can be 3-5 μm, and of course, the depth of the groove 11 can also be other values. For example... Figure 14 As shown, the cover plate 10 is fixedly connected to the functional layer 231, and the groove 11 and the functional layer 231 form an airtight chamber 50. The orthogonal projection of the movable structure 231b and the electrical interconnection structure 23a on the cover plate 10 is located inside the groove 11, and the movable structure 231b is suspended in the airtight chamber 50.

[0187] The cover plate 10 can be made of silicon, glass, or other materials. Furthermore, the cover plate 10 can be connected to the functional layer 231 via wafer bonding, which can include, but is not limited to, silicon-silicon hermetically sealed bonding, silicon-silicon vacuum bonding, anodic bonding, and eutectic bonding. In some embodiments, when the cover plate 10 is made of silicon, the cover plate 10 and the functional layer 231 can be bonded via silicon-silicon hermetically sealed bonding or silicon-silicon vacuum bonding. In some embodiments, when the cover plate 10 is made of glass, the cover plate 10 and the functional layer 231 are anodicly bonded.

[0188] S105. A passivation layer 30 with a window is formed on the side of the support layer 21 away from the substrate 23, with the window exposing the isolation island 232 of the substrate 23.

[0189] Specifically, in combination Figure 14 and Figure 15 It is understood that after forming the airtight chamber 50, a passivation layer 30 is deposited on the side of the support layer 21 away from the substrate 23. The material of the passivation layer 30 includes one or a combination of silicon nitride, silicon oxide, silicon oxynitride, and silicon dioxide. Then, a window is made in the passivation layer 30 to form a window that exposes the isolation island 232.

[0190] S106. Form substrate electrode leads 40 within the window that are electrically connected to the isolation island 232, thereby obtaining... Figure 3 The MEMS device 320 shown is shown.

[0191] Specifically, the substrate electrode lead 40 can be formed in the window by sputtering aluminum, and the material of the substrate electrode lead 40 is aluminum. It should be noted that the material of the substrate electrode lead 40 is not limited to aluminum, and can also be other conductive materials, such as copper.

[0192] In the description of the embodiments of this application, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, an indirect connection through an intermediate medium, or the internal connection of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this application according to the specific circumstances. The terms "first," "second," "third," "fourth," etc. (if present) are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0193] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of this application, and are not intended to limit them. Although the embodiments of this application have been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A substrate assembly (20), characterized in that, include: The substrate (23) includes a functional layer (231) of an integral structure and an isolation island (232); The support layer (21) has a first through hole (211); The insulating layer (22) includes a first insulating portion (221), a second insulating portion (222), and a second through-hole (223). The functional layer (231), the first insulating portion (221), and the support layer (21) are stacked sequentially along the thickness direction of the substrate assembly (20). The second insulating portion (222) is located inside the first through-hole (211) and is fixedly connected to the first insulating portion (221). The second through-hole (223) penetrates the first insulating portion (221) and the second insulating portion (222). The isolation island (232) fills the interior of the second through-hole (223) and is electrically isolated from the support layer (21) through the insulating layer (22).

2. The substrate assembly (20) according to claim 1, characterized in that, The functional layer (231) is made of the same material as the isolated island (232).

3. The substrate assembly (20) according to claim 2, characterized in that, Both the functional layer (231) and the isolation island (232) are made of monocrystalline silicon.

4. The substrate assembly (20) according to claim 3, characterized in that, The lattice constant of the functional layer (231) is consistent with that of the isolated island (232).

5. The substrate assembly (20) according to any one of claims 1 to 4, characterized in that, The material of the support layer (21) is polycrystalline silicon.

6. The substrate assembly (20) according to any one of claims 1 to 5, characterized in that, The ratio of the depth of the second insulating portion (222) in the thickness direction of the substrate assembly (20) to the width of the second insulating portion (222) in the radial direction of the second through hole (223) is greater than or equal to 10.

7. The substrate assembly (20) according to claim 6, characterized in that, The ratio of the depth to the width of the second insulating portion (222) is greater than or equal to 20, and the ratio of the depth to the width of the second insulating portion (222) is less than or equal to 50.

8. The substrate assembly (20) according to any one of claims 1 to 7, characterized in that, The first insulating part (221) and the second insulating part (222) are an integral structure.

9. The substrate assembly (20) according to any one of claims 1 to 8, characterized in that, The first insulating portion (221) includes a plurality of insulator layers stacked along the thickness direction of the substrate assembly (20).

10. The substrate assembly (20) according to any one of claims 1 to 9, characterized in that, The insulating layer (22) is made of silicon dioxide, silicon nitride, or silicon oxynitride.

11. A MEMS device (320), characterized in that, Includes the substrate assembly (20) as described in any one of claims 1 to 10: The substrate assembly (20) further includes a third through hole (25) that penetrates the first insulating portion (221) of the insulating layer (22) along the thickness direction of the substrate assembly (20) and exposes a portion of the surface of the support layer (21).

12. The MEMS device (320) according to claim 11, characterized in that, The MEMS device (320) also includes a cover plate (10) located on the side of the functional layer (231) of the substrate (23) away from the support layer (21); The functional layer (231) includes an anchor point (231a), a movable structure (231b), and a support structure (231c). The anchor point (231a) is electrically connected to the isolation island (232) and forms an electrical interconnection structure (23a) with the isolation island (232). The movable structure (231b) is electrically connected to the anchor point (231a). Both the anchor point (231a) and the movable structure (231b) are electrically isolated from the support structure (231c). The support structure (231c) is fixedly connected to the cover plate (10) and is used to support the cover plate (10). The orthographic projection of the movable structure (231b) on the cover plate (10) is located inside the orthographic projection of the third through hole (25) on the cover plate (10), so that the movable structure (231b) is suspended above the insulating layer (22).

13. The MEMS device (320) according to claim 12, characterized in that, The cover plate (10) has a groove (11) on the side near the functional layer (231). The functional layer (231) and the inner wall of the groove (11) form an airtight chamber (50). The movable structure (231b) is suspended in the airtight chamber (50).

14. The MEMS device (320) according to claim 12 or 13, characterized in that, The MEMS device (320) also includes: A passivation layer (30) is located on the side of the substrate assembly (20) away from the cover plate (10) and has a window that exposes the isolation island (232); The substrate electrode lead (40) is at least partially disposed within the window and electrically connected to the isolation island (232).

15. The MEMS device (320) according to any one of claims 12 to 14, characterized in that, The MEMS device (320) is a high-density interconnect device, which includes multiple MEMS device microstructures arranged in an array. Each MEMS device microstructure includes the movable structure (231b) and multiple electrical interconnect structures (23a). Any two electrical interconnect structures (23a) are electrically isolated. The isolation island (232) of each electrical interconnect structure (23a) is electrically isolated from the support layer (21) through the insulating layer (22).

16. An electronic device, characterized in that, It includes a circuit board (310) and a MEMS device (320) as claimed in any one of claims 11 to 15, the MEMS device (320) being electrically connected to the circuit board (310).

17. A method for fabricating a MEMS device (320), characterized in that, include: Fabricating a substrate assembly (20), the substrate assembly (20) includes a support layer (21), an insulating layer (22), and a substrate (23); wherein, fabricating the substrate assembly (20) includes: A substrate (23) is prepared, the substrate (23) including a functional layer (231) and isolation islands (232); An insulating structure is formed, which covers the surface of the isolation island (232) and the exposed area of ​​the side surface of the functional layer (231) connected to the isolation island (232); An epitaxial layer is epitaxially grown on the surface of the insulating structure away from the substrate (23); The epitaxial layer and the insulating structure are thinned sequentially until the isolation island (232) is exposed to form a support layer (21) and an insulating layer (22).

18. The manufacturing method according to claim 17, characterized in that, The preparation of the substrate (23) includes: Provide substrate; The substrate is etched to form the substrate (23).

19. The manufacturing method according to claim 17 or 18, characterized in that, The formation of the insulating structure includes: The insulating structure is formed by chemical vapor deposition, physical vapor deposition, or thermal growth.

20. The manufacturing method according to any one of claims 17 to 19, characterized in that, After the substrate assembly (20) is prepared, the manufacturing method further includes: The functional layer (231) of the substrate (23) is etched to form a movable structure (231b). A third through-hole (25) is formed through the insulating layer (22) so that the movable structure (231b) is suspended in the insulating layer (22) to obtain a MEMS structure; The functional layer (231) of the MEMS structure is bonded to the cover plate (10) with a groove (11), and the functional layer (231) and the inner wall of the groove (11) form an airtight cavity (50) so that the movable structure (231b) is suspended above the cover plate (10).

21. The manufacturing method according to claim 20, characterized in that, After forming the airtight chamber (50), the manufacturing method further includes: A passivation layer (30) with a window is formed on the side of the support layer (21) away from the substrate (23), the window exposing the isolation island (232) of the substrate (23). A substrate electrode lead (40) electrically connected to the isolation island (232) is formed within the window.

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