Wafer testing method, device and wafer testing machine

Abstract

The present disclosure provides a wafer testing method, a wafer testing device and a wafer testing machine, and belongs to the technical field of optoelectronic manufacturing. The testing method comprises: scanning a wafer to obtain initial position information of each chip on the wafer; checking current position information of a preset marker chip; determining an offset threshold based on the current position information and the initial position information of the preset marker chip; and determining that the position of the wafer is offset if the offset threshold exceeds a tolerance threshold. The embodiments of the present disclosure can improve the problem of probe positioning error caused by wafer position offset in the wafer testing process, and improve the testing efficiency of the wafer.

Description

Technical Field

[0001] This disclosure relates to the field of optoelectronic manufacturing technology, and in particular to a wafer testing method, apparatus and wafer testing machine. Background Technology

[0002] The goal of automated testing for light-emitting diode (LED) wafers is to guide test probes to accurately contact the chip electrode pads through a high-precision positioning system, thereby completing the detection of electrical performance parameters. The positioning accuracy directly determines the test yield and the risk of chip and probe damage.

[0003] The wafer testing process for related technologies typically includes: first, using a high-precision CCD vision system to perform a rapid, low-resolution scan of the entire wafer to establish a position index map of all wafer chips and determine the initial coordinates of each chip; during formal testing, after the machine moves to each chip location, it uses a CCD for high-precision local positioning to guide the probes to the pads to complete the test.

[0004] However, during the single-wafer testing process, which can last for several hours, factors such as equipment vibration, temperature drift, and thermal expansion and contraction of the lens can cause a slight relative offset between the CCD camera coordinate system and the equipment motion coordinate system. The relevant technology cannot detect the offset that occurs during the process. The cumulative offset will directly lead to inaccurate probe positioning, resulting in test failure, chip damage, or even probe damage. Summary of the Invention

[0005] This disclosure provides a wafer testing method, apparatus, and wafer testing machine, which can improve the problem of probe positioning errors caused by wafer position offset during wafer testing, thereby improving wafer testing efficiency. The technical solution is as follows: On one hand, this disclosure provides a wafer testing method, the testing method including: scanning the wafer to obtain initial position information of each chip on the wafer; checking the current position information of a preset marker chip; determining an offset threshold based on the current position information of the preset marker chip and the initial position information; if the offset threshold exceeds a tolerance threshold, determining that the wafer position has shifted.

[0006] In one implementation of this disclosure, scanning the wafer to obtain the initial position information of each chip on the wafer includes: performing a global scan of the wafer, establishing a Cartesian coordinate system with the surface of the wafer as a reference, and storing the coordinate information of each chip as the initial position information of the corresponding chip.

[0007] In one implementation of this disclosure, after performing a global scan of the wafer and establishing a Cartesian coordinate system based on the surface of the wafer, the method further includes: selecting N chips dispersed on the edge and center of the wafer as the preset marker chips, where N≥3.

[0008] In another implementation of this disclosure, checking the current position information of the preset marker chip includes: moving the preset marker chip to the center of the field of view of the vision system; and imaging and positioning the preset marker chip through the vision system to obtain the current position information of the preset marker chip.

[0009] In another implementation of this disclosure, determining the offset threshold based on the current position information and the initial position information of the preset marker chip includes: calculating the coordinate difference between the current position information and the initial position information of the preset marker chip to obtain the coordinate offset in different directions.

[0010] In another implementation of this disclosure, the initial position information of the preset marker chip includes (X0, Y0), the current position information of the preset marker chip includes (X1, Y1), and the coordinate offset includes (△X, △Y), where △X = X1 - X0 and △Y = Y1 - Y0. After determining that the position of the wafer has shifted, the method further includes: using the coordinate offset as a compensation value and superimposing it on the initial position information of all chips generated by scanning, and updating the coordinates (Xi, Yi) of each chip under test to (Xi - △X, Yi - △Y).

[0011] In another implementation of this disclosure, after determining that the position of the wafer has shifted, the method further includes: if the shift threshold exceeds a safety threshold, then outputting an alarm message.

[0012] In another implementation of this disclosure, the tolerance threshold is ±3μm and the safety threshold is ±10μm.

[0013] On the other hand, embodiments of this disclosure provide a wafer testing apparatus, the testing apparatus comprising: a scanning module for scanning the wafer to obtain initial position information of each chip on the wafer; an inspection module for inspecting the current position information of a preset marker chip; and a data processing module for determining an offset threshold based on the current position information and the initial position information of the preset marker chip, and further for determining that the wafer's position has shifted if the offset threshold exceeds a tolerance threshold.

[0014] On the other hand, embodiments of this disclosure provide a wafer testing machine for implementing the wafer testing method as described above.

[0015] The beneficial effects of the technical solutions provided in this disclosure include at least the following: The wafer testing method provided in this disclosure sets the offset checking step before the formal test starts after the wafer scan is completed. This does not interrupt the continuous process of subsequent batch testing and does not increase the testing time of a single chip. Therefore, it does not affect the overall test cycle and is adapted to the high efficiency requirements of wafer testing.

[0016] Offset determination is achieved by comparing the positions of preset marker chips. There is no need to repeatedly perform high-precision local positioning on all chips on the entire wafer. Offset evaluation can be completed by only verifying the coordinates of a small number of marker chips, which greatly reduces the computing power and time cost of additional detection. At the same time, the offset threshold is calculated based on the difference between the initial position information and the current position information, which can accurately capture relative offset and avoid the problem that related technologies cannot detect mid-course offset.

[0017] Offset determination is performed before test initiation. If the offset threshold exceeds the tolerance threshold, calibration or process interruption can be triggered in a timely manner, fundamentally preventing probe positioning inaccuracies caused by accumulated offsets. This reduces the risk of test failures, chip damage, and even probe damage, ensuring the positioning accuracy and yield stability of subsequent batch testing of tens of thousands of chips on the entire wafer. Furthermore, the testing method only requires adding a chip marking verification step to the existing testing foundation, without significant modifications to the existing probe station's CCD vision system and motion control module. It is low-cost and easy to integrate into existing wafer testing production lines. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a flowchart of a wafer testing method provided in an embodiment of this disclosure; Figure 2 This is a flowchart of another wafer testing method provided in an embodiment of this disclosure; Figure 3 This is a schematic diagram of a preset marker chip on a wafer provided in an embodiment of this disclosure; Figure 4 This is a schematic diagram of a wafer testing apparatus provided in an embodiment of this disclosure.

[0020] The markings in the diagram are explained as follows: 10. Wafers; 20. Preset marker chip; 100. Scanning module; 200. Inspection module; 300. Data processing module. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0022] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the elements or objects preceding “comprising” or “including” encompass the elements or objects listed following “comprising” or “including” and their equivalents, and do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” “right,” “top,” and “bottom,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0023] Figure 1 This is a flowchart of a wafer testing method provided in an embodiment of this disclosure. Figure 1 As shown, the test method includes: Step S11: Scan the wafer to obtain the initial position information of each chip on the wafer.

[0024] Step S12: Check the current position information of the preset marker chip.

[0025] Step S13: Determine the offset threshold based on the current position information and initial position information of the preset marker chip.

[0026] Step S14: If the offset threshold exceeds the tolerance threshold, it is determined that the wafer position has shifted.

[0027] The wafer testing method provided in this disclosure sets the offset checking step before the formal test starts after the wafer scan is completed. This does not interrupt the continuous process of subsequent batch testing and does not increase the testing time of a single chip. Therefore, it does not affect the overall test cycle and is adapted to the high efficiency requirements of wafer testing.

[0028] Offset determination is achieved by comparing the positions of preset marker chips. There is no need to repeatedly perform high-precision local positioning on all chips on the entire wafer. Offset evaluation can be completed by only verifying the coordinates of a small number of marker chips, which greatly reduces the computing power and time cost of additional detection. At the same time, the offset threshold is calculated based on the difference between the initial position information and the current position information, which can accurately capture relative offset and avoid the problem that related technologies cannot detect mid-course offset.

[0029] Offset determination is performed before test initiation. If the offset threshold exceeds the tolerance threshold, calibration or process interruption can be triggered in a timely manner, fundamentally preventing probe positioning inaccuracies caused by accumulated offsets. This reduces the risk of test failures, chip damage, and even probe damage, ensuring the positioning accuracy and yield stability of subsequent batch testing of tens of thousands of chips on the entire wafer. Furthermore, the testing method only requires adding a chip marking verification step to the existing testing foundation, without significant modifications to the existing probe station's CCD vision system and motion control module. It is low-cost and easy to integrate into existing wafer testing production lines.

[0030] Figure 2 This is a flowchart of another wafer testing method provided in an embodiment of this disclosure. Figure 2 As shown, the test method includes: Step S21: Perform a global scan of the wafer, establish a Cartesian coordinate system with the wafer surface as the reference, and store the coordinate information of each chip as the initial position information of the corresponding chip.

[0031] For example, the initial position information of the preset marker chip includes (X0, Y0).

[0032] Specifically, this may include: performing a global low-resolution fast scan of the entire wafer mounted on the wafer stage, establishing a Cartesian coordinate system based on the wafer surface, and simultaneously recording features such as wafer edges and flat edges to complete coordinate system calibration; identifying features such as the outline and pad positions of all chips during the scanning process, extracting the center coordinates and feature identification information of each chip, storing the coordinate information of each chip as the initial position information of the corresponding chip, and finally generating a wafer map containing the chip position index of the entire wafer to provide a coordinate reference for subsequent testing processes.

[0033] Step S22: Select N chips dispersed on the edge and center of the wafer as preset marker chips, where N≥3.

[0034] Figure 3 This is a schematic diagram of a preset marker chip on a wafer provided in an embodiment of this disclosure. For example... Figure 3 As shown, five chips dispersed at the edge and center of wafer 10 are selected as preset marker chips 20.

[0035] Specifically, this may include selecting N (e.g., 4-6) chips scattered around the edge and center of the wafer from the wafer map as preset marker chips.

[0036] The selection range of the preset marker chips covers the outer perimeter and the central core area of ​​the wafer, avoiding offset fitting errors caused by concentrated distribution.

[0037] For example, special structure chips with high contrast and obvious features can be selected, such as alignment marks pre-set in the process or non-functional alignment chips, to ensure the accuracy of subsequent imaging and positioning.

[0038] Step S23: Move the preset marker chip to the center of the field of view of the vision system.

[0039] Specifically, this may include: based on the initial position information of the preset marker chips stored in the wafer map, controlling the wafer stage to move sequentially to the theoretical coordinate position of each preset marker chip, so that the target preset marker chip moves to the center of the field of view of the vision system (e.g., CCD system) and completes the initial alignment of the preset marker chips.

[0040] Step S24: Image and locate the preset marker chip using a vision system to obtain the current position information of the preset marker chip.

[0041] Specifically, this may include: triggering the vision system to perform small-range high-precision local imaging at the current position, extracting feature points (such as pad edges) of the preset marker chip through image recognition algorithms, calculating the center coordinates of the preset marker chip in the current vision system coordinate system, converting the coordinates into coordinates in the machine tool motion coordinate system, and storing them as the current position information of the preset marker chip.

[0042] For example, the current position information of the preset marker chip includes (X1, Y1).

[0043] Step S25: Calculate the coordinate difference between the current position information and the initial position information of the preset marker chip to obtain the coordinate offset in different directions.

[0044] Specifically, this may include: extracting the initial position information (X0, Y0) and current position information (X1, Y1) of the preset marker chips, and calculating the coordinate difference of a single preset marker chip point by point; if N≥3 preset marker chips are selected, the overall translational offset (△X, △Y) of the visual system coordinate system can be calculated by least squares fitting, where △X=X1-X0, △Y=Y1-Y0, thus achieving accurate quantification of the coordinate system offset.

[0045] Step S26: If the offset threshold does not exceed the tolerance threshold, the wafer position is determined to be normal, and the chip testing process continues.

[0046] For example, the tolerance threshold is ±3μm.

[0047] Specifically, this may include comparing the absolute value of the calculated translation offset (ΔX, ΔY) with a preset tolerance threshold.

[0048] If both |△X| and |△Y| are less than or equal to the tolerance threshold, the wafer position is determined to be normal and there is no significant offset between the vision system and the machine coordinate system. The system will then automatically enter the subsequent chip testing process without interrupting the production cycle.

[0049] Step S27: If the offset threshold exceeds the tolerance threshold, it is determined that the wafer position has shifted.

[0050] For example, the tolerance threshold is ±3μm.

[0051] If either |△X| or |△Y| is greater than the tolerance threshold, it is determined that the wafer position has shifted, and the relative position between the vision system and the machine tool motion coordinate system has changed. This requires triggering subsequent offset compensation or alarm processes to avoid the accumulation of offset leading to inaccurate probe positioning.

[0052] Step S271: Use the coordinate offset as a compensation value and superimpose it on the initial position information of all chips generated by the scan, and update the coordinates (Xi, Yi) of each chip under test to (Xi-△X, Yi-△Y).

[0053] Specifically, this can include: using the calculated coordinate offset (△X, △Y) as a compensation value, superimposing it onto the initial position information of all chips under test generated by global scanning, updating the stored coordinates (Xi, Yi) of each chip under test to (Xi-△X, Yi-△Y), and batch correcting the target position coordinates of the entire wafer chips; after the compensation is completed, the test process can be started normally without manual intervention, realizing full automation of the process.

[0054] Step S272: If the offset threshold exceeds the safety threshold, output an alarm message.

[0055] For example, the safety threshold is ±10μm.

[0056] If the offset threshold exceeds the preset safety threshold, it is determined that the excessive offset may indicate a mechanical abnormality (such as machine vibration or severe thermal expansion and contraction of the lens). An audible and visual alarm is immediately issued to the operator, and the machine is suspended. The operation interface displays a curve comparing the current offset with historical data, prompting technicians to check the equipment status and avoid damage to the probe and chip.

[0057] In this embodiment, offset detection is embedded between global scanning and testing, without interrupting subsequent batch testing processes. Offset detection can be completed simply by verifying N preset marker chips, without increasing the overall testing cycle time. Compared to related technologies that cannot detect offsets during testing, this method can accurately capture minute coordinate system offsets caused by machine vibration, temperature drift, and lens thermal expansion and contraction.

[0058] Meanwhile, a tiered judgment standard is set for tolerance threshold (±3μm) and safety threshold (±10μm). When the offset does not exceed the tolerance, the test is directly advanced. When the offset is between the tolerance and the safety threshold, the test is automatically compensated and then performed. When the offset exceeds the safety threshold, an alarm is triggered and the machine is stopped. This avoids test failure and chip damage caused by small offsets, and also prevents secondary damage to the equipment under large offsets. It can reduce probe wear and improve test yield.

[0059] Furthermore, when the offset exceeds the limit, the coordinates of all wafer chips are automatically corrected in batches without the need for manual rescanning and calibration. The compensation process is fully automated, adapting to the high throughput requirements of wafer testing, and is especially suitable for testing scenarios with millions of chips, such as LED wafers and Micro-LED wafers.

[0060] Taking a 6-inch LED wafer as an example, the testing procedure is as follows: First, the machine completes a global low-resolution scan of the entire LED wafer. A rectangular coordinate system is established with the flat edge of the wafer as the reference. During the scan, a special alignment MARK point is identified as a preset marker chip. Its initial position information is (X0, Y0) = (0, 0). This coordinate has been stored as the initial reference data.

[0061] Simultaneously, the initial coordinates of the 100th chip under test on the entire wafer are obtained by scanning as (X1, Y1) = (1, 1), and the coordinates of the remaining chips are stored in the wafer map according to this rule.

[0062] Next, an offset check process is performed before the formal test: Select the MARK point as the unique preset marker chip (N=1, this example only takes 1 for simplified calculation, in actual mass production it is recommended to take 4-6 scattered marker points to improve accuracy), and control the stage to move the MARK point to the center of the vision system's field of view.

[0063] The vision system is triggered to perform high-precision local positioning, and the current position information of the MARK point is obtained as (X1, Y1) = (5, -5).

[0064] The coordinate offset is calculated using the formula: △X = X1 - X0 = 5 - 0 = 5μm, △Y = Y1 - Y0 = -5 - 0 = -5μm. That is, the vision system coordinate system is offset by 5μm in the positive X direction and 5μm in the negative Y direction relative to the machine tool motion coordinate system.

[0065] The tolerance threshold is set to ±3μm. In this calculation, |△X|=5μm>3μm and |△Y|=5μm>3μm both exceed the tolerance threshold, indicating that the wafer position has shifted and triggering the compensation process.

[0066] Since the offset of 5μm does not exceed the safety threshold of ±10μm, the automatic compensation mode is adopted, and the offset is used as the compensation value and superimposed on the initial position information of all chips under test.

[0067] For the 100th chip under test with initial coordinates (1, 1), the compensated coordinates are: Xi - ΔX = 1 - 5 = -4μm, Yi - ΔY = 1 - (-5) = 6μm. That is, the updated test target coordinates of the chip are (-4, 6). The instrument will then move to this corrected coordinate position to perform probe piercing tests without manual intervention.

[0068] If the offset exceeds ±10μm, an additional audible and visual alarm will be triggered and the machine will be paused, prompting the operator to check for abnormal factors such as machine vibration and lens thermal expansion and contraction.

[0069] In this example, offset compensation avoids the problem of probe misalignment on the pads caused by the original 5μm offset. Without compensation, the probe will be positioned at the initial coordinates (1,1), which can easily lead to test failure or damage to the chip pads. After compensation, the probe positioning error can be controlled within ±1μm, ensuring test yield.

[0070] Figure 4 This is a schematic diagram of a wafer testing apparatus provided in an embodiment of this disclosure. Figure 4 As shown, the testing device includes a scanning module 100, an inspection module 200, and a data processing module 300.

[0071] The scanning module is used to scan the wafer to obtain the initial position information of each chip on the wafer.

[0072] The inspection module is used to check the current position information of the preset marker chip.

[0073] The data processing module is used to determine an offset threshold based on the current position information and the initial position information of the preset marker chip. The data processing module is also used to determine that the position of the wafer has shifted if the offset threshold exceeds the tolerance threshold.

[0074] Optionally, the scanning module is also used to perform a global scan of the wafer, establish a Cartesian coordinate system with the surface of the wafer as a reference, and store the coordinate information of each chip as the initial position information of the corresponding chip.

[0075] Optionally, the scanning module is also used to select N chips dispersed on the edge and center of the wafer as preset marker chips, where N≥3.

[0076] Optionally, the inspection module is also used to move the preset marker chip to the center of the field of view of the vision system; and to obtain the current position information of the preset marker chip by imaging and positioning the preset marker chip through the vision system.

[0077] Optionally, the data processing module is also used to calculate the coordinate difference between the current position information and the initial position information of the preset marker chip, and obtain the coordinate offset in different directions.

[0078] Optionally, the initial position information of the preset marker chip includes (X0, Y0), the current position information of the preset marker chip includes (X1, Y1), and the coordinate offset includes (△X, △Y), where △X = X1 - X0 and △Y = Y1 - Y0.

[0079] The data processing module is also used to superimpose the coordinate offset as a compensation value onto the initial position information of all chips generated by the scan, and update the coordinates (Xi, Yi) of each chip under test to (Xi-△X, Yi-△Y).

[0080] Optionally, the data processing module is also used to output alarm information if the offset threshold exceeds the safety threshold.

[0081] Optionally, the tolerance threshold is ±3μm and the safety threshold is ±10μm.

[0082] This disclosure provides a wafer testing machine for implementing the wafer testing method described above.

[0083] The wafer testing machine includes: a support stage, a motion slide, a vision positioning system, and electrical performance testing components.

[0084] The support stage is used to fix the wafer and is usually equipped with a vacuum adsorption system to ensure that the wafer does not shift or deform during testing; it can move the wafer to the target chip position.

[0085] The motion slide adopts a transmission structure driven by a linear motor or lead screw, with a motion resolution of up to 0.1μm and a positioning accuracy of ≤±2μm, ensuring the positional accuracy of the carrier platform movement.

[0086] Optionally, the visual positioning system includes a CCD camera and a light source control module. The CCD camera comprises a global low-resolution scanning lens and a local high-precision positioning lens. The global scanning is used to establish a full-wafer chip location index map, while the local positioning is used to perform high-precision imaging of the pre-marked chip and the pads of the chip under test, extracting feature coordinates. The light source control module provides suitable lighting conditions for visual imaging, ensuring image contrast of features such as chip pads and improving positioning accuracy.

[0087] Optionally, the electrical performance testing components include probe cards and a testing machine. The probe cards are arranged according to the chip pad layout and directly contact the chip pads to draw electrical signals. The testing machine can generate the voltage, current, and timing signals required for testing, acquire chip response data, and complete full-dimensional electrical performance tests such as open and short circuits, leakage current, functionality, and high-frequency characteristics.

[0088] The wafer testing method performed by the wafer testing machine provided in this embodiment sets the offset checking step before the formal test starts after the wafer scan is completed. This does not interrupt the continuous process of subsequent batch testing and does not increase the testing time of a single chip. Therefore, it does not affect the overall test cycle and is adapted to the high efficiency requirements of wafer testing.

[0089] Offset determination is achieved by comparing the positions of preset marker chips. There is no need to repeatedly perform high-precision local positioning on all chips on the entire wafer. Offset evaluation can be completed by only verifying the coordinates of a small number of marker chips, which greatly reduces the computing power and time cost of additional detection. At the same time, the offset threshold is calculated based on the difference between the initial position information and the current position information, which can accurately capture relative offset and avoid the problem that related technologies cannot detect mid-course offset.

[0090] Offset determination is performed before test initiation. If the offset threshold exceeds the tolerance threshold, calibration or process interruption can be triggered in a timely manner, fundamentally preventing probe positioning inaccuracies caused by accumulated offsets. This reduces the risk of test failures, chip damage, and even probe damage, ensuring the positioning accuracy and yield stability of subsequent batch testing of tens of thousands of chips on the entire wafer. Furthermore, the testing method only requires adding a chip marking verification step to the existing testing foundation, without significant modifications to the existing probe station's CCD vision system and motion control module. It is low-cost and easy to integrate into existing wafer testing production lines.

[0091] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A method for testing wafers, characterized in that, The testing method includes: Scan the wafer to obtain the initial position information of each chip on the wafer; Check the current position information of the preset marker chip; An offset threshold is determined based on the current position information and the initial position information of the preset marker chip; If the offset threshold exceeds the tolerance threshold, it is determined that the position of the wafer has shifted.

2. The test method according to claim 1, characterized in that, Scanning the wafer to obtain the initial position information of each chip on the wafer includes: A global scan is performed on the wafer, a Cartesian coordinate system is established with the surface of the wafer as a reference, and the coordinate information of each chip is stored as the initial position information of the corresponding chip.

3. The test method according to claim 2, characterized in that, After performing a global scan of the wafer and establishing a Cartesian coordinate system based on the surface of the wafer, the process further includes: N chips are selected from the wafer and dispersed at the edge and center of the wafer as the preset marker chips, where N≥3.

4. The test method according to claim 1, characterized in that, Checking the current position information of the preset marker chip includes: Move the preset marker chip to the center of the field of view of the vision system; The preset marker chip is imaged and located by the vision system to obtain the current position information of the preset marker chip.

5. The test method according to claim 1, characterized in that, Determining the offset threshold based on the current position information and the initial position information of the preset marker chip includes: Calculate the coordinate difference between the current position information and the initial position information of the preset marker chip to obtain the coordinate offset in different directions.

6. The test method according to claim 5, characterized in that, The initial position information of the preset marker chip includes (X0, Y0), the current position information of the preset marker chip includes (X1, Y1), and the coordinate offset includes (△X, △Y), where △X = X1 - X0 and △Y = Y1 - Y0. After determining that the wafer's position has shifted, the process further includes: The coordinate offset is used as a compensation value and superimposed on the initial position information of all chips generated by the scan, so that the coordinates (Xi, Yi) of each chip under test are updated to (Xi-△X, Yi-△Y).

7. The test method according to any one of claims 1 to 6, characterized in that, After determining that the wafer's position has shifted, the process further includes: If the offset threshold exceeds the safety threshold, an alarm message will be output.

8. The test method according to claim 7, characterized in that, The tolerance threshold is ±3μm, and the safety threshold is ±10μm.

9. A wafer testing apparatus, characterized in that, The testing apparatus includes: The scanning module is used to scan the wafer to obtain the initial position information of each chip on the wafer; The inspection module is used to check the current position information of the preset marker chip; The data processing module is used to determine an offset threshold based on the current position information and the initial position information of the preset marker chip, and is also used to determine that the position of the wafer has shifted if the offset threshold exceeds the tolerance threshold.

10. A wafer testing machine, characterized in that, The wafer testing machine is used to implement the wafer testing method as described in any one of claims 1 to 8.

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