A multi-channel high-speed data acquisition and adaptive transmission method

Abstract

The application discloses a kind of multi-channel high-speed data acquisition and adaptive transmission method, including obtaining the digital sampling signal of multi-channel radar echo;Inter-channel collaborative common mode interference suppression is carried out to digital sampling signal, and common mode component is stripped and effective signal component is extracted;Extract residual frequency offset to generate dynamic local oscillator signal, and the digital down-conversion of effective signal component obtains mixed frequency signal;Adaptive noise suppression weighting based on double time scale feature detection is carried out to mixed frequency signal;Target extraction factor is calculated in combination with pre-configured operating mode bandwidth and frequency offset state, and polyphase anti-aliasing filtering and extraction are executed;According to target extraction factor, fine filtering coefficient and quantization bit width compression strategy are adaptively selected, filtering and parallel packing are carried out, and are transmitted through high-speed optical interface.The application alleviates physical link bandwidth bottleneck, and improves data throughput and processing robustness.

Description

Technical Field

[0001] This invention relates to the field of high-speed radar data processing and transmission technology, and in particular to a multi-channel high-speed data acquisition and adaptive transmission method. Background Technology

[0002] As advanced radar systems develop towards higher resolution and wider-area surveillance, the amount of raw echo data generated by multi-channel high-sampling-rate analog-to-digital converters is increasing exponentially. Real-time, high-throughput, and high-fidelity acquisition, processing, and transmission of these massive broadband signals are of fundamental technical importance for backend computing platforms to achieve high-precision target detection, tracking, identification, and complex environment reconstruction.

[0003] Current typical radar data acquisition links usually employ a front-end chip to collect data, which is then uploaded to a back-end server for centralized algorithm processing via a standard high-speed bus (such as PCIe) or a general Ethernet interface. This traditional cascaded architecture easily reaches its limit in terms of the actual effective bandwidth of the bus physical interface when dealing with continuous high-speed data streams of tens or even hundreds of gigabits, resulting in transmission constraints. Furthermore, the long data transfer paths between different physical units, coupled with the complex handshake and encapsulation overhead of using a general network protocol stack, inevitably introduce high transmission latency and unpredictable timing jitter. In addition, in complex physical operating environments, the unavoidable physical coupling crosstalk between multi-channel analog links further increases the risk of front-end signal distortion.

[0004] In summary, existing data transmission and processing architectures face common technical challenges when dealing with next-generation massive broadband radar echoes: severely limited throughput bandwidth, difficulty in guaranteeing deterministic low latency, and insufficient system robustness under complex non-stationary interference. Therefore, it is necessary to investigate a method that can effectively improve the throughput and transmission stability of multi-channel massive data processing. Summary of the Invention

[0005] Purpose of the invention: To provide a multi-channel high-speed data acquisition and adaptive transmission method to solve the above-mentioned problems existing in the prior art.

[0006] Technical solution: A multi-channel high-speed data acquisition and adaptive transmission method, comprising:

[0007] Acquire digital sampling signals from multi-channel radar echoes;

[0008] Inter-channel collaborative common-mode interference suppression is performed on the digital sampled signal, common-mode components are stripped and effective signal components are extracted;

[0009] The residual frequency offset is extracted to generate a dynamic local oscillator signal, and the effective signal components are digitally down-converted and mixed using the dynamic local oscillator signal to obtain a mixed signal.

[0010] The mixed signal is subjected to adaptive noise suppression weighting based on dual time-scale feature detection to obtain a weighted baseband signal;

[0011] The target extraction factor is calculated by combining the pre-configured radar operating mode bandwidth and the current frequency offset state. The target extraction factor is then used to perform multiphase anti-aliasing filtering and downsampling extraction on the weighted baseband signal to obtain the extracted data.

[0012] Based on the target extraction factor, the fine filtering coefficients and quantization bit width compression strategy are adaptively selected. The extracted data is then filtered and packaged in parallel based on the selected fine filtering coefficients and quantization bit width compression strategy to obtain encapsulated data, which is then transmitted through a high-speed optical interface.

[0013] Beneficial effects: By employing a multi-rate decimation strategy based on link and frequency offset awareness, and an adaptive bit-width compression strategy, the physical bandwidth constraint of the optical port, the front-end signal bandwidth, and the frequency offset margin are dynamically coupled to adaptively reduce the sampling rate and quantization bit width without truncating the effective radar spectrum. This mechanism reduces the data bus occupancy rate, solves the technical bottleneck of massive data overflowing the physical link payload in ultra-wideband operating mode, and achieves non-blocking continuous transmission in all modes.

[0014] A pure hardware pipeline data channel was constructed, running directly from the RF analog front-end to the optical interface. This, combined with a high-speed and high-capacity hierarchical storage architecture and direct network protocol stack hardware encapsulation, reduced protocol overhead and timing jitter caused by general-purpose processor intervention and software system scheduling. This compressed the processing and packet transmission delays of multi-channel data, which is beneficial for meeting the real-time requirements of radar closed-loop control and high-frequency data interaction.

[0015] A multi-dimensional collaborative adaptive processing mechanism is introduced in both the spatial and temporal domains. In the spatial domain, inter-channel orthogonal projection based on dual-verification gating is introduced to effectively eliminate hardware common-mode crosstalk. In the temporal domain, a dual-timescale feature detection mechanism is introduced to dynamically suppress burst pulse interference, supplemented by residual frequency offset compensation based on delay conjugate autocorrelation. This enables the system to maintain target echo fidelity and system stability even under harsh operating conditions characterized by extremely low signal-to-noise ratios and strong pulse interference. Attached Figure Description

[0016] Figure 1 This is a flowchart of the multi-channel high-speed data acquisition and adaptive transmission method of the present invention.

[0017] Figure 2 This is a flowchart of the present invention for stripping common-mode components and extracting effective signal components.

[0018] Figure 3 This is a flowchart of the dual verification gating process of the present invention.

[0019] Figure 4 This is a flowchart of the process for extracting multidimensional subspaces according to the present invention. Detailed Implementation

[0020] Example 1: This example provides a multi-channel high-speed data acquisition and adaptive transmission device based on RFSoC. The device's physical architecture deeply integrates an RF analog front-end, a high-performance digital signal processing array, and an ultra-high-speed fiber optic communication interface.

[0021] Specifically, the core processing unit of the device uses an on-chip radio frequency system-on-a-chip (RFSoC). This chip integrates a multi-channel direct radio frequency analog-to-digital converter (RF-ADC), a multi-channel direct radio frequency digital-to-analog converter (RF-DAC), programmable logic (PL) resources, and a multi-core processor system (PS) on a single silicon chip.

[0022] In this embodiment, the eight independent ADC channels built into the RFSoC chip are connected to an external front-end signal conditioning circuit. The front-end signal conditioning circuit receives the echo analog signal from the radar downlink via an SSMA (Sub-miniature version A) coaxial connector, performs necessary filtering and gain amplification, and then converts the single-ended analog signal into a differential analog signal, which is then fed into the eight ADC channels for digital sampling. Similarly, the eight independent DAC channels built into the RFSoC chip are also connected to the corresponding conditioning circuit and SSMA connector to generate the excitation waveform for the radar uplink.

[0023] In terms of memory architecture design, this embodiment adopts a physically isolated dual DDR4 memory pool strategy to match access requirements at different time scales.

[0024] On one hand, a first DDR4 storage cluster, for example, consisting of four DDR4 chips with a total capacity of 4GB, is connected to the PS end of the processing system. This first DDR4 storage cluster is mainly controlled by a non-real-time operating system or bare-metal management program running on the PS end, and is used to cache large amounts of radar historical frame data, system global configuration parameters, and intermediate data when executing offline diagnostic algorithms.

[0025] On the other hand, a second DDR4 memory cluster, for example composed of two DDR4 chips with a total capacity of 2GB, is directly connected to the programmable logic unit (PL). This second DDR4 memory cluster serves as an ultra-low latency high-speed cache for the hardware computing unit, dedicated to storing core algorithm coefficients frequently accessed in real-time signal processing pipelines, such as down-conversion, multiphase decimation, and filtering processes. Examples include pre-built filter coefficient libraries and local oscillator waveform lookup tables. This dual-memory pool design avoids the uncertainty and latency introduced by real-time high-speed data streams competing for bus bandwidth with non-real-time management data.

[0026] Furthermore, regarding the ultra-high-speed data optical transmission unit, the device integrates two independent 100G QSFP28 optical modules at the edge of the printed circuit board. These two optical modules are directly connected to the programmable logic (PL) end via a high-speed serial transceiver. Inside the PL end, two 100G UDP protocol stacks composed entirely of hardware logic are deployed.

[0027] To achieve load balancing for massive data throughput, the eight ADC channels at the front end are divided into two physical binding paths: the processing data of ADC1 to 4 are fixedly mapped to the first 100GUDP protocol stack and transmitted by the first optical module; the processing data of ADC5 to 8 are mapped to the second 100GUDP protocol stack and transmitted by the second optical module.

[0028] By using a dual-link parallel topology, the data throughput of the entire system can be smoothly expanded to 200Gbps when the single-port bandwidth is limited in ultra-wideband operating mode.

[0029] In addition, the device is equipped with a Board Management Controller (BMC) circuit. This BMC circuit contains an independent microcontroller (such as the STM32 series) and is connected to the system's complex multi-rail low-noise power supply network and precision clock distribution network.

[0030] BMC is used to monitor voltage fluctuations, current consumption, and operating temperature of the core chip in the entire system, and to control the power-on and power-off startup sequence of the device, thereby ensuring the stable operation of RFSoC chips and optical modules under high peak power consumption scenarios.

[0031] Based on the aforementioned hardware platform, the analog radar echo signal, after conditioning, enters the ADC and is converted into a digital data stream. This digital data stream, within the PL (Plug-in) terminal of the RFSoC, undergoes a series of adaptive processing steps—common-mode rejection, digital down-conversion, adaptive noise weighting, multi-rate decimation, and bit-width packetization—complete entirely by a pure hardware logic pipeline without intervention from the PS (Power Supply) CPU. The processed, encapsulated data words are then directly fed into the hardware UDP protocol stack and transmitted to the remote server via an optical module with extremely low deterministic latency. Subsequent embodiments will elaborate on the specific signal processing methods and steps executed within the PL terminal.

[0032] Example 2 provides a multi-channel adaptive data processing and transmission method, which is the entire process from digital sampling signal acquisition to final optical port encapsulation and transmission, including the following steps:

[0033] Step 201: Acquire the digital sampling signal of the multi-channel radar echo.

[0034] In this embodiment, the digital sampling signal originates from the analog-to-digital converter unit at the front end of the radar receiving system.

[0035] Specifically, the analog radio frequency echo signal, after being filtered and conditioned by the radio frequency front-end, is input to the analog-to-digital converter (ADC) for high-frequency sampling. For example, the system is configured with eight synchronously sampling ADC channels, the ADC sampling frequency is set to 2.5 GHz, and the quantization bit width of a single sampling point is 16 bits. The resulting massive amount of digital sampled signals constitutes the raw input data stream for all subsequent digital signal processing pipelines. Based on this, the digital sampled signals exist in the form of continuous parallel data words in the hardware programmable logic unit and flow downstream to the module at line speed.

[0036] Step 202: Perform inter-channel collaborative common-mode interference suppression on the digital sampling signal, strip the common-mode component and extract the effective signal component.

[0037] To address the issues of inter-channel crosstalk and power ripple introduced by multi-channel radar receiving systems sharing the same printed circuit board power supply network and clock tree, this embodiment introduces a cross-channel collaborative processing mechanism in the spatial domain dimension.

[0038] Specifically, radar echo signals exhibit inherent spatial differences in amplitude and phase across different physical channels, while common-mode interference introduced by hardware physical coupling links displays a highly correlated rank-1 or low-rank spatial structure across all channels. The system performs block statistical feature analysis on the multi-channel parallel digital sampling signals, calculates the covariance feature matrix (covariance matrix) of the current data block, and uses an eigenvalue decomposition correlation algorithm to extract the principal feature directions characterizing the common-mode interference energy.

[0039] Then, an orthogonal complement space is constructed within this multidimensional spatial domain. The digital sampling signals of each channel are projected onto this orthogonal complement space, thereby stripping away highly correlated common-mode components without truncating the radar target echo energy. The signal output after the above orthogonal projection processing is the effective signal component, which is a clean service signal with system-level common-mode noise removed.

[0040] Step 203: Extract residual frequency offset from the data after extraction based on the historical processing cycle, generate dynamic local oscillator signal, and use dynamic local oscillator signal to perform digital down-conversion mixing on effective signal components to obtain mixed signal.

[0041] After acquiring the valid signal components, the system enters the down-conversion processing stage in the frequency domain. Traditional down-conversion schemes using a fixed local oscillator frequency will cause a shift in the center frequency of the demodulated baseband signal when faced with carrier drift from the radar transmitter or Doppler shift caused by high-speed target movement.

[0042] To address this issue, this step utilizes a closed-loop feedback mechanism to extract the residual frequency offset value in the system's digital domain in real time. Based on the extracted residual frequency offset, an internal complex numerically controlled oscillator (CNC oscillator) is driven to generate a dynamic local oscillator signal. This dynamic local oscillator signal contains a dynamic phase compensation sequence used to cancel the residual frequency offset in real time. Furthermore, using a complex multiplier tree in pure hardware logic, the dynamic local oscillator signal is multiplied point-by-point with the effective signal components, achieving a precise shift of the signal spectrum from the high-frequency intermediate frequency band to the zero-IF baseband. The output of this complex multiplication operation is the mixer signal.

[0043] Step 204: Perform adaptive noise suppression weighting on the mixing signal based on dual time-scale feature detection to obtain the weighted baseband signal.

[0044] Considering that the actual working environment of radar not only contains stable Gaussian white noise, but is also often accompanied by sudden broadband pulse interference, this embodiment performs adaptive amplitude weighting based on feature detection on the mixing signal.

[0045] Specifically, two exponential smoothing trackers with different memory time depths are used to perform parallel statistical updates on the instantaneous power characteristics of the mixing signal. The first tracker is used to quickly respond to transient changes in signal amplitude, while the second tracker is used to smoothly estimate the slowly varying noise floor of the background. By comparing the output power differences of the two trackers in real time, the system can detect sudden interference events in the current electromagnetic environment and calculate the weighting coefficients used to suppress noise at the current moment. Multiplying these weighting coefficients with the corresponding mixing signal achieves dynamic amplitude suppression of high-power interference components in the time domain, thereby outputting a weighted baseband signal.

[0046] Furthermore, as an alternative implementation, if the system is known to operate in a controlled and stable electromagnetic environment without sudden pulse interference, the adaptive noise suppression weighting process based on dual time-scale feature detection can also be configured to replace the conventional mean power weighting method based on a single fixed-length sliding time window, in order to reduce the dynamic consumption of hardware multiplier-accumulator resources.

[0047] Step 205: Calculate the target extraction factor by combining the pre-configured radar operating mode bandwidth and the current frequency offset state corresponding to the residual frequency offset, and use the target extraction factor to perform multiphase anti-aliasing filtering and downsampling extraction on the weighted baseband signal to obtain the extracted data.

[0048] After noise suppression is achieved, the transmission bottleneck of limited physical bandwidth of the fiber optic link is encountered. Due to the huge differences in target signal bandwidth in different radar operating modes, such as the extremely narrow bandwidth in precision tracking mode and the extremely wide bandwidth in synthetic aperture imaging mode, using a fixed decimation rate will result in severe signal truncation in broadband mode, or cause a large amount of redundant data in narrowband mode, thus wasting optical port bandwidth.

[0049] Therefore, the system obtains the pre-configured radar operating mode bandwidth issued by the main control terminal, as well as the current frequency offset state determined by step 203, and calculates a maximum integer downsampling factor that can satisfy the digital signal processing non-aliasing oversampling theorem and reserve a sufficient frequency offset protection band, i.e., the target extraction factor.

[0050] Subsequently, based on the determined target decimation factor, an anti-aliasing low-pass filter is performed on the weighted baseband signal, and redundant sampling points are discarded at intervals specified by the target decimation factor. Specifically, this filtering and decimation process is executed through polyphase decomposition and merging, allowing each polyphase branch of the filter to operate directly in the downsampled, low-speed clock domain. After the above processing, the data stream that originally operated at the full sampling rate of the analog-to-digital converter is proportionally reduced, and the output is the decimated data.

[0051] Step 206: Adaptively select fine filtering coefficients and quantization bit width compression strategy according to the target extraction factor. Based on the selected fine filtering coefficients and quantization bit width compression strategy, filter and pack the extracted data in parallel to obtain encapsulated data and transmit it through a high-speed optical interface.

[0052] Since the Nyquist bandwidth boundary of the extracted data stream has changed, continuing to use a fine filter with a fixed cutoff frequency will cause the filter transition band to intrude into the effective signal spectrum range.

[0053] Therefore, using the target extraction factor as the read address index, fine-filtering coefficients matching the current Nyquist bandwidth are loaded from a coefficient mapping library pre-stored in the cache. These fine-filtering coefficients are then used to perform in-band flattening compensation and out-of-band residual mirror component filtering on the extracted data.

[0054] Meanwhile, the physical bus bandwidth of the fiber optic interface is a rigid constraint. In order to ensure that the data rate of a single link does not overflow the effective payload of the optical port in the high throughput mode corresponding to the minimum decimation factor, the system adaptively selects the corresponding quantization bit width compression strategy according to the target decimation factor.

[0055] For example, a 16-bit compression strategy is selected when the target decimation factor is 2, and a 32-bit full-precision strategy is selected when the target decimation factor is 8. After truncating the low-bit data by executing the quantization bit-width compression strategy, the hardware elastic buffer unit is used to concatenate multiple consecutive sampling points of data after speed reduction and bit-width variation in parallel, and align them to the 512-bit fixed data bus of the 100G Ethernet protocol standard to obtain the encapsulated data.

[0056] Finally, the encapsulated data is injected into the hardware User Datagram Protocol (UDP) network protocol stack and transmitted at line speed to the backend server cluster via an external high-speed optical interface.

[0057] Example 3: Based on the above examples, the specific process of inter-channel cooperative common-mode interference suppression is described.

[0058] This spatial domain common-mode interference stripping mechanism addresses the highly correlated common-mode crosstalk problem introduced by the shared power network and clock tree of multi-channel analog-to-digital converters. It achieves interference suppression through covariance matrix feature extraction and dual-verification gating.

[0059] Step 301: Under the condition of no front-end radar echo input, short-circuit the analog input terminal of the device to the analog ground level and collect the initial clean common-mode sampling data of multiple channels.

[0060] During the system power-on initialization phase, the ideal assumption of uniform common-mode distribution often fails due to inherent physical differences between the front-end amplifiers of each analog-to-digital conversion channel and the printed circuit board traces. Therefore, the device enters calibration mode, disconnects external RF signals, and pulls the analog channel inputs down to analog ground. The data acquired at this time contains only internal power supply ripple, clock crosstalk, and channel-specific thermal noise, constituting the initial clean common-mode sampling data.

[0061] Step 302: Calculate the local covariance features of the initial clean common-mode sampling data of multiple consecutive data blocks and sum and average them to obtain the average covariance features.

[0062] To obtain stable spatial correlation statistics, the system collects a preset number of data blocks. For each data block, the inner product between samples from each channel is calculated and the mean is taken to obtain the covariance matrix within the block. The covariance matrices of all collected data blocks are summed element-wise and divided by the number of blocks to obtain the average covariance feature. Through this summation and averaging process, independent thermal noise cross terms approach zero, while highly correlated common-mode interference features are extracted and retained in the main diagonal and off-diagonal elements of the covariance matrix.

[0063] Step 303: Extract the baseline feature direction vector from the average covariance features using an iterative algorithm.

[0064] Based on the obtained average covariance features, the eigenvalue decomposition algorithm is used to extract the eigenvector corresponding to the largest eigenvalue.

[0065] Since the system is in a pure common-mode state with no signal input at this time, the extracted reference feature direction vector represents the actual gain and polarity distribution mapping relationship of various common-mode interference sources coupled to each physical channel in the actual hardware system.

[0066] Step 304: The extracted baseline feature direction vector is normalized using the second norm to satisfy the unit norm constraint. This ensures that the subsequent inner product calculation result γ(m) corresponds to the spatial direction similarity (i.e., the absolute value of the cosine of the included angle), and its numerical range is constrained to between 0 and 1, giving the setting of the structural similarity threshold a clear geometric meaning. The baseline feature direction vector is then stored as a pre-configured calibration reference vector for use as a comparison benchmark during online real-time structural similarity calculation.

[0067] After obtaining the reference feature direction vector, it is written into the high-speed register group inside the programmable logic unit and stored as a pre-configured calibration reference vector. When entering the normal radar receiving mode, this vector will serve as a spatial topology metric for evaluating whether the main direction extracted online belongs to common-mode interference, avoiding misjudgments caused by inconsistent hardware channel gains.

[0068] According to one aspect of this application, inter-channel cooperative common-mode interference suppression is performed on a digitally sampled signal, stripping the common-mode component and extracting the effective signal component, including:

[0069] Step 305: Divide the digital sampling signal into continuous current data blocks in the time dimension.

[0070] Once in online operation, the system receives a digital sampled signal from the RF front-end, which includes a mixture of radar echoes and common-mode interference. A counter in the hardware pipeline truncates the continuous data stream into non-overlapping, equal-length segments according to a set clock cycle, forming the current data block. In a specific implementation, the data block length can be set to 256 sampling times, a length that provides sufficient sample space for covariance estimation while maintaining low computational latency.

[0071] Step 306: Calculate the local covariance features of the current data block, and perform exponential weighted smoothing of the local covariance features with the historical covariance data of the previous data block to obtain the smoothed covariance features.

[0072] At the boundary of each current data block, the system calculates the local covariance features encompassing the interrelationships of all channels. Due to the non-stationary nature of the radar signal environment, directly using the single-block covariance would lead to frequent fluctuations in the direction of subsequently extracted features. Therefore, an exponential moving average filter is introduced, with the following operational relationship:

[0073] R _hat (m)=β _cm *R _hat (m-1)+(1-β _cm )*C(m);

[0074] Among them, R _hat (m) represents the smoothed covariance feature of the current data block, β_cm R is the forgetting factor. _hat (m-1) represents the historical covariance data of the previous data block, and C(m) represents the local covariance feature of the current data block. The preset forgetting factor is greater than or equal to 0.90 and less than or equal to 0.99. The larger the value, the higher the weight of the historical data and the stronger the smooth decay effect, but the slower the response speed to slowly changing coupling characteristics such as temperature drift.

[0075] Step 307: Use an iterative algorithm to extract the principal feature direction vector representing the spatial distribution of common-mode interference from the smooth covariance features;

[0076] Step 308: Construct the orthogonal complement space corresponding to the main feature direction vector, and project the digital sampling signal into the orthogonal complement space to remove the common mode component and obtain the effective signal component.

[0077] When the control logic is active, for each clock cycle of the multi-channel sampled vector within the current data block, its projected component along the principal characteristic direction is subtracted. This process is achieved by calculating the inner product of the digital sampled signal and the principal characteristic direction vector, and then multiplying this inner product by the principal characteristic direction vector. After this subtraction operation, the signal vector is confined to a subspace orthogonal to common-mode interference. The result of this orthogonal projection is the effective signal component free from the influence of common-mode interference.

[0078] Step 309: When no condition is met, bypass projection operation is performed, and the unprojected digital sampled signal is directly used as the valid signal component.

[0079] If the energy concentration is judged to be low or the structural similarity is below a set threshold, it indicates that the currently extracted main feature direction is dominated by randomly distributed broadband radar target signals or independent noise floor. The system determines that performing a forced projection operation at this time would cause severe distortion of the signal waveform, so it executes bypass logic through a multiplexer. Matrix transformation operations are not applied to the data of each channel of the current data block; the original input digital sampling signal is directly passed through and output as valid signal components.

[0080] Step 310: Extract multiple sequentially orthogonal feature direction vectors from the smoothed covariance features and the subsequently updated residual covariance features.

[0081] In a further optional implementation, for complex physical scenarios where multiple independent common-mode interference sources exist in the system, these interference sources can specifically include high-frequency ripple from the switching power supply and phase noise from the analog-to-digital converter sampling clock. Since these two types of interference sources coexist and their physical coupling paths to each channel are different, a single main feature direction cannot cover the entire interference subspace dimension. In this scenario, the system executes multi-dimensional subspace extraction logic, sequentially extracting feature vectors corresponding to the second largest feature value until a preset upper limit for the extraction dimension is reached. This upper limit can be set to a value of 3, thereby obtaining multiple sequentially orthogonal feature direction vectors.

[0082] Step 311: After extracting each feature direction vector, subtract the projection component of the corresponding direction from the current covariance features to update the residual covariance features.

[0083] During the iterative extraction process, the weighting effect of the extracted feature directions needs to be eliminated from the covariance matrix. The computational steps involve calculating the autocorrelation matrix of the extracted feature direction vectors and multiplying it by the corresponding eigenvalues. This product matrix term is then subtracted from the covariance feature matrix of the previous cycle to obtain the residual covariance features. Subsequent iterations are all initiated based on the updated residual covariance features, achieving matrix shrinkage and dimensionality reduction.

[0084] The corresponding eigenvalues ​​are obtained by calculating the Rayleigh quotient of the eigendirection vector and the covariance eigenma matrix, that is, by left-multiplying the eigendirection vector by the covariance eigenma matrix and then right-multiplying it by the transpose of the vector. This calculation process shares the same results as the molecular calculation of energy concentration in step 309.

[0085] Step 312: For each extracted feature direction vector, calculate the corresponding energy concentration and structural similarity independently, and filter out the effective interference direction set based on whether the dual conditions are met.

[0086] For each feature direction vector generated in the above extraction process, the system substitutes it into the calculation modules of steps 309 and 310 to calculate the corresponding gating parameters. Then, it compares the dual threshold conditions of energy and structure, retains only the feature direction vectors that satisfy all dual gating constraints, and removes the random component directions that fail to meet the conditions. Finally, the retained feature direction vectors together constitute the effective interference direction set.

[0087] Step 313: Project the digital sampled signal into the orthogonal complement space of the joint subspace composed of the effective interference direction set to obtain the effective signal components.

[0088] Utilizing the set of mutually orthogonal vectors encompassed in the effective interference direction set, the system sequentially performs inner product calculations and dimension reduction subtraction operations on the input multi-channel data vectors. Each vector subtraction operation removes the common-mode dimension component of an independent physical interference source from the multi-dimensional geometric space. After completing the dimension reduction projection of all retained direction vectors, the system outputs the effective signal components under the multi-source interference suppression scenario to the subsequent signal processing pipeline.

[0089] According to one aspect of this application, it also includes:

[0090] The main feature direction vector output from the previous data block is used as the initial start vector for the iterative algorithm of the current data block.

[0091] When extracting the common mode principal feature direction, if each data block uses a random vector or a vector of all 1s as the starting point, it will require a large number of iterations to reach the convergence threshold, which cannot meet the real-time requirements under extremely high sampling rates.

[0092] Considering that the spatial distribution of the hardware physical coupling path remains stable within a short time interval between adjacent data blocks, this step extracts the feature vectors that have converged in the previous processing cycle and directly assigns them to the iterative algorithm of the current cycle as the starting point of the iteration, thereby realizing the inheritance of the initial state of the algorithm.

[0093] The initial starting vector is used to perform exponential iteration on the smooth covariance features corresponding to the current data block to accelerate convergence and extract the principal feature direction vector at the current time.

[0094] Matrix multiplication is performed using the initial starting vector and smoothed covariance features to calculate a new direction vector. The L2 norm of this vector is then calculated, followed by normalized division. Based on the initial state inheritance mechanism, this process achieves the required accuracy after a very small number of iterations. In a preferred embodiment, the maximum number of iterations is set to 2. The output after this fixed number of iterations and normalization is the principal feature direction vector at the current moment.

[0095] According to one aspect of this application, after extracting the principal feature direction vector representing the spatial distribution of common-mode interference from the smooth covariance features using an iterative algorithm, and before constructing the orthogonal complement space corresponding to the principal feature direction vector, a dual verification gating is further performed:

[0096] Step 1: Calculate the energy concentration of the principal feature direction vector in the smooth covariance feature.

[0097] To avoid misidentifying the radar's own echo signal as interference, the system quantifies the extracted direction. The calculated energy concentration reflects the power share of the main characteristic direction, and its specific calculation relationship is as follows:

[0098] ρ(m)=(v_1 T *R _hat (m)*v _1 ) / tr(R _hat (m));

[0099] Where ρ(m) is the energy concentration, v _1 Principal feature direction vector, v _1 T For its transpose, R _hat (m) represents the smoothing covariance feature, and tr(...) is the matrix trace function, representing the total power of all channels. When strong common-mode interference exists, the power in the principal component direction is absolutely dominant, and this ratio increases monotonically.

[0100] Step 2: Calculate the structural similarity between the main feature direction vector and the pre-configured calibration reference vector.

[0101] The system calculates the absolute value of the inner product between the principal feature direction vector and the pre-configured calibration reference vector saved in step 304 in a multi-dimensional space. The calculation formula is as follows:

[0102] γ(m)=abs(v _1 T *v _cal );

[0103] Where γ(m) is the structural similarity, abs is the absolute value function, and v _1 T The transpose of the principal feature direction vector, v _cal This is a pre-configured calibration reference vector. This value measures the cosine of the angle between the two vectors' spatial lines; the closer the value is to 1, the more parallel their spatial topological orientations.

[0104] Step 3: Determine whether the energy concentration is greater than the preset energy concentration threshold and whether the structural similarity is greater than the preset structural similarity threshold.

[0105] The system utilizes a hardware comparator module to simultaneously compare the calculated energy concentration with a preset energy concentration threshold, and also compares the structural similarity with a preset structural similarity threshold. The preset energy concentration threshold can be set to 0.25 to verify the proportion of the main direction power to the total power of all channels; the preset structural similarity threshold can be set to 0.70. These two numerical judgments constitute a rigorous dual-verification logic gate.

[0106] Step 4: When the dual conditions are met, the step of constructing the orthogonal complement space of the corresponding main feature direction vector is triggered.

[0107] If the outputs of the two logical judgment operations above are both logically true, it indicates that the currently extracted spatial direction has both the high concentration of energy characteristics required for interference and conforms to the common-mode coupling geometry of the physical hardware circuit. The system control logic will then activate the subsequent spatial projection dimensionality reduction operation.

[0108] Example 4 provides a method for frequency offset estimation based on delay conjugate autocorrelation, specifically the implementation process of extracting residual frequency offset in the frequency tracking stage. Addressing the carrier drift or Doppler shift issues that exist in multi-channel radar data after digital down-conversion, a closed-loop frequency compensation system is constructed by extracting phase increments from historical data.

[0109] Step 401: Obtain the historical extracted data after fine filtering.

[0110] In this embodiment, the historical decimated data refers to the baseband complex signal sequence that has undergone anti-aliasing decimation and out-of-band noise filtering in the previous radar processing frame. The data from this node is chosen as the input source for frequency estimation because the current sampling rate is reduced after decimation, thereby decreasing the number of multiplication operations in subsequent autocorrelation calculations. Simultaneously, the fine filter removes in-band and out-of-band interference noise, resulting in the highest signal-to-noise ratio in the entire digital signal processing chain. This data is acquired by directly reading the dual-port random access memory (DRAM) within the field-programmable gate array (FPGA) used for caching inter-frame data.

[0111] In some optional implementations, to avoid interference from the transient response of the fine filter during the frame start stage on the frequency estimation accuracy, the system automatically skips a number of consecutive sampling points in the frame header when acquiring historical decimated data. The number of skipped sampling points is equal to the order of the fine filter, thereby ensuring that all samples involved in the estimation are in the steady-state output range and avoiding the introduction of estimation errors by invalid transient data.

[0112] Upon system power-on reset or the start of the first frame processing, the buffered data used for frequency offset estimation is initialized to an all-zero vector, corresponding to an initial estimated value of zero hertz for the residual frequency offset. The dynamic local oscillator signal then operates from the nominal local oscillator frequency with zero frequency offset. Those skilled in the art will understand that in a closed-loop frequency tracking system, starting from zero frequency offset initialization and undergoing feedback iterations across several processing frames, the system will complete frequency pulling and reach a steady-state operating state within a finite time. This initialization method is a standard engineering practice in this field.

[0113] Step 402: Perform a delay conjugate autocorrelation operation on the historical extracted data based on the pre-configured delay amount to obtain the complex correlation result.

[0114] After obtaining the steady-state historical data, the system hardware pipeline performs sample-by-sample complex multiplication and accumulation operations on it. The relationship satisfies:

[0115] R=Σ(y(n)*y _conj (n-τ)) / N _est ;

[0116] Where R represents the complex correlation result of the output, Σ represents the summation operation over all valid sampling points, and y(n) represents the historical extracted data at the current sampling time. _conj (n-τ) represents the complex conjugate of the data after being delayed by a pre-configured delay amount τ, and N _est This represents the total number of valid samples participating in the accumulation calculation. In the underlying logic circuit implementation, the above single complex multiplication is decomposed into 4 real multiplications and 2 real additions or subtractions. The accumulator bit width is set to 44 bits based on the total number of valid samples to prevent numerical overflow during thousands of accumulations.

[0117] Furthermore, the choice of the pre-configured delay τ directly determines the unambiguous observation range of the phase increment extraction. In order to maintain a constant unambiguous physical boundary at different downsampling rates, the pre-configured delay is inversely proportional to the current downsampling factor.

[0118] For example, when the decimation factor is set to 2 and the corresponding baseband sampling rate is 1.25 GHz, the pre-configured delay is set to 8; when the decimation factor is set to 16 and the corresponding baseband sampling rate is 156.25 MHz, the pre-configured delay is set to 1. Through this dynamic mapping mechanism, the unambiguous frequency range of the system in any operating mode remains constant at ±78.125 MHz, covering the maximum frequency offset tolerance range preset by the radar system.

[0119] Step 403: Calculate the argument of the complex correlation result and extract the average phase increment of the historical data after extraction.

[0120] After completing the autocorrelation accumulation of all samples within a frame, the system extracts the real and imaginary parts of the complex correlation results to calculate their relative angle in the complex plane. The average phase increment is the statistical average of the phase deflection of the baseband signal after a pre-configured delay.

[0121] In the specific hardware implementation, the system uses a coordinate rotation digital computer algorithm to replace the traditional arctangent operation with pure logic gates.

[0122] Specifically, the real and imaginary parts of the complex correlation results are injected as input channel data into the coordinate rotation digital computer pipeline. Without consuming any digital signal processing multiplier resources, a 16-bit precision angle value is calculated solely through cascaded iterations of 16 shift registers and adders. This angle value directly corresponds to the average phase increment, and its output value is limited to the range of -π to +π.

[0123] Step 404: The average phase increment is combined with the pre-configured delay and the current sampling rate to calculate the residual frequency offset, and the dynamic local oscillator signal is updated based on the residual frequency offset.

[0124] After obtaining the average phase increment in angular form, the system converts it from the phase domain to the frequency domain. The relationship satisfies:

[0125] δ _f =(f _sp / (2*pi*τ))*θ;

[0126] Where, δ _f For the calculated residual frequency offset, f _sp Here, pi represents the current sampling rate corresponding to the historical extracted data, τ represents the constant value of pi, θ represents the pre-configured delay, and θ represents the average phase increment of the solution output. Since some parameters in the extraction formula can be pre-calculated statically, the system combines the fixed parameters into a single constant multiplier, allowing the conversion process to be completed in a field-programmable gate array (FPGA) with only a single fixed-point multiplication.

[0127] After obtaining the residual frequency offset, the system inputs it as an error feedback parameter into the proportional-integral control loop, and calculates the real-time dynamic frequency compensation amount for the current frame by combining it with the historical state of the previous frame.

[0128] The real-time dynamic frequency compensation drives the phase accumulator module of the digitally controlled oscillator to update and generate a dynamic local oscillator signal with phase correction characteristics clock cycle by clock cycle. This dynamic local oscillator signal is injected into the mixer multiplier of the current data frame, thereby eliminating the baseband spectrum offset caused by residual frequency deviation in a closed loop.

[0129] Example 5 further illustrates the adaptive noise suppression weighting process based on dual time-scale feature detection.

[0130] To address the simultaneous presence of stationary Gaussian white noise and sudden impulse interference in radar echoes, precise response and interference suppression to transient electromagnetic environments are achieved through full-scale normalized scaling and coordinated detection by fast and slow dual-path exponential moving average trackers.

[0131] Step 501: Obtain the full-scale amplitude reference of the analog-to-digital converter.

[0132] In this embodiment, the system needs to establish a unified dimensional reference standard to eliminate the influence of hardware sampling accuracy on the algorithm threshold setting. The system obtains the quantization bit width parameter of the analog-to-digital converter in the front-end hardware circuit and calculates the full-scale amplitude reference based on this parameter. For example, when the quantization bit width of the analog-to-digital converter is configured to 16 bits, its supported discrete value range is limited by the binary code length. The system calculates 2 to the power of 15 to obtain the value 32768 as the full-scale amplitude reference. This reference represents the maximum absolute amplitude that the analog-to-digital converter can output without signal clipping distortion.

[0133] In some alternative implementations, the full-scale amplitude reference can be pre-programmed into a read-only memory, or dynamically sent by the main control unit to the configuration register of the digital signal processing pipeline via a programmable logic bus during the system power-on reset phase for latching.

[0134] Step 502: The instantaneous amplitude normalization process of the mixing signal is performed using the full-scale amplitude reference, and the signal amplitude is mapped to a unified scale space to ensure that the scale for subsequent determination of preset interference amplitude conditions has dimensional consistency.

[0135] After obtaining the full-scale amplitude reference, the system performs a sample-by-sample division ratio conversion on the mixing signal output from the digital downconverter module. _norm (n)=y _mix (n) / A _FS ;

[0136] Among them, y _norm (n) represents the normalized mixing signal, y _mix (n) represents the original input mixing signal, A _FS It serves as the full-scale amplitude reference.

[0137] After the above division operation, the original signal amplitude, which could reach tens of thousands, is mapped to a normalized unified scaling space ranging from -1 to +1. This normalization operation ensures that the subsequent power detection thresholds no longer depend on the specific hardware platform gain settings, thus guaranteeing the dimensional consistency and portability of the algorithm under different radar receiver configurations.

[0138] Step 503: Extract the instantaneous power characteristics (instantaneous amplitude characteristics) of the mixing signal.

[0139] The system performs power dimension conversion on the normalized mixed signal. Specifically, it extracts the in-phase and quadrature components of the mixed signal, calculates their squares, and sums them to obtain the instantaneous power feature, which characterizes the instantaneous power of the signal at the current sampling moment. This feature, as a non-negative real number sequence, is input to the subsequent parallel power tracking module.

[0140] Step 504: The instantaneous power features are iteratively updated sample by sample using an exponential smoother with a first memory depth to obtain the fast tracking noise power.

[0141] The first power estimation branch is initiated in the time dimension. The fast tracking branch does not apply amplitude gating to the instantaneous power features at all times, and performs unconditional iterative updates on a sample-by-sample basis:

[0142] P _fast (n)=λ _f *P _fast (n-1)+(1-λ _f )*P _inst (n);

[0143] Among them, P _fast (n) represents the fast tracking noise power updated at the current sampling time, λ _f P is a forgetting factor with the first memory depth. _fast (n-1) represents the fast tracking noise power at the previous sampling time, P _inst (n) represents the instantaneous power feature extracted at the current sampling moment. This gateless design enables the fast tracking branch to respond promptly to power surges caused by sudden pulse interference events, providing a sensitive reference value for subsequent dual-channel comparison detection.

[0144] In one example, it could also be: using an exponential smoother with a first memory depth to perform unconditional iteration updates on the instantaneous power features on a sample-by-sample basis to obtain the fast tracking noise power;

[0145] Specifically, a preset interference amplitude condition is set, and a hardware comparator is used to implement gating judgment. This gating judgment is used by the slow tracking branch. The fast tracking branch does not apply amplitude gating to the instantaneous power characteristics at all times, and performs unconditional iterative updates on a sample-by-sample basis.

[0146] In this embodiment, the forgetting factor λ _f It can be set to 0.9, which is equivalent to a sliding time window of length 10. This enables the fast tracking noise power to respond to sudden changes in the external electromagnetic environment within an extremely short clock cycle, achieving agile tracking of transient pulses.

[0147] The instantaneous power characteristics at the current moment are compared with the preset interference amplitude conditions using a comparator.

[0148] Step 505: Simultaneously use an exponential smoother with a second memory depth to iteratively update the instantaneous power characteristics that meet the preset interference amplitude conditions to obtain the slow tracking noise power, wherein the second memory depth is greater than the first memory depth.

[0149] While performing the fast tracing operation, the system starts a second parallel power estimation branch in the time dimension.

[0150] Unlike the fast tracking branch, the slow tracking branch is designed to stably estimate a clean background noise floor over time. Therefore, it needs to remove high-amplitude samples containing radar target echoes and sudden interference energy. The system sets a preset interference amplitude condition, specifically a normalized power of 0.05, as the amplitude gating criterion. When the instantaneous power characteristic is less than 0.05, the current sample is determined to belong to the valid noise space and is allowed to participate in the slow tracking power update; otherwise, it is determined to contain radar target echoes or strong interference, and the slow tracker maintains its previous value at the current moment.

[0151] Similarly, under the premise of satisfying the preset interference amplitude condition, the relationship is:

[0152] P _slow (n)=λ _s *P _slow (n-1)+(1-λ _s )*P _inst (n);

[0153] Among them, P _slow (n) represents the slow tracking noise power updated at the current sampling time, λ _s P is a forgetting factor with second-degree memory depth. _slow (n-1) represents the slow tracking noise power at the previous sampling time, P _inst (n) represents the instantaneous power feature extracted at the current sampling time.

[0154] The forgetting factor λ_s is set to a value greater than the first memory depth, for example, 0.99, which is equivalent to a sliding time window of length 100. In a stable radar background noise environment, this slow tracking branch can provide a baseline estimate of background power with minimal statistical variance and a smooth curve, overcoming the numerical jitter problem caused by short time window estimation.

[0155] Step 506: Calculate the ratio of the relative deviation between the fast tracking noise power and the slow tracking noise power to obtain a transient characterization index for characterizing the current interference environment.

[0156] In order to make intelligent decisions between the two trackers, one fast and one slow, the system introduces a transient detector module to quantify the degree of discrepancy between them.

[0157] η(n) = abs(P) _fast (n)-P _slow (n)) / (P _slow (n)+ε);

[0158] Where η(n) is the transient characterization index calculated and output at the current sampling time, abs is the absolute value function, and P _fast(n) represents the fast tracking noise power, P _slow (n) represents the slow tracking noise power, and ε is a minimal constant to prevent division by zero errors.

[0159] The value of the minimum constant ε can be set to 10 to the power of -10. This value is slightly larger than the quantization noise floor power, which avoids hardware divider overflow caused by the denominator being zero, and does not introduce perceptible deviations into the calculation of normal signal power.

[0160] In a stable background noise environment, the outputs of the fast tracking branch and the slow tracking branch tend to be consistent, and the transient performance index remains at a low level. When a noise floor jump occurs in the electromagnetic environment, the fast tracking branch, with its shorter memory depth, tracks the noise floor change first, while the slow tracking branch, due to its higher inertial lag response, causes a deviation in their outputs. This results in a rapid increase in the transient performance index, exceeding the preset transient switching threshold. The system then switches to the fast tracking branch to obtain a noise floor estimate that is closer to the current environment.

[0161] Step 507: When the transient characterization index is greater than the preset transient switching threshold, the fast tracking noise power is selected as the target noise power; otherwise, the slow tracking noise power is selected as the target noise power. The target noise power is used for subsequent weighted execution steps.

[0162] The system's data selector module performs hard switching based on transient performance indicators. The preset transient switching threshold can be set to 0.3. In a stable background noise environment, the outputs of the fast tracking branch and the slow tracking branch tend to be consistent, and the transient performance indicator remains at a low level. The system determines that it is currently in a stable state, and the data selector activates the slow tracking branch, using its output as the target noise power. When a sudden change in noise floor occurs in the electromagnetic environment, the fast tracking branch tracks the power change first, while the slow tracking branch, due to its higher inertial lag, responds with a significant deviation between the two outputs. The transient performance indicator quickly exceeds the preset transient switching threshold, and the system determines that it is currently in a transient state. The data selector switches to the fast tracking branch output as the target noise power. Through this quantization gating of relative deviation, adaptive locking is achieved for complex, non-stationary noise environments.

[0163] Step 508: Use an exponential smoother with a second memory depth to perform a global iterative update on the instantaneous power characteristics that have not been filtered by amplitude conditions to obtain the global signal power.

[0164] The system activates a third power estimation branch to assess the total energy level, which includes radar echoes, target signals, and all background noise. This branch accepts all instantaneous power characteristics of the inputs without imposing any thresholding or discarding logic. The relationship satisfies:

[0165] P _signal (n)=λ_s *P _signal (n-1)+(1-λ _s )*P _inst (n);

[0166] Among them, P _signal (n) represents the updated global signal power at the current sampling time, λ _s P is a forgetting factor with second-degree memory depth. _signal (n-1) represents the global signal power at the previous sampling time, P _inst (n) represents the instantaneous power feature extracted at the current sampling time. This branch also reuses a forgetting factor with a parameter of 0.99 to ensure the stability of the total signal power estimation.

[0167] Step 509: Calculate the power ratio of the target noise power to the global signal power, determine the adaptive weighting coefficient based on the difference between the base gain reference value and the power ratio, and restrict the adaptive weighting coefficient to a non-negative value.

[0168] After obtaining the pure noise floor estimate and the total power of the mixed signal, the system calculates the attenuation factor used for dynamically modulating the signal amplitude. The relationship satisfies:

[0169] α(n) = max(0, 1 - P) _noise (n) / (P _signal (n)+ε));

[0170] Where α(n) is the adaptive weighting coefficient calculated at the current sampling time, max is the maximum value function, 1 is the basic gain reference value, and P _noise (n) represents the target noise power selected in step 507, P _signal (n) represents the global signal power updated in step 508, and ε is a minimal constant to prevent division by zero errors.

[0171] When the input signal contains extremely strong radar target echoes, the global signal power is much greater than the target noise power, and the power ratio approaches 0. The calculated adaptive weighting coefficient approximates the baseline gain of 1, achieving lossless signal penetration. When the background noise floor of the external electromagnetic environment increases overall, the target noise power tracks to the increased noise floor level, the power ratio increases, and the adaptive weighting coefficient decreases accordingly, achieving dynamic suppression of the increased noise floor. For transient, isolated high-power pulse interference, since its amplitude exceeds the preset interference amplitude condition, such samples do not participate in noise power estimation. The system excludes them from noise floor tracking through a gating mechanism, avoiding contamination of the noise floor estimation by pulse interference.

[0172] Step 510: Amplitude modulation of the corresponding mixing signal is performed using adaptive weighting coefficients to obtain a weighted baseband signal.

[0173] The system feeds the mixed signal into a delay-aligned buffer in the hardware pipeline to compensate for the pipeline clock cycle delay introduced by the parallel power tracking calculation. Subsequently, a hardware digital multiplier performs sample-by-sample scalar multiplication modulation on the delayed-aligned mixed signal and the adaptive weighting coefficients calculated in step 509. The complex signal sequence output after this dynamic amplitude modulation is the weighted baseband signal, which has had its energy spikes from burst pulse interference removed in the time domain.

[0174] Furthermore, in an alternative approach, if it is known in advance that the radar system is deployed in a stable test environment controlled by electromagnetic shielding, the fast tracking branch and transient detector module can be bypassed by modifying the configuration of the control registers in the field-programmable gate array.

[0175] At this point, the system degradation uses a single fixed-length sliding time window to calculate a single background noise floor, thereby meeting the system noise reduction requirements while shutting down redundant logic operation units to reduce the overall dynamic power consumption of the chip.

[0176] Example 6: Based on the above examples, the process of multi-rate decimation and cross-frame handover based on link and frequency offset sensing is described. By jointly calculating the hard bandwidth constraints of the optical communication link, the radar operating mode bandwidth, and the real-time frequency offset, the optimal downsampling rate is dynamically and adaptively calculated, and a complete underlying hardware anomaly protection and cross-frame handover protocol are provided.

[0177] Step 601: Obtain the pre-configured set of candidate extraction factors.

[0178] In this embodiment, the system needs to predetermine a set of available downsampling ratios based on the physical carrying capacity limit of the fiber optic link and the constraints of the hardware processing clock. Specifically, the system obtains a pre-configured set of candidate decimation factors, which consists of multiple positive integers. For example, this set can be configured to include the values ​​2, 4, 8, and 16. The value 2 in the set corresponds to the maximum data throughput ultrawideband mode supported by the system, and the value 16 corresponds to the minimum data throughput narrowband tracking mode supported by the system.

[0179] Step 602: Based on the pre-configured radar operating mode bandwidth, calculate the lower limit of the bandwidth that satisfies the oversampling theorem, and set the oversampling constraint condition for the target signal bandwidth.

[0180] The system receives radar operating mode configuration parameters from the upper-level main control unit via the processor's internal bus and parses them to obtain the pre-configured radar operating mode bandwidth. To prevent spectral folding and aliasing during digital signal downsampling processing, the system introduces an oversampling factor and calculates an oversampling constraint threshold.

[0181] Their relation satisfies: Cos1 = κ * B_w;

[0182] Where Co_os1 is the initial oversampling constraint threshold, κ is the set oversampling factor, and B_w is the pre-configured radar operating mode bandwidth.

[0183] The oversampling factor κ is usually set to a real number greater than 2.0, such as 2.5. This value not only satisfies the basic requirements of the Nyquist sampling theorem, but also reserves 25% of the extra spectral space as the transition band margin of the anti-aliasing filter.

[0184] Step 603: Based on the current frequency offset state, calculate the extended bandwidth including the absolute value of the frequency offset, and set the protection bandwidth constraint condition including the frequency offset compensation margin.

[0185] Considering that radar echo signals may still have incompletely eliminated transient residual frequency offsets after dynamic mixing, directly performing dead-zone extraction based on the nominal bandwidth might cause the edges of the frequency offset signal to be truncated by the filter. The system acquires the current frequency offset state output by the frequency tracking module and amplifies the absolute value of this frequency offset to extend it into the equivalent bandwidth of the signal. The relationship satisfies:

[0186] B _eff =B _w +2*abs(δ _ferr ); C _os2 =κ*B _eff ;

[0187] Where B_eff is the equivalent signal bandwidth including frequency offset compensation margin, B _w The pre-configured radar operating mode bandwidth, abs is the absolute value function, δ _ferr To obtain the current frequency offset state, C _os2 κ is the oversampling constraint threshold that ultimately incorporates the frequency offset protection bandwidth constraint.

[0188] Step 604: Calculate the corresponding downsampling rate by combining the original sampling rate of the system with the factors in the candidate extraction factor set, and select the largest factor that makes the downsampling rate simultaneously satisfy the oversampling constraint and the protection bandwidth constraint as the target extraction factor.

[0189] The system iterates through all elements in the candidate extraction factor set, dividing the system's original high-frequency sampling rate by each element to calculate the theoretical downsampling rate for each factor. Subsequently, the system uses a numerical comparator to filter factors whose theoretical downsampling rate is greater than or equal to the oversampling constraint threshold C. _os2The system selects all valid candidate factors. Among these valid candidate factors, the system selects the factor with the largest value as the target extraction factor. Selecting the factor with the largest value means that the system reduces the output data stream rate and saves the transmission bandwidth resources of the subsequent fiber optic interface while ensuring the safety of signal frequency domain fidelity.

[0190] Step 605: Determine whether the target extraction factor initially calculated based on the oversampling constraint and the protection bandwidth constraint is lower than the lower limit of the candidate extraction factor set.

[0191] After calculating the theoretically optimal extraction factor, the system performs boundary safety checks in the hardware state machine. The system extracts the smallest element from the candidate extraction factor set as the safety lower limit and compares the target extraction factor obtained from the aforementioned screening calculation with this safety lower limit.

[0192] Step 606: If the value is lower than the lower limit, the target decimation factor actually used will be clamped to the lower limit, triggering a bandwidth overflow alarm state and stopping the update of the frequency offset compensation parameters used to generate the dynamic local oscillator signal; if the value is not lower than the lower limit, the target decimation factor initially calculated will be used as the target decimation factor actually used.

[0193] When the system detects that the theoretically required decimation factor is lower than the hardware-supported safety lower limit, the system determines that it is currently in a state of severe data bandwidth depletion. In a specific numerical verification scenario, assuming the radar operating mode bandwidth is set to 500 MHz, the detected current absolute frequency offset is 50 MHz, and the set oversampling factor is 2.5, substituting into the constraint formula, the equivalent signal bandwidth is calculated to be 600 MHz, and the oversampling constraint threshold is 1500 MHz. If the original sampling rate of the system's front-end analog-to-digital converter is 2500 MHz, then the theoretically maximum allowable decimation ratio is 2500 / 1500 = 1.67.

[0194] Since the theoretical value of 1.67 is less than the lower limit of 2 for the candidate extraction factor set, the system triggers underflow exception protection logic. The system forcibly performs a numerical clamping operation, assigning the target extraction factor output downstream to the lower limit value of 2.

[0195] Meanwhile, the system sets the bandwidth overflow alarm flag to logic state 1 in the general-purpose status register. To prevent uncontrolled frequency offset feedback from further exacerbating the extreme situation of insufficient system bandwidth, the system disconnects the frequency tracking feedback closed loop, forcing the frequency offset compensation parameters of the downconverter module to remain at the value of the previous normal cycle and no longer updating.

[0196] Step 607: Based on the currently calculated target decimation factor, decompose the pre-configured anti-aliasing low-pass filter into a corresponding number of multiphase sub-filter banks.

[0197] After obtaining a valid and securely verified target decimation factor, the system reconstructs its internal operational structure. To reduce the timing convergence pressure and dynamic power consumption of the multiplier under ultra-high original sampling rates, the system employs a polyphase structure decomposition technique. The system mathematically decomposes the original high-order single-rate finite impulse response filter into multiple parallel low-speed sub-filter branches, the number of which equals the target decimation factor. These branches collectively constitute a polyphase sub-filter bank, and the operating clock frequency of the internal arithmetic logic unit of each branch is proportionally reduced to the original clock frequency divided by the target decimation factor.

[0198] Step 608: At the frame boundary of the radar data frame, empty the current multiphase filter data pipeline.

[0199] Because the dynamic switching of the target decimation factor causes the historical state data of the shift register inside the filter to no longer match the timing of the new tap mode, the system uses hardware to extract the synchronization frame tail flag signal of the radar data frame to locate the end boundary. When the frame boundary is reached, the system control logic forcibly clears all multiplier pipeline registers, accumulators, and data delay buffers inside the polyphase filter, thereby eliminating inter-symbol crosstalk interference from invalid historical data remaining in the previous data frame to the starting data of the new frame.

[0200] Step 609: Synchronously load the multiphase sub-filter bank that matches the target decimation factor of the new frame, and perform seamless cross-frame switching and downsampling decimation.

[0201] While performing pipeline emptying operations, the system uses the target decimation factor as the starting address pointer to read the corresponding coefficients in batches from the high-speed dynamic random access memory directly connected to the programmable logic terminal via the direct memory access controller. The system then quickly injects the read coefficient sets into the parallel coefficient multiplier register of the multiphase sub-filter bank.

[0202] When the first valid sampling point of a new frame of data arrives at the data port, the system initiates the multiphase filter with updated coefficients to perform multiply-accumulate operations, and outputs the processed result data precisely according to the gating enable signal corresponding to the target decimation factor. Through this timing control accurate to the clock cycle, the system completes seamless online switching of multi-rate processing link parameters across frames without losing any valid radar pulses.

[0203] Example 7 describes a fine filtering and bit-width compression packetization mechanism based on extraction linkage. This mechanism uses an offline pre-built filter coefficient library and online adaptive query loading, combined with dynamic bit-width truncation and elastic buffer splicing to prevent DC bias, to ensure that the radar baseband signal can achieve distortion-free, full-line-speed encapsulated transmission under the capacity limitation of the optical fiber physical link.

[0204] Before performing online signal processing, the system performs an offline coefficient library construction phase.

[0205] Step 701: Traverse all feasible factors in the pre-configured candidate decimation factor set, and calculate the normalized Nyquist cutoff boundary that satisfies the anti-aliasing folding theorem and the radar baseband signal bandwidth according to the decimation sampling rate corresponding to each feasible factor.

[0206] Specifically, in an offline design environment, the computer acquires a pre-configured set of candidate decimation factors containing all legal downsampling ratios. For each specific value in the set, since downsampling changes the equivalent sampling frequency of the signal, the absolute cutoff frequency is calculated according to the Nyquist sampling theorem and converted into a normalized angular frequency in the digital domain. The relationship satisfies:

[0207] Ω _cf =(B _w / 2+δ _fg ) / (f _s / (2*D _opt ));

[0208] Among them, Ω _cf For the normalized Nyquist cutoff boundary, B _w δ is the target radar signal bandwidth. _fg f is the set spectrum protection margin. _s D represents the original sampling rate. _opt This represents the feasible factor currently being traversed. This calculation process ensures that, at different decimation rates, the filter's passband always covers the valid traffic signal, while the stopband effectively suppresses aliasing regions.

[0209] Step 702: Based on each normalized Nyquist cutoff boundary, generate offline multiphase anti-aliasing filter coefficient set and fine filter coefficient set that match each feasible factor.

[0210] After obtaining the normalized Nyquist cutoff boundaries for each decimation mode, the system invokes a digital filter synthesis algorithm to generate the corresponding impulse response sequences. For the multiphase anti-aliasing filter coefficient set, an equal-ripple approximation algorithm is used to generate finite impulse response filter coefficients with high stopband attenuation characteristics, and the coefficients are rearranged into multiple parallel-computed sub-filter sequences based on the feasibility factor. For the fine-filter coefficient set, the Kaiser window function method is used to generate a coefficient sequence with a smooth transition band to compensate for the passband ripple caused by the previous multiphase filtering. Through the above offline synthesis algorithm, a filter coefficient matrix covering all potential operating modes is generated.

[0211] Step 703: The generated fine filtering coefficient groups are mapped and stored using the corresponding feasible factors as indexes, and a pre-configured fine filtering coefficient library is pre-built for online query and call.

[0212] The computer equipment quantizes the generated floating-point coefficient sequence into fixed-point binary machine code and generates a configuration file according to the target hardware platform's memory address mapping rules. This configuration file is burned into the non-volatile memory attached to the field-programmable gate array (FPGA) and loaded into the on-chip or off-chip high-speed dynamic random access memory (DRAM) during system power-on initialization. The storage structure uses the value of the feasibility factor as the lookup key for the starting address offset, thereby constructing a pre-configured fine-filter coefficient library within the physical storage medium, providing static data support for subsequent real-time switching of the online pipeline.

[0213] Once in the online processing phase, the system takes over the low-speed data stream after multiphase anti-aliasing extraction and performs post-processing.

[0214] Step 704: Using the currently effective target extraction factor as the query key, search for and match the corresponding coefficient group from the pre-configured fine filtering coefficient library; wherein, the cutoff frequency corresponding to different coefficient groups in the pre-configured fine filtering coefficient library is adapted to the Nyquist bandwidth corresponding to the candidate target extraction factor.

[0215] At the boundary moments of the radar data frame, the hardware state machine acquires the target extraction factor output by the front-end decision module. The system uses this value as the address index parameter of the direct memory access controller and initiates a read transaction request to the pre-configured fine filter coefficient library during this clock cycle. Since the offline phase has ensured a strict binding between the physical address and the extraction mode, the system can hit and read the filter coefficient set that perfectly matches the current Nyquist bandwidth, avoiding the huge logical resource overhead and time delay caused by online real-time calculation of filter coefficients.

[0216] Step 705: Load the matched coefficient group as fine filtering coefficients, perform filtering processing on the extracted data, and obtain finely filtered data.

[0217] The returned coefficient sequence is distributed to the parallel multiplier array register of the fine filtering module via the internal data bus, overwriting the old coefficients. Subsequently, the fine filtering module performs a linear convolution operation with the updated fine-filtered coefficients and the decimated input data. This filtering process operates in the low-speed clock domain after downsampling, effectively filtering out residual image frequency interference generated at the baseband edges due to the decimation operation, and outputting a complex signal data stream with high in-band flatness and a high signal-to-noise ratio.

[0218] Step 706: Map the corresponding bit width truncation level according to the size range of the target extraction factor, and use the mapped bit width truncation level as the quantization bit width compression strategy.

[0219] Because the physical line rate of fiber optic interfaces has a theoretical upper limit, for example, the maximum payload of a single link is 96Gbps, under a very small target decimation factor, if the full-precision quantization bit width is maintained, the bus data throughput will exceed this physical limit. The system internally uses a static mapping table to output preset compression instructions based on the numerical range into which the target decimation factor falls. Specifically, when the target decimation factor is 2, the system maps and outputs a 16-bit truncation level; when the target decimation factor is 4, the system maps and outputs a 24-bit truncation level; and when the target decimation factor is greater than or equal to 8, the system maps and outputs a 32-bit lossless level. The truncation instructions output by the mapping are configured as a quantization bit width compression strategy, thereby controlling the data packet size at the sending end from the information theory source.

[0220] Step 707: When reducing the data word width and discarding low-order data, a convergent rounding algorithm is used to round the truncation critical bits to eliminate the DC bias interference of the radar signal baseband introduced by the direct truncation operation, so as to obtain compressed data that retains the effective dynamic range.

[0221] When performing quantization bit width compression, if the system directly discards low-order data bits, the mean of its statistical error will always be negative, equivalent to superimposing a parasitic DC component into the radar baseband signal. This component will severely interfere with the subsequent Doppler frequency calculation. Therefore, the system superimposes a decision logic at the least significant bit of the retained high-order data. When the discarded highest bit is 1 and all subsequent low-order bits are not all 0, a carry-over of 1 is added to the retained bits; when the discarded highest bit is 1 and all subsequent low-order bits are all 0, the carry-over is determined based on whether the least significant bit of the retained bits is odd or even, forcibly rounding the result to the nearest even number. By executing this convergent rounding algorithm, the statistical mean of the quantization error is constrained to 0, thus removing DC bias interference while compressing the data width.

[0222] Step 708: Perform a bit width truncation operation corresponding to the quantization bit width compression strategy on the extracted data after fine filtering coefficient processing to obtain compressed data.

[0223] The system hardware truncation module receives the wide bit width fixed-point number output by the fine filtering module, and according to the quantization bit width compression strategy issued in step 706, combined with the convergence rounding judgment logic in step 707, synchronously performs bit width reduction on the in-phase and quadrature components of each signal sample. The processed signal word is the compressed data, which retains the effective dynamic range of the radar signal to the greatest extent while meeting the strong constraints of link bandwidth.

[0224] Step 709: Use the elastic buffer unit to concatenate the compressed data of multiple consecutive clock cycles in parallel, and align the boundary of the concatenated data word to the preset fixed bus width to obtain the packaged data.

[0225] After acquiring the compressed data, the system faces a physical problem of data bit width mismatch with the standard communication protocol interface. The preset fixed bus bit width can be configured to 512 bits to adapt to the standard data interface of the user datagram protocol hardware protocol stack. When the compressed data is transmitted in parallel through four channels and each sample is 16 bits, the amount of data generated in a single clock cycle is 64 bits. The system continuously writes the compressed data into the elastic buffer unit and accumulates and concatenates it into a 512-bit data block after the internal counter reaches 8 clock cycles. If the periodic generation of compressed data cannot be divided evenly by the preset bit width, the elastic buffer unit uses a register chain spanning clock cycles to retain the remainder bits and seamlessly concatenates them with the input data of the next cycle. Through this elastic aggregation and assembly mechanism, the system outputs encapsulated data that fully conforms to the protocol stack interface standard. In addition, in some alternative implementations, if hardware storage resources are limited, the system can force alignment by padding the high bits of data words that are less than the bus bit width with a sequence of all zeros, and explicitly indicate the payload length in the header field of the generated network packet so that the receiving end can remove invalid padding bits.

[0226] On the hardware platform described in the above embodiments, system-level verification was performed under the operating conditions of 8 channels, a 2.5GHz sampling rate, and a 16-bit quantization width. When the radar operates in 500MHz wideband mode and the target decimation factor is 2, the single-link effective data throughput reaches 80Gbps, and the dual-link parallel total throughput reaches 160Gbps, achieving non-blocking continuous transmission at full sampling rate. The end-to-end deterministic processing delay from the ADC sampling moment to the transmission of the first byte by the optical module is less than 1 microsecond. Under pulse interference conditions with injected power higher than 20dB of the signal, the baseband signal after adaptive noise suppression weighting maintains the spectral integrity of the target echo. Those skilled in the art will understand that specific performance indicators may vary depending on the hardware platform configuration, operating mode parameters, and electromagnetic environment.

[0227] The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the specific details in the above embodiments. Within the scope of the technical concept of the present invention, various equivalent transformations can be made to the technical solutions of the present invention, and these equivalent transformations all fall within the protection scope of the present invention.

Claims

1. A multi-channel high-speed data acquisition and adaptive transmission method, characterized in that, include: Acquire digital sampling signals from multi-channel radar echoes; Inter-channel collaborative common-mode interference suppression is performed on the digital sampled signal, common-mode components are stripped and effective signal components are extracted; The residual frequency offset is extracted to generate a dynamic local oscillator signal, and the effective signal components are digitally down-converted and mixed using the dynamic local oscillator signal to obtain a mixed signal. The mixed signal is subjected to adaptive noise suppression weighting based on dual time-scale feature detection to obtain the weighted baseband signal; The target extraction factor is calculated by combining the pre-configured radar operating mode bandwidth and the current frequency offset state. The target extraction factor is then used to perform multiphase anti-aliasing filtering and downsampling extraction on the weighted baseband signal to obtain the extracted data. Based on the target extraction factor, the fine filtering coefficient and quantization bit width compression strategy are adaptively selected. Based on the selected fine filtering coefficient and quantization bit width compression strategy, the extracted data is filtered and packaged in parallel to obtain the encapsulated data and transmitted through the high-speed optical interface. Adaptive noise suppression weighting based on dual-time-scale feature detection is applied to the mixed signal, including the following feature detection and basis estimation steps: Extract the instantaneous power characteristics of the mixing signal; The instantaneous power features are updated unconditionally on a sample-by-sample basis using an exponential smoother with a first memory depth to obtain the fast tracking noise power; The instantaneous power characteristics that meet the preset interference amplitude conditions are iteratively updated using an exponential smoother with a second memory depth to obtain the slow tracking noise power, wherein the second memory depth is greater than the first memory depth. Calculate the ratio of the relative deviation between the fast tracking noise power and the slow tracking noise power to obtain a transient characterization index for characterizing the current interference environment; When the transient characterization index is greater than the preset transient switching threshold, the fast tracking noise power is selected as the target noise power. Otherwise, select the slow tracking noise power as the target noise power.

2. The method according to claim 1, characterized in that, Inter-channel coordinated common-mode interference suppression is performed on the digital sampled signal, stripping the common-mode component and extracting the effective signal component, including: Divide the digital sampled signal into continuous current data blocks in the time dimension; Calculate the local covariance features of the current data block, and then perform exponential weighted smoothing of the local covariance features with the historical covariance data of the previous data block to obtain the smoothed covariance features; An iterative algorithm is used to extract the principal feature direction vector representing the spatial distribution of common-mode interference from the smoothed covariance features; Construct an orthogonal complement space corresponding to the main feature direction vector, and project the digital sampling signal into the orthogonal complement space to remove the common-mode component and obtain the effective signal component.

3. The method according to claim 2, characterized in that, After extracting the principal feature direction vector representing the spatial distribution of common-mode interference from the smooth covariance features using an iterative algorithm, and before constructing the orthogonal complement space of the corresponding principal feature direction vector, a dual verification gating process is also included: Calculate the energy concentration of the principal feature direction vector in the smoothed covariance feature; Calculate the structural similarity between the main feature direction vector and the pre-configured calibration reference vector; Determine whether the energy concentration is greater than a preset energy concentration threshold and whether the structural similarity is greater than a preset structural similarity threshold; When both conditions are met, the step of constructing the orthogonal complement space of the corresponding main feature direction vector is triggered. When no condition is met, the bypass projection operation directly uses the unprojected digital sampled signal as the valid signal component.

4. The method according to claim 3, characterized in that, In multi-interference source scenarios, the process of extracting the main feature direction vector representing the spatial distribution of common-mode interference and performing dual verification gating is further extended to a multi-dimensional subspace extraction process, specifically including: Multiple orthogonal feature direction vectors are extracted sequentially from the smoothed covariance features and the subsequently updated residual covariance features. After extracting each feature direction vector, the projection component of the corresponding direction is subtracted from the current covariance features to update the residual covariance features. For each extracted feature direction vector, the corresponding energy concentration and structural similarity are calculated independently, and a set of effective interference directions is obtained based on the judgment results of whether the dual conditions are met. The effective signal components are obtained by projecting the digital sampled signal into the orthogonal complement space of the joint subspace composed of the set of effective interference directions.

5. The method according to claim 1, characterized in that, Extracting residual frequency offset to generate a dynamic local oscillator signal includes: Obtain historical extracted data after fine filtering; Perform a delay conjugate autocorrelation operation based on a pre-configured delay amount on the historical extracted data to obtain complex correlation results; Calculate the argument of the complex correlation results and extract the average phase increment of the historical data after extraction; The residual frequency offset is obtained by proportionally converting the average phase increment with the pre-configured delay and the current sampling rate, and the dynamic local oscillator signal is updated based on the residual frequency offset.

6. The method according to claim 1, characterized in that, The adaptive noise suppression weighting based on dual-time-scale feature detection for the mixed signal also includes the following weighting execution steps: The global signal power is obtained by using an exponential smoother to perform global iterative updates on the instantaneous power characteristics that have not been filtered by amplitude conditions. Calculate the power ratio of the target noise power to the global signal power, determine the adaptive weighting coefficient based on the difference between the base gain reference value and the power ratio, and restrict the adaptive weighting coefficient to a non-negative value; The corresponding mixing signal is amplitude modulated using adaptive weighting coefficients to obtain a weighted baseband signal.

7. The method according to claim 1, characterized in that, The target extraction factor is calculated by combining the pre-configured radar operating mode bandwidth with the current frequency offset, including: Obtain the pre-configured set of candidate extraction factors; Oversampling constraints on the target signal bandwidth are set based on the pre-configured radar operating mode bandwidth. Based on the current frequency offset state, set protection bandwidth constraints that include frequency offset compensation margin; Among the candidate extraction factors, the largest factor that makes the downsampling rate simultaneously satisfy both the oversampling constraint and the guard bandwidth constraint is selected as the target extraction factor.

8. The method according to claim 7, characterized in that, When selecting the maximum factor that simultaneously satisfies the oversampling constraint and the guard bandwidth constraint as the target decimation factor, an anomaly protection step is also included: Determine whether the target extraction factor initially calculated based on the oversampling constraint and the guard bandwidth constraint is lower than the lower limit of the candidate extraction factor set; If the value is below the lower limit, the actual target extraction factor will be clamped to the lower limit, triggering a bandwidth overflow alarm and stopping the update of the frequency offset compensation parameters used to generate the dynamic local oscillator signal.

9. The method according to claim 1, characterized in that, The fine filtering coefficients are adaptively selected based on the target extraction factor, including: Using the currently active target extraction factor as the query key, the corresponding coefficient group is searched and matched from the pre-configured fine filtering coefficient library; Among them, the cutoff frequencies corresponding to different coefficient groups in the pre-configured fine filtering coefficient library are adapted to the Nyquist bandwidth corresponding to the candidate target extraction factor; The matched coefficient set is loaded as fine filtering coefficients, and the extracted data is then filtered.

Images