Navigation signal simulation source channel generation method based on minimum bit width quantization

Abstract

The application relates to a navigation signal simulation source channel generation method based on minimum bit width quantization. The method comprises the following steps: calculating a minimum quantization bit width satisfying a maximum equivalent carrier-to-noise ratio degradation amount according to test scene parameters; estimating single-channel resource consumption based on the minimum quantization bit width, combining satellite channel numbers to determine whether a logical scale constraint of a target FPGA platform is satisfied, adjusting the maximum equivalent carrier-to-noise ratio degradation amount and recalculating if the constraint is not satisfied until the constraint is satisfied; configuring quantization bit widths of all channels in a digital baseband generation link according to the quantization bit widths satisfying the constraint; generating baseband signals of a single satellite by using the configured channels, and performing digital combining on the baseband signals of all channels, and outputting the combined signals to a DAC interface. The method can realize miniaturization and portability of equipment.

Description

Technical Field

[0001] This application relates to the field of satellite navigation signal simulation and testing technology, and in particular to a method for generating navigation signal simulation source channels based on minimum bit width quantization. Background Technology

[0002] The basic working principle of the navigation signal analog source is as follows: In the digital domain, a carrier wave, pseudocode and message are generated independently for each satellite. After modulation and power adjustment, all channel signals are digitally combined and then converted into radio frequency signals by a DAC and output to the receiver under test.

[0003] In typical existing analog source architectures, each channel's digital processing link, including carrier NCO, pseudocode NCO, modulation, and filtering, typically uses a 14-16 bit width. While high bit width is beneficial for signal quality, it incurs significant overhead in single-channel logic resources and DSP multipliers. In multi-system, multi-frequency scenarios, such as GPS plus BDS plus Galileo plus GLONASS, a single frequency point can exceed 40 satellites, and three frequencies can exceed 120 channels. This overhead is proportionally amplified, leading to the following prominent problems: High bit width architectures force analog sources to rely on large-scale, high-end FPGAs, with single-chip logic unit requirements often exceeding 100K, resulting in high power consumption and heat dissipation pressure, making portable, handheld GNSS analog sources unfeasible under existing architectures; large-scale FPGAs themselves are expensive, and when deployed across multiple workstations on production lines, each workstation needs a full-specification analog source, making the total cost of ownership unbearable; channel density is constrained by hardware scale, and once logic resources are exhausted, further expansion is difficult, typically requiring upgrades to larger FPGAs or cascading multiple FPGAs; many functional verification / production line pass-through scenarios do not require the highest accuracy, but traditional architectures struggle to adjust bit width according to the scenario. Summary of the Invention

[0004] Therefore, it is necessary to provide a navigation signal analog source channel generation method based on minimum bit width quantization that can solve the technical problem that the existing high bit width architecture can only deploy analog sources on large-scale high-end FPGA platforms, which seriously restricts the miniaturization and portability of devices.

[0005] A method for generating analog source channels for navigation signals based on minimum bit-width quantization, the method comprising: Step 1: Obtain test scenario parameters, including the maximum acceptable equivalent carrier-to-noise ratio degradation, the number of satellite channels to be simulated, and the logic size constraints of the target FPGA platform; Step 2: Calculate the minimum quantization bit width that satisfies the maximum equivalent carrier-to-noise ratio degradation based on the test scenario parameters; Step 3: Estimate the single-channel resource consumption based on the minimum quantization bit width, and determine whether the logic scale constraint of the target FPGA platform is met by combining the number of satellite channels. If not, increase the maximum equivalent carrier-to-noise ratio degradation and re-execute Step 2 until the constraint is met. Step 4: Configure the quantization bit width of each channel in the digital baseband generation link according to the quantization bit width that meets the logic size constraint; Step 5: Generate the baseband signal of a single satellite using the configured channels, digitally combine the baseband signals of all channels, and output the combined signal to the DAC interface.

[0006] The aforementioned method for generating navigation signal analog source channels based on minimum bit-width quantization uses the receiver-side equivalent carrier-to-noise ratio degradation as a signal quality constraint to calculate the minimum quantization bit width that meets the test scenario requirements, and performs closed-loop adjustments in conjunction with the target FPGA logic size constraints. Therefore, the bit width configuration of each channel is no longer selected solely based on empirical fixed high bit widths, but is determined simultaneously by test accuracy and hardware resource constraints. In some functional testing, production line testing, or portable testing scenarios, the digital baseband generation link can be configured to 1-4 bits to reduce the resource consumption of single-channel logic and multiplication. Attached Figure Description

[0007] Figure 1 This is a flowchart illustrating a method for generating a navigation signal analog source channel based on minimum bit-width quantization in one embodiment. Figure 2 Quantization bit width and equivalent in one embodiment A schematic diagram of the degradation relationship curves; (a) is a schematic diagram of quantization noise budget / theoretical noise carrying capacity, and (b) is a schematic diagram of the receiver degradation caused by quantization noise. Degradation simulation curves; Figure 3 This is a schematic diagram of a navigation signal analog source system architecture based on minimum bit width quantization in one embodiment. Detailed Implementation

[0008] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0009] In one embodiment, such as Figure 1 As shown, a method for generating analog source channels for navigation signals based on minimum bit-width quantization is provided, including the following steps: Step 1: Obtain test scenario parameters, including the maximum acceptable equivalent carrier-to-noise ratio degradation, the number of satellite channels to be simulated, and the logic size constraints of the target FPGA platform.

[0010] The test scenario parameters reflect the type of receiver under test, the test items, and the limitations of the hardware platform. The maximum acceptable equivalent carrier-to-noise ratio degradation is the upper limit of signal quality loss allowed in engineering. The number of satellite channels N to be simulated determines the combining complexity. The logic size constraint of the target FPGA platform, which does not exceed 30K logic cells, directly limits the available hardware resources.

[0011] Step 2: Calculate the minimum quantization bit width that satisfies the maximum equivalent carrier-to-noise ratio degradation based on the test scenario parameters.

[0012] Based on the correlation deampling gain characteristics of GNSS receivers, the minimum quantization bit width required for a given number of channels and degradation tolerance is derived by using a quantization noise link budget model. This avoids the resource waste caused by fixed high bit widths in traditional architectures and provides a quantitative basis for dynamic trade-offs between resources and accuracy.

[0013] Step 3: Estimate the single-channel resource consumption based on the minimum quantization bit width, and determine whether the logic scale constraint of the target FPGA platform is met by combining the number of satellite channels. If not, increase the maximum equivalent carrier-to-noise ratio degradation and re-execute Step 2 until the constraint is met.

[0014] If the total resources corresponding to the theoretical minimum bit width still exceed the target FPGA size, then the degradation tolerance should be appropriately relaxed (i.e., a slightly larger tolerance should be allowed). (Loss), recalculate a lower bit width until a balance is struck between resources and performance. This adaptive iterative mechanism improves the portability of this application across different hardware platforms.

[0015] Step 4: Configure the quantization bit width of each channel in the digital baseband generation link according to the quantization bit width that meets the logical size constraint.

[0016] Configurable quantization bit width B The value ranges from 1 to 4 bits. In practice, the phase accumulator of the carrier NCO maintains a high bit width to ensure frequency resolution, while the amplitude output lookup result is truncated to... B The pseudocode generator maintains a 1-bit pseudocode output; modulation and power scaling employ low-bit-width multiplication and truncation strategies. This preserves the necessary accuracy for signal generation while reducing single-channel resource consumption.

[0017] Step 5: Generate the baseband signal of a single satellite using the configured channels, digitally combine the baseband signals of all channels, and output the combined signal to the DAC interface.

[0018] When merging channels, the sums of each channel need to be accumulated. To avoid overflow, the intermediate accumulation results are expanded to approximately [value missing]. The bit width is then remapped to the DAC input bit width in the final stage. Through the above steps, the entire analog source system can be integrated into a single small FPGA / SoC without the need for multiple FPGA cascades, thereby achieving miniaturization and portability of the device while maintaining the signal quality usable in engineering.

[0019] Accordingly, this application does not merely aim to reduce the quantization bit width, but rather incorporates the low bit width configuration into the receiver's equivalent carrier-to-noise ratio degradation budget and hardware resource constraints. For functional testing or batch testing scenarios that do not require the highest metrological accuracy, this configuration can reduce redundant hardware overhead and improve the feasibility of a small FPGA / SoC platform supporting multi-channel analog sources.

[0020] In one embodiment, the minimum quantization bit width that satisfies the maximum equivalent carrier-to-noise ratio degradation is calculated based on the test scenario parameters, including: Based on the test scenario parameters, the minimum quantization bit width required to satisfy the maximum equivalent carrier-to-noise ratio degradation is calculated as follows: ; in, The carrier-to-noise ratio corresponding to the receiver's thermal noise floor, in dB-Hz; The maximum permissible equivalent carrier-to-noise ratio degradation, in dB; Number of satellite channels; This refers to the DAC sampling rate, measured in Hz. The unit is dB; This is the peak factor of the combined signal relative to the root mean square amplitude. The logarithmic terms in the above formulas are all calculated in the dB domain.

[0021] Specifically, the system parameters, including sampling rate, number of channels, thermal noise floor, and performance requirements including maximum degradation, will be considered. With the required bit width This direct correlation allows designers to quantitatively select the lowest-cost hardware configuration. For example, under typical parameters, =100, fs=120MHz, dB-Hz, At 0.1dB, the calculation yields... =2 bits, thus avoiding the blind use of high bit width.

[0022] In one embodiment, based on the quantization bit width and number of satellite channels The equivalent carrier-to-noise ratio degradation at the receiver end is calculated as follows: ; in, This represents the equivalent carrier-to-noise ratio degradation, expressed in dB. The single-star equivalent carrier-to-noise ratio is determined solely by quantization noise, in dB-Hz. This represents the carrier-to-noise ratio corresponding to the receiver's thermal noise floor, expressed in dB-Hz. This formula is equivalent to the linear noise spectral density expression. ,in and These are the linear spectral densities of quantization noise and thermal noise, respectively.

[0023] Specifically, the simulated source generation includes The combined digital baseband signal from the satellites is fed into the receiver under test after being up-converted by a DAC. Assume the DAC sampling rate is... Quantization bit width is bit, DAC full-scale voltage is The uniform quantization step size is For uniform quantization, the quantization noise power in the linear domain is: ; If expressed in dB and converted to unit bandwidth, it can be written as: ; in, To quantize the linear value of the total noise power, This represents the logarithm of the total quantization noise power relative to the full-scale sinusoidal reference power; This represents the logarithm of the quantization noise power spectral density relative to the full-scale sinusoidal reference power. Accordingly, This represents the linear value of the quantized noise spectral density. Linear spectral density will be used when dealing with noise addition, and dB-Hz will be used when dealing with carrier-to-noise ratio or link budget subtraction.

[0024] Analysis of receiver-side equivalent C / N0 degradation: Let the first of the combined signals be... The power of each satellite is , For satellite channel number, within signal bandwidth Internally, the DAC output side can be written as: ; in, For the first The signal-to-noise ratio of each satellite relative to the quantization noise at the DAC output. This refers to the bandwidth of a single satellite signal.

[0025] The equivalent carrier-to-noise ratio at the receiver end is approximately determined by the combined effects of thermal noise and quantization noise, and can be written in the linear domain as: ; in, The linear value of the receiver's thermal noise spectral density. To quantize the linear value of the noise spectral density, For the first The linear power of the satellite. If expressed in dBm / Hz, It can be approximated as commonly used as dBm / Hz, The receiver noise figure; in relation to Before comparing or adding the quantization noise, the power should be converted to the same reference power using the DAC full-scale power and link gain.

[0026] Under multi-satellite combining conditions, the combining amplitude can be approximated by a Gaussian distribution. Let the combining RMS amplitude be... To avoid cropping, the following conditions must be met: ; in, As the peak factor, it is often taken as approximately in engineering. . When satellites of equal power are combined, , For single-star amplitude and single-star power .

[0027] Therefore, the power of a single star relative to the full-scale sinusoidal reference power can be obtained. The approximate relationship is as follows. All power quantities below are expressed in the dB domain: ; in, For full-amplitude sinusoidal reference power, according to When normalizing, we can take it as .

[0028] The equivalent carrier-to-noise ratio for single-star quantization can then be written as: ; Expanding on this further: ; In the above formula The quantization SNR of a full-amplitude sine wave already implicitly includes the PAR of the sine wave itself. (i.e., 3dB). The peak-to-average power ratio loss of the synthesized signal relative to the sine wave is... ,in The peak-to-average power ratio (PAPR) of the synthesized signal is represented by the factor. The normalized reference is derived from the PAR of the sine wave itself. Numerical analysis is performed on typical parameters: taking... , , Peak-to-average power loss is calculated as 9 dB. hour ), Peak-to-average power ratio loss: , ,have to In this typical multi-star generation scenario, the equivalent quantization noise... The degradation is 45–50 dB-Hz above the typical thermal noise dominance range, therefore the additional degradation is relatively small. Substituting this into the receiver's equivalent carrier-to-noise ratio degradation... The peak-to-average power ratio loss is calculated to be 9 dB, and the example results are as follows ( As shown in Table 1.

[0029] Table 1

[0030] The theoretical values ​​in Table 1 are based on a uniform quantization noise model. . The time model agrees well with the Monte Carlo simulation (deviation). dB); hour The model slightly underestimates the quantization noise power; Monte Carlo simulations show an actual degradation of approximately 0.33 dB. In a typical multi-satellite scenario (…), Even considering peak-to-average power ratio (PAPR) loss, when the quantization bit width is reduced from 16-bit to 1-bit, the equivalent C / N0 degradation at the receiver is approximately 0.3dB, with a theoretical value of approximately 0.30dB and a simulated value of approximately 0.33dB. Meanwhile, the resource consumption per channel can be reduced to about one-tenth of the original. This resource-precision relationship allows the analog source to maintain the quality of usable signals while reducing the overall logic size of the system, providing a physical basis for equipment miniaturization. When the power is reduced, the power ratio of a single star increases. Generally larger; Degradation will increase with increasing size. The specific limits should be verified against the target equipment parameters and test indicators.

[0031] Verify the theoretical formula using the Monte Carlo method: Generate The random spreading code combined signal of the satellite, after Quantization noise power is measured after -bit mid-riser uniform quantization. ,according to Calculate the quantized noise spectral density and the thermal noise spectral density. Comparison; among which, This is the thermal noise spectral density calculated based on single-star power and thermal noise floor in the simulation. Each set of parameters was run 20 times and the average was taken.

[0032] Simulation conditions: , The modulation method is BPSK(1). The integration time is 1ms, and the simulation results are shown in Table 2.

[0033] Table 2

[0034] Comparison of simulation results and theoretical values: The two match well (deviation) ); The simulation degradation (0.33dB) is slightly greater than the theoretical value (0.30dB), which is due to uniform quantization under 1-bit quantization. The model slightly underestimates the actual quantization noise power. Even at the worst-case scenario (1-bit, N=100, 0.33dB), the degradation is still less than the engineering acceptable threshold of 0.5 dB.

[0035] Regarding the selection of the thermal noise floor: the above simulation results show that... This corresponds to the level of a typical commercial receiver. If the receiver under test has an even lower thermal noise floor (such as a high-sensitivity metrology-grade receiver), then... Equivalent under the same bit width The degradation will be amplified ( When the value is 1, it is approximately 0.57 dB. When the value is 2, the bit width is approximately 0.15dB. At this point, the bit width needs to be increased according to the bit width backoff strategy.

[0036] For production line functional testing and routine R&D verification scenarios, the receiver's thermal noise floor is typically in the 42–45 dB-Hz range. =2 Degradation < 0.08 dB, =1 Degradation of approximately 0.3dB is within the acceptable range for engineering purposes and will not affect production testing.

[0037] In one embodiment, when Furthermore, when it is necessary to further reduce in-band quantization noise, Sigma-Delta modulation is applied to the combined digital signal. The noise transfer function of the Sigma-Delta modulator is designed as follows: ,in Let be the noise transfer function. For z-domain variables, or This represents the modulator order.

[0038] Specifically, in extremely low bit-width (1~2 bits) scenarios, a first- or second-order digital Sigma-Delta modulator can be optionally added after combining to push quantization noise to higher frequencies, thereby further reducing the noise floor within the signal bandwidth. For example, in a multi-station testing scenario on a production line, where multiple terminals are simultaneously performing single-frequency functional tests, each requiring approximately 10 satellites. The constraint is to provide multiple independent RF outputs while keeping costs under control, and the volume of the analog source at each station must meet the requirements for dense deployment in the production line cabinets. This embodiment uses the following configuration... The total number of channels is configured according to the multi-station target, employing multi-channel parallel combining and multiple DAC outputs. Single-station analog sources can be deployed on ultra-small FPGAs, significantly reducing the space occupied by each station. Key implementation points include low-bit-width channel parallel generation, followed by the addition of a first-order digital Sigma-Delta modulator after combining. This approach pushes quantization noise to higher frequencies, further reducing the noise floor within the signal bandwidth; it utilizes multiple independent combining links; and output consistency and acquisition success rate are used as acceptance criteria. The judgment criterion is that, under preset power and Doppler test scenarios, the acquisition success rate maintains acceptable engineering consistency compared to the high bit-width reference scheme.

[0039] First-order modulation Afterwards, the in-band quantization noise can be effectively attenuated, so that the equivalent C / N0 at B=2bit degrades or even falls below the theoretically calculated value, thereby realizing high-density, low-cost multi-channel RF output on an ultra-small FPGA.

[0040] In one embodiment, the quantization bit width can be 1 bit, 2 bits, 3 bits, or 4 bits.

[0041] Specifically, the aforementioned bit widths cover different requirements for testing accuracy and hardware scale. 1-2 bits are suitable for scenarios sensitive to size and power consumption, such as multi-station production lines, handheld devices, and battery-powered systems; 3-4 bits can be used for scenarios with higher signal quality requirements, such as portable field testing; and the traditional 14-16 bits are reserved for rack-mounted laboratory equipment such as metrology calibration and certification testing. By dynamically selecting the bit width, the same hardware platform can be adapted to different testing scenarios.

[0042] In one embodiment, the target FPGA platform is constrained to have a logic size of no more than 30K logic cells.

[0043] Specifically, this constraint corresponds to a typical small FPGA / SoC platform. In a traditional 16-bit architecture, a 40-channel analog source requires approximately 100K~150K logic units, which cannot meet this constraint; however, in the solution of this application, [the following is omitted as the text is incomplete and requires further context]. B =3-bit. The critical operation bit width is reduced from 16-bit to 3-bit, and the single-channel logic resource is reduced to about 1 / 5. With full-link resource estimation including NCO lookup table, low-width multiplication, accumulator, control logic and DAC interface, the 40-channel system can be implemented in a closed loop on a small FPGA with about 28K logic cells. This configuration is conducive to the miniaturization of portable four-system full constellation (GPS L1 plus BDS B1I plus Galileo E1 plus GLONASS G1) analog sources.

[0044] In one embodiment, the quantization bit width is selected based on the different thermal noise floor of the receiver: when the receiver thermal noise floor corresponds to Minimum quantization bit width at 42~45dB-Hz Take 2 bits or 1 bit; when Minimum quantization bit width at 48dB-Hz Take 3 bits or 4 bits.

[0045] Specifically, this strategy reflects the differences in receiver sensitivity. For production line functional testing and routine R&D verification scenarios, the receiver's thermal noise floor is typically in the 42~45dB-Hz range. B =2 Degradation less than 0.08 dB, B =1 degradation is approximately 0.3dB, both within acceptable engineering ranges; however, for high-sensitivity metrology-grade receivers with thermal noise floor as low as 48dB-Hz, the equivalent C / N0 degradation at the same bit width will be amplified, for example... B When the value is 1, it is approximately 0.57 dB. B When the value is 2, the error is approximately 0.20dB. At this point, the bit width needs to be increased to 3~4 bits according to the bit width back-off strategy to ensure the test accuracy.

[0046] In one embodiment, when configuring the channel quantization bit width, the amplitude output lookup result of the phase accumulator of the carrier NCO is truncated to... Bit.

[0047] Specifically, the carrier NCO includes a phase accumulator and a sine / cosine lookup table. The phase accumulator maintains a high bit width to ensure frequency resolution without degradation at the Hz level, while the amplitude value output by the lookup table is determined according to... Truncation or rounding is performed. This design ensures carrier frequency accuracy while avoiding excessively wide multiplier inputs, thus effectively reducing DSP resource consumption.

[0048] In one embodiment, during digital combining, the intermediate accumulation results of each channel accumulation are expanded to... The bits are then remapped to the DAC input bit width at the final stage. To minimize the quantization bit width, N This refers to the number of satellite channels.

[0049] Specifically, assuming =2 bits N If the value is 40, the intermediate accumulation result needs to be expanded to 2+6=8 bits to prevent overflow during multi-channel accumulation. During the final stage remapping, the sign can be extended or truncated according to the native input bit width of the DAC. Alternatively, the low bit width signal can be mapped to the high bit width input of the DAC after Sigma-Delta modulation, realizing the collaborative design of noise shaping between the digital and analog domains.

[0050] In one embodiment, before outputting to the DAC interface, the combined digital signal is bit-width mapped according to the native quantization bit width of the DAC to ensure that the quantization bit width of the DAC is not less than the digital baseband output bit width.

[0051] Specifically, a conventional high-speed DAC (12~16 bits, ≥120Msps) can meet the requirements of the embodiments of this application. When using a Sigma-Delta modulator to map a low-bit-width signal (2-bit) to a 14-bit DAC, the mapping method should be determined by combining the DAC's native bit width, effective number of bits, sampling rate, and subsequent filtering conditions to reduce the impact of additional quantization errors on the DAC side on the noise shaping effect of the pre-stage.

[0052] In a specific embodiment, Figure 2 The quantization bit width and equivalent are given. A schematic diagram of the degradation relationship curves; (a) is a schematic diagram of quantization noise budget / theoretical noise carrying capacity, and (b) is a schematic diagram of the receiver degradation caused by quantization noise. The degradation simulation curves are shown. The horizontal axis represents the quantization bit width B (1~4 bits), and the vertical axis represents the equivalent C / N0 degradation amount ΔC / N0 (dB). It can be seen that the degradation amount decreases rapidly with increasing B; and when N=100 and C / N0,thermal=45dB-Hz, the degradation amount corresponding to B=2 is approximately 0.07dB (theoretical)~0.08dB (simulation), and B=1 corresponds to approximately 0.30dB (theoretical)~0.33dB (simulation). The simulation and theoretical values ​​agree well when B≥2, verifying the accuracy of the model.

[0053] In one embodiment, such as Figure 3 As shown, the navigation signal analog source system based on minimum bit width quantization includes: a multi-channel digital baseband generation unit, each channel generating a single satellite baseband signal in B bits, including a carrier NCO, a pseudo-code NCO and pseudo-code generator, and a modulator; and a digital combiner, which accumulates all channels, expanding the intermediate bit width to approximately [value missing]. Optional noise shaping unit performs digital Sigma-Delta modulation on the combined signal; DAC interface outputs the processed digital signal in DAC input format. All of the above units are integrated into a single small FPGA / SoC, eliminating the need for multiple FPGA cascading.

[0054] It should be understood that, although Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0055] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0056] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method for generating analog source channels for navigation signals based on minimum bit-width quantization, characterized in that, The method includes: Step 1: Obtain test scenario parameters, including the maximum acceptable equivalent carrier-to-noise ratio degradation, the number of satellite channels to be simulated, and the logic size constraints of the target FPGA platform; Step 2: Calculate the minimum quantization bit width that satisfies the maximum equivalent carrier-to-noise ratio degradation based on the test scenario parameters; Step 3: Estimate the single-channel resource consumption based on the minimum quantization bit width, and determine whether the logic scale constraint of the target FPGA platform is met by combining the number of satellite channels. If not, increase the maximum equivalent carrier-to-noise ratio degradation amount and re-execute Step 2 until the constraint is met. Step 4: Configure the quantization bit width of each channel in the digital baseband generation link according to the quantization bit width that meets the logical size constraints; Step 5: Generate the baseband signal of a single satellite using the configured channels, digitally combine the baseband signals of all channels, and output the combined signal to the DAC interface.

2. The method according to claim 1, characterized in that, The minimum quantization bit width that satisfies the maximum equivalent carrier-to-noise ratio degradation is calculated based on the test scenario parameters, including: Based on the test scenario parameters, the minimum quantization bit width that satisfies the maximum equivalent carrier-to-noise ratio degradation is calculated as follows: ; in, The carrier-to-noise ratio corresponding to the receiver's thermal noise floor. The maximum allowable equivalent carrier-to-noise ratio degradation. Number of satellite channels; This refers to the DAC sampling rate, measured in Hz. , It is the peak factor of the combined signal relative to the root mean square amplitude.

3. The method according to claim 1, characterized in that, The method further includes: Based on quantization bit width and number of satellite channels The equivalent carrier-to-noise ratio degradation at the receiver end is calculated as follows: ; in, This represents the equivalent carrier-to-noise ratio degradation, expressed in dB. The single-star equivalent carrier-to-noise ratio is determined solely by quantization noise, in dB-Hz. This represents the carrier-to-noise ratio corresponding to the receiver's thermal noise floor, expressed in dB-Hz.

4. The method according to claim 1, characterized in that, The target FPGA platform is constrained to have a logic size of no more than 30K logic cells.

5. The method according to claim 1, characterized in that, The method further includes: The quantization bit width is selected based on the receiver's thermal noise floor: when the receiver's thermal noise floor corresponds to... Minimum quantization bit width at 42~45dB-Hz Take 2 bits or 1 bit; when Minimum quantization bit width at 48dB-Hz Take 3 bits or 4 bits.

6. The method according to claim 1, characterized in that, When configuring the channel quantization bit width, the amplitude output lookup result of the phase accumulator of the carrier NCO is truncated to... Bit.

7. The method according to claim 1, characterized in that, In the digital combining process, the intermediate accumulation results of each channel accumulation are expanded to... The bits are then remapped to the DAC input bit width at the final stage. To minimize the quantization bit width, This refers to the number of satellite channels.

8. The method according to claim 1, characterized in that, The method further includes: Before outputting to the DAC interface, the combined digital signal is mapped to the bit width according to the DAC's native quantization bit width to ensure that the DAC's quantization bit width is not less than the digital baseband output bit width.

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