Display module and display device

Abstract

The display module and the display device are provided.The display module includes a first substrate, a second substrate and a liquid crystal layer, the first substrate is provided with a plurality of spacers, the second substrate is provided with spacer pedestals corresponding to the plurality of spacers, the second substrate further includes a driving circuit layer arranged on the first substrate and an alignment layer arranged on the surface of the second substrate close to the first substrate; the driving circuit layer includes a plurality of gate signal lines arranged along a first direction, a plurality of data signal lines arranged along a second direction and a plurality of transistors, the data signal lines include a plurality of spacer pedestals, the data signal lines are electrically connected to the first poles of the transistors, the gate signal lines are electrically connected to the control poles of the transistors, and the alignment layer has substantially the same thickness at the parts of the spacer pedestals. The display module of the embodiment of the present disclosure can improve the display stripes caused by the uneven diffusion of the alignment mode at the spacer pedestals.

Description

Technical Field

[0001] This disclosure relates to the field of display technology. More specifically, it relates to a display module and a display device. Background Technology

[0002] Polyimide (PI) alignment layer is the main material for anchoring liquid crystal molecules. Through the ionic bonds and intermolecular forces between the alignment layer and the liquid crystal molecules, the liquid crystal molecules are arranged in a certain way along the friction direction on the surface of the display substrate. The quality of the thermal PI alignment layer directly affects the performance parameters of the liquid crystal display panel, such as picture quality, contrast ratio, threshold voltage, response time and viewing angle.

[0003] However, the PI alignment layer is currently difficult to diffuse evenly at the corresponding position on the spacer substrate, resulting in display stripes in display products. Summary of the Invention

[0004] The purpose of this disclosure is to provide a display module and display device to improve the diffusion uniformity of the orientation layer material at the septum base position, thereby improving display stripes.

[0005] To achieve the above objectives, the present disclosure adopts the following technical solution: This disclosure provides a display module, including: a first substrate, a second substrate, and a liquid crystal layer disposed between the first substrate and the second substrate. The first substrate is provided with a plurality of spacers, and the second substrate is provided with spacer bases corresponding to the plurality of spacers. The second substrate further includes: a driving circuit layer disposed on the first substrate, and an alignment layer disposed on the surface of the second substrate near the first substrate; The driving circuit layer includes: a plurality of gate signal lines arranged along a first direction, a plurality of data signal lines arranged along a second direction, and a plurality of transistors, wherein the data signal lines include a plurality of spacer bases. The data signal line is electrically connected to the first electrode of the transistor, and the gate signal line is electrically connected to the control electrode of the transistor. The portion of the orientation layer located on the septum base has approximately the same thickness.

[0006] Optionally, the driving circuit layer includes a first metal layer, and the second substrate further includes a plurality of first interconnect lines and a plurality of first redundant leads. The plurality of transistors includes a plurality of first transistors. One end of the first interconnect line is electrically connected to a spacer base, and the other end is electrically connected to a first electrode of the first transistor. The first interconnect lines, the first redundant leads, and the spacer base are located in the first metal layer. The first redundant lead protrudes from the septum base, and the extension direction and position of the first redundant lead and the first connecting line corresponding to the same septum base are symmetrical with respect to the central axis of the septum base along the first direction.

[0007] Optionally, the driving circuit layer includes a first metal layer, the second substrate further includes a plurality of second interconnect lines, the data signal line includes a plurality of spacer bases and a connection portion connecting the spacer bases, and the plurality of transistors includes a plurality of second transistors; One end of the second connection line is electrically connected to the connection part, and the other end is electrically connected to the first electrode of the second transistor. The second connection line and the data signal line are located in the first metal layer.

[0008] Optionally, the second substrate further includes: a pixel electrode layer disposed on the driving circuit layer, the pixel electrode layer including a plurality of pixel electrodes arranged in an array; Two gate signal lines are provided between every two rows of pixel electrodes, and one data signal line is provided every two columns of pixel electrodes.

[0009] Optionally, the driving circuit layer includes a first metal layer, the second substrate further includes a plurality of third interconnect lines, and the plurality of transistors includes a plurality of third transistors; The orthogonal projection of the spacer base on the first substrate is located between the two gate signal lines. The spacer base is electrically connected to the first electrode of the two third transistors through two third connection lines, and the control electrode of the two third transistors is electrically connected to the two gate signal lines. The third connecting line and the spacer base are located in the first metal layer; The two third transistors are projected onto the first substrate and are located on either side of the central axis extending along the first direction of the corresponding spacer base. The extension direction and position of the two third connecting lines protruding from the spacer base are symmetrical with respect to the central axis.

[0010] Optionally, the driving circuit layer includes a first metal layer, the second substrate further includes a plurality of fourth interconnect lines, and the plurality of transistors includes a plurality of fourth transistors; The data signal line includes a plurality of septum bases and a connecting portion connecting the septum bases. The connecting portion includes a first connecting portion extending in a first direction and a second connecting portion connecting the first connecting portion and the septum bases. The orthogonal projection of the spacer base on the first substrate is located between the two gate signal lines. The spacer base is electrically connected to the first electrode of the two fourth transistors through two fourth connection lines, and the control electrode of the two fourth transistors is electrically connected to the two gate signal lines. The second connecting part, the fourth connecting line, and the spacer base are located in the first metal layer; The second connecting part and the fourth connecting line, which protrude from the septum base, are symmetrical in their extension direction and position relative to the central axis of the septum base along the first direction.

[0011] Optionally, the driving circuit layer includes: a first metal layer, a first insulating layer and a first conductive layer sequentially stacked on the first substrate. The driving circuit layer also includes a fifth connection line and a sixth connection line, wherein the fifth connection line and the spacer base are located in the first metal layer. The first metal layer also includes a plurality of first openings located at the edge of the spacer base. The first insulating layer is located on the surface of the first metal layer away from the first substrate. The first insulating layer includes a plurality of second openings. The orthogonal projection of the second openings on the first substrate at least partially covers the orthogonal projection of the first openings on the first substrate. One end of the fifth connection line is electrically connected to the first electrode of the transistor, and the second end is electrically connected to the spacer substrate via the sixth connection line, which is located in the first conductive layer.

[0012] Optionally, the driving circuit layer includes: a first metal layer, a first insulating layer and a first conductive layer sequentially stacked on the first substrate; the driving circuit layer also includes a seventh connection line; the plurality of transistors includes a plurality of sixth transistors; and the spacer base and the first electrode of the sixth transistor are located in the first metal layer. The first metal layer also includes a plurality of third openings, the first insulating layer is located on the surface of the first metal layer away from the first substrate, and the first insulating layer includes a plurality of fourth openings, the orthogonal projection of the fourth openings on the first substrate at least partially covers the orthogonal projection of the third openings on the first substrate. One end of the fourth opening, as projected onto the first substrate, contacts the edge of the spacer base as projected onto the first substrate, and the other end contacts the edge of the first electrode of the sixth transistor as projected onto the first substrate. The seventh connection line is electrically connected to the spacer base and the first electrode of the sixth transistor, and the seventh connection line is located in the first conductive layer.

[0013] Optionally, the driving circuit layer includes: a first metal layer, a first insulating layer and a first conductive layer sequentially stacked on a first substrate, wherein the first insulating layer is located on the surface of the first metal layer away from the first substrate, and the first conductive layer is located on the surface of the first conductive layer away from the first substrate. The first conductive layer includes a capping layer, the orthographic projection of which on the first substrate at least partially covers the orthographic projection of the spacer base on the first substrate, and the first conductive layer is a transparent metal oxide material.

[0014] Optionally, the driving circuit layer includes a first metal layer, and the spacer base is located on the first metal layer. The spacer base has a grid structure, a porous structure, or a surface uneven structure.

[0015] Optionally, the driving circuit layer includes: a first metal layer and a first insulating layer sequentially stacked on a first substrate, wherein the first insulating layer is located on the surface of the first metal layer away from the first substrate, and the first spacer base is located on the first metal layer; The first insulating layer covers the spacer base, and the thickness of the portion of the first metal layer covering the spacer base is less than or equal to 100 nm. Alternatively, the driving circuit layer may further include an active layer located on the surface of the first metal layer near the first substrate, wherein the orthographic projection of the active layer on the first substrate covers the orthographic projection of the spacer base on the first substrate, and the distance between the edge of the active layer and the edge of the spacer base is greater than or equal to 1 µm.

[0016] A second aspect of this disclosure provides a display device including the display module described above.

[0017] The beneficial effects of this disclosure are as follows: This disclosure addresses existing problems by providing a display module and display device. By improving the structure and pattern of the spacer base, the diffusion uniformity of the alignment layer at the corresponding position on the spacer base is enhanced, ensuring that the portion of the alignment layer on the spacer base has approximately the same thickness. This avoids local aggregation of the alignment layer on the surface of the spacer base, thereby improving the problem of fine horizontal stripes during display, enhancing the display effect, and showing broad application prospects. Attached Figure Description

[0018] The specific embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0019] Figure 1 A schematic diagram illustrating the appearance of display stripes in a display product based on related technologies; Figure 2 A schematic diagram showing fine horizontal stripes appearing in the display area of ​​a liquid crystal display panel; Figure 3 Show further details Figure 1 The thickness curves of different regions of the array substrate alignment surface were obtained by multi-point photoresist barrier height testing in areas with horizontal stripes. Figure 4A and 4B The following are shown: a partial electron microscope scan image of another object corresponding to form 1 and a cross-section showing the local thickness in the circled area of ​​the image; Figure 5A and 5B The following are shown: a partial electron microscope scan image of another object corresponding to form 1 and a cross-section showing the local thickness in the circled area of ​​the image; Figure 6 A schematic diagram of a second substrate according to an embodiment of the present disclosure is shown; Figure 7A partial schematic diagram of a second substrate according to another embodiment of the present disclosure is shown; Figure 8 A schematic diagram of a second substrate according to another embodiment of the present disclosure is shown; Figure 9 A partial schematic diagram of a second substrate according to another embodiment of the present disclosure is shown; Figure 10 A schematic diagram of a second substrate according to another embodiment of the present disclosure is shown; Figure 11 A schematic diagram of a second substrate according to another embodiment of the present disclosure is shown; Figure 12 A schematic diagram of a second substrate according to another embodiment of the present disclosure is shown; Figure 13 Show along Figure 12 A cross-sectional view taken along the midline AA'; Figure 14 A schematic diagram of a second substrate according to another embodiment of the present disclosure is shown; Figure 15 A schematic diagram of a second substrate according to another embodiment of the present disclosure is shown; Figure 16 A schematic diagram of a second substrate according to another embodiment of the present disclosure is shown; Figure 17 A schematic diagram of a second substrate according to another embodiment of the present disclosure is shown; Figure 18 A partial cross-sectional view of the edge region of the spacer base of a second substrate according to another embodiment of the present disclosure is shown; Figure 19 A partial cross-sectional view of the edge region of the spacer base of a second substrate according to another embodiment of the present disclosure is shown. Detailed Implementation

[0020] To more clearly illustrate this disclosure, the preferred embodiments and accompanying drawings will be used for further description. Similar components in the drawings are indicated by the same reference numerals. Those skilled in the art should understand that the specific description below is illustrative rather than restrictive and should not be construed as limiting the scope of protection of this disclosure.

[0021] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of one or more parts in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0022] It should be noted that although the terms "first," "second," etc., may be used herein to describe various components, members, elements, regions, layers, and / or parts, these components, members, elements, regions, layers, and / or parts should not be limited by these terms. Rather, these terms are used to distinguish one component, member, element, region, layer, and / or part from another. Thus, for example, the first component, first member, first element, first region, first layer, and / or first part discussed below may be referred to as a second component, second member, second element, second region, second layer, and / or second part without departing from the teachings of this disclosure.

[0023] Furthermore, the terms "having", "containing", and "including" used in this disclosure are all open-ended, meaning that when a module is described as "having", "containing", or "including" a first element, a second element, and / or a third element, it indicates that the module includes other elements in addition to the first element, the second element, and / or the third element.

[0024] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the described constituent elements. Therefore, the description is not limited to the terms used in the specification and may be appropriately replaced as appropriate.

[0025] In this disclosure, unless otherwise stated, the term "co-layered arrangement" means a layer, component, or other structure formed by patterning two (or more) structures using the same patterning process, and their materials may be the same or different. For example, the precursors forming multiple co-layered arrangements may be made of the same material, while the final materials may be the same or different.

[0026] The alignment layer material in liquid crystal display products is typically polyimide (PI), which should possess good film-forming, mechanical, alignment, and electrical characteristics. Regarding mechanical properties, the PI solution adheres to the display substrate surface through ionic bonds, intermolecular forces, and mechanical anchoring. During the diffusion of the PI solution onto the substrate, due to the non-uniformity of molecular chain segment movement, a nanoscale periodic peak-valley microstructure naturally exists on the alignment layer surface. For the PI solution to fully diffuse on the TFT substrate surface, it needs to overcome the potential energy barrier of these peaks and valleys to fill the gaps. This is crucial for the two-phase bonding surfaces to achieve molecular-level (i.e., within the van der Waals radius) proximity and generate adhesive force.

[0027] The inventors' research and testing revealed that the film thickness at the edge region of the alignment layer in the spacer substrate used to support the liquid crystal cell is 2-3 times that of the normal region. Analysis and deduction revealed that the mechanism is that the PI liquid in the edge region heats up faster than in the center region, has a larger air contact area, and the solvent evaporation rate is faster. The edge region solidifies first, and the adjacent unevaporated liquid continues to flow and solidify outwards, resulting in a thicker PI alignment layer at the edge. Furthermore, the spacer is typically located on the color filter substrate, and the spacer substrate is located on the array substrate. The surface roughness and interface state, PI material, and coating process significantly affect the PI diffusion capability. If the transistor and PI material have poor compatibility, film shrinkage and aggregation during PI pre-curing will increase the PI thickness at the spacer substrate location. Inconsistent PS compression ratios lead to cell thickness differences in different regions, resulting in optical mura, affecting yield and image quality. Additionally, the transistor structures and other peripheral structures around the spacer substrate of the array substrate can also cause PI aggregation.

[0028] The inventors further verified and analyzed the principles behind the aforementioned problems with the spacer base through simulation and physical disassembly. For example... Figures 1 to 3 As shown, Figure 1 The diagram shows a fine horizontal stripe pattern appearing in the display area of ​​a liquid crystal display panel. Figure 2 Lines 1 and 2 respectively show the following according to Figure 1 The direction of the arrow shown ( Figure 2 The thickness difference of the liquid crystal cell surface in different areas was obtained by optical ranging (represented by the horizontal axis). Figure 3 Show further details Figure 1 A horizontal striped area appears in the image. After simulating tapping, shaking, and pressing the screen, follow the direction of the arrow ( Figure 3 The thickness curves of different regions on the alignment surface of the array substrate were obtained by sequentially measuring the height of the photoresist barrier at multiple points (represented by the horizontal axis). Figure 2 It can be seen that when the liquid crystal display panel displays stripes, there are periodic fluctuations on the surface of the liquid crystal cell that are consistent with the stripe variation pattern. Further multi-point testing of the liquid crystal cell revealed that the thickness of different regions of the alignment surface of the array substrate at corresponding positions exhibits periodic fluctuations consistent with the stripe variation pattern.

[0029] further, Figure 4A and Figure 4B The images show partial electron microscope (SEM) images of the physical object with a connection line leading out from one side of the data line (morphology 1) and cross-sections showing the local thickness in the circled areas. Significant differences in the alignment layer thickness are observed on the surface of the curved spacer substrate, resulting in a large overall film thickness variation. Furthermore, when the high point contacts the spacer, its overall thickness is also greater than in the normal area. Figure 5A and Figure 5BThe images show partial electron microscope (SEM) images of configuration 2, where the connecting line extends from the opposite side of the data line. The images also show cross-sectional curves within the circled areas indicating local thickness. Significant differences in the alignment layer thickness on the spacer base surface are observed, resulting in a large overall film thickness variation. Furthermore, when the lowest point contacts the spacer, its overall cell thickness is also smaller than in the normal area. This further confirms that regardless of the configuration, the inconsistent diffusion of the alignment layer on the spacer base surface leads to inconsistent cell thickness in the display panel, thus causing display stripes.

[0030] In summary, the inventors discovered through research that solving the problem of inconsistent diffusion of the alignment layer on the surface of the septum base is the key to solving the problem of display stripes.

[0031] In view of this, embodiments of the present disclosure provide a display module, including: a first substrate, a second substrate, and a liquid crystal layer disposed between the first substrate and the second substrate, wherein the first substrate is provided with a plurality of spacers, and the second substrate is provided with spacer bases corresponding to the plurality of spacers. The second substrate further includes: a driving circuit layer disposed on the first substrate, and an alignment layer disposed on the surface of the second substrate near the first substrate; The driving circuit layer includes: a plurality of gate signal lines arranged along a first direction, a plurality of data signal lines arranged along a second direction, and a plurality of transistors, wherein the data signal lines include a plurality of spacer bases; The data signal line is electrically connected to the first electrode of the transistor, and the gate signal line is electrically connected to the control electrode of the transistor. The portion of the orientation layer located on the septum base has approximately the same thickness.

[0032] In this embodiment, by setting the portion of the alignment layer located on the spacer base to have approximately the same thickness, the diffusion uniformity of the alignment layer at the corresponding position on the spacer base is improved, local aggregation of the alignment layer on the surface of the spacer base is avoided, thereby improving the problem of fine horizontal stripes that appear during display and enhancing the display effect.

[0033] In a specific example, refer to Figure 6 As shown in the figure, a schematic diagram of a second substrate with spacer bases is presented in a display module. In this example, the second substrate is an array substrate. The display module includes a driving circuit layer disposed on a first substrate and an alignment layer disposed on the surface of the second substrate near the first substrate.

[0034] Specifically, such as Figure 6As shown, the driving circuit layer includes: a plurality of gate signal lines 101 arranged along a first direction (i.e., the Y direction in the figure), a plurality of data signal lines 102 arranged along a second direction (i.e., the X direction in the figure), and a plurality of transistors T. The data signal lines 102 include a plurality of spacer bases PS'. A pixel electrode layer is included between the driving circuit layer and the alignment layer. The pixel electrode layer includes a plurality of pixel electrodes 103 arranged in an array. In addition, a common electrode layer may also be included between the driving circuit layer and the alignment layer. The common electrode layer includes a common electrode 104. The pixel electrodes 103 are used to define pixels of the display module. When a voltage is applied to the pixel electrodes 103 and the common electrode 104, the potential difference between them drives the liquid crystal corresponding to the pixel electrode 103 to deflect, thereby controlling the pixel grayscale of the display module.

[0035] It should be noted that in this article, when there is no need to distinguish between time-separation structures or devices, a general term is used. When distinction is required, a "-" and a "serial number" are added after the corresponding general term for differentiation. For example, when no distinction is required, transistors are generally referred to as "T". When it is necessary to distinguish between the first transistor and the second transistor, the first transistor is represented as "T-1" and "T-2" respectively. When further distinction is required for the first transistor, it is further represented as first transistor T-1-1 and first transistor T-1-2. As another example, when no distinction is required, spacer bases are generally referred to as "PS'". When distinction is required, spacer bases are represented as "PS'-1" and "PS'-2" respectively. The representation of other structures in the following text is similar and will not be elaborated here.

[0036] In this example, such as Figure 6 As shown, the second substrate is a dual-gate pixel structure. The dual-gate pixel structure refers to a pixel architecture in which the number of gate signal lines 101 of the display panel is doubled and the number of data signal lines 102 is halved. That is, a data signal line 102 is set between two columns of pixel electrodes 103, a data signal line 102 is set every two columns of pixel electrodes, and two gate signal lines 101 are set between every two rows of pixel electrodes 103.

[0037] The first substrate is a substrate that allows visible light to pass through, such as glass, quartz, or plastic. The gate signal line 101 is disposed in the gate layer, which can be at least one metal including gold (Au), silver (Ag), copper (Cu), molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), and nickel (Ni), or a single-layer structure or at least two stacked structures selected from molybdenum / aluminum / molybdenum (Mo / Al / Mo), molybdenum / copper (Mo / Cu), molybdenum-niobium alloy / copper (MoNb / Cu), and molybdenum-niobium alloy / copper / molybdenum-titanium alloy (MoNb / Cu / MoTi). The data signal line 102 can be disposed in the source / drain metal layer of the driving circuit layer. The source / drain metal layer can be a single-layer, double-layer, or multi-layer structure, and its material can include at least one metal including gold (Au), silver (Ag), copper (Cu), molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), and nickel (Ni), or an alloy of two or more metals.

[0038] Pixel electrode 103 is located on the pixel electrode layer, and common electrode 104 is located on the common electrode layer. Both can be made of transparent conductive materials, and each can include at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc aluminum oxide (AZO), and zinc gallium oxide (GZO). For example, common electrode 104 can be made of... Figure 7 The block electrode shown is a pixel electrode 103, which is a slit electrode. Those skilled in the art should understand that this disclosure is not intended to limit the patterns of the common electrode and the pixel electrode. In some embodiments, the pixel electrode can be a block electrode and the common electrode can be a slit electrode.

[0039] The display module also includes multiple common electrode lines 105, which may be located in the source / drain metal layer, for example, in the same layer as the data signal lines 102. The common electrode lines 105 may be disposed between two columns of pixel electrodes 102, with one common electrode line disposed every two columns of pixel electrodes 103. When the data signal lines 102 and the common electrode signal lines 105 are disposed in the same layer, they are alternately disposed.

[0040] Continue to refer to Figure 6 As shown, the data signal line 102 includes the plurality of spacer bases PS', which correspond to spacers on the first substrate. The spacers are also referred to as "PS". The spacer bases PS' are used to support the spacers after the first substrate and the second substrate are assembled.

[0041] In this example, the spacer base PS' is disposed between the two rows of pixel electrodes 103, because there are two gate signal lines 101 disposed between the two rows of pixel electrodes 103, and the spacer base PS' is disposed between the two gate signal lines 101.

[0042] In this embodiment, the plurality of transistors T includes a plurality of first transistors T-1. The second substrate of the display module also includes a plurality of first connection lines L1 and a plurality of first redundant leads L2. One end of the first connection line is electrically connected to the spacer base PS', and the other end is electrically connected to the first electrode of the first transistor T-1. It should be understood that the second electrode of the first transistor T-1 is electrically connected to a pixel electrode 103, wherein the first electrode is one of the source and drain, and the second electrode is the other of the source and drain. The control electrode of the first transistor T-1 is disposed in the gate layer and is electrically connected to the gate signal line 101. The first connection lines L1, the first redundant leads L1', and the spacer base PS' are all located in the first metal layer, for example, the three are disposed in the same layer.

[0043] The first redundant lead L2 protrudes from the septum base PS', and the extension direction and position of the first redundant lead L2 and the first connecting line L1 corresponding to the same septum base PS' are symmetrical with respect to the central axis OO' of the septum base PS' along the first direction Y. In this document, "protruding" means extending along a direction parallel to the surface of the septum base PS'.

[0044] For example, such as Figure 6 As shown, the same spacer base PS' corresponds to two first transistors T-1-1. These two first transistors T-1-1 are located on both sides of the central axis OO' along the first direction Y. The first electrodes of the two first transistors T-1-1 are electrically connected to the spacer base PS' via first connection lines L1-1 respectively disposed on both sides, so as to be electrically connected to the data signal line 102 via the spacer base PS'. The control electrodes of the first transistors T-1-1 are respectively electrically connected to the corresponding gate signal lines 101. Both the control electrode and the gate signal line 101 can be disposed in the second metal layer. For example, the second metal layer can be called the gate layer.

[0045] In the embodiments of this disclosure, a first redundant line L2-1 protruding from the spacer base PS' is provided at a position symmetrical to the central axis OO' and not connected to the first connecting line L1-1, and the extension direction of the first redundant line L1'-1 is also symmetrical to the first connecting line L1-1 with respect to the central axis OO'. Here, "the extension direction of the first redundant line L1'-1 is also symmetrical to the first connecting line L1-1 with respect to the central axis OO'" means that if the first connecting line L1-1 forms a first angle with one side of the spacer base PS' at the connection position, then the protruding direction of the first redundant line L1'-1 from the spacer base PS' forms a second angle with another side symmetrical to that side, and the first angle and the second angle are approximately equal.

[0046] In another example, such as Figure 6As shown, the same spacer base PS' corresponds to two first transistors T-1-2. These two first transistors T-1-2 are located on the same side of the central axis OO' along the first direction Y, and the first electrodes of the two first transistors T-1-2 are electrically connected to the corresponding spacer base PS' via two first connection lines L1-2 respectively disposed on this same side, so as to be electrically connected to the data signal line 102 via the spacer base PS'. Both the control electrode and the gate signal line 101 can be disposed in the second metal layer, for example, the second metal layer can be called the gate layer.

[0047] In the embodiments of this disclosure, a first redundant line L1'-2 protruding from the spacer base PS' is provided at a position symmetrical to the central axis OO' and not connected to the first connecting line L1-2. The extension direction of the first redundant line L1'-1 is also symmetrical to the first connecting line L1-1 with respect to the central axis OO'. The meaning of "the extension direction of the first redundant line L1'-1 is also symmetrical to the first connecting line L1-1 with respect to the central axis OO'" is similar to that described above and will not be repeated here.

[0048] Figure 7 A partial structural diagram of another example is shown, in which the same spacer base PS' corresponds to two first transistors T-1-3, which are located on the same side of the central axis OO' along the first direction Y. The first poles of the two first transistors T-1-3 are electrically connected to the corresponding spacer base PS' via first connection lines L1-3 respectively disposed on this same side, and are electrically connected to the data signal line 102 via the spacer base PS'.

[0049] The first connection line L1-3 includes a first sub-section L1-3-1 shared by the two first transistors T-1-3 and a second sub-section L1-3-2 electrically connected to the first sub-section L1-3-1 and electrically connecting the two first transistors T-1-3 together, so that the first connection line L1-3 of the two first transistors T-1-3 has only one connection end that directly contacts the spacer base PS'. In this example, the first sub-section L1-3-1 extends along the second direction X.

[0050] In the embodiments of this disclosure, a first redundant line L1'-3 protruding from the spacer base PS' is provided at a position symmetrical to the central axis OO' and not connected to the first connecting line L1-3, and the extension direction of the first redundant line L1'-3 is also symmetrical to the first connecting line L1-3 with respect to the central axis OO'. That is, the spacer base PS' corresponds to a first redundant line L2-3, and the first redundant line L1'-3 protrudes along the second direction X from a position on the other side of the symmetry with respect to the first sub-part L1-3 of the first connecting line L1-3.

[0051] The above configuration provides a first redundant line at a position where the spacer base PS' is symmetrical with respect to the central axis OO' and where no first connecting line is provided. The extension direction of the first redundant line is symmetrical with respect to the extension direction of the first connecting line with respect to the central axis OO'. The first connecting line provides traction at the position where it connects to the spacer base PS'. At the same time, another traction force is applied to the spacer base PS' in the symmetrical direction through the first redundant line at the position symmetrical with respect to the first connecting line. When the PI liquid formed on the surface of the second substrate flows and solidifies, it can diffuse sufficiently and uniformly at the position corresponding to the spacer base PS', improving the aggregation of the alignment layer in this area. As a result, the thickness of the alignment layer on the surface at this position is approximately the same, improving the display mura problem, enhancing the user experience, and improving display stripes.

[0052] It should be noted that, although Figure 6 The above two examples illustrate the same second substrate, namely, in the same second substrate, the first transistors corresponding to some spacer bases PS' are located on different sides relative to the central axis OO', and the first transistors corresponding to other spacer bases PS' are located on the same side relative to the central axis OO'. However, this disclosure is not intended to be limited to this. In some embodiments, the same substrate may include any two of the above examples, and in some embodiments, the same second substrate may include only one of the above examples.

[0053] It should also be noted that, although Figure 6 and Figure 7 The diagram illustrates a dual-gate pixel structure. However, those skilled in the art will understand that a non-dual-gate pixel structure can also be constructed if only one gate signal line is provided between two rows of pixel electrodes, and the spacer base is only connected to the transistor. In this case, a first redundant lead can protrude from the spacer base. The extension direction and position of the first redundant lead and the first connecting line corresponding to the same spacer base are symmetrical with respect to the central axis of the spacer base along the first direction, thereby improving the diffusion uniformity of the PI material.

[0054] In some alternative embodiments, based on the dual-gate pixel structure, the symmetrical balance of the applied traction force can be achieved by utilizing the positional relationship between the spacer base PS' and the two transistors in the dual-gate pixel structure without setting redundant signal lines.

[0055] Reference Figure 8 As shown, the difference between this embodiment and the previous embodiment is that the second substrate of the display module includes multiple third connection lines L3, and the multiple transistors include multiple third transistors T-3-1.

[0056] Specifically, such as Figure 8The second substrate of the dual-gate pixel structure shown has a spacer base PS' projected onto the first substrate between two gate signal lines 101. The spacer base PS' is electrically connected to the first electrode of two third transistors T-3-1 via two third connection lines L3-1, and the control electrodes of the two third transistors T-3-1 are electrically connected to the two gate signal lines 101. The third connection lines and the spacer base are located in the same first metal layer, while the gate signal lines 101 are located in the second metal layer, such as the gate layer.

[0057] Two third transistors T-3-1 are projected onto the first substrate and located on either side of the central axis OO' of the corresponding spacer base PS' along the first direction Y. The extension direction and position of the third connecting line L3-1 protruding from the spacer base PS' are symmetrical with respect to the central axis OO'. For example, in this example, the extension direction of the third connecting line L3-1 from the portion protruding from the connection position with the spacer base PS' is both along the second direction X, while the sidewall of the spacer base PS' at the connection position is along the first direction Y. The extension direction of the two third connecting lines L3-1 from the portion protruding from the connection position with the spacer base PS' is symmetrical with respect to the central axis OO'.

[0058] In another example, Figure 9 A partial structural schematic diagram of another second substrate based on a dual-gate pixel structure is shown. The same spacer base PS' corresponds to two third transistors T-3-2, which are located on opposite sides of the central axis OO' along the first direction Y. The first terminals of the two third transistors T-3-2 are electrically connected to the spacer base PS' via third connection lines L3-2 respectively disposed on both sides, so as to be electrically connected to the data signal line 102 via the spacer base PS'.

[0059] In this example, the extension direction and position of the third connecting line L3-2 protruding from the septum base PS' are symmetrical with respect to the central axis OO'. The extension direction of the third connecting line L3-1 from the portion protruding at the connection position with the septum base PS' is both along the second direction X, and the included angles θ1 and θ2 between the sidewalls of the septum base PS' at the connection position are approximately equal, thus the extension directions of the two third connecting lines L3-1 from the portions protruding at the connection positions with the septum base PS' are symmetrical with respect to the central axis OO'.

[0060] It is worth noting that, based on the different pattern shapes of the spacer base PS', the extension directions of the third connecting lines on both sides at the connection point are different, so as to ensure that the extension direction and position of the third connecting line L3-2 protruding from the spacer base PS' are symmetrical with respect to the central axis OO'.

[0061] By utilizing the above configuration and taking advantage of the characteristic that the dual-gate signal lines of the dual-gate pixel structure correspond to two transistors, and by placing two third transistors on opposite sides symmetrically relative to the central axis OO' of the spacer base PS', the extension direction of the protruding position connecting the spacer base PS' is symmetrical with respect to the central axis OO'. This ensures that the spacer base PS' receives a balanced and symmetrical lateral traction force from the connecting lines, allowing for even diffusion when the PI liquid at the spacer base PS' solidifies. Consequently, the thickness of the alignment layer on the surface at this location is approximately the same, improving the display murmur problem and enhancing the user experience.

[0062] It should be noted that, in combination Figure 8 As can be seen, this example illustrates two different embodiments of the structure described above, which have different relationships between the spacer base, transistor and connecting line, on the same second substrate. That is, the second substrate in this disclosure can use the structures of the different embodiments described above in combination. In other words, structures that include the first redundant line and structures that do not include the first redundant line but only rely on the third connecting line to achieve symmetrical arrangement of traction force can appear simultaneously in one second substrate.

[0063] In addition, although Figure 8 The same second substrate is shown to include structures, but this disclosure is not intended to be limited thereto. In some embodiments, the same second substrate may include any two of the structures in the examples above, and in some embodiments, the same second substrate may include only one of the structures in the examples above.

[0064] In some alternative embodiments, refer to Figure 10 As shown, the difference between this embodiment and the previous embodiment is that the display module includes multiple second connection lines L2, the data signal line 102 includes multiple spacer bases PS' and a connection portion 102-2 connecting the spacer bases PS', the connection portion 102-2 extends along the first direction Y, and the multiple transistors include multiple second transistors T-2. One end of the second connection line L2 is electrically connected to the connection portion, and the other end is electrically connected to the first electrode of the second transistor. The second connection line L2 and the data signal line 102 are located in the first metal layer.

[0065] In other words, in this embodiment, the electrical connection between the data signal line and the first pole of the transistor is not achieved through the connection between the connecting line and the spacer base PS'. Instead, the first pole is directly connected to the connecting part 102-2, which is the main body of the data signal line, via the second connecting line L2. That is, the spacer base PS' has no other leads except for the connection with the connecting part 102-2.

[0066] With this setting, even if the second connecting line L2 and the data signal line 102, i.e. the septum substrate PS', are located in the same metal layer, since there is no direct connection between the two, no lateral traction force relative to the central axis OO' will be applied to the septum substrate PS'. As a result, during the formation of the alignment layer corresponding to the position of the septum substrate PS', the PI liquid can diffuse evenly, thereby improving the aggregation of the alignment layer in this area and improving the display stripes.

[0067] For example, refer to Figure 10 As shown, the same spacer base PS' corresponds to two second transistors T-2-1. These two second transistors T-2-1 are located on opposite sides of the central axis OO' along the first direction Y. The first electrodes of the two second transistors T-2-1 are electrically connected to the connection portion 102-2 of the data signal line 102 via second connection lines L2-1 respectively provided on both sides, thereby achieving an electrical connection with the data signal line while avoiding the spacer base PS'. The control electrode and gate signal line 101 of the second transistor T-2-1 can both be disposed in the second metal layer, for example, the second metal layer can be called the gate layer.

[0068] In another example, refer to Figure 10 As shown, the same spacer base PS' corresponds to two second transistors T-2-2. These two second transistors T-2-2 are located on the same side of the central axis OO' along the first direction Y. The first electrodes of the two second transistors T-2-2 are electrically connected to the connection portion 102-2 of the data signal line 102 via two second connection lines L2-2 disposed on this same side, thereby achieving both electrical connection with the data signal line and avoiding the spacer base PS'. The control electrode and gate signal line 101 of the second transistor T-2-2 can both be disposed in the second metal layer, for example, the second metal layer can be called the gate layer.

[0069] It should be noted that, although Figure 10 The above two examples illustrate the same second substrate, in which the second transistors corresponding to some spacer bases PS' are located on different sides relative to the central axis OO', and the second transistors corresponding to other spacer bases PS' are located on the same side relative to the central axis OO'. However, this disclosure is not intended to be limited to this. In some embodiments, the same second substrate may contain only one of the structures described above.

[0070] It should also be noted that, although Figure 10The diagram illustrates a dual-gate pixel structure. However, those skilled in the art will understand that in a non-dual-gate pixel structure where only one gate signal line is provided between two rows of pixel electrodes, and where one spacer base corresponds to only one transistor, the spacer base can also be avoided by using a second connecting line to electrically connect the first electrode of the transistor to the connecting portion. This prevents signal lines extending in other directions from exerting a pulling force on the spacer base, thereby improving the diffusion uniformity of the PI material on the surface of the spacer base.

[0071] Those skilled in the art should also understand that the structures and functions described in this embodiment and those in the above embodiments are similar in structure and function to those in the above embodiments, and will not be described again here.

[0072] In some alternative embodiments, refer to Figure 11 As shown, the difference between this embodiment and the previous embodiment is that the display module further includes multiple fourth connection lines L4, and the multiple transistors include multiple fourth transistors T-4. The data signal line 102 includes multiple spacer bases PS' and a connection portion 102-2 connecting the spacer bases PS'. The connection portion 102-2 includes a first connection portion 102-2-1 extending along the first direction Y and a second connection portion 102-2-2 connecting the first connection portion 102-2-1 and the spacer base PS'.

[0073] The orthogonal projection of the spacer base PS' on the first substrate is located between the two gate signal lines 101. The spacer base PS' is electrically connected to the first electrode of the two fourth transistors T-4 through two fourth connection lines L4 respectively. The control electrode of the two fourth transistors T-4 is electrically connected to the two gate signal lines 101 respectively.

[0074] The second connecting part 102-2-2, the fourth connecting line L4 and the spacer base PS' are located in the first metal layer. The second connecting part 102-2-2 and the fourth connecting line L4 protruding from the spacer base PS' are symmetrical with respect to the central axis OO' of the spacer base PS' along the first direction Y.

[0075] With this configuration, a second connecting portion 102-2-2 and a fourth connecting line L4 are provided in the metal layer located on the same layer as the septum substrate PS'. The fourth connecting line is connected to the first electrode of the fourth transistor T-4. The second connecting portion 102-2-2 serves both as an extension of the first connecting portion 102-2-1 to form the data signal line 102 and as a lead-out portion symmetrical with respect to the central axis OO' of the fourth connecting line L4, thereby providing symmetrical traction force to the septum substrate PS' in cooperation with the fourth connecting line L4. As a result, the PI liquid located at the septum substrate PS' can spread uniformly during curing due to the symmetrical and uniform traction force, thereby improving the aggregation of the alignment layer in this area and improving the display stripes.

[0076] In some alternative embodiments, such as Figure 12 and Figure 13 As shown, the difference between this embodiment and the embodiment described above is that the driving circuit layer includes: a first metal layer 201, a first insulating layer 202 and a first conductive layer 203 sequentially stacked on the first substrate. The driving circuit layer also includes a fifth connecting line L5 and a sixth connecting line L6. The fifth connecting line L5 and the spacer base PS' are located on the first metal layer 201, and the second connecting line L6 is located on the first conductive layer 203.

[0077] The first metal layer also includes a plurality of first openings CK1 located at the edge of the spacer base PS'. A first insulating layer 202 is located on the surface of the first metal layer away from the first substrate. The first insulating layer 202 includes a plurality of second openings CK2, the orthographic projections of the second openings CK2 on the first substrate at least partially covering the orthographic projections of the first openings CK1 on the first substrate. One end of the fifth connection line L5 is electrically connected to the first terminal of the transistor, and the second end is electrically connected to the spacer base PS' via a sixth connection line. Figure 12 In the example, this transistor can be referred to as the fifth transistor T-5. Additionally, as... Figure 13 As shown, below the first metal layer 201, there may also be an active layer 204 electrically connected thereto and a second insulating layer 205 located below the active layer 204 for insulating it from the active layer 204. The second insulating layer 205 may be, for example, a gate insulating layer. Additionally, the first insulating layer 202 may be an inorganic insulating layer, commonly referred to as "PVX". Furthermore, the first conductive layer 203 may be a transparent metal oxide film layer, for example, it may be on the same layer as the pixel electrode layer or the common electrode layer.

[0078] With the above configuration, although the fifth connection line L5 connecting the first electrode of the transistor and the spacer base PS' are both located in the same first metal layer 201, a first opening CK1 is provided in the first metal layer 201. This first opening CK1 can be located in the edge region of the spacer base PS' near the fifth connection line L5. In this way, the spacer base PS' is isolated from the fifth connection line L5 in the same layer by the first opening CK1, thereby preventing the fifth connection line L5 from exerting a lateral pulling force on the spacer base PS'. At the same time, a second opening CK2 is provided in the first insulating layer 202, and the second opening CK2 is designed to at least partially cover the first opening CK1. A sixth connection line L6 is provided in the second conductive layer 203 to electrically connect the spacer base PS' and the fifth connection line L5.

[0079] Thus, while utilizing the first opening CK1 to block lateral traction force, signal transmission is formed through the upper conductive layer as the sixth connecting line, thereby avoiding the application of asymmetrical traction force to the spacer substrate PS' when electrically connecting to the first electrode of the transistor. Furthermore, the PI liquid located at the spacer substrate PS' can spread uniformly during curing due to the symmetrical and uniform traction force, thereby improving the aggregation of the alignment layer in this area and improving the display stripes.

[0080] It should be noted that, as Figure 12 As shown in the present embodiment, regardless of whether the two transistors, as shown by the fifth transistor T-5-1, are located on different sides of the data signal line 102, or whether the two transistors, as shown by the fifth transistor T-5-2, are located on the same side of the data signal line 102, since both the fifth connecting line L5-1 and the fifth connecting line L5-2 are separated by the first opening CK1, the presence of the fifth connecting line L5 and the electrical connection will not affect the diffusion uniformity of the PI liquid.

[0081] Furthermore, those skilled in the art should understand that the structure in this embodiment can cooperate with the structures in the various embodiments described above, and all appear together in a second substrate. Of course, a second substrate may also include only one such structure. Figure 12 Examples shown include the fifth transistor being placed on the same side or on different sides.

[0082] In some other alternative embodiments, such as Figure 14 As shown, this embodiment is similar to Figure 12 The embodiment shown differs in that the driving circuit layer includes a seventh connection line L7 located on the first conductive layer 203, the plurality of transistors include a plurality of sixth transistors T-6, and the spacer base PS' and the first electrode of the sixth transistor T-6 are located on the first metal layer.

[0083] The first metal layer also includes a plurality of third openings CK3. The first insulating layer 202 is located on the surface of the first metal layer away from the first substrate. The first insulating layer includes a plurality of fourth openings CK4. The orthogonal projection of the fourth opening CK4 on the first substrate at least partially covers the orthogonal projection of the third opening CK3 on the first substrate. One end of the orthogonal projection of the fourth opening CK4 on the first substrate contacts the edge of the orthogonal projection of the spacer base PS' on the first substrate, and the other end contacts the edge of the orthogonal projection of the first electrode of the sixth transistor T-6 on the first substrate. The seventh connecting line L7 is electrically connected to the spacer base and the first electrode of the sixth transistor T-6. The seventh connecting line L7 is located in the first conductive layer.

[0084] With the above configuration, the opening in the first metal layer can be further enlarged so that the third opening CK3 is located on one side of the edge of the spacer base PS' and on the other side of the edge of the first pole of the sixth transistor T6, thus eliminating the need to set a connecting line in the first metal layer, and then forming an electrical connection relationship by means of the seventh connecting line in the first conductive layer, which is another layer.

[0085] Thus, while utilizing the third opening CK3 to block lateral traction force, signal transmission is formed through the upper conductive layer as the seventh connecting line, thereby avoiding the application of asymmetrical traction force to the spacer substrate PS' when electrically connecting to the first electrode of the transistor. Furthermore, the PI liquid located at the spacer substrate PS' can spread uniformly during curing due to the symmetrical and uniform traction force, thereby improving the aggregation of the alignment layer in this area and improving the display stripes.

[0086] It should be noted that, as Figure 14 As shown in the embodiments of this disclosure, regardless of whether the two transistors, as shown in the sixth transistor T-6-1, are located on different sides of the data signal line 102, or whether the two transistors, as shown in the sixth transistor T-6-2, are located on the same side of the data signal line 102, the electrical connection between the spacer base PS' and the first electrode of the transistor will not affect the diffusion uniformity of the PI liquid because the third opening CK3 separates the first metal layer.

[0087] In some other alternative embodiments, such as Figure 15 As shown, the display module also includes multiple eighth connection lines. One end of the first connection line is electrically connected to the spacer base PS', and the other end is electrically connected to the first electrode of the transistor. The first connection line and the spacer base PS' are located in the first metal layer. The transistor is the seventh transistor T-7.

[0088] The driving circuit layer includes: a first metal layer, a first insulating layer, and a first conductive layer sequentially stacked on the first substrate. The first insulating layer is located on the surface of the first metal layer away from the first substrate, and the first conductive layer is located on the surface of the first conductive layer away from the first substrate. The first conductive layer includes a capping layer, the orthographic projection of which at least partially covers the orthographic projection of the spacer base PS' on the first substrate. The first insulating layer can be an inorganic insulating layer, commonly referred to as "PVX". Alternatively, the first conductive layer can be a transparent metal oxide film layer, for example, it can be on the same layer as the pixel electrode layer or the common electrode layer.

[0089] Specifically, the first conductive layer includes a capping layer whose orthogonal projection on the first substrate at least partially covers the orthogonal projection of the spacer abutment on the first substrate, and the first conductive layer is a transparent metal oxide material. For example, the material of the first conductive layer is ITO.

[0090] Furthermore, those skilled in the art should understand that the structure in this embodiment can cooperate with the structures in the various embodiments described above and coexist in a second substrate. Of course, a second substrate may also include only one example, as shown in the figure, where the fifth transistor is disposed on the same side or the seventh transistor is disposed on different sides.

[0091] Because the PVX used as the first insulating layer is typically a silicon nitride thin film, this film is usually the surface material closest to the alignment layer in the spacer substrate portion. This material has low surface energy, poor hydrophilicity, and weak affinity for PI, making PI difficult to spread. During flow, it tends to roll rather than diffuse, macroscopically manifesting as PI aggregation. If a capping layer, represented by ITO, is designed on the PVX, the ability of PI to spread on ITO increases, thereby changing the flowability, optimizing PI aggregation, and thus improving the diffusion uniformity during PI liquid curing, improving the display stripe problem.

[0092] In some other alternative embodiments, such as Figure 16 As shown, this embodiment is similar to Figure 15 The difference in the illustrated embodiment is that the second substrate improves the diffusion uniformity of the PI liquid during curing by changing the surface structure of the spacer base PS'.

[0093] Specifically, the driving circuit layer includes a first metal layer, and the display module also includes a plurality of eighth connection lines L8. One end of each eighth connection line L8 is electrically connected to a spacer base PS', and the other end is electrically connected to the first electrode of a transistor. The eighth connection lines L8 and the spacer base PS' are located in the first metal layer. The spacer base PS' is a mesh structure, a porous structure, or a surface uneven structure. For example, as shown... Figure 16 The top view shows a septum base PS' with an uneven or porous structure. Figure 17 The spacer base PS' is shown to be a grid structure.

[0094] By modifying the surface microphysical structure of the septum substrate, the molecular motion of PI liquid is hindered during curing, resulting in reduced fluidity, reduced PI shrinkage, and decreased aggregation. At the same time, the edges of the uneven, grid, or porous structures restrict lateral diffusion, changing the flow direction and range, thereby improving PI aggregation.

[0095] In some alternative embodiments, the inventors discovered through research that by reducing the morphological thickness discontinuity of the spacer base PS' structure, the flowability of the alignment layer PI during coating can be effectively reduced.

[0096] For example, such as Figure 18 and Figure 19 As shown, the driving circuit layer includes a first metal layer 201 and a first insulating layer 202 sequentially stacked on a first substrate. The first insulating layer 202 is located on the surface of the first metal layer 201 away from the first substrate, and the spacer base is located in the first metal layer 201. The first insulating layer 202 is also called "PVX", and it is typically an inorganic material layer. Figure 18 As shown, below the first metal layer 201, there is also an active layer 204 electrically connected thereto, and a second insulating layer 205 located below the active layer. The second insulating layer can be a gate insulating layer.

[0097] In particular, such as Figure 18 As shown, the first insulating layer covers the spacer base, and the thickness h1 of the portion of the first metal layer covering the spacer base is less than or equal to 100 nm.

[0098] By thinning the first insulating layer on the surface of the spacer base, the step difference h2 between the surface of the first insulating layer at the spacer base location and the surface of the first insulating layer in other areas around the spacer base can be reduced from approximately 520 nm to 320 nm.

[0099] In particular, such as Figure 19 As shown, instead of directly reducing the thickness of the first insulating layer above the spacer base, this example extends the length of the active layer 204 located below the spacer base by a distance exceeding a predetermined range from the edge of the spacer base surface compared to a conventional structure, thus forming a channel-like morphology. Optionally, the orthographic projection of the active layer 204 on the first substrate covers the orthographic projection of the spacer base on the first substrate, and the distance w between the edge of the active layer 204 and the edge of the spacer base is greater than or equal to 1µm. With this configuration, the step height h3 between the surface of the first insulating layer at the septum base location and the surface of the first insulating layer in other areas around the septum base can also be reduced compared to existing technologies.

[0100] Another aspect of this disclosure provides a display device including the aforementioned display module. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator; this embodiment does not limit this. By loading the above display module, the display device can effectively improve the display mura caused by uneven diffusion of the alignment layer on the surface of the spacer base, possessing high commercial value and display level.

[0101] Since the display module included in the display device provided in this embodiment is the same as the display panel provided in the above embodiments, the previous embodiments are also applicable to the display device provided in this embodiment, and will not be described in detail in this embodiment.

[0102] Obviously, the above embodiments of this disclosure are merely examples for clearly illustrating this disclosure, and are not intended to limit the implementation of this disclosure. For those skilled in the art, other variations or modifications can be made based on the above description. It is impossible to exhaustively list all implementation methods here. Any obvious variations or modifications derived from the technical solutions of this disclosure are still within the protection scope of this disclosure.

Claims

1. A display module, characterized in that, include: A first substrate, a second substrate, and a liquid crystal layer disposed between the first substrate and the second substrate. The first substrate is provided with a plurality of spacers, and the second substrate is provided with spacer bases corresponding to the plurality of spacers. The second substrate further includes: a driving circuit layer disposed on the first substrate, and an alignment layer disposed on the surface of the second substrate near the first substrate; The driving circuit layer includes: a plurality of gate signal lines arranged along a first direction, a plurality of data signal lines arranged along a second direction, and a plurality of transistors, wherein the data signal lines include the plurality of spacer bases. The data signal line is electrically connected to the first electrode of the transistor, and the gate signal line is electrically connected to the control electrode of the transistor. The orientation layer has approximately the same thickness at the portion located on the septum base.

2. The display module according to claim 1, characterized in that, The driving circuit layer includes a first metal layer, and the second substrate further includes a plurality of first interconnect lines and a plurality of first redundant leads. The plurality of transistors includes a plurality of first transistors. One end of each first interconnect line is electrically connected to the spacer base, and the other end is electrically connected to the first electrode of the first transistor. The first interconnect lines, the first redundant leads, and the spacer base are located on the first metal layer. The first redundant lead protrudes from the septum base, and the extension direction and position of the first redundant lead and the first connecting line corresponding to the same septum base are symmetrical with respect to the central axis of the septum base along the first direction.

3. The display module according to claim 1, characterized in that, The driving circuit layer includes a first metal layer, the second substrate further includes a plurality of second interconnect lines, the data signal lines include the plurality of spacer bases and connecting portions connecting the spacer bases, and the plurality of transistors include a plurality of second transistors. One end of the second connecting line is electrically connected to the connecting portion, and the other end is electrically connected to the first electrode of the second transistor. The second connecting line and the data signal line are located in the first metal layer.

4. The display module according to claim 1, characterized in that, The second substrate further includes: a pixel electrode layer disposed on the driving circuit layer, the pixel electrode layer comprising a plurality of pixel electrodes arranged in an array. Two gate signal lines are provided between every two rows of pixel electrodes, and one data signal line is provided every two columns of pixel electrodes.

5. The display module according to claim 4, characterized in that, The driving circuit layer includes a first metal layer, and the second substrate further includes a plurality of third interconnect lines. The plurality of transistors includes a plurality of third transistors. The orthographic projection of the spacer base on the first substrate lies between the two gate signal lines. The spacer base is electrically connected to the first electrode of the two third transistors via two third connection lines, and the control electrodes of the two third transistors are electrically connected to the two gate signal lines. The third connecting line and the spacer base are located in the first metal layer. The two third transistors are projected onto the first substrate and are located on either side of the central axis extending along the first direction of the corresponding spacer base. The two third connecting lines protrude from the spacer base in a symmetrical direction and position relative to the central axis.

6. The display module according to claim 4, characterized in that, The driving circuit layer includes a first metal layer, and the second substrate further includes a plurality of fourth interconnect lines. The plurality of transistors includes a plurality of fourth transistors. The data signal line includes the plurality of spacer bases and a connecting portion connecting the spacer bases. The connecting portion includes a first connecting portion extending along the first direction and a second connecting portion connecting the first connecting portion and the spacer base. The orthographic projection of the spacer base on the first substrate lies between the two gate signal lines. The spacer base is electrically connected to the first electrode of the two fourth transistors via two fourth connection lines, and the control electrodes of the two fourth transistors are electrically connected to the two gate signal lines. The second connecting portion, the fourth connecting line, and the spacer base are located on the first metal layer. The second connecting portion and the fourth connecting line, which protrude from the septum base, are symmetrical in their extension direction and position relative to the central axis of the septum base along the first direction.

7. The display module according to claim 1, characterized in that, The driving circuit layer includes: a first metal layer, a first insulating layer, and a first conductive layer sequentially stacked on the first substrate. The driving circuit layer also includes a fifth connection line and a sixth connection line, wherein the fifth connection line and the spacer base are located on the first metal layer. The first metal layer further includes a plurality of first openings located at the edge of the spacer base. The first insulating layer is located on the surface of the first metal layer away from the first substrate. The first insulating layer includes a plurality of second openings, the orthographic projections of the second openings on the first substrate at least partially covering the orthographic projections of the first openings on the first substrate. One end of the fifth connection line is electrically connected to the first electrode of the transistor, and the second end is electrically connected to the spacer base via the sixth connection line, which is located in the first conductive layer.

8. The display module according to claim 1, characterized in that, The driving circuit layer includes: a first metal layer, a first insulating layer, and a first conductive layer sequentially stacked on the first substrate. The driving circuit layer also includes a seventh connection line. The plurality of transistors includes a plurality of sixth transistors. The spacer abutment and the first electrode of the sixth transistor are located on the first metal layer. The first metal layer further includes a plurality of third openings. The first insulating layer is located on the surface of the first metal layer away from the first substrate. The first insulating layer includes a plurality of fourth openings, the orthographic projection of which on the first substrate at least partially covers the orthographic projection of which on the first substrate is a third opening. One end of the orthographic projection of the fourth opening onto the first substrate contacts the edge of the orthographic projection of the spacer base onto the first substrate, and the other end contacts the edge of the orthographic projection of the first electrode of the sixth transistor onto the first substrate. The seventh connection line is electrically connected to the spacer base and the first electrode of the sixth transistor, and the seventh connection line is located in the first conductive layer.

9. The display module according to claim 1, characterized in that, The driving circuit layer includes: a first metal layer, a first insulating layer, and a first conductive layer sequentially stacked on the first substrate, wherein the first insulating layer is located on the surface of the first metal layer away from the first substrate, and the first conductive layer is located on the surface of the first conductive layer away from the first substrate. The first conductive layer includes a capping layer, the orthographic projection of which on the first substrate at least partially covers the orthographic projection of the spacer abutment on the first substrate, and the first conductive layer is a transparent metal oxide material.

10. The display module according to claim 1, characterized in that, The drive circuit layer includes a first metal layer, and the spacer base is located on the first metal layer. The spacer base has a mesh structure, a porous structure, or a surface with unevenness.

11. The display module according to claim 1, characterized in that, The driving circuit layer includes: a first metal layer and a first insulating layer sequentially stacked on the first substrate, wherein the first insulating layer is located on the surface of the first metal layer away from the first substrate, and a first spacer base is located on the first metal layer. The first insulating layer covers the spacer base, and the thickness of the portion of the first metal layer covering the spacer base is less than or equal to 100 nm, or The driving circuit layer further includes an active layer located on the surface of the first metal layer near the first substrate, wherein the orthographic projection of the active layer on the first substrate covers the orthographic projection of the spacer base on the first substrate, and the distance between the edge of the active layer and the edge of the spacer base is greater than or equal to 1µm.

12. A display device, characterized in that, The display module includes any one of claims 1-11.

Images