Mask and method of manufacturing a mask

Abstract

A method of manufacturing a mask includes performing a plasma treatment on a capping layer formed on a reflective multilayer stack to form a compound layer. The mask includes a reflective multilayer stack disposed on a substrate, a capping layer disposed on the reflective multilayer stack, and an absorbing layer disposed on the capping layer. An opening is formed in the absorbing layer, and the compound layer is located in the opening.

Description

Technical Field

[0001] This disclosed embodiment relates to a mask and a method for manufacturing a mask. Background Technology

[0002] Manufacturing challenges can arise when seeking to reduce the size of semiconductor devices while increasing their complexity. To address these challenges, advanced photolithography techniques, such as extreme ultraviolet (EUV) lithography, have been applied to semiconductor device manufacturing processes. EUV lithography uses a reflective photomask to irradiate a photoresist layer with patterned EUV radiation. This patterned EUV radiation can create patterns in the photoresist layer, which can then be used to create patterns in the substrate beneath the photoresist layer. However, the processes associated with the use, fabrication, and cleaning of photomasks in EUV lithography can adversely affect photomask performance. Summary of the Invention

[0003] This disclosure provides a method for manufacturing a mask, the method comprising the following steps: forming a reflective multilayer stack on a substrate; forming a capping layer on the reflective multilayer stack, wherein the capping layer comprises at least one of rhodium and ruthenium; subjecting the capping layer to plasma treatment to form a compound layer on the capping layer, wherein the compound layer comprises at least one of rhodium and ruthenium, and at least one additional element; forming an absorption layer on the compound layer; and etching openings in the absorption layer to expose the compound layer.

[0004] Another embodiment of this disclosure provides a method for manufacturing a mask, comprising the following steps: etching openings in a mask template, wherein the mask template includes: a substrate; a reflective multilayer stack disposed on the substrate; a capping layer disposed on the reflective multilayer stack, wherein the capping layer includes at least one selected from rhodium and ruthenium; and an absorber layer disposed on the capping layer, wherein the openings expose the capping layer. The method further includes plasma treating the capping layer to form a compound layer on the capping layer within the openings, wherein the compound layer includes oxygen and at least one selected from rhodium and ruthenium.

[0005] Another embodiment of this disclosure discloses a mask for extreme ultraviolet (EUV) lithography. The mask includes: a reflective multilayer stack disposed on a substrate; a first capping layer disposed on the reflective multilayer stack; a second capping layer disposed on the first capping layer, wherein the second capping layer includes at least one of rhodium and ruthenium and has a different composition from the first capping layer; an absorption layer disposed on the second capping layer; and an opening formed in the absorption layer to expose a compound layer disposed on the second capping layer, wherein the compound layer includes at least one of a rhodium compound and a ruthenium compound. Attached Figure Description

[0006] This disclosure is in conjunction with the appendixFigure 1 This is the easiest way to understand the text. It's important to emphasize that, according to industry standard practice, the features are not drawn to scale; they are for illustrative purposes only. In reality, the dimensions of various features may be arbitrarily increased or decreased for the purpose of discussing clarity.

[0007] Figure 1 An extreme ultraviolet lithography tool according to an embodiment of this disclosure is shown.

[0008] Figure 2 A detailed schematic diagram of an extreme ultraviolet lithography tool according to an embodiment of this disclosure is shown.

[0009] Figure 3 A cross-sectional view of an EUV mask according to an embodiment of this disclosure is shown.

[0010] Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 and Figure 15 A cross-sectional view is shown of a method for manufacturing an EUV mask according to an embodiment of this disclosure.

[0011] Figure 16A , Figure 16B and Figure 16C A cross-sectional view of an EUV mask according to an embodiment of this disclosure is shown.

[0012] Figure 17 A schematic diagram of a plasma processing apparatus according to an embodiment is shown.

[0013] Figure 18 , Figure 19 and Figure 20 This is a flowchart of a method for manufacturing a mask according to an embodiment of the present disclosure.

[0014] Figure 21 This is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Detailed Implementation

[0015] It should be understood that the following disclosure provides many different embodiments or examples to implement different features of this disclosure. Specific embodiments or examples of components and configurations described below are for the purpose of simplifying this disclosure. These are, of course, merely examples and are not intended to constitute limitation. For example, component dimensions are not limited to the disclosed range or values, but may depend on process conditions and / or the characteristics required by the apparatus. Furthermore, in the following description, the formation of a first feature above or on a second feature includes embodiments where the first and second features are in direct contact, and may also include embodiments where other features are formed between the first and second features such that the first and second features are not in direct contact. For simplicity and clarity, various features may be arbitrarily depicted at different scales.

[0016] Furthermore, this document may use spatially relative terms such as "beneath," "below," "lower," "above," "upper," "top," "bottom," and "middle" to conveniently describe the relationship between one component or feature shown in the figures and another, without excluding the presence of additional structures above, below, or between said features. Spatially relative terms are intended to encompass different orientations of the device in use or operation, other than those shown in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly. Additionally, the term "made of" may mean "comprising" or "consisting of."

[0017] Furthermore, in the manufacturing processes described below, there may be one or more additional operations between the described operations, and the order of operations may be changed. In this disclosure, the phrase "one of A, B, and C" means "A, B, and / or C (A, B, C, A and B, A and C, B and C, or A, B, and C)," and unless otherwise stated, does not mean one element from A, one element from B, and one element from C. In the following embodiments, the materials, configurations, dimensions, processes, and / or operations described with respect to one embodiment (e.g., one or more figures) may be applicable to other embodiments, and their detailed description may be omitted.

[0018] Figure 1This is a schematic diagram of an extreme ultraviolet (EUV) lithography tool 2 according to some embodiments of the present disclosure. The EUV lithography tool 2 includes an EUV radiation source 100 for generating extreme ultraviolet radiation, an exposure device 200 (such as a scanning device), and an excitation laser source 300. The EUV radiation source 100 and the exposure device 200 are mounted on the main floor MF of a clean room, while the excitation laser source 300 is mounted on the ground floor BF below the main floor. The EUV radiation source 100 and the exposure device 200 are placed on base plates PP1 and PP2, respectively, via shock absorbers DP1 and DP2. The EUV radiation source 100 and the exposure device 200 are coupled to each other via a coupling mechanism, which may include a focusing unit.

[0019] The extreme ultraviolet (EUV) lithography tool 2 is designed to expose a photoresist layer to extreme ultraviolet light (also referred to herein as extreme ultraviolet radiation). The photoresist layer is a material sensitive to EUV light. The EUV lithography system uses an EUV radiation source 100 to generate EUV light, for example, EUV light with a wavelength range between about 1 nanometer and about 100 nanometers. In a particular example, the EUV radiation source 100 generates EUV light with a wavelength centered at about 13.5 nanometers. In this embodiment, the EUV radiation source 100 utilizes a laser-produced plasma (LPP) mechanism to generate EUV radiation.

[0020] Exposure apparatus 200 includes various reflective optical components, such as convex / concave / planar mirrors, a mask holding mechanism including a mask stage, and a wafer holding mechanism. Extreme ultraviolet radiation generated by extreme ultraviolet radiation source 100 is guided by the reflective optical components to a mask fixed on the mask stage. In some embodiments, the mask stage includes an electrostatic chuck (e-chuck) for securing the mask.

[0021] Figure 2This is a detailed schematic diagram of an extreme ultraviolet (EUV) lithography tool according to an embodiment of the present disclosure, showing the use of a patterned beam of EUV light to expose a photoresist layer 211 coated on a substrate 210. The exposure apparatus 200 is an integrated circuit lithography tool, such as a stepper, scanning device, stepping and scanning system, direct-write system, or device using a contact and / or proximity mask. It is configured with one or more optical components 205a, 205b, for example, irradiating a mask 205c (also called a reticle or photomask) with an EUV beam to generate a patterned beam, and one or more reduction projection optics 205d, 205e for projecting the patterned beam onto the photoresist layer 211 disposed on the substrate 210. In this embodiment, mask 205c is a reflective mask. Mechanical components (not shown) may be provided to generate controlled relative movement between substrate 210 and mask 205c. Extreme ultraviolet (EUV) radiation source 100 includes an EUV radiator ZE for emitting EUV light in chamber 105, which is reflected by mirror collector 110 and enters the exposure apparatus 200 along a path to irradiate photoresist layer 211 on substrate 210. In some embodiments, substrate 210 is a semiconductor substrate. In some embodiments, the semiconductor substrate is a semiconductor wafer, such as a silicon wafer or other type of wafer to be patterned.

[0022] like Figure 1 As shown, the extreme ultraviolet radiation source 100 includes a target droplet generator 115 and a mirror collector 110 enclosed by a chamber 105. In some embodiments, the target droplet generator 115 includes a storage tank for containing source material and a nozzle 120 through which target droplets (DP) of the source material are supplied into the chamber 105. In some embodiments, the target droplets (DP) are droplets of tin (Sn), lithium (Li), or an alloy of Sn and Li. In some embodiments, each target droplet (DP) has a diameter ranging from about 10 micrometers (µm) to about 100 µm. For example, in one embodiment, the target droplet (DP) is a tin droplet having a diameter of about 10 µm to about 100 µm. In other embodiments, the target droplet (DP) is a tin droplet having a diameter of about 25 µm to about 50 µm. In some embodiments, the target droplets DP are supplied through nozzle 120 at a rate ranging from about 50 droplets per second (i.e., about 50 Hz jet frequency) to about 50,000 droplets per second (i.e., about 50 kHz jet frequency). Droplet receiver 125 is used to capture excess target droplets. For example, some target droplets may be intentionally missed by the laser pulse.

[0023] In some embodiments, the excitation laser LR2 generated by the excitation laser source 300 is a pulsed laser. The excitation laser source 300 may include a laser generator 310, a laser guiding optics assembly 320, and a focusing device 330. In some embodiments, the laser generator 310 includes a carbon dioxide (CO2) or neodymium-doped yttrium aluminum garnet (Nd:YAG) laser source with a wavelength in the infrared region of the electromagnetic spectrum. For example, in one embodiment, the laser generator 310 has a wavelength of 9.4 µm or 10.6 µm. The laser light LR1 generated by the excitation laser source 300 is guided by the laser guiding optics assembly 320 and focused by the focusing device 330 to form the excitation laser LR2, which is then introduced into the extreme ultraviolet radiation source 100.

[0024] In some embodiments, the excitation laser LR2 comprises a pre-heat laser and a main laser. In these embodiments, the pre-heat laser pulse (which may be interchangeably referred to herein as a "pre-pulse") is used to heat (or preheat) a given target droplet to generate a low-density target plume having multiple smaller droplets, which is then heated (or reheated) by a pulse from the main laser, resulting in increased extreme ultraviolet emission. In some embodiments, the pre-heat laser pulse has a spot size of about 100 µm or less, and the main laser pulse has a spot size in the range of about 150 µm to about 300 µm. In some embodiments, the pre-heat laser and main laser pulses have pulse durations in the range of about 10 ns to about 50 ns, and pulse frequencies in the range of about 1 kHz to about 100 kHz. In some embodiments, the pre-heat laser and main laser have an average power in the range of about 1 kilowatt (kW) to about 50 kW. In one embodiment, the pulse frequency of the excitation laser LR2 is matched to the ejection frequency of the target droplet DP.

[0025] The excitation laser LR2 is guided into the excitation region ZE through a window (or lens). The window is made of a suitable material that is substantially transparent to the laser beam. The generation of the pulsed laser is synchronized with the ejection of the target droplet DP through the nozzle 120. As the target droplet moves through the excitation region, a pre-pulse heats the target droplet and transforms it into a low-density target plume. The delay between the pre-pulse and the main pulse is controlled to allow the target plume to form and expand to an optimal size and geometry. In some embodiments, the pre-pulse and the main pulse have the same pulse duration and peak power. When the main pulse heats the target plume, high-temperature plasma is generated. The plasma emits extreme ultraviolet radiation, which is collected by a mirror collector 110. The mirror collector 110 further reflects and focuses the extreme ultraviolet radiation for use in an exposure apparatus 200 to perform a photolithography exposure process. In some embodiments, the mirror collector 110 is designed to have an elliptical geometry. In some embodiments, the mirror collector 110 is designed with appropriate coating materials and shapes to function as a mirror for collecting, reflecting and focusing extreme ultraviolet light.

[0026] In some embodiments, the coating material of the mirror collector 110 is a reflective multilayer stack similar to an extreme ultraviolet (EUV) mask. In some instances, the coating material of the mirror collector 110 includes a reflective multilayer (e.g., multiple Mo / Si film pairs) and may further include a capping layer (e.g., ruthenium or rhodium) coated on top of the reflective multilayer to substantially reflect EUV light. In some embodiments, the mirror collector 110 may further include a grating structure designed for efficient scattering of laser beams directed onto the mirror collector 110. For example, a silicon nitride layer is coated on the mirror collector 110 and patterned to have a grating pattern.

[0027] In this type of extreme ultraviolet radiation source 100, the plasma generated by the laser application will produce physical debris, such as ions, gases, and atoms of droplets, as well as the required extreme ultraviolet radiation. It is necessary to prevent material from accumulating on the mirror collector 110 and to prevent physical debris from leaving the chamber 105 and entering the exposure apparatus 200.

[0028] Because gas molecules absorb extreme ultraviolet (EUV) light, photolithography systems used for EUV patterning can be maintained in a vacuum or low-pressure environment to avoid intensity loss of EUV light. In some embodiments, a buffer gas is supplied from a first buffer gas supplier 130 through a pulsed laser in a mirror collector 110 to the opening of the molten tin droplet. In some embodiments, the buffer gas is H2, He, Ar, N2, or another inert gas. The buffer gas can also be supplied via one or more second buffer gas suppliers 135 toward and / or around the edge of the mirror collector 110. Furthermore, chamber 105 includes one or more gas outlets 140 to allow the buffer gas to exit chamber 105. Hydrogen (H2) has a low absorption rate for EUV radiation. In some embodiments, hydrogen can be excited by EUV radiation to produce hydrogen (H2). Hydrogen radicals can be used for cleaning purposes. Upon reaching the coated surface of the mirror collector 110, hydrogen radicals can chemically react with droplet metal contaminants to form hydrides, such as metal hydrides. When tin (Sn) is used as the droplet, hydrogen radicals can react with tin to form stanzanol (SnH4), a gaseous byproduct of the extreme ultraviolet light generation process. The gaseous SnH4 can then be pumped out through outlet 140.

[0029] In some embodiments, the extreme ultraviolet lithography tool may further include other modules or be integrated (or coupled) with other modules in some embodiments.

[0030] Masks used in extreme ultraviolet (EUV) lithography may include a reflective multilayer stack disposed on a substrate, one or more capping layers disposed on the reflective multilayer stack, and an absorption layer disposed on the one or more capping layers. In some embodiments, a compound layer comprising one or more rhodium compounds is disposed on the one or more capping layers. The compound layer can enhance chemical resistance and inhibit ion diffusion into the mask's reflective multilayer stack. The chemical resistance and protection of the reflective multilayer stack can extend the mask's lifetime.

[0031] The mask may comprise a substrate made of a low thermal expansion material, such as doped titanium dioxide silica, or any other suitable low thermal expansion material, such as fused silica, fused quartz, silicon, silicon carbide, black diamond, and / or any one or more other known low thermal expansion materials, to minimize image distortion caused by mask heating in extreme ultraviolet lithography environments. The mask substrate may have a low defect level, such as a high-purity single-crystal substrate, and low surface roughness as measured using atomic force microscopy. The mask substrate may transmit light within a predetermined spectrum, such as visible wavelengths, near-infrared wavelengths close to the visible spectrum, and ultraviolet wavelengths. In some embodiments, the mask substrate absorbs EUV wavelengths and deep ultraviolet (DUV) wavelengths. Figure 3 A cross-sectional view of a mask 205c according to an embodiment of the present disclosure is shown, including a mask substrate 10 made of a suitable material, such as a low thermal expansion material.

[0032] The mask may include a reflective multilayer stack formed on a mask substrate. The reflective multilayer stack may include multiple pairs of thin films, such as molybdenum-silicon (Mo / Si) thin film pairs (e.g., in each thin film pair, a molybdenum layer is above or below a silicon layer). Alternatively, the reflective multilayer stack may include molybdenum-beryllium (Mo / Be) thin film pairs, or other suitable materials configured to highly reflect extreme ultraviolet light. Figure 3A reflective multilayer stack 20 is shown, comprising alternating molybdenum layers 17 and silicon layers 19 disposed on a first main surface of a mask substrate 10. In some embodiments, the multilayer stack 20 provides Fresnel resonant reflections at the interface between molybdenum and silicon layers with different refractive indices and appropriate thicknesses. The thickness of the layers may depend on the incident light wavelength and the angle of incidence of the light to be used with the extreme ultraviolet mask. For a given angle of incidence, the thickness of each layer of the multilayer stack 20 can be selected to achieve maximum constructive interference of the light reflected at different interfaces of the multilayer stack 20. Uniform thickness and low surface roughness of each layer in the multilayer stack 20 provide high-quality Fresnel resonant reflections. In some embodiments, the thickness of each layer in the multilayer stack 20 is 5-7 nanometers. In some embodiments, the number of layers in the multilayer stack 20 is in the range of 20 to 100, but any number of layers is allowed as long as sufficient reflectivity is maintained to image the photoresist layer on the target substrate. In some embodiments, the reflectivity of the reflective multilayer stack is higher than about 70%. In some embodiments, the reflective multilayer stack 20 includes about 30 to about 60 alternating molybdenum and silicon layers. In other embodiments, the multilayer stack 20 includes about 40 to about 50 alternating molybdenum and silicon layers. The alternating layers, such as silicon and molybdenum layers, of the reflective multilayer stack 20 can be formed by any one or more methods such as ion beam deposition (IBD), atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), and plasma-enhanced CVD (PECVD).

[0033] Mask 205c may include one or more overlay layers disposed on a reflective multilayer stack. Figure 3A first capping layer 23 disposed on a multilayer stack 20 is shown. In some embodiments, the first capping layer serves as a buffer layer. In some embodiments, the first capping layer 23 is made of a transition metal element or composition, and alternatively or additionally, may be made of a metal oxide, metal nitride, amorphous carbon, or other suitable material. In some embodiments, the first capping layer 23 is made of one or more transition metal elements. Examples of transition metal elements suitable for use in the first capping layer 23 include tantalum, ruthenium, niobium, rhodium, zirconium, and iridium. Other suitable materials for the first capping layer include B4C and graphene. In some embodiments, the first capping layer 23 is made of an alloy of two or more transition metal elements. In some embodiments, the first capping layer 23 is made of a compound comprising one or more transition metal elements. In some embodiments, the first capping layer 23 is made of any one or more of a halide, oxide, nitride, carbide, or boride of one or more transition metal elements. Examples of halides suitable for the first capping layer include fluorides, chlorides, bromides, and iodides. In some embodiments, the first capping layer 23 is made of one or more of tantalum oxide, ruthenium oxide such as RuO2, niobium oxide, rhodium oxide such as Rh2O3, zirconium oxide, iridium oxide such as IrO2, ruthenium-rhodium alloy, tantalum nitride, ruthenium nitride, niobium nitride, rhodium nitride, tantalum carbide, ruthenium carbide, niobium carbide, rhodium carbide, tantalum boride, ruthenium boride, niobium boride, rhodium boride, tantalum fluoride, ruthenium fluoride, niobium fluoride, rhodium fluoride, tantalum chloride, ruthenium chloride, niobium chloride, rhodium chloride, tantalum bromide, ruthenium bromide, niobium bromide, rhodium bromide, tantalum iodide, ruthenium iodide, niobium iodide, and rhodium iodide. In some embodiments, the first capping layer 23 has a thickness ranging from about 0.5 nanometers to about 10 nanometers, from about 1 nanometer to about 9 nanometers, from about 2 nanometers to about 8 nanometers, from about 3 nanometers to about 7 nanometers, or from about 4 nanometers to about 6 nanometers.

[0034] Mask 205c may include a second overlay 25 disposed on the reflective multilayer stack 20. In some forms, a first overlay 23 is disposed on the reflective multilayer stack 20, and the second overlay 25 is disposed on the first overlay 23, with the first overlay located between the reflective multilayer stack and the second overlay. The first overlay 23 can protect the reflective multilayer stack 20 from oxidation during the manufacturing process. Thus, the first overlay can protect and stabilize the reflective multilayer stack. In some embodiments, the first overlay is omitted from the mask, and the second overlay is disposed on the reflective multilayer stack. In some embodiments, the second overlay is disposed directly on the reflective multilayer stack, and no first overlay is located between the second overlay and the reflective multilayer stack.

[0035] Figure 3A second cover layer 25 disposed on a first cover layer 23 is shown. In some embodiments, the second cover layer 25 comprises at least one of rhodium, a rhodium alloy, ruthenium, a ruthenium alloy, a mixture of ruthenium and B4C, and an inert metal. In some embodiments, the inert metal comprises at least one of niobium, zirconium, and iridium. In some embodiments, the second cover layer 25 is made of rhodium or ruthenium. In some embodiments, the second cover layer 25 is formed entirely of rhodium or ruthenium. In some embodiments, the second cover layer 25 comprises one or more materials described herein for the first cover layer 23. In some embodiments, the first cover layer 23 comprises one or more materials described herein for the second cover layer 25. In some embodiments, the mask comprises both the first cover layer 23 and the second cover layer 25, and the compositions of the first and second cover layers are different. In some embodiments, the mask comprises both the first cover layer 23 and the second cover layer 25, and the compositions of the first and second cover layers are the same. In some embodiments, the second cover layer 25 has a thickness ranging from about 1 nanometer to about 7 nanometers, from about 2 nanometers to about 6 nanometers, or from about 3 nanometers to about 5 nanometers. In some embodiments, the first cover layer 23 and the second cover layer 25 are formed independently by one or more of IBD, ALD, PVD, CVD and PECVD.

[0036] The mask may include a compound layer disposed on one or more cover layers. In some embodiments, the compound layer is located between the absorber layer and the cover layer. In some embodiments, the compound layer is located on top of the cover layer. Figure 3 An embodiment of a compound layer 27 disposed on a second cover layer 25 is shown.

[0037] The compound layer can have a compact and dense structure, protecting the underlying capping layer and reflective multilayer stack from ionic or molecular contamination during mask fabrication, mask cleaning processes, and extreme ultraviolet (EUV) exposure processes. The compound layer also provides chemical resistance and extends mask lifetime.

[0038] In some embodiments, the compound layer comprises one or more of a rhodium compound and a ruthenium compound. In some embodiments, the rhodium compound present in the compound layer comprises rhodium oxide (e.g., Rh₂O₃). x O yThe compound layer comprises one or more of rhodium and rhodium alloy oxides, where x ranges from about 1 to about 2 and y ranges from about 1 to about 3.5. In some embodiments, the rhodium alloy oxide comprises at least one inert metal. In some embodiments, the inert metal of the rhodium alloy oxide comprises at least one of niobium, zirconium, and iridium. In some embodiments, the compound layer contains rhodium and one or more non-rhodium elements, and one or more non-rhodium elements are present in the compound layer in an amount of about 25 atomic% to about 75 atomic% based on the total amount of all atoms in the compound layer. In some embodiments, the compound layer comprises one or more compounds that simultaneously contain rhodium and oxygen. In some embodiments, the atomic ratio of rhodium atoms to oxygen atoms (Rh:O) in the compound layer ranges from about 2:1 to about 1:5. In some embodiments, the compound layer comprises RhO, RhO 0.5 RhO 1.5 Rh2O2, Rh2O 2.5 Rh2O3 and Rh2O 3.5 One or more of the following. In some embodiments, the compound layer does not include rhodium nitride. When attempting to form a compound layer on a capping layer comprising or formed of rhodium using nitrogen plasma, the nitrogen plasma may penetrate the capping layer without reacting with the rhodium. Therefore, in some embodiments, a compound layer comprising rhodium nitride is not formed. In some embodiments, the ruthenium compound present in the compound layer includes ruthenium oxide (e.g., Ru). a O b Where a is in the range of about 1 to about 2 and b is in the range of about 1 to about 3.5), ruthenium nitride (e.g., Ru). c N d (where c is in the range of about 1 to about 2 and d is in the range of about 1 to about 3.5), one or more of ruthenium alloy oxides and ruthenium alloy nitrides. In some embodiments, the ruthenium alloy oxide comprises at least one inert metal. In some embodiments, the inert metal of the ruthenium alloy oxide comprises at least one of niobium, zirconium, and iridium.

[0039] Certain forms of ruthenium oxide and ruthenium nitride can naturally form on the capping layer during mask fabrication. However, these naturally formed ruthenium oxides and ruthenium nitrides may have insufficient material density, potentially leading to reduced mask lifetime and inadequate mask protection. However, ruthenium oxide (e.g., the aforementioned Ru...) can be formed under the process conditions discussed below. a O b ) and ruthenium nitride (e.g., the aforementioned Ru) c N dOne or more of these compounds can have a compact structure (e.g., grain size and hexagonal close-packed (HCP) crystal structure >10%) by forming a compound layer on a capping layer including ruthenium and providing protection against the mask.

[0040] In some embodiments, the compound layer is polymorphic. In some embodiments, the compound layer may include portions having an amorphous structure and portions having a crystalline structure. In some embodiments, the compound layer comprises portions having an amorphous structure and portions having an HCP crystalline structure. The structure of the compound layer can be determined by methods such as X-ray diffraction (XRD), transmission electron microscopy (TEM), or scanning transmission electron microscopy (STEM). In some embodiments, the compound layer has more than 10% by volume of HCP structure, while the remaining volume portion of the compound layer is amorphous. In some embodiments, the HCP structure has a unit cell comprising six rhodium atoms and nine atoms of non-rhodium elements (e.g., oxygen). In some embodiments, the HCP structure has a unit cell comprising six ruthenium atoms and nine atoms of non-ruthenium elements (e.g., oxygen).

[0041] In some embodiments, the compound layer comprises less than 5 vol% of a body-centered cubic structure, while in other embodiments, the compound layer does not include a body-centered cubic structure. In some embodiments, the compound layer comprises less than 5 vol% of a face-centered cubic structure, while in other embodiments, the compound layer does not include a face-centered cubic structure. In some embodiments, the portion of the compound layer having a crystalline structure is polycrystalline. In some embodiments, the polycrystalline structure has an average grain size greater than 0 and less than or equal to about 300 nanometers, as determined from TEM images. In some embodiments, the polycrystalline structure has an average grain size ranging from about 10 nanometers to about 50 nanometers. In some embodiments, the lattice constant of the crystal structure is about 5.14. In some embodiments, the compound layer has a thickness of less than about 20 nanometers, or a thickness ranging from about 5 nanometers to about 15 nanometers. In some embodiments, the amorphous portion of the compound layer comprises from about 0 wt% to about 65 wt% of Rh₂O₃, from about 0 wt% to about 30 wt% of RhO, and from 0 wt% to about 5 wt% of Rh element. In some embodiments, the thickness of the compound layer is greater than the thickness of the capping layer directly beneath the compound layer. In other embodiments, the thickness of the compound layer is less than the thickness of the capping layer directly beneath the compound layer.

[0042] A mask may include an absorbent layer disposed on a compound layer and one or more capping layers. For example... Figure 3 As shown, in some embodiments, the absorption layer 30 is disposed on the compound layer 27. The absorption layer 30 is configured to absorb radiation with wavelengths in the extreme ultraviolet radiation range. The absorption layer 30 may be formed as a single layer or multiple layers. The absorption layer 30 can be patterned by removing a portion of the absorption layer. The remaining portion of the patterned absorption layer 30 absorbs light, and the portion of the mask where the absorption layer has been removed can reflect light patterns guided to the photoresist layer. The absorption layer 30 may be patterned to define a semiconductor device integrated circuit (IC) layer. In some embodiments, patterns such as hole structures, line structures, or cavity structures are formed in the absorption layer 30 to expose structures beneath the mask, such as the compound layer or one or more overlay layers. In some embodiments, the absorption layer includes tantalum, boron, tantalum nitride, boron tantalum nitride, titanium, nickel, chromium, ruthenium, platinum, germanium, nickel, lanthanum, molybdenum, palladium, zirconium, nickel silicide, titanium nitride, chromium oxide, aluminum oxide, aluminum-copper alloys, alloys comprising two or more of these, or compounds comprising two or more of these. In some embodiments, the absorbent layer is formed by PVD or sputtering processes.

[0043] Mask 205c may include an anti-reflection layer 35 disposed on the absorption layer 30. In some embodiments, the anti-reflection layer 35 is made of one or more of silicon dioxide, silicon nitride, tantalum borate, tantalum pentoxide, chromium oxide (Cr2O3), or indium tin oxide (ITO). The anti-reflection layer 35 can reduce the reflection of photolithography radiation. Figure 3 An antireflective layer 35 disposed on the absorber layer 30 is shown. The antireflective layer 35 may be patterned together with the absorber layer 30 by removing portions of the antireflective layer and the absorber layer to expose structures beneath the mask, such as a compound layer or one or more capping layers. In some embodiments, the antireflective layer is formed by one or more of ALD, PVD, CVD, and PECVD.

[0044] The mask 205c may include a conductive back-side coating 15 located on the main surface of the substrate 10 opposite to the reflective multilayer stack 20. Figure 3 A conductive back-side coating 15 is shown disposed on a second main surface of substrate 10. The conductive back-side coating 15 can be used to hold the mask 205c by electrostatic chucking during photolithography operations. In one embodiment, the conductive back-side coating 15 is formed of a ceramic compound comprising chromium nitride or any suitable material to electrostatically hold the mask. In some embodiments, the conductive back-side coating 15 comprises chromium nitride (CrN), chromium oxynitride (CrON), or other suitable conductive materials. In some embodiments, the thickness of the conductive back-side coating 15 is in the range of about 20 nanometers to about 100 nanometers. The conductive back-side coating 15 can be formed by CVD, ALD, molecular beam epitaxy (MBE), PVD, pulsed laser deposition, electron beam evaporation, ion beam assisted evaporation, or any other suitable method for forming a thin film. In some embodiments, the conductive back-side coating 15 covers the entire back side of the mask substrate 10. In some embodiments, the conductive back-side coating 15 covers a portion of the back side of the mask substrate 10.

[0045] In some embodiments, the photomask includes a substrate, a reflective multilayer stack disposed on the substrate, one or more capping layers disposed on the reflective multilayer stack, an absorbing layer disposed on the one or more capping layers, and an antireflective layer optionally disposed on the absorbing layer. In some embodiments, the photomask includes a substrate, a reflective multilayer stack disposed on the substrate, one or more capping layers disposed on the reflective multilayer stack, a compound layer disposed on the one or more capping layers, an absorbing layer disposed on the compound layer, and an antireflective layer optionally disposed on the absorbing layer. In some embodiments, the mask 205c includes a pattern formed in the absorbing layer. In some embodiments, the reflective multilayer stack, the compound layer, and the one or more capping layers reflect extreme ultraviolet radiation, while the absorbing layer absorbs extreme ultraviolet radiation.

[0046] like Figure 3 As shown, one or more circuit patterns 50 can be formed on the mask by partially removing the anti-reflective layer 35 and the absorbent layer 30. Furthermore, the mask includes a black border region 70 surrounding the circuit pattern area. In some embodiments, the black border region penetrates beneath the reflective multilayer stack and into the substrate. The circuit pattern and the black border region can be formed by one or more etching operations (e.g., O2 plasma etching).

[0047] Figures 4 to 15 This is a cross-sectional view of an embodiment of a method for manufacturing a mask. It should be understood that... Figures 4 to 15 Additional operations are provided before, during, and after the process shown, and some of the described operations can be replaced or eliminated, and the order of operations / processes can be changed.

[0048] Reference Figure 4 The system provides, forms, or receives a mask substrate 10. In some embodiments, a back-side coating layer 15 is formed or deposited on the back side of the substrate 10. Figure 5 In this process, a reflective multilayer stack 20 is formed or deposited on the front side of the substrate 10. Figure 6 Shown in Figure 5 An embodiment of forming or depositing a first capping layer 23 on a reflective multilayer stack 20 is shown. Figure 7 This shows that a second cover layer 25 is formed or deposited on the first cover layer 23.

[0049] Figure 7 Further illustrated is a plasma treatment 24 performed on the second capping layer 25 according to one embodiment. The plasma treatment 24 involves forming or depositing a compound layer 27 on the second capping layer 25, such as... Figure 8As shown. In some embodiments, the second capping layer 25 is made of a single element. In some embodiments, plasma processing converts a portion of the element constituting the second capping layer 25 into a compound. In some embodiments, plasma processing directs plasma to an exposed capping layer made of an element such as rhodium or ruthenium to form a compound layer such as rhodium oxide or ruthenium oxide. In some embodiments, the power applied by the plasma processing apparatus during plasma processing is in the range of about 100 W to about 800 W. When the applied power is below the above range, plasma processing may not adequately form a compound layer. When the applied power is above the above range, plasma processing may damage the underlying capping layer. In some embodiments, the temperature of the processing chamber of the apparatus during plasma processing is in the range of about 20°C to about 50°C. When the temperature in the chamber is below the above range, the process may not adequately form a compound layer. When the temperature is above the above range, plasma processing may damage the capping layer. In some embodiments, the pressure in the chamber during plasma processing is in the range of about 1 mTorr to about 10 mTorr. When the pressure is below the above range, plasma processing may not adequately form a compound layer. When the pressure is maintained above the aforementioned range, plasma treatment may damage the coating. In some embodiments, it is used... Figure 17 The plasma processing equipment shown is used for plasma processing.

[0050] In some embodiments, plasma processing includes applying power to one or more gas species in a processing chamber to generate plasma. In various embodiments, the gas species include N2, combinations of N2 and Ar, combinations of N2 and He, O2, combinations of O2 and Ar, combinations of O2 and He, combinations of N2 and O2, combinations of N2, O2 and He, or combinations of N2, O2 and Ar. In some embodiments, the formation of the compound layer is due to the decay of a capping layer exposed to plasma energy. In some embodiments, the capping layer provides a portion of the material forming the compound layer during plasma processing. In some embodiments, the capping layer is made of rhodium, and the plasma converts a portion of the rhodium in the capping layer into a compound layer during plasma processing. In embodiments where the capping layer is made of rhodium and the gas supplied to the processing chamber by the plasma processing includes O2, the generated plasma converts a portion of the rhodium in the capping layer into a compound layer comprising rhodium and oxygen.

[0051] exist Figure 9 In this process, the absorbent layer 30 is formed or deposited on the compound layer 27. Figure 10In this embodiment, circuit pattern 50 is formed in the absorber layer 30 to expose a portion of the compound layer 27. In some embodiments, the circuit pattern is formed using a photolithography process, which includes forming a photoresist layer on the absorber layer, patterning the photoresist layer to be exposed to photochemical radiation, developing the exposed photoresist layer to form openings in the photoresist layer, and etching the underlying absorber layer through the openings in the photoresist layer to form the circuit pattern. In some embodiments, the compound layer serves as an etch stop layer during the etching process.

[0052] Figure 11 Another embodiment is shown, wherein the absorber layer 30 is formed on Figure 7 On the second cover layer 25 shown. In Figure 12 In this embodiment, the circuit pattern 50 is formed in the absorber layer 30 to expose a portion of the second capping layer 25. In this embodiment, the second capping layer serves as an etch stop layer when the circuit pattern is formed using an etching process. Figure 13 The plasma treatment 26 of the second capping layer 25 is shown. (Example) Figure 14 As shown, plasma treatment 26 involves forming a compound layer 29 on the second capping layer 25. The compound layer 29 is formed on the area of ​​the second capping layer 25 exposed in the openings of the circuit pattern 50. The compound layer 29 can be processed using plasma treatment equipment and... Figure 7 and Figure 8 The compound layer 27 formed in the process is formed under plasma treatment conditions.

[0053] In some embodiments, the compound layer is located between the cover layer and the absorbent layer, and in one or more regions outside the openings in the absorbent layer. In some embodiments, the compound layer is not located above the cover layer in regions outside the openings in the absorbent layer.

[0054] Figure 15 As shown Figure 13 As shown, another embodiment of forming a compound layer 31 on the second cover layer 25. The compound layer 31 can be used with... Figure 7 and Figure 8The compound layer 27 is formed using plasma processing equipment and plasma processing conditions associated with the formation of the compound layer 27. The compound layer 31 may also extend between the absorber layer 30 and the capping layer 25. In some embodiments, when forming the compound layer 31, one or more of the following values ​​are higher: the applied power of the plasma processing equipment, the temperature in the processing chamber, and the pressure in the processing chamber. In some embodiments, the compound layer extending between the capping layer and the absorber layer is formed by controlling the applied power of the plasma processing equipment within the range of about 100 watts to about 1000 watts during plasma processing. When the applied power is below the above range, plasma processing may not adequately form the compound layer, and the compound layer may not extend between the absorber layer and the capping layer. When the applied power is above the above range, plasma processing may damage the underlying capping layer. In some embodiments, the compound layer extending between the capping layer and the absorber layer is formed by controlling the chamber temperature of the equipment during plasma processing within the range of about 20 degrees Celsius to about 50 degrees Celsius. When the temperature in the chamber is below the aforementioned range, the process may not adequately form the compound layer, and the compound layer may not extend between the absorber and capping layers. When the temperature is above the aforementioned range, plasma treatment may damage the capping layer. In some embodiments, a compound layer extending between the capping and absorber layers can be formed by controlling the pressure in the chamber within the range of about 1 mTorr to about 15 mTorr during plasma treatment. When the pressure is below the aforementioned range, plasma treatment may not adequately form the compound layer, and the compound layer may not extend between the absorber and capping layers. When the pressure is maintained above the aforementioned range, plasma treatment may damage the capping layer. In some embodiments, the processing temperature in the plasma treatment apparatus chamber when forming compound layer 31 is higher than the temperature when forming compound layer 29. In some embodiments, the processing pressure in the plasma treatment apparatus chamber when forming compound layer 31 is higher than the pressure when forming compound layer 29. In some embodiments, the applied power for generating plasma when forming extended compound layer 31 is higher than the power when forming compound layer 29. By increasing the magnitude of one or more processing conditions during plasma treatment, the plasma will become more activated and as Figure 15 As shown, the compound layer 31 extends in the region between the absorber layer 30 and the second capping layer 25 near the opening 50. In some embodiments, the distance L1 from the edge of the absorber layer 30 at the circuit pattern 50 to the end of the compound layer between the absorber layer 30 and the second capping layer 25 is greater than about 0.5 nanometers. In some embodiments, the distance is in the range of about 0.7 nanometers to about 1.5 nanometers. In the region between the absorber layer and one or more capping layers, the thickness of the compound layer 31 can be in the range of about 1 nanometer to about 20 nanometers.

[0055] In various embodiments, compound layers 27, 29, 31 are formed on a ruthenium-containing capping layer using the processing conditions described herein, and compound layers 27, 29, 31 comprise ruthenium oxide (e.g., the aforementioned Ru). a O b ) and ruthenium nitride (e.g., the aforementioned Ru) c N d One or more of the following, the compound layer has a compact structure (e.g., grain size and HCP portion >10% as described herein). Such a compound layer can provide the protection of the mask. In some embodiments, when using the processing conditions described herein, relatively non-compact and naturally formed ruthenium oxide and ruthenium nitride materials will not form in the ruthenium-containing capping layer. In some embodiments, respectively as Figure 10 , Figure 14 and Figure 15 The compound layers 27, 29, and 31 shown, when formed on a ruthenium-containing overlay using the processing conditions described herein, do not include relatively loosely packed and naturally formed ruthenium oxide and ruthenium nitride.

[0056] Figure 16A A cross-sectional view of an embodiment of a mask is shown, which includes an absorbent layer 30 disposed above a compound layer 36. Figure 16B It shows Figure 16A The cross-sectional view of the magnified portion of the mask of region 33 shown. Figure 16C A cross-sectional view of another embodiment of the mask is shown, in which compound layer 36 protects reflective multilayer stack 20 from ion penetration and degradation.

[0057] Figure 17 A plasma processing apparatus 400 according to some embodiments is shown. The apparatus 400 includes a substrate 102 and an outer wall 104, the outer wall including a port for receiving a mask substrate M in a chamber 107. In some embodiments, the mask substrate includes at least one low thermal expansion substrate, a reflective multilayer stack disposed above the low thermal expansion substrate, and one or more overlay layers disposed above the reflective multilayer stack. The apparatus 400 further includes a substrate ladder 106, which includes a base 108, an insulator 111, an insulating substrate 118, a support rod 121, and a bellows assembly 112. The mask substrate M is placed on the base 108, which includes an RF bias and a disk-shaped platform made of aluminum, titanium, or other non-reactive metal. The base 108 is supported and insulated by the insulator 111.

[0058] Insulator 111 is a monolithic insulator, and in some embodiments includes a non-reactive insulating material such as ceramic or quartz. Insulator 111 insulates the sides and bottom of base 108 and directs radio frequency power to the top surface of base 108, and thus through the mask substrate M. Insulator 111 is supported by insulating substrate 118. Support rod 121 supports base 108, insulator 111, and insulating substrate 118, and vertically moves mask substrate M between a release position (where mask substrate M is introduced and removed from chamber 107) and a processing position (where mask substrate M is held during plasma processing). Bellows assembly 112 isolates and surrounds support rod 121 when chamber 107 is under vacuum. Chamber cover 116 covers and seals chamber 107 during plasma processing.

[0059] The substrate support includes a base 108, an insulator 111, an insulating substrate 118, a support rod 121, and a bellows assembly 112, which serves as an RF cathode connected to an RF power supply 124. The chamber 107 also includes one or more deposition shields and cover rings surrounding the various chamber assemblies to prevent unwanted reactions between the assemblies and the process materials.

[0060] To create the plasma required for processing the mask substrate M, an RF coil 128 is provided. The coil 128 is disposed within a resonator housing 130 located above a chamber cover 116 (or lid). The coil 128 is vertically aligned with an outer wall 104 and is powered by an RF coil power supply 132. During plasma processing, RF power is supplied, and a gas suitable for performing the plasma processing (e.g., O2) is introduced through a gas inlet 114. Plasma 136 is generated when the RF coil 128 senses and couples power from the RF coil power supply 132 into the process gas. RF power is then supplied to a chamber 107, causing high voltage and high current to impact the gas within the chamber. When RF power is supplied to chamber 107, the bottom surface of the chamber cover 116 acts as the anode, and the substrate support acts as the cathode. Charged ions are attracted to the substrate support, which carries an opposite charge. These ions react with the exposed overlay of the mask substrate M. In order to establish and maintain the necessary environmental conditions in chamber 107, a pressure control device 138 is connected to chamber 107. The pressure control device 138 is, for example, a turbopump or other similar pump capable of establishing near-vacuum conditions (i.e., chamber pressure in the millitor (mTorr) range).

[0061] Device 400 is controlled by system controller 190, which facilitates the control and automation of device 400 and typically includes a central processing unit (CPU), memory, and support circuitry (or I / O). The CPU can be any form of computer processor used to control various system functions, substrate movement, chamber processes, and supporting hardware (e.g., sensors, robots, motors, etc.) in an industrial setup, and to monitor processes (e.g., substrate support temperature, power supply variables, chamber process time, I / O signals, etc.). Memory is connected to the CPU and can be one or more readily available memory modules, such as random access memory (RAM), read-only memory (ROM), floppy disk, hard disk, or any other form of local or remote digital memory. Software instructions and data can be encoded and stored in memory to instruct the CPU. Support circuitry is also connected to the CPU to support the processor in a conventional manner. Support circuitry includes caches, power supplies, frequency circuits, input / output circuitry systems, subsystems, and the like. A program (or computer instructions) that can be read by system controller 190 determines which tasks will be performed on the substrate. The program is software readable by the system controller 190, containing code for executing and monitoring, performing and controlling movements within the device 400, and tasks related to various process formulation tasks and formulation steps. For example, the system controller 190 includes program code containing a substrate positioning instruction set for operating the substrate support; an airflow control instruction set for operating a flow control valve to set the gas flow rate to the processing chamber 107; a gas pressure control instruction set for operating a throttle valve or gate valve to maintain pressure in the processing chamber 107; a temperature control instruction set for controlling the temperature control system in the substrate support; and a process monitoring instruction set for monitoring the process in the processing chamber 107.

[0062] Figure 18 A flowchart of a method for manufacturing a mask according to some embodiments is shown. The method includes operation 1001, forming a reflective multilayer stack 20 on a substrate 10. The method includes operation 1002, forming capping layers 23, 25 on the reflective multilayer stack. The method further includes operation 1003, subjecting the capping layers to plasma treatment to form a compound layer 27. The method includes operation 1004, forming an absorption layer 30 on the compound layer 27. The method further includes operation 1005, etching openings 50 in the absorption layer to expose the compound layer 27.

[0063] Figure 19 A flowchart of a method for manufacturing a mask according to some embodiments is shown. The method includes operation 2001, etching openings in a mask template. The method includes operation 2002, plasma treating a capping layer 25 exposed in the openings to form compound layers 29, 31 on the capping layer.

[0064] Figure 20 A flowchart of a method for manufacturing a mask according to some embodiments is shown. The method includes operation 3001, forming a reflective multilayer stack 20 on a substrate 10. The method includes operation 3002, forming capping layers 23, 25 on the reflective multilayer stack. The method optionally includes operation 3003, performing plasma treatment on the capping layers 23, 25 to form a compound layer 27 on the capping layers. The method further includes operation 3004, forming an absorption layer 30 on the capping layers 23, 25. The method further includes operation 3005, etching an opening 50 in the absorption layer 30. The method optionally includes operation 3006, performing plasma treatment on the capping layers 23, 25 in the opening to form compound layers 29, 31 on the capping layers.

[0065] Figure 21 A flowchart of a method for manufacturing a semiconductor device according to some embodiments is shown. The method includes operation 4001, directing extreme ultraviolet (EUV) radiation to a mask containing compound layers 27, 29, 31 disposed on capping layers 23, 25 according to embodiments of this disclosure, and then performing operation 4002, reflecting patterned light from the mask onto a photoresist layer disposed on a semiconductor substrate. The EUV-exposed photoresist layer is then developed to form a pattern. The pattern corresponds to an integrated circuit to be formed on the substrate. Additional semiconductor device manufacturing operations may then be performed to obtain the desired semiconductor device. In some embodiments, the desired semiconductor device includes active devices such as diodes, field-effect transistors (FETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar transistors, high-voltage transistors, high-frequency transistors, chip FETs such as nanosheet FETs, fin field-effect transistors (FinFETs), gate-all-around (GAA) FETs, other three-dimensional (3D) FETs, other memory cells, and combinations thereof.

[0066] The compound layer of the mask serves to protect the underlying layers, such as reflective multilayer stacks and capping layers. In some embodiments disclosed herein, the compound layer serves to prevent ions or other small molecules from diffusing into the mask and damaging or contaminating the reflective multilayer stack. In some embodiments disclosed herein, the compound layer also provides general chemical resistance to protect the reflective multilayer stack.

[0067] According to one embodiment, a method of manufacturing a mask includes forming a reflective multilayer stack on a substrate. The method further includes forming a capping layer on the reflective multilayer stack, wherein the capping layer includes at least one of rhodium and ruthenium. The method further includes plasma treating the capping layer to form a compound layer on the capping layer, wherein the compound layer includes at least one of rhodium and ruthenium, and at least one additional element. The method further includes forming an absorption layer on the compound layer. The method further includes etching openings in the absorption layer to expose the compound layer. In one embodiment, the content of the at least one additional element in the compound layer ranges from about 25 atomic% to about 75 atomic% based on the total amount of all atoms in the compound layer. In one embodiment, the compound layer includes rhodium and oxygen. In one embodiment, the ratio of rhodium to oxygen in the compound layer ranges from 2:1 to 1:5. In one embodiment, the capping layer is provided with rhodium during plasma treatment to form the compound layer. In one embodiment, the compound layer includes at least one element having the formula Rh x O y The compound, wherein x ranges from 1 to 2 and y ranges from 1 to 3.5. In one embodiment, the opening comprises a circuit pattern. In one embodiment, the plasma treatment comprises generating at least one of nitrogen plasma or oxygen plasma.

[0068] According to another embodiment, a method of manufacturing a mask includes etching an opening in the mask template. The mask template includes a substrate, a reflective multilayer stack disposed on the substrate, a capping layer disposed on the reflective multilayer stack, wherein the capping layer includes at least one of rhodium and ruthenium, and an absorber layer disposed on the capping layer, wherein the opening exposes the capping layer. The method further includes plasma processing the capping layer to form a compound layer on the capping layer in the opening, wherein the compound layer includes oxygen and at least one of rhodium and ruthenium. In one embodiment, the capping layer provides at least one of rhodium and ruthenium for the compound layer during the plasma processing. In one embodiment, the ratio of rhodium to oxygen in the compound layer ranges from 2:1 to 1:5. In one embodiment, the plasma processing further forms a compound layer in a region between the absorber layer and the capping layer adjacent to the opening. In one embodiment, the compound layer includes at least one having the formula Rh x O y The compounds, wherein x ranges from 1 to 2 and y ranges from 1 to 3.5.

[0069] According to another embodiment, a mask for extreme ultraviolet (EUV) lithography includes a reflective multilayer stack disposed on a substrate. The mask further includes a first capping layer disposed on the reflective multilayer stack; a second capping layer disposed on the first capping layer, wherein the second capping layer includes at least one of rhodium and ruthenium and has a different composition from the first capping layer; an absorption layer disposed on the second capping layer; and an opening formed in the absorption layer and exposing a compound layer disposed on the second capping layer, wherein the compound layer includes at least one of a rhodium compound and a ruthenium compound. In one embodiment, the compound layer is located in a region outside one or more openings between the absorption layer and the second capping layer. In one embodiment, the compound layer extends from the opening into a region adjacent to the opening between the absorption layer and the second capping layer. In one embodiment, the compound layer includes rhodium and oxygen. In one embodiment, the ratio of rhodium to oxygen in the compound layer ranges from 2:1 to 1:5. In one embodiment, the compound layer includes at least one compound having the formula Rh x O y The compound, wherein x ranges from 1 to 2 and y ranges from 1 to 3.5. In one embodiment, the opening comprises a circuit pattern.

[0070] According to another embodiment, a method of manufacturing a semiconductor device includes guiding extreme ultraviolet radiation onto a mask; and reflecting patterned light from the mask onto a photoresist layer disposed on a semiconductor substrate. The mask includes a reflective multilayer stack disposed on the substrate; a capping layer disposed on the reflective multilayer stack, wherein the capping layer includes at least one of rhodium and ruthenium; an absorption layer disposed on the capping layer; and an opening formed in the absorption layer and exposing a compound layer disposed on the capping layer, wherein the compound layer includes at least one of rhodium and ruthenium. In one embodiment, the compound layer further includes at least one additional element other than at least one of rhodium and ruthenium. In one embodiment, the content of the at least one additional element in the compound layer ranges from about 25 atomic% to about 75 atomic% based on the total amount of all atoms in the compound layer. In one embodiment, the compound layer is located between the absorption layer and the capping layer in a region outside the opening. In one embodiment, the compound layer extends from the opening into a region between the absorption layer and the capping layer near the opening. In one embodiment, the compound layer includes rhodium and oxygen. In one embodiment, the ratio of rhodium to oxygen in the compound layer ranges from 2:1 to 1:5. In one embodiment, the compound layer includes at least one element having the formula Rh x O y The compound, wherein x ranges from 1 to 2 and y ranges from 1 to 3.5. In one embodiment, the opening comprises a circuit pattern.

[0071] According to another embodiment, the mask for extreme ultraviolet lithography includes a reflective multilayer stack disposed on a substrate; a capping layer disposed on the reflective multilayer stack, wherein the capping layer includes ruthenium; a compound layer disposed on the capping layer and including ruthenium and oxygen; an absorption layer disposed on the capping layer; and an opening formed in the absorption layer, wherein the compound layer is exposed in the opening. In one embodiment, the compound layer is located between the capping layer and the absorption layer in at least one region outside the opening. In one embodiment, the compound layer is not located on the capping layer in a region outside the opening.

[0072] According to another embodiment, a method of manufacturing a mask includes forming a reflective multilayer stack on a substrate; forming a capping layer on the reflective multilayer stack; performing a plasma treatment on the capping layer to form a compound layer on the capping layer, wherein the compound layer includes oxygen and at least one of rhodium and ruthenium; forming an absorber layer on the capping layer; and etching an opening in the absorber layer. In one embodiment, the plasma treatment of the capping layer is performed after etching the opening. In one embodiment, the plasma treatment of the capping layer forms a compound layer on the capping layer within the opening. In one embodiment, the plasma treatment of the capping layer further forms a compound layer in a region between the capping layer and the absorber layer. In one embodiment, the plasma treatment is performed before forming the absorber layer on the capping layer, and the compound layer is located between the absorber layer and the capping layer.

[0073] The foregoing has outlined the features of several embodiments or examples to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments or examples introduced herein. Those skilled in the art should also recognize that such equivalent constructions should not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to this document without departing from the spirit and scope of this disclosure.

Claims

1. A method for manufacturing a mask, the method comprising: A reflective multilayer stack is formed on the substrate; A capping layer is formed on the reflective multilayer stack, wherein the capping layer comprises at least one of rhodium and ruthenium; The capping layer is subjected to plasma treatment to form a compound layer on the capping layer, wherein the compound layer includes at least one of rhodium and ruthenium, and at least one additional element; An absorption layer is formed on the compound layer; as well as An opening is etched in the absorbent layer to expose the compound layer.

2. The method of claim 1, wherein the content of the at least one additional element in the compound layer ranges from about 25 atomic% to about 75 atomic% based on the total amount of all atoms in the compound layer.

3. The method of claim 1, wherein the compound layer comprises rhodium and oxygen.

4. The method according to claim 3, wherein the ratio of rhodium to oxygen in the compound layer is in the range of 2:1 to 1:

5.

5. The method of claim 4, wherein the capping layer is provided with rhodium during the plasma treatment to form the compound layer.

6. A method for manufacturing a mask, comprising: An opening is etched into a photomask, wherein the photomask comprises: substrate, Reflective multilayer stacks disposed on the substrate A capping layer disposed on the reflective multilayer stack, wherein the capping layer comprises at least one of rhodium and ruthenium, and An absorbent layer disposed on the cover layer, wherein the opening exposes the cover layer; and The capping layer is subjected to plasma treatment to form a compound layer on the capping layer within the opening, wherein the compound layer comprises oxygen and at least one of rhodium and ruthenium.

7. The method of claim 6, wherein the plasma treatment further forms the compound layer in the region between the absorber layer and the capping layer adjacent to the opening.

8. The method of claim 6, wherein the compound layer comprises at least one having the formula Rh x O y Compounds in which x ranges from 1 to 2 and y ranges from 1 to 3.

5.

9. A mask for extreme ultraviolet (EUV) lithography, comprising: Reflective multilayer stacking disposed on a substrate; A first cover layer disposed on the reflective multilayer stack; A second cover layer disposed on the first cover layer, wherein the second cover layer comprises at least one of rhodium and ruthenium and has a different composition from the first cover layer; An absorbent layer disposed on the second cover layer; as well as An opening formed in the absorbent layer exposes a compound layer disposed on the second cover layer, wherein the compound layer includes at least one of a rhodium compound and a ruthenium compound.

10. The mask of claim 9, wherein the compound layer is located between the absorber layer and the second cover layer, and in at least one region outside the opening.

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