Data processing system, data processing method, chip and electronic device

Abstract

The application discloses a data processing system, a data processing method, a chip and electronic equipment, and belongs to the technical field of data processing. The data processing system comprises a main processor, a coprocessor and a storage unit; the main processor and the coprocessor are connected through a kernel channel; the kernel channel is a channel formed by a kernel interface of the main processor and a kernel interface of the coprocessor; the main processor and the coprocessor are also connected with the storage unit respectively; the storage unit stores audio data to be processed; the main processor is used for sending a target instruction to the coprocessor through the kernel channel; the coprocessor is used for receiving the target instruction through the kernel channel, obtaining the audio data to be processed from the storage unit in response to the target instruction, and processing the audio data to be processed. Since the target instruction is transmitted between the main processor and the coprocessor through the kernel channel, the instruction control flow is simpler, and the efficiency of processing the audio data to be processed is improved.

Description

Technical Field

[0001] This application relates to the field of data processing technology, and in particular to a data processing system, data processing method, chip, and electronic device. Background Technology

[0002] With the development of science and technology, people have an increasing demand for audio data processing, and a large number of audio processing chips have appeared on the market.

[0003] Currently, some audio processing chips employ a processor and hardware accelerator solution. Their working principle is as follows: the hardware accelerator acts as an external device with an independent bus. The hardware accelerator's internal configuration registers are mapped to the chip's memory space, while the processor reads and writes control registers via the independent bus to control the hardware accelerator's operation. In this solution, because the processor needs to frequently access the bus to control the hardware accelerator, the instruction control flow is complex, and the coupling between the processor and the hardware accelerator is low, resulting in low efficiency in audio data processing. Summary of the Invention

[0004] To address the problems in the related technologies, embodiments of this application provide a data processing system, a data processing method, a chip, and an electronic device. The technical solution is as follows: In one aspect, this application provides a data processing system, which includes a main processor, a coprocessor, and a storage unit; The main processor and the coprocessor are connected via a kernel channel, which is a channel formed by the kernel interface of the main processor and the kernel interface of the coprocessor; the main processor and the coprocessor are also respectively connected to the storage unit, which stores audio data to be processed. The main processor is used to send a target instruction to the coprocessor through the kernel channel. The target instruction contains the data address of the audio data to be processed. The data address is used to indicate the location of the audio data to be processed in the storage unit. The coprocessor is used to receive the target instruction through the kernel channel, and in response to the target instruction, to retrieve the audio data to be processed from the storage unit, and to process the audio data to be processed.

[0005] In another aspect, this application provides a data processing method applied to a data processing system, the data processing system including a main processor, a coprocessor, and a storage unit, wherein the main processor and the coprocessor are respectively connected to the storage unit, and the storage unit stores audio data to be processed; the method includes: A target instruction is sent through a kernel channel, the target instruction containing the data address of the audio data to be processed; the data address is used to indicate the location of the audio data to be processed in the storage unit; wherein, the kernel channel is a channel formed by the kernel interface of the main processor and the kernel interface of the coprocessor; In response to the target instruction, the audio data to be processed is retrieved from the storage unit and processed.

[0006] In another aspect, this application provides a chip that includes at least one data processing system as described in one of the preceding aspects.

[0007] In another aspect, this application provides an electronic device that includes a data processing system as described in one aspect above, or a chip as described in another aspect above.

[0008] In another aspect, this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the data processing method as described in one of the preceding aspects.

[0009] In another aspect, embodiments of this application provide a computer program product, including a computer program that, when processed and executed, implements the data processing method as described in one of the above aspects.

[0010] In another aspect, embodiments of this application provide an application publishing platform for publishing computer program products, wherein when the computer program products are run on a computer, the computer executes to implement the data processing method as described in one aspect above.

[0011] The beneficial effects of the technical solutions provided in this application include at least the following: The data processing system provided in this application includes a main processor, a coprocessor, and a storage unit. The main processor and coprocessor are connected via a kernel channel, which is a channel formed by the kernel interfaces of the main processor and the coprocessor. Both the main processor and coprocessor are also connected to the storage unit, which stores audio data to be processed. The main processor sends a target instruction to the coprocessor via the kernel channel. The target instruction contains the data address of the audio data to be processed, which indicates the location of the audio data in the storage unit. The coprocessor receives the target instruction via the kernel channel and, in response to the target instruction, retrieves the audio data to be processed from the storage unit and processes the audio data. Because the main processor and coprocessor transmit the target instruction via the kernel channel, and the coprocessor processes the audio data based on this target instruction, the instruction control process does not require a separate bus, simplifying the instruction control flow and increasing the coupling between the main processor and coprocessor, thereby improving the efficiency of processing the audio data. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a schematic diagram of the structure of a data processing system provided in an exemplary embodiment of this application; Figure 2 This is a schematic diagram of the structure of another data processing system provided in an exemplary embodiment of this application; Figure 3 This application relates to an exemplary embodiment. Figure 2 A schematic diagram of a data transmission flow within a buffer area; Figure 4 This is a schematic diagram of the core architecture of a data processing system provided in an exemplary embodiment of this application; Figure 5 This application relates to an exemplary embodiment. Figure 4 A schematic diagram of the data processing flow of a data processing system; Figure 6 This is a schematic flowchart of a data processing method provided in an exemplary embodiment of this application; Figure 7 This is a schematic diagram of the structure of an electronic device provided in an exemplary embodiment of this application. Detailed Implementation

[0014] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0015] In this article, "multiple" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0016] The solution provided in this application can be used in real-world scenarios where people use electronic devices to process audio data in their daily lives. To facilitate understanding, some terms and application scenarios involved in the embodiments of this application will be briefly introduced below.

[0017] Direct Memory Access (DMA) is a technology that allows external devices or dedicated controllers to read and write data directly to the system's main memory without relying on the intervention of the Central Processing Unit (CPU).

[0018] Instruction Set Architecture (ISA) is a set of fundamental interface specifications agreed upon between computer hardware (processor) and software (compiler, operating system). It defines the instruction set, registers, data types, memory addressing modes, etc., that software can use.

[0019] System on Chip (SoC): An integrated circuit design approach that integrates all the key functional components of a complete electronic system or product onto a single chip.

[0020] RISC-V is an open, modular, and extensible instruction set architecture (ISA) that supports custom extension instructions.

[0021] The I2S (Inter-IC Sound) interface is a serial bus standard specifically designed for transmitting audio data between digital audio devices. It separates clock signals from data signals, effectively avoiding audio distortion, and is a core interface for connecting chips such as CPUs and DSPs.

[0022] With the development of science and technology, various electronic devices have appeared in people's daily lives, and people can use electronic devices for entertainment, learning, and so on. Among them, playing audio data is a basic function of most electronic devices. However, as people's requirements for sound quality and sound latency continue to increase, the need for audio data processing is growing. Electronic devices need to be equipped with corresponding audio processing chips to realize various optimization functions.

[0023] For example, common embedded audio processing chips mainly use general-purpose processors and digital signal processors (DSPs). In solutions using general-purpose processors, the operation relies entirely on software programming, with algorithms for processing audio data executed serially on a single processor. While general-purpose processors offer flexible algorithm programming, they are not specifically designed for audio data processing. Most of their instruction sets and hardware architecture are geared towards a wide range of general computing tasks. In actual audio data processing, these instruction sets do not easily interact internally, resulting in low instruction efficiency and low data transfer efficiency. Furthermore, when faced with complex audio data, their algorithm processing performance is insufficient. Forcing a general-purpose processor to operate at high clock speeds will further increase system power consumption and reduce system energy efficiency.

[0024] In the DSP processor-based approach, the principle is to use a dedicated DSP processor as the core, combined with peripheral circuits such as audio and clock circuits, to form an integrated audio processing unit. Real-time processing is achieved through the DSP's hardware architecture. While this approach offers faster processing speeds compared to using general-purpose processors and can handle more complex audio data more flexibly, DSP processors typically employ closed or dedicated instruction set architectures. Their software development toolchains are not standardized, resulting in a closed ecosystem and high costs for the entire porting and development process, making it difficult to adapt to the demands of rapidly updating audio algorithms.

[0025] Currently, to mitigate the drawbacks of the two aforementioned solutions, some manufacturers produce audio processing chips that combine a processor and a hardware accelerator. The working principle is as follows: the hardware accelerator acts as an external device with an independent bus. Its internal configuration registers are mapped to the chip's memory space, while the processor reads and writes control registers via the independent bus to control the hardware accelerator's operation. In this solution, because the processor needs to frequently access the bus to control the hardware accelerator, the instruction control flow is complex, and the coupling between the processor and the hardware accelerator is low, resulting in low efficiency in audio data processing.

[0026] To address the problems in related technologies, simplify instruction control in the audio data processing process, and improve the efficiency of processing audio data, this application provides a data processing system. This system allows the main processor and coprocessor to be connected via a kernel channel, enabling target instructions to be transmitted through the kernel channel without requiring a separate bus. This increases the coupling between the main processor and coprocessor, thereby improving the internal interaction efficiency of the data processing system.

[0027] Please refer to Figure 1 This illustrates a schematic diagram of the structure of a data processing system provided in an exemplary embodiment of this application. Figure 1 As shown, the data processing system 100 includes a main processor 101, a coprocessor 102, and a storage unit 103; The main processor 101 and the coprocessor 102 are connected through a kernel channel, which is a channel formed by the kernel interface of the main processor 101 and the kernel interface of the coprocessor 102. The main processor 101 and the coprocessor 102 are also connected to a storage unit 103, which stores audio data to be processed.

[0028] When it is necessary to process the audio data to be processed, the main processor 101 inside the data processing system 100 can send a target instruction to the coprocessor 102 through the kernel channel. This target instruction contains the data address of the audio data to be processed, which indicates the location of the audio data in the storage unit 103. Correspondingly, the coprocessor 102 can receive the target instruction through the kernel channel and, in response to the target instruction, retrieve the audio data to be processed from the storage unit 103 and process the audio data. In other words, within the data processing system 100, the main processor 101 sends a target instruction to the coprocessor 102 through the kernel channel, and the coprocessor 102 receives and responds to the target instruction, executing the task of processing the audio data to be processed.

[0029] Optionally, after receiving the target instruction, the coprocessor 102 can retrieve the audio data to be processed from the storage unit 103 according to the data address of the audio data to be processed contained in the target instruction, and perform the task of processing the audio data to be processed. That is, in response to the target instruction, the coprocessor can retrieve the audio data to be processed from the storage unit 103 according to the data address of the audio data to be processed contained in the target instruction, and select its own internal processing algorithm to process it, thereby completing the processing of the audio data to be processed.

[0030] Optionally, the kernel interface of the main processor 101 is equivalent to the sending end of the target instruction, and the kernel interface of the coprocessor is equivalent to the receiving end of the target instruction. When the target instruction is generated inside the main processor 101, the main processor 101 can recognize the target instruction and send it directly through its own kernel interface. The kernel interface on the side of the coprocessor 102 can receive the target instruction, thereby realizing the transmission of the target instruction in the kernel channel. Optionally, in this scheme, the main processor 101 can be a processor with a RISC-V architecture, which can integrate custom RISC-V instructions.

[0031] Optionally, the coprocessor 102 may integrate processing algorithms for processing the audio data to be processed. For example, the processing algorithms include, but are not limited to, core algorithms such as decoding, encoding, filtering, mixing, noise reduction, echo cancellation, sample rate conversion, real-time stream management, and Fast Fourier Transform (FFT).

[0032] Optionally, the target instruction sent by the main processor 101 to the coprocessor 102 can be a custom RISC-V instruction. After receiving the target instruction through its own kernel interface, the coprocessor 102 can respond and execute the processing of the audio data to be processed. Optionally, developers can create various functional RISC-V custom instructions for the main processor 101. The main processor 101 selects which RISC-V custom instruction (i.e., the target instruction) to send to the coprocessor 102 through the kernel channel based on actual needs, realizing the process of directly issuing tasks to the coprocessor 102, making the instruction interaction between the two closer and the control efficiency higher.

[0033] In summary, the data processing system provided in this application includes a main processor, a coprocessor, and a storage unit. The main processor and coprocessor are connected via a kernel channel, which is a channel formed by the kernel interfaces of the main processor and the coprocessor. Both the main processor and coprocessor are also connected to the storage unit, which stores audio data to be processed. The main processor sends a target instruction to the coprocessor via the kernel channel. The target instruction contains the data address of the audio data to be processed, which indicates the location of the audio data in the storage unit. The coprocessor receives the target instruction via the kernel channel and, in response, retrieves the audio data to be processed from the storage unit and processes the audio data. Because the main processor and coprocessor transmit the target instruction via the kernel channel, and the coprocessor processes the audio data based on this target instruction, the instruction control process does not require a separate bus, simplifying the instruction control flow and increasing the coupling between the main processor and coprocessor, thereby improving the efficiency of processing the audio data.

[0034] The following section describes the above-mentioned data processing system in terms of its specific components. Figure 1 The proposed solutions are illustrated with examples. Please refer to them. Figure 2 This illustrates a schematic diagram of the structure of another data processing system provided in an exemplary embodiment of this application. Figure 2 As shown, the data processing system 200 includes a main processor 201, a coprocessor 202, and a storage unit 203; The main processor 201 and the coprocessor 202 are connected through a kernel channel, which is a channel formed by the kernel interface of the main processor 201 and the kernel interface of the coprocessor 202. The main processor 201 and the coprocessor 202 are also connected to the storage unit 203, which stores the audio data to be processed.

[0035] When it is necessary to process the audio data to be processed, the main processor 201 inside the data processing system 200 can send a target instruction to the coprocessor 202 through the kernel channel. This target instruction contains the data address of the audio data to be processed, which indicates the location of the audio data in the storage unit 203. Correspondingly, the coprocessor 202 can receive the target instruction through the kernel channel and, in response to the target instruction, retrieve the audio data to be processed from the storage unit 203 and process the audio data. In other words, within the data processing system 200, the main processor 201 sends a target instruction to the coprocessor 202 through the kernel channel, and the coprocessor 202 receives and responds to the target instruction, executing the task of processing the audio data to be processed.

[0036] Optionally, before the main processor 201 sends the target instruction, the main processor 201 also obtains the data address of the audio data to be processed and generates the target instruction based on the data address of the audio data to be processed. That is, before the main processor 201 sends the target instruction, it obtains the data address of the audio data to be processed and generates the target instruction to be sent based on the data address of the audio data to be processed.

[0037] Optionally, in the method where the target instruction only contains the target instruction, after the main processor sends the target instruction to the coprocessor, the coprocessor can process the audio data to be processed according to its internal default processing algorithm. This default processing algorithm can be pre-set in the coprocessor by the developers.

[0038] In one possible implementation, the target instruction contains not only the data address of the audio data to be processed, but also a parameter address. This parameter address is used to indicate the location of the target parameter value required by the algorithm parameters corresponding to the processing algorithm adopted by the coprocessor in the storage unit 203. Accordingly, the main processor 201 needs to obtain the parameter address in addition to the corresponding data address, and then generate the required target instruction.

[0039] Taking the main processor 201 as a processor with a RISC-V architecture and the target instruction as a custom RISC-V instruction as an example, when the coprocessor 202 needs to use a filtering algorithm to process the audio data to be processed, the main processor 201 needs to prepare the audio data to be processed and the filter coefficients. If the location of the audio data to be processed in the storage unit 203 is represented by src_addr and the location of the filter coefficients in the storage unit 203 is represented by coef_addr, the main processor 201 needs to obtain data including src_addr and coef_addr before generating the target instruction. The target instruction generated by the main processor 201 based on the obtained data address and parameter address of the audio data to be processed can be as follows: FIR_FILTER [src_addr], [coef_addr]. Optionally, the inclusion of the data address and parameter address of the audio data to be processed in the target instruction is also exemplary. In practical applications, other parameters may also be included, such as the length of the audio data to be processed, as long as the coprocessor 202 can accurately run the corresponding processing algorithm through the target instruction. This solution does not limit the specific number of contents contained in the target instruction.

[0040] Optionally, the aforementioned storage unit 203 includes a storage area 204 and a cache area 205; during the process of the main processor 201 preparing the audio data to be processed, the main processor 201 is also used to move the audio data to be processed from the storage area 204 to the cache area 205 according to the time sequence of the audio data to be processed; when obtaining the data address of the audio data to be processed, the main processor 201 is specifically used to obtain the data address of the audio data to be processed after it has been moved from the storage area 204 to the cache area 205.

[0041] For example, under normal circumstances, the data processing system 200 stores the acquired audio data in storage area 204. When specific audio data needs to be processed (i.e., audio data to be processed), the main processor 201 controls the movement of this audio data from storage area 204 to cache area 205. The audio data to be processed in cache area 205 can then wait for the coprocessor 202 to retrieve it after receiving the target instruction and perform the corresponding processing. In other words, this solution divides storage unit 203 into storage area 204 and cache area 205. Storage area 204 is used for normal storage of various data (including audio data), while cache area 205 is used when needed. When audio data to be processed needs to be moved from storage area 204 to cache area 205, this facilitates the coprocessor 202 in quickly retrieving the audio data and improves the efficiency of processing the audio data.

[0042] For example, storage area 204 stores various types of data. When the data processing system 200 needs to process audio data 1, the main processor 201 selects the necessary parameter values ​​for the processing algorithm and moves the audio data 1 and the selected parameter values ​​from storage area 204 to cache area 205. When the main processor 201 obtains the data address of the audio data to be processed, it obtains the data address corresponding to the audio data to be processed already stored in cache area 205, and then generates the target instruction.

[0043] Taking the case where the coprocessor 202 needs to use a filtering algorithm to process the audio data to be processed as an example, the main processor 201 needs to prepare the audio data to be processed and the filter coefficients. Let S_addr1 represent the location of audio data 1 in storage area 204, and L_addr1 represent the location of the parameter value of the filter coefficient selected by the main processor 201 in storage area 204. Before generating the target instruction, the main processor 201 will move audio data 1 and the parameter value of the selected filter coefficient from storage area 204 to cache area 205. Let S_addr2 represent the location of the main processor... 201 moves the audio data to a position after buffer area 205. L_addr2 indicates that the main processor 201 moves the parameter values ​​of the selected filter coefficients to a position after buffer area 205. The main processor 201 can obtain the data address of the audio data to be processed after being moved from storage area 204 to buffer area 205: S_addr2, and the parameter address after being moved from storage area 204 to buffer area 205: L_addr2. The target instruction generated by the main processor 201 based on the obtained data address and parameter address of the audio data to be processed can be: FIR_FILTER [S_addr2], [L_addr2], length. Optionally, in the above Figure 2 In the data processing system 200, a bus matrix 206 is also included. The main processor 201 is connected to the storage unit 203 via the bus matrix 206. The bus matrix 206 is also connected to an external device 207, which is used to move the audio data to be processed from the storage area to the cache area according to the time sequence of the audio data to be processed. When the main processor 201 moves the audio data to be processed from the storage area to the cache area, the main processor 201 specifically controls the operation of the external device through the bus matrix. That is to say, the process of the main processor 201 moving the audio data to be processed from the storage area to the cache area is as follows: the main processor 201 interacts with the external device 207 through the bus matrix 206 to ensure that the external device 207 works normally. In fact, the main body executing the data movement is the external device 207. The main processor 201 indirectly realizes the movement of the audio data to be processed by controlling the external device 207.

[0044] Optionally, in practical applications, the audio data to be processed is usually a data set containing multiple consecutive frames. To ensure the temporal continuity of the audio data, the main processor 201 can control the external device 207 to move the audio data to be processed from the storage area to the cache area according to the temporal order of the audio data (i.e., the order of each frame). For example, the external device 207 may include a DMA unit, and the main processor 201 can control the DMA unit in the external device 207 to work through the bus matrix 206, with the DMA unit performing the work of moving the audio data to be processed.

[0045] Optionally, the bus matrix 206 is a parallel on-chip network that allows multiple master devices (such as the master processor, coprocessor, and DMA in this solution) to access multiple slave devices (such as the memory units in this solution) simultaneously.

[0046] In one possible implementation, the aforementioned cache area 205 is configured with N buffer blocks, where N is an integer greater than or equal to 2; each buffer block is used to store one frame of audio data to be processed. When moving the audio data to be processed from the storage area to the cache area, the main processor 201 is specifically used to move each frame of audio data to be processed from the storage area to the N buffer blocks; when retrieving the audio data to be processed from the storage unit 203 in response to the target instruction, and when processing the audio data to be processed, the coprocessor 202 is specifically used to retrieve each frame of audio data to be processed sequentially from the N buffer blocks in response to the target instruction, and process each frame of audio data to be processed.

[0047] In other words, to facilitate the storage of each frame of audio data to be processed, N buffer blocks can be set up in the buffer area 205, and each buffer block can hold one frame of audio data to be processed. The main processor 201 can move the audio data to be processed from the storage area 204 to the N buffer blocks in the time sequence of each frame. For example, N=5, which are buffer block one, buffer block two... buffer block five. For the first to fifth frames of audio data to be processed in the storage area 204, the main processor 201 can move the first frame of audio data to be processed to buffer block one, move the second frame of audio data to be processed to buffer block two, and so on, moving the first five frames of audio data to be processed to the various buffer blocks in the buffer area 205. Based on the above target instructions, the coprocessor 202 can extract each frame of audio data to be processed from these five buffer blocks in sequence and process it.

[0048] It should be noted that when the target instruction includes the data address and parameter address of the audio data to be processed, for the target parameter value that needs to be moved from storage area 204 to cache area 205, the main processor 201 can simultaneously move the target parameter value into cache area 205 while moving the audio data to be processed from storage area 204 to cache area 205. For example, when moving the audio data to be processed in the first frame to buffer block one, the target parameter value can also be carried in the audio data to be processed in the first frame, thus moving the target parameter value into buffer block one as well. In addition, for the above-mentioned scheme of using bus matrix 206 to control external device 207, the moving operation here can also be implemented by the DMA unit in external device 207, which will not be elaborated here.

[0049] Optionally, taking N=2 as an example, in this scheme, when retrieving the audio data to be processed from storage unit 203 in response to the target instruction, and processing the audio data to be processed, the coprocessor 202 is specifically used to, in response to the target instruction, retrieve the audio data to be processed from another buffer block while the main processor 201 is moving the audio data to be processed of the (X+1)th frame into one of the buffer blocks, and process the audio data to be processed of the Xth frame, where X is an integer greater than or equal to 1. For example, in this implementation, while the main processor 201 is moving the audio data to be processed of the second frame into one of the buffer blocks, the target instruction for processing the audio data to be processed of the first frame has already been sent to the coprocessor 202. In response to this target instruction, the coprocessor 202 retrieves the audio data to be processed of the first frame from another buffer block.

[0050] Optionally, the coprocessor 202 is also used to write the processing result into the target buffer block. The processing result is obtained by the coprocessor 202 processing the audio data to be processed in the Xth frame. The target buffer block is a buffer block in the buffer area 205 that stores the audio data to be processed in the Xth frame. The main processor 201 is also used to output the processing result and move the audio data to be processed in the (X+2)th frame into the target buffer block after the coprocessor 202 writes the processing result into the target buffer block.

[0051] For example, if there are two buffer blocks (buffer block A and buffer block B) in buffer area 205, the main processor 201 controls the DMA unit in external device 207 to move the first frame of audio data to be processed to buffer block A, and the DMA unit moves the second frame of audio data to be processed to buffer block B. After the DMA unit completes the movement of the first frame of audio data to be processed to buffer block A, the main processor 201 can generate a corresponding target instruction and send it to the coprocessor 202 through the kernel channel. The coprocessor 202 responds to the target instruction, retrieves the first frame of audio data to be processed from buffer block A, and processes it. While the coprocessor 202 is processing the first frame (i.e., X=1) of audio data, the DMA unit can continue to move the second frame (i.e., X+1) of audio data to be processed to buffer block B.

[0052] After the coprocessor 202 finishes processing the audio data of the first frame, it can write the processing result into buffer block A (i.e., the target buffer block at this time). After the coprocessor 202 writes the processing result into buffer block A, the main processor 201 can also output the processing result and let the DMA unit continue to move the audio data of the third frame (i.e., X+2) into buffer block A.

[0053] In one possible implementation, after each processing result is written to the target buffer block, the coprocessor 202 can set a status flag to a target value. This target value indicates that the coprocessor 202 has completed processing the audio data to be processed in a buffer block. The main processor 201 can periodically or in real-time monitor this status flag to promptly understand whether the coprocessor 202's processing is complete. For example, the status flag can be 0 or 1. When it is 1, it indicates that the coprocessor 202 has completed processing the audio data to be processed in a buffer block; when it is 0, it indicates that the coprocessor 202 has not yet obtained any processing results. After the coprocessor 202 completes processing the first frame of audio data to be processed, it writes the obtained processing result to the target buffer block and sets the status flag to 1. When the main processor 201 detects that the status flag is 1, it outputs the processing result and allows the DMA unit to continue moving the third frame of audio data to be processed into the target buffer block.

[0054] Optionally, in addition to waiting for the main processor 201 to monitor the status flag set by the coprocessor 202, the coprocessor 202 can also actively send the value of the status flag to the main processor 201 through the kernel channel, so that the main processor 201 can know its own processing status.

[0055] Optionally, the external device 207 may also include an I2S unit. The main processor 201 may output the processing result in the following way: control the DMA operation in the external device 207 through the bus matrix 206, and send the processing result from the target buffer block to the I2S unit to realize data output.

[0056] Please refer to Figure 3 This illustrates an exemplary embodiment of the present application relating to Figure 2 A schematic diagram illustrating the data transmission flow within a buffer area. (For example...) Figure 3 As shown, the buffer includes a first buffer block 301 and a second buffer block 302. Within the first frame 303, the main processor 201 can control the DMA unit to move the audio data to be processed in the first frame into the first buffer block 301. After the DMA unit completes the transfer of the audio data to be processed in the first frame into the first buffer block 301, the main processor 201 can generate a corresponding target instruction and send it to the coprocessor 202 through the kernel channel. The coprocessor 202, in response to the target instruction, retrieves the audio data to be processed in the first frame from the first buffer block 301 and processes it. During the processing of the audio data to be processed in the first frame by the coprocessor 202, the DMA unit can continue to move the audio data to be processed in the second frame into the second buffer block 302. That is, the second frame includes both the step of the coprocessor 202 processing the audio data to be processed in the first frame and the step of the DMA unit moving the audio data to be processed in the second frame into the second buffer block 302.

[0057] Optionally, in the above Figure 3 When entering the third frame, if the coprocessor 202 has completed processing the audio data to be processed in the first frame in the first buffer block 301, after writing the processing result into the first buffer block 301, the main processor 201 can transmit the processing result to the I2S unit for output, and allow the DMA unit to continue moving the audio data to be processed in the third frame into the first buffer block 301. At this time, relative to the time of the second frame, the DMA unit has also completed moving the audio data to be processed in the second frame into the second buffer block 302. The main processor 201 can also generate the corresponding target instruction and send it to the coprocessor 202 through the kernel channel. The coprocessor 202 responds to the target instruction, obtains the audio data to be processed in the second frame in the second buffer block 302, and processes it.

[0058] Optionally, in the above Figure 3When entering the fourth frame, if the coprocessor 202 has completed processing the audio data to be processed in the second frame in the second buffer block 302, after writing the processing result into the second buffer block 302, the main processor 201 can transmit the processing result to the I2S unit for output, and allow the DMA unit to continue moving the audio data to be processed in the fourth frame into the second buffer block 302. At this time, relative to the time of the third frame, the DMA unit has also completed moving the audio data to be processed in the third frame into the first buffer block 301. The main processor 201 can also generate the corresponding target instruction and send it to the coprocessor 202 through the kernel channel. The coprocessor 202 responds to the target instruction, obtains the audio data to be processed in the third frame in the first buffer block 301, and processes it. In this way, based on the pipeline mechanism of the two buffer blocks, the audio data to be processed can be processed continuously like on a conveyor belt, with seamless connection between each frame.

[0059] Optionally, if the data processing system 200 further includes a bus matrix 206, the coprocessor 202 is also connected to the storage unit 203 via the bus matrix 206. When retrieving audio data to be processed from the storage unit 203 in response to a target instruction, and when processing the audio data to be processed, the coprocessor is specifically used to retrieve the audio data to be processed from the storage unit 203 via a first channel or a second channel in response to the target instruction, and to process the retrieved audio data to be processed. The first channel is the channel through which the coprocessor is connected to the storage unit via the bus matrix, and the second channel is the channel through which the coprocessor is directly connected to the storage unit 203 without using the bus matrix.

[0060] In other words, in the above Figure 2 In this configuration, the coprocessor 202 and the storage unit 203 are connected not only directly but also indirectly via a bus matrix 206. Upon receiving a target instruction, the coprocessor can select either the first or second channel to retrieve the required audio data from the storage unit 203. In one possible implementation, the generated target instruction may also include channel parameters. If the channel parameters instruct the coprocessor 202 to access the data directly, the second channel is selected to retrieve the audio data; if the channel parameters instruct the coprocessor 202 to access the data indirectly, the first channel is selected.

[0061] Optionally, when the coprocessor needs to write the processing result, it can also choose the first channel or the second channel, which will not be elaborated here.

[0062] Optionally, if the target instruction includes the data address and parameter address of the audio data to be processed, when processing the audio data to be processed, the coprocessor 202 is specifically used to obtain the audio data to be processed from the storage unit 203 according to the data address included in the target instruction; the coprocessor 202 is also specifically used to obtain the target parameter value required by the algorithm parameter corresponding to the processing algorithm from the storage unit 203 according to the parameter address included in the target instruction; the coprocessor 202 is also specifically used to adjust the algorithm parameter corresponding to the processing algorithm to the target coefficient value, and process the audio data to be processed according to the adjusted processing algorithm. That is, after receiving the target instruction, the coprocessor 202 will obtain the audio data to be processed from the storage unit 203 according to the data address included in the target instruction; and obtain the target parameter value required by the algorithm parameter corresponding to the processing algorithm from the storage unit 203 according to the parameter address included in the target instruction; the coprocessor 202 will adjust the algorithm parameter corresponding to the processing algorithm to the target coefficient value, and then process the audio data to be processed according to the adjusted processing algorithm.

[0063] For example, taking a filtering algorithm as an example, the algorithm parameters corresponding to this filtering algorithm are filter coefficients. The filter coefficient selected by the main processor 201 is p (i.e., the required target coefficient value is p). In the generated target instruction, the parameter address included is the location of the filter coefficient p in the storage unit 203. The coprocessor 202 can obtain p from the storage unit 203 according to this parameter address, adjust the filter coefficient corresponding to the filtering algorithm to p, and then perform filtering processing on the audio data to be processed.

[0064] In one possible implementation, the coprocessor 202 includes at least two processing algorithms. When adjusting the algorithm parameters corresponding to the processing algorithms to the target coefficient values, the coprocessor is further specifically used to adjust the algorithm parameters of the processing algorithm corresponding to the target instruction or the parameter address contained in the target instruction to the target coefficient values. Optionally, in this solution, different custom instructions can be designed for different processing algorithms. The coprocessor 202 can identify which processing algorithms need to be used by recognizing the target instruction or the parameter address contained in the target instruction. For example, for a method using a filtering algorithm, the parameter address may include a "coef" field. If the coprocessor 202 recognizes that the parameter address includes a "coef" field, it knows that it needs to use a filtering algorithm for processing. Therefore, when adjusting the algorithm parameters corresponding to the processing algorithms to the target coefficient values, it directly adjusts the filter coefficients of the filtering algorithm.

[0065] If other algorithms, such as noise reduction algorithms, are required, a recognizable field corresponding to the noise reduction algorithm can be added to the parameter address included in the target instruction. If the coprocessor 202 recognizes that the parameter address also contains a recognizable field corresponding to the noise reduction algorithm, it knows that it also needs to use a noise reduction algorithm for processing. Therefore, when adjusting the algorithm parameters corresponding to the processing algorithm to the target coefficient value, the algorithm parameters of the noise reduction algorithm also need to be adjusted. Similarly, in this solution, the coprocessor 202 can simultaneously use multiple algorithms to process the audio data to be processed.

[0066] The above example demonstrates how coprocessor 202 identifies the appropriate processing algorithm by recognizing partial fields of the parameter addresses contained in the target instruction. In practical applications, corresponding fields can also be added directly to the name of the target instruction, allowing coprocessor 202 to identify the target instruction and determine the appropriate processing algorithm. For example, target instruction one might use a filtering algorithm, target instruction two might use a filtering algorithm combined with a noise reduction algorithm, and so on. These details will not be elaborated upon here.

[0067] In one possible implementation, the number of coprocessors 202 can be greater than or equal to 2. During the design, the main processor 201 controls the processing order of the multiple coprocessors 202, allowing the multiple coprocessors 202 to process the audio data to be processed in the storage unit 203 simultaneously, and to re-integrate the processing results according to the time order of the audio data to be processed, and output the processing results in a timely manner, so as to improve the overall processing efficiency.

[0068] In summary, the data processing system provided in this application includes a main processor, a coprocessor, and a storage unit. The main processor and coprocessor are connected via a kernel channel, which is a channel formed by the kernel interfaces of the main processor and the coprocessor. Both the main processor and coprocessor are also connected to the storage unit, which stores audio data to be processed. The main processor sends a target instruction to the coprocessor via the kernel channel. The target instruction contains the data address of the audio data to be processed, which indicates the location of the audio data in the storage unit. The coprocessor receives the target instruction via the kernel channel and, in response, retrieves the audio data to be processed from the storage unit and processes the audio data. Because the main processor and coprocessor transmit the target instruction via the kernel channel, and the coprocessor processes the audio data based on this target instruction, the instruction control process does not require a separate bus, simplifying the instruction control flow and increasing the coupling between the main processor and coprocessor, thereby improving the efficiency of processing the audio data.

[0069] In addition, in this solution, key computing and transmission units such as the buffer area, bus matrix, and coprocessor are always busy during data processing. Moreover, the entire system divides the continuous audio stream into continuous data frames for processing, and the three stages of data transfer, core computing, and result output are completely overlapped in time to form a pipeline. This ensures that the computing and input / output times are completely overlapped, eliminating the bottleneck of waiting for data transfer in traditional solutions.

[0070] In addition, the design of a double-buffered block mechanism in the cache area ensures that while the coprocessor is processing the audio data to be processed in the Mth frame (M is an integer greater than or equal to 2), the DMA unit is already moving the audio data to be processed in the M+1th frame in parallel, and the main processor is scheduling the output of the processed result of the M-1th frame. This deep pipeline ensures the continuous saturation utilization of hardware resources (DMA unit, coprocessor, bus matrix) and maximizes the throughput of the entire system.

[0071] Below, we will discuss the above from the perspective of the core architecture layer of the data processing system. Figure 2 The illustrated embodiments are provided as examples. Please refer to them. Figure 4 This illustrates a schematic diagram of the core architecture of a data processing system provided in an exemplary embodiment of this application. Figure 4 As shown, the data processing system 400 includes a general control layer 401, a hardware acceleration layer 402, and a data retrieval layer 403.

[0072] The control general layer 401 mainly includes the main processor. Figure 4 In this context, the main processor can be a RISC-V processor. Its primary functions are: running the operating system or scheduler, handling general tasks such as protocol stack, user interaction, and system control. It is also responsible for triggering and coordinating the processing of audio data to be processed.

[0073] The hardware acceleration layer 402 mainly includes a co-processor, and the control general layer 401 and the hardware acceleration layer 402 are connected through a kernel channel. The main function of the hardware acceleration layer 402 is to integrate the hardware logic corresponding to various algorithms (such as filtering, FFT, and encoding / decoding core operations) for processing the audio data to be processed. The hardware acceleration layer 402 can receive tasks directly from the control general layer 401 through the kernel channel, achieving close interaction of instruction sets. Since the co-processor in this scheme is not connected to a slow, independent bus, but rather serves as a functional extension of the main processor, it ensures real-time response and high bandwidth to the target instructions issued by the main processor.

[0074] The data access layer 403 mainly includes a bus matrix, storage units, and external devices. The main processor in the general control layer 401 can control external devices through the bus matrix, while the storage units can share / access internally stored data with other master devices through the bus matrix. The storage units may contain random access memory (RAM), which can be divided into a cache area called DATA MEM (Data Memory). DATA MEM is used to temporarily store data required by the program during runtime in the data processing system. In other words, the other storage areas in RAM besides DATA MEM can be used as described above. Figure 2 The storage area in the example, and DATA MEM can be used as the above. Figure 2 The cache area in the example.

[0075] Optionally, the external device also includes an I2S unit and a DMA unit. The DMA unit can operate independently, continuously performing data transfer between the I2S unit and the DATA MEM in the background, and notifying the main processor of the transfer completion via interrupts or flags. The I2S unit can be used for input / output audio streams.

[0076] Please refer to Figure 5 This illustrates an exemplary embodiment of the present application relating to Figure 4 A schematic diagram of the data processing flow of a data processing system. For example... Figure 5 As shown, the data processing flow may include the following steps: Step 501: The main processor configures the audio data to be processed and the algorithm parameters.

[0077] Optionally, in this step, configuring the audio data to be processed and the algorithm parameters is equivalent to the main processor storing the audio data to be processed in DATA MEM through the bus matrix, and selecting the parameter values ​​of the algorithm parameters (if only the filtering algorithm is used, then the algorithm parameters are the filter coefficients).

[0078] Step 502: The main processor sends the target instruction to the coprocessor through the kernel channel.

[0079] Optionally, the main processor generates a target instruction based on the data address of the audio data to be processed and the parameter address of the parameter values ​​stored in the DATA MEM, and sends it to the coprocessor through the kernel channel. For example, the generated target instruction could be: FIR_FILTER [src_addr], [coef_addr], length. Here, the [src_addr] field indicates the position of the audio data to be processed in the DATA MEM, the [coef_addr] field indicates the position of the filter coefficients in the DATA MEM, and length indicates the length of the audio data to be processed.

[0080] Optionally, the process of the main processor generating and sending target instructions to the coprocessor can be referenced above. Figure 2 The process executed by the main processor will not be described in detail here.

[0081] Step 503: The coprocessor performs data processing.

[0082] Optionally, upon receiving the target instruction, the coprocessor is immediately activated (i.e., awakened by the main processor) and directly accesses memory based on the address in the target instruction. For example, upon receiving the target instruction FIR_FILTER [src_addr], [coef_addr], length, the coprocessor can identify each field and directly access the DATA MEM through the Bus Matrix to read the audio data to be processed and the parameter values ​​of the algorithm, and perform calculations within its internal hardware logic. Details of the data processing performed by the coprocessor in this step can be found above. Figure 2 The process of execution by the coprocessor will not be described in detail here.

[0083] Optionally, once activated, the coprocessor can also act as the master device of the bus matrix, independently reading data from DATAMEM, performing calculations, and writing back the results without the intervention of the master processor.

[0084] Optionally, in this step, the main processor is freed up. That is, after issuing the target instruction, the main processor can immediately switch to executing other tasks (such as processing the protocol stack, updating the display, etc.) without waiting. In other words, the main processor can now process its respective tasks in parallel with the coprocessor.

[0085] Step 504: The coprocessor notifies the main processor that processing is complete.

[0086] Optionally, after the coprocessor has completed its processing (including the entire process of reading data, calculating, and writing back the results), it can set a simple status flag to notify the main processor whether it has finished processing.

[0087] Step 505: The main processor outputs the processing result.

[0088] Optionally, the main processor can instruct the DMA unit to send the processing result to the I2S unit output, or proceed with further processing. The description of the processing result can be found above. Figure 2 The relevant content will not be repeated here.

[0089] In summary, because the main processor and coprocessor transmit target instructions through the kernel channel, and the coprocessor processes the audio data based on these instructions, the instruction control process does not require a separate bus, resulting in a simpler instruction control flow and higher coupling between the main processor and coprocessor. This improves the efficiency of processing audio data. Furthermore, it allows computation, data transfer, and other tasks to be performed in parallel, enhancing the overall utilization of hardware resources and providing system-level support for low-latency, high-throughput processing of continuous audio streams.

[0090] Furthermore, this solution can complete complex signal processing tasks with fewer instruction cycles, thus significantly improving computational throughput at the same clock frequency. Simultaneously, the high efficiency and independent operation of the coprocessor allow the overall system to effectively reduce the main processor load and system power consumption while performing high-performance audio processing.

[0091] In addition, the hardware acceleration layer provided by this solution allows for configuration and customization according to specific application requirements, while the extension mechanism of the custom instruction set also provides the possibility for subsequent adaptation to new algorithm requirements, thus ensuring computing performance while taking into account the adaptability of the design and the convenience of development.

[0092] Please refer to Figure 6 This illustration shows a schematic flowchart of a data processing method provided in an exemplary embodiment of this application. This data processing method can be applied to the data processing systems of the various embodiments described above, and the structure of the data processing system can be referenced to the descriptions in the various embodiments above. Figure 6 As shown, the method includes the following steps: Step 601: Send the target instruction through the kernel channel. The target instruction contains the data address of the audio data to be processed. The data address is used to indicate the location of the audio data to be processed in the storage unit. The kernel channel is a channel composed of the kernel interface of the main processor and the kernel interface of the coprocessor.

[0093] Step 602: In response to the target instruction, retrieve the audio data to be processed from the storage unit and process the audio data to be processed.

[0094] Optionally, before sending the target instruction via the kernel channel, the method further includes: Get the data address of the audio data to be processed; Generate target instructions based on the data address of the audio data to be processed.

[0095] Optionally, the storage unit includes a storage area and a cache area; Before obtaining the data address of the audio data to be processed, the method also includes: According to the time sequence of the audio data to be processed, the audio data to be processed is moved from the storage area to the cache area; Obtain the data address of the audio data to be processed, including: Get the data address of the audio data to be processed after it has been moved from the storage area to the cache area.

[0096] Optionally, the buffer area is configured with N buffer blocks, where N is an integer greater than or equal to 2; each buffer block is used to store one frame of audio data to be processed. Moving the audio data to be processed from the storage area to the cache area includes: The audio data to be processed for each frame is moved from the storage area to N buffer blocks; In response to the target instruction, the audio data to be processed is retrieved from the storage unit and processed, including: In response to the target instruction, the system sequentially retrieves the audio data to be processed from each of the N buffer blocks and processes the retrieved audio data of each frame.

[0097] Optional, N equals 2; In response to the target instruction, the audio data to be processed is retrieved from the storage unit and processed, including: In response to the target instruction, while the data processing system is moving the audio data to be processed of the (X+1)th frame into one of the buffer blocks, the system retrieves the audio data to be processed of the Xth frame from the other buffer block and processes the audio data to be processed of the Xth frame, where X is an integer greater than or equal to 1.

[0098] Optionally, after processing the audio data to be processed, the method further includes: The processing result is written into the target buffer block. The processing result is the result obtained by the coprocessor processing the audio data to be processed in the Xth frame. The target buffer block is the buffer block in the buffer area that stores the audio data to be processed in the Xth frame. The processing result is output and the audio data to be processed in frame X+2 is moved into the target buffer block.

[0099] Optionally, the data processing system also includes a bus matrix, through which the main processor is connected to the storage unit. The bus matrix is ​​also connected to external devices. The external devices are used to move the audio data to be processed from the storage area to the cache area according to the time sequence of the audio data to be processed. Moving the audio data to be processed from the storage area to the cache area includes: The external devices are controlled by a bus matrix to move the audio data to be processed from the storage area to the buffer area.

[0100] Optionally, the data processing system also includes a bus matrix, through which the coprocessor is connected to the memory unit; In response to the target instruction, the audio data to be processed is retrieved from the storage unit and processed, including: In response to the target instruction, the coprocessor selects to acquire the audio data to be processed through either the first channel or the second channel, and processes the acquired audio data to be processed. The first channel is the channel through which the coprocessor is connected to the storage unit via a bus matrix, and the second channel is the channel through which the coprocessor is directly connected to the storage unit without using a bus matrix.

[0101] Optionally, the target instruction may also include a parameter address, which indicates the location in the memory unit of the target parameter value required by the processing algorithm used by the coprocessor. Processing the audio data to be processed includes: Based on the parameter address contained in the target instruction, retrieve the target parameter value required by the algorithm parameters corresponding to the processing algorithm from the storage unit; Adjust the algorithm parameters corresponding to the processing algorithm to the target coefficient values, and process the audio data to be processed according to the adjusted processing algorithm.

[0102] Optionally, the coprocessor contains at least two processing algorithms; Adjust the algorithm parameters corresponding to the processing algorithm to the target coefficient values, including: Adjust the algorithm parameters of the processing algorithm corresponding to the target instruction or the parameter address contained in the target instruction to the target coefficient value.

[0103] It should be noted that the steps performed by the data processing system in this method embodiment can refer to the above. Figure 2 The details and processes executed by the main processor and coprocessor in the example will not be elaborated here.

[0104] In summary, because the main processor and coprocessor in the data processing system transmit target instructions through the kernel channel, the system can promptly respond to the target instructions after generating them and process the audio data to be processed. The instruction control process does not need to go through an independent bus, the instruction control flow is simpler, and the coupling between the main processor and coprocessor is higher, thereby improving the efficiency of processing the audio data to be processed.

[0105] Optionally, embodiments of this application also provide a chip that includes at least one data processing system as shown in the above embodiments.

[0106] Optionally, embodiments of this application also provide an electronic device, which includes at least one data processing system as shown in the above embodiments, or includes one of the above-described chips.

[0107] Please refer to Figure 7 This illustrates a schematic diagram of the structure of an electronic device provided in an exemplary embodiment of this application. Figure 7 The electronic device shown includes components such as a processor 710, a memory 720, a transceiver 730, a display unit 740, an input unit 750, a sensor 760, an audio circuit 770, and a power supply module 780.

[0108] The processor 710 is the control center of the electronic device. It connects various parts of the electronic device via various interfaces and lines. By running or executing software programs and / or modules stored in the memory 720, and by calling data stored in the memory 720, it performs various functions and processes data, thereby providing overall monitoring of the electronic device. Optionally, the processor 710 may include one or more processing units; optionally, the processor 710 may integrate an application processor, which mainly handles operating devices, user interfaces, and application programs. Of course, it may also include other processors, which are not listed here.

[0109] The memory 720 can be used to store software programs and modules. The processor 710 executes various functional applications and data processing of the electronic device by running the software programs and modules stored in the memory 720. The memory 720 may mainly include a program storage area and a data storage area. The program storage area may store the operating device and application programs required for at least one function (such as sound playback function, image playback function, etc.); the data storage area may store data created according to the use of the electronic device (such as audio data, telephone directory, etc.). In addition, the memory 720 may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other volatile solid-state storage device.

[0110] Transceiver 730 can provide solutions for wireless communication applications in electronic devices, including wireless local area networks (WLANs) (such as wireless fidelity (Wi-Fi) networks), Bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), and infrared (IR) technologies. Transceiver 730 can be one or more devices integrating at least one communication processing module; for example, it can integrate an antenna with a baseband processor, or it can integrate an antenna with a modem processor, etc., without limitation.

[0111] The display unit 740 can be used to display information input by the user or information provided to the user, as well as various menus of the electronic device. The display unit 740 can be configured in the form of a liquid crystal display (LCD), an organic light-emitting diode (OLED), or other similar devices, and there is no limitation on this.

[0112] The input unit 750 can be used to receive input digital or character information and generate key signal inputs related to user settings and function control of the electronic device. Specifically, the input unit 750 can collect user operations on or near it and drive corresponding connected devices according to a pre-set program. Furthermore, the input unit 750 may include a touch panel, which can be implemented using various types such as resistive, capacitive, infrared, and surface acoustic wave touch panels. In addition to the touch panel, the input unit 750 may also include other input devices. Specifically, other input devices may include, but are not limited to, one or more of the following: function keys (such as volume control buttons, power buttons, etc.), trackballs, joysticks, etc.

[0113] Electronic devices may also include at least one sensor 760, such as a gyroscope sensor, a motion sensor, and other sensors. Motion sensors may include accelerometers for detecting the magnitude of acceleration in various directions, and when stationary, they can detect the magnitude and direction of gravity. These can be used for applications that identify the attitude of the electronic device, such as screen orientation switching, related games, and magnetometer attitude calibration. Other sensors that may be configured in electronic devices, such as pressure gauges, barometers, hygrometers, thermometers, and infrared sensors, are not detailed here.

[0114] The audio circuit 770 may include a speaker and a microphone, providing an audio interface between the user and the electronic device. The audio circuit 770 can convert received audio data into electrical signals and transmit them to the speaker, where the speaker converts them into sound signals for output. Conversely, the microphone converts collected sound signals into electrical signals, which are then received by the audio circuit 770, converted back into audio data, and output to the processor 710 for processing. The audio data is then transmitted via a video circuit to, for example, another electronic device, or output to the memory 720 for further processing.

[0115] The electronic device also includes a power module 780 that supplies power to the various components. Optionally, the power module 780 can be logically connected to the processor 710 through a power management device, thereby enabling the power management device to manage functions such as charging, discharging, and power consumption.

[0116] Although not shown, the electronic device may also include a camera. Optionally, the camera may be positioned in the front or rear of the electronic device, and this application embodiment does not limit this.

[0117] It is understood that the structures illustrated in the embodiments of this application do not constitute a specific limitation on the electronic device. In other embodiments of this application, the electronic device may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0118] Optionally, the aforementioned electronic devices may include, but are not limited to, wearable devices (such as smart bracelets, smartwatches, smart glasses, etc.), mobile phones, tablets, laptops, smart glasses, smartwatches, MP4 (Moving Picture Experts Group Audio Layer IV) players, desktop computers, laptop computers, and other devices with displays.

[0119] Normally, the above Figure 7 The electronic devices shown need to be equipped with a corresponding operating system and run on that operating system. For example, the operating system of the electronic devices can be Android, iOS, Linux, etc.

[0120] Optionally, embodiments of this application also provide a computer-readable medium having a computer program stored thereon, which, when executed by a processor, implements all or part of the steps performed by the data processing system in the data processing methods of the various embodiments described above.

[0121] Optionally, embodiments of this application also provide a chip containing an executable computer program. When the chip executes the computer program, it implements all or part of the steps performed by the data processing system in the data processing methods of the above embodiments.

[0122] Optionally, embodiments of this application also provide a computer program product, including a computer program that, when processed and executed, implements the data processing methods of the various embodiments described above.

[0123] Optionally, embodiments of this application also provide an application publishing platform for publishing computer program products. When the computer program product is run on a computer, it causes the computer to execute all or part of the steps of the data processing methods described in the above embodiments, which are executed by the data processing system.

[0124] It should be noted that the methods provided in the above embodiments are only illustrative examples of the division of functional modules when controlling the data processing system. In practical applications, the functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. Furthermore, the methods provided in the above embodiments and the embodiments of the data processing system belong to the same concept, and their specific implementation process can be found in the embodiments of the data processing system, which will not be repeated here. Moreover, the various embodiments provided in this application can be combined with each other.

[0125] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0126] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0127] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A data processing system, characterized in that, The data processing system includes a main processor, a coprocessor, and a storage unit; The main processor and the coprocessor are connected via a kernel channel, which is a channel formed by the kernel interface of the main processor and the kernel interface of the coprocessor; the main processor and the coprocessor are also respectively connected to the storage unit, which stores audio data to be processed. The main processor is used to send a target instruction to the coprocessor through the kernel channel. The target instruction contains the data address of the audio data to be processed. The data address is used to indicate the location of the audio data to be processed in the storage unit. The coprocessor is used to receive the target instruction through the kernel channel, and in response to the target instruction, to retrieve the audio data to be processed from the storage unit, and to process the audio data to be processed.

2. The data processing system according to claim 1, characterized in that, The main processor is also used to obtain the data address of the audio data to be processed, and generate the target instruction based on the data address of the audio data to be processed.

3. The data processing system according to claim 2, characterized in that, The storage unit includes a storage area and a cache area; The main processor is also configured to move the audio data to be processed from the storage area to the cache area according to the time sequence of the audio data to be processed; When obtaining the data address of the audio data to be processed, the main processor is specifically used to obtain the data address of the audio data to be processed after it has been moved from the storage area to the cache area.

4. The data processing system according to claim 3, characterized in that, The buffer area contains N buffer blocks, where N is an integer greater than or equal to 2; each buffer block is used to store one frame of audio data to be processed. When moving the audio data to be processed from the storage area to the cache area, the main processor is specifically used to move the audio data to be processed for each frame from the storage area to the N buffer blocks; When the coprocessor retrieves the audio data to be processed from the storage unit in response to the target instruction and processes the audio data to be processed, the coprocessor is specifically used to retrieve the audio data to be processed from each of the N buffer blocks in sequence in response to the target instruction, and process the audio data to be processed from each of the retrieved frames.

5. The data processing system according to claim 4, characterized in that, The N is equal to 2; When the coprocessor retrieves the audio data to be processed from the storage unit in response to the target instruction and processes the audio data to be processed, the coprocessor is specifically used to retrieve the audio data to be processed from the Xth frame from another buffer block in response to the target instruction, while the main processor moves the audio data to be processed of the X+1th frame into one of the buffer blocks, and processes the audio data to be processed of the Xth frame, where X is an integer greater than or equal to 1.

6. The data processing system according to claim 5, characterized in that, The coprocessor is also used to write the processing result into the target buffer block. The processing result is the result obtained by the coprocessor processing the audio data to be processed in the Xth frame. The target buffer block is a buffer block in the buffer area that stores the audio data to be processed in the Xth frame. The main processor is also configured to output the processing result and move the audio data to be processed of the (X+2)th frame into the target buffer block after the coprocessor writes the processing result into the target buffer block.

7. The data processing system according to any one of claims 3 to 6, characterized in that, The data processing system also includes a bus matrix, through which the main processor is connected to the storage unit. The bus matrix is ​​also connected to an external device, which is used to move the audio data to be processed from the storage area to the cache area according to the time sequence of the audio data to be processed. When moving the audio data to be processed from the storage area to the cache area, the main processor is specifically used to control the operation of the external device through the bus matrix.

8. The data processing system according to claim 1, characterized in that, The data processing system also includes a bus matrix, and the coprocessor is connected to the storage unit through the bus matrix; When the coprocessor retrieves audio data to be processed from the storage unit in response to a target instruction and processes the audio data to be processed, the coprocessor is specifically used to retrieve the audio data to be processed from the storage unit through a first channel or a second channel in response to the target instruction, and process the retrieved audio data to be processed; wherein, the first channel is the channel through which the coprocessor is connected to the storage unit via the bus matrix, and the second channel is the channel through which the coprocessor is directly connected to the storage unit without going through the bus matrix.

9. The data processing system according to claim 1, characterized in that, The target instruction also includes a parameter address, which is used to indicate the location of the target parameter value required by the algorithm parameters corresponding to the processing algorithm used by the coprocessor in the storage unit; When processing the audio data to be processed, the coprocessor is also specifically used to obtain the target parameter value required by the algorithm parameter corresponding to the processing algorithm from the storage unit according to the parameter address contained in the target instruction; The coprocessor is also specifically used to adjust the algorithm parameters corresponding to the processing algorithm to the target coefficient value, and to process the audio data to be processed according to the adjusted processing algorithm.

10. The data processing system according to claim 9, characterized in that, The coprocessor contains at least two processing algorithms; When adjusting the algorithm parameters corresponding to the processing algorithm to the target coefficient value, the coprocessor is further specifically used to adjust the algorithm parameters of the processing algorithm corresponding to the target instruction or the parameter address contained in the target instruction to the target coefficient value.

11. A data processing method, characterized in that, The method is applied to a data processing system, which includes a main processor, a coprocessor, and a storage unit. The main processor and the coprocessor are respectively connected to the storage unit, which stores audio data to be processed. A target instruction is sent through a kernel channel, the target instruction containing the data address of the audio data to be processed; the data address is used to indicate the location of the audio data to be processed in the storage unit; wherein, the kernel channel is a channel formed by the kernel interface of the main processor and the kernel interface of the coprocessor; In response to the target instruction, the audio data to be processed is retrieved from the storage unit and processed.

12. A chip, characterized in that, The chip includes at least one data processing system as described in any one of claims 1 to 10.

13. An electronic device, characterized in that, The electronic device includes a data processing system as described in any one of claims 1 to 10, or includes at least one chip as described in claim 12.

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