A branch predictor for a superscalar processor

Abstract

The application discloses a branch predictor of a superscalar processor and relates to the technical field of processors. The predictor generates BTB read indexes, BTB tags and BHT read indexes of a current and adjacent fetch packet query path in parallel to read data; determines a hit result according to the BTB tags and read BTB table items, and then expands the hit result and corresponding table items to original 2-byte positions in the query path to determine a plurality of continuous original 2-byte positions as a plurality of candidate slot positions, and determine BTB hit results, BTB table items and read BHT table items of each candidate slot position; determines a jump direction of a branch instruction according to the information of each candidate slot position, and completes selection of a first jump branch, prediction of a target address and generation of an instruction mask. The predictor also updates related states after completing prediction, and repairs corresponding data according to a prediction error feedback of an execution unit. The application can take into account throughput and hardware overhead.

Description

Technical Field

[0001] This invention belongs to the field of processors, and specifically relates to a branch predictor for a superscalar processor. Background Technology

[0002] In recent years, high-performance processors have widely adopted superscalar and deep pipeline architectures. Compared to the classic five-stage pipeline, high-performance processors are more complex in their microarchitecture, typically featuring deeper pipeline stages and multiple parallel execution units (such as arithmetic, multiplication, and division) capable of processing different types of instructions simultaneously. In this architecture, the branch prediction unit (i.e., the branch predictor) is particularly crucial: due to the significantly increased number of pipeline stages between the instruction fetch stage and the actual branch instruction result, branch prediction errors can lead to a large number of instructions being flushed out, resulting in severe performance loss. Especially in superscalar processors, where the fetch bandwidth can typically reach 4 to 8 instructions per cycle, the penalty for prediction errors is even more significant, potentially negating the performance gains brought by deep pipelines and high fetch bandwidth. Therefore, high-performance processors place extremely high demands on branch prediction accuracy.

[0003] However, existing branch predictors still suffer from limited throughput, high cost, and high power consumption. These issues need to be addressed. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a branch predictor for a superscalar processor. The technical problem to be solved by this invention is achieved through the following technical solution: This invention provides a branch predictor for a superscalar processor, comprising: The branch target buffer (BTB) has multiple entries for storing information about different branch instructions; The front-end global history register GHR is used to record the direction history of the latest N valid branch instructions; The branch history table (BHT) is used to record the historical jump trends of conditional branch instructions. The parallel hash generation and reading module is used to generate adjacent fetch addresses based on the current fetch address, and to generate BTB read index, BTB tag and BHT read index corresponding to the current fetch packet query path and the adjacent fetch packet query path in parallel based on the value of the front-end GHR record, and to read data from BTB and BHT using the BTB read index and BHT read index. The hit determination module is used to compare the BTB tag with the BTB tags in the read candidate BTB entries in parallel to determine whether each candidate BTB entry has a tag hit. The position expansion and rearrangement module is used to determine the original 2-byte position of the candidate BTB table entry hit by each tag in the corresponding query path, and use the current fetch address to select consecutive original 2-byte positions from the positions covered by the current fetch packet query path and the adjacent fetch packet query path as candidate slots obtained by multiple rearrangements, and determine the BTB hit status, candidate BTB table entry and read BHT table entry corresponding to each candidate slot; The direction prediction synthesis module is used to determine the direction prediction result of the branch instruction at each BTB-hit candidate slot based on the BTB hit status, BHT entry and candidate BTB entry corresponding to the candidate slot. The first jump branch selection module is used to select the candidate slot where the branch instruction to jump is located, as indicated by the first direction prediction result, and obtain the selection result indicating whether there is a selected candidate slot. The target address and instruction mask generation module is used to generate an instruction mask and the predicted target address to be used in the current instruction fetch packet based on the selection result.

[0005] In some embodiments, the BTB has multiple entries, each entry storing the target address offset of an identified branch instruction, the BTB tag, the valid bit, instruction type information, instruction length information, and location-related information, wherein the instruction type information includes an instruction type flag, and the location-related information includes a physical memory identifier and a slot offset flag. The front-end GHR is used to record the direction history of the latest N valid branch instructions using N-bit binary code. The direction history of a valid branch instruction is used to indicate whether the jump direction of the valid branch instruction is a jump. BHT has multiple entries, each of which is used to store the historical jump tendency of a conditional branch instruction. The branch predictor also includes a return address stack (RAS); the RAS is used to push or pop addresses from the stack.

[0006] In some embodiments, the parallel hash generation and reading module includes: The parallel hash generation module performs hash operations in parallel on specific bit segments of the current fetch address and adjacent fetch addresses to obtain the N-bit BTB read index and M-bit BTB tag corresponding to the current fetch packet query path and the adjacent fetch packet query path, respectively. The N-bit BTB read index corresponding to the current fetch packet query path and the adjacent fetch packet query path are used as intermediate inputs for generating the BHT index, and hashed with the N-bit binary code recorded by the front-end GHR to obtain the N-bit BHT read index corresponding to the current fetch packet query path and the adjacent fetch packet query path, where N and M are both positive integers. The data reading and writing module is used to read multiple entries from the BTB as multiple candidate BTB entries by using the BTB read index corresponding to the current fetch packet query path and the adjacent fetch packet query path, and to read multiple BHT entries from the BHT by using the BHT read index corresponding to the current fetch packet query path and the adjacent fetch packet query path.

[0007] In some embodiments, the hit determination module is specifically used to perform parallel comparisons between the BTB tag corresponding to the current fetch packet query path and the BTB tags recorded in each candidate BTB table entry read using the query path for each query path in the current fetch packet query path and the adjacent fetch packet query paths, and determine that the tag of the candidate BTB table entry is hit when the BTB tags are consistent and the valid bit in the candidate BTB table entry is valid; otherwise, determine that the tag of the candidate BTB table entry is not hit. The position unpacking and rearrangement module is specifically used to determine the original 2-byte position of each candidate BTB entry hit by a tag in the current fetch packet query path or adjacent fetch packet query path based on the physical memory identifier, slot offset flag, and instruction length information in the candidate BTB entry hit by each tag. It obtains the current fetch packet query path and adjacent fetch packet query path by taking the original 2-byte position corresponding to the candidate BTB entry hit by the tag in the current fetch packet query path and adjacent fetch packet query paths as the BTB hit position, and the original 2-byte position corresponding to the candidate BTB entry not hit by the tag as the BTB miss position. The BTB hit status corresponding to each original 2-byte position covered by the packet query path is determined. Based on the address bit representing the 2-byte start offset in the current fetch address, multiple consecutive original 2-byte positions are selected from all original 2-byte positions covered by the current fetch packet query path and the adjacent fetch packet query paths. These selected original 2-byte positions are used as multiple candidate slots obtained through rearrangement. At the same time, the BTB hit status, candidate BTB entries, and read BHT entries corresponding to each selected original 2-byte position are used as the BTB hit status, candidate BTB entries, and read BHT entries corresponding to a candidate slot obtained through rearrangement.

[0008] In some embodiments, the direction prediction synthesis module is specifically configured to, for each candidate slot, when the BTB hit status of the candidate slot indicates a BTB hit, it indicates that there is a branch instruction at the candidate slot, and when the instruction type information recorded in the candidate BTB entry corresponding to the candidate slot indicates that the branch instruction at the candidate slot is a conditional branch instruction, use the historical jump tendency corresponding to the candidate slot as the direction prediction result of the branch instruction at the candidate slot; when the BTB hit status of the candidate slot indicates a BTB hit, and the instruction type information recorded in the candidate BTB entry corresponding to the candidate slot indicates that the branch instruction at the candidate slot is an unconditional jump instruction, a function call instruction, or a function return instruction, predict the direction prediction result of the branch instruction at the candidate slot as a jump; The first jump branch selection module is specifically used to select the candidate slot where the first direction prediction result is a jump from all the candidate slots hit by BTB, and obtain the selection result indicating whether there is a selected candidate slot.

[0009] In some embodiments, the target address and instruction mask generation module includes: an instruction mask generation module; The instruction mask generation module is used to generate control information to change the next instruction fetch address when the selection result indicates that there is a selected candidate slot, and generate a first instruction mask according to the position of the selected candidate slot, wherein the first instruction mask indicates that all candidate slots after the selected candidate slot are invalid; and to generate a second instruction mask when the selection result indicates that there is no selected candidate slot, wherein the second instruction mask indicates that all rearranged candidate slots are valid.

[0010] In some embodiments, the target address and instruction mask generation module further includes: a target address generation module; The target address generation module is configured to: when the selection result indicates the existence of a selected candidate slot, read the target address offset and instruction type information from the candidate BTB entry corresponding to the selected candidate slot; when the read instruction type information indicates that the branch instruction at the selected candidate slot is a conditional branch instruction, an unconditional jump instruction, or a function call instruction, add the instruction address of the branch instruction at the selected candidate slot to the read target address offset to obtain the predicted target address; when the read instruction type information indicates that the branch instruction at the selected candidate slot is a function return instruction and the stack top address of the RAS is valid, use the stack top address of the RAS as the predicted target address; when the selection result indicates the absence of a selected candidate slot, maintain the sequential instruction fetch path and do not output the predicted target address used to change the next instruction fetch address.

[0011] In some embodiments, the predicted target address and the instruction mask constitute the front-end prediction result generated by the branch predictor; the instruction mask is used to indicate whether each candidate slot obtained from the plurality of rearrangements is valid; the branch predictor further includes: The speculative update module is used to record the direction prediction results of valid candidate branch instructions with non-jump properties before the first jump branch when there are valid candidate branch instructions in the current instruction fetch packet, and to record the direction prediction results of the first jump branch using binary code values ​​representing non-jump properties, and to store the recorded binary code values ​​in the front-end GHR; when there is no first jump branch but there are valid candidate branch instructions, it records the direction prediction results of the valid candidate branch instructions in the current instruction fetch packet using binary code values ​​representing non-jump properties, and stores the recorded binary code values ​​in the front-end GHR; and when the first jump branch is a function call instruction, it pushes the next address into the RAS in the order determined by the instruction length information of the function call instruction, wherein the first jump branch is the branch instruction at the selected candidate slot, and the valid candidate branch instruction refers to the branch instruction at the candidate slot that is hit by BTB and is valid; The prediction error correction module is used to trigger pipeline flushing when it receives a prediction error feedback packet after the execution unit executes the prediction result of the front end, and to correct the binary code value or table entry content of at least one of the front end GHR, BTB, BHT and RAS according to the prediction error feedback packet.

[0012] In some embodiments, the branch predictor further includes: Parallel conflict detectors are used to monitor whether at least two threads initiate write requests to the same BTB or BHT entry within the same period. A hardware arbitrator is used to arbitrate requests when at least two threads initiate write requests to the same BTB or BHT entry within the same cycle, using a combination of static priority and dynamic polling.

[0013] In some embodiments, the branch predictor further includes: The SRAM write-back delay module is used to serialize the write requests that have been reserved after conflict detection and arbitration into write requests in consecutive cycles when at least two threads generate valid write requests for different BTB entries in the same cycle, and the BTB is implemented with a single write port static random access memory.

[0014] Compared with the prior art, the beneficial effects of the present invention are as follows: 1) This invention generates BTB and BHT read indices for the current fetch packet query path and adjacent fetch packet query paths in parallel. After reading data using these indices, it sequentially completes hit determination, position expansion, candidate slot rearrangement, direction synthesis, and first jump branch selection. This enables the processing of multiple candidate branch positions within one clock cycle, improving the fetch prediction throughput of the superscalar processor. At the same time, by sharing hash calculation logic, BTB, BHT, front-end GHR, and candidate slot rearrangement logic, it avoids setting up a completely independent branch predictor for each candidate slot, thus achieving a trade-off between prediction throughput and hardware overhead. This improves prediction throughput while avoiding additional hardware overhead.

[0015] 2) This invention securely solves the problem of concurrent access to shared prediction resources in a multi-threaded environment by designing a parallel, multi-level hybrid prediction architecture, ensuring data consistency and system stability. Furthermore, the closed-loop control method combining speculative updates and repairs enables the branch predictor to achieve dynamic learning and state correction without sacrificing speed. Specialized optimizations for special instructions such as function calls / function returns further improve the overall prediction accuracy.

[0016] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the instruction fetching unit provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the branch predictor of the superscalar processor provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of BHT provided in an embodiment of the present invention. Detailed Implementation

[0018] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0019] This invention provides a high-performance, high-accuracy, multi-threaded, and power-optimized branch prediction solution. Specifically, this invention proposes a branch predictor for superscalar processors, applicable to a nine-stage dual-issue superscalar pipeline architecture based on the fifth-generation Reduced Instruction Set Computer – V (RISC-V) instruction set. This pipeline sequentially includes: Fetch Stage 1 (IF1), Fetch Stage 2 (IF2), Alignment Stage (ALIGN), Decode Stage (DECODE), Execution Stage 1 (EX1), Execution Stage 2 (EX2), Execution Stage 3 (EX3), Commit Stage, and Write-back Stage (WB). The branch predictor primarily resides in IF1 and IF2 stages. IF1 is used to generate the read indexes of the Branch Target Buffer (BTB) for the current fetch packet query path and adjacent fetch packet query paths, as well as the BTB tags and the Branch History Table (BHT) read indexes, and to initiate data reading. IF2 is used to complete the BTB tag and valid bit hit determination, the position expansion of the hit result, the reordering of candidate slot programs, direction prediction, first jump branch selection, target address generation, and instruction mask generation. The Execution Unit (EXU) is used to verify the branch prediction results and to provide correction information to the branch predictor when a prediction error occurs.

[0020] Please see Figure 1 , Figure 1 This is a schematic diagram of the Instruction Fetch Unit (IFU). For example... Figure 1 As shown, the IFU includes a program counter (PC), a fetch control module, a branch predictor, an instruction cache module, a tightly coupled instruction memory, and an alignment module. The fetch control module and the branch predictor operate at IF1 and IF2 levels, respectively, while the alignment module operates at ALIGN level. The fetch control module maintains the PC and selects the next fetch address based on the prediction target address output by the branch predictor. The alignment module aligns the instructions in the fetch packet and, in conjunction with the instruction mask, removes invalid instructions following branch instructions predicted as jumps.

[0021] Please see Figure 2 , Figure 2This is a schematic diagram of the branch predictor for a superscalar processor provided in an embodiment of the present invention. The branch predictor includes: a BTB, a front-end global history register (GHR), a BHT, a return address stack (RAS), a parallel hash generation and reading module, a hit determination module, a position expansion and rearrangement module, a direction prediction synthesis module, a first jump branch selection module, and a target address and instruction mask generation module; wherein, the BTB, BHT, RAS, and front-end GHR constitute a hybrid prediction core.

[0022] The Branch Block (BTB) has multiple entries. Each entry stores the BTB tag of an identified branch instruction, the target address offset, instruction type information, instruction length information, location-related information, and valid bits. Instruction type information includes: function call (CALL) flag, function return (RET) flag, and unconditional jump flag. Location-related information includes either or both of the slot offset flag (boffset) and physical memory bank identifier; the memory bank is called a Bank. The target address offset is added to the instruction address of the branch instruction (i.e., the branch PC) to generate the predicted target address. Branch instructions refer to actual control flow instructions such as conditional branch instructions, unconditional jump instructions, CALL instructions, or RET instructions. Instruction length information can be represented by the symbol pc4, which distinguishes whether the next sequential address is PC+2 or PC+4. The slot offset flag boffset, together with the instruction length information, determines the 2-byte location corresponding to the BTB entry. The CALL flag, RET flag, and unconditional jump flag indicate deterministic jump types such as function calls, function returns, or unconditional jumps. The functions of BTB tags, target address offsets, instruction type information, instruction length information, location-related information, and valid bits will be explained in detail in later sections, and will not be discussed here.

[0023] For example, a BTB may include two physical banks, Bank0 and Bank1, and both Bank0 and Bank1 include two paths, way0 and way1, accessing the corresponding storage locations according to the BTB read index. Here, way represents a data storage location, and way0 and way1 represent two different data storage locations within a bank. Therefore, when the BTB is implemented using a two-way set-associative approach, a BTB read index for the current fetch packet query path can read four original candidate BTB entries from the two paths of the two physical banks. A BTB read index for an adjacent fetch packet query path can also read four original candidate BTB entries. These original candidate BTB entries need to undergo BTB tag and valid bit hit judgment, position expansion, and program order reordering to form the final four rearranged candidate slot BTB prediction results. The hit judgment of BTB tags and valid bits, as well as position expansion and program order reordering, will be described in detail in later sections and will not be specifically described here. The physical implementation of the BTB can use Static Random-Access Memory (SRAM) or standard logic flip-flops. In other embodiments, the BTB can also be configured as a fully associative structure or other set-associative structures depending on capacity and implementation cost. The two-way set-associative structure can employ a Least Recently Used (LRU) replacement strategy; the fully associative structure can employ a replacement strategy based on the bit state vector used. It should be noted that these strategies are existing strategies, and this invention will not elaborate on them.

[0024] The front-end GHR uses an N-bit binary code to maintain (i.e., record) the direction history of the N most recent valid branch instructions. Each bit indicates whether a corresponding valid branch instruction jumps or does not, where N is a positive integer greater than 1, and a valid branch instruction refers to a branch instruction at a valid candidate slot. For example, the front-end GHR can be 7 bits. It should be noted that during the prediction process of the branch predictor, since the corresponding branch instructions have not yet been executed by the backend execution unit, the actual execution results of these branch instructions are not yet determined. Therefore, the N-bit code value maintained in the frontend GHR during this process is speculative and is called the speculative historical state value. This speculative historical state value is updated according to the direction prediction results of the valid candidate branch instructions in the current fetch packet and participates in the generation of the BHT read index. Furthermore, when the backend execution unit determines that the jump direction prediction of a certain branch instruction is incorrect, the execution unit will feed back the correct historical state value to correct the corresponding value in the speculative historical state value. It should be noted that the specific principles of the use, updating and correction of the speculative historical state value in the frontend GHR will be explained in detail in a later section and will not be explained in detail here.

[0025] The BHT has multiple entries, each storing the historical jump tendencies of a conditional branch instruction mapped to that entry by a BHT index. For example, the total capacity of the BHT is 512 entries, each implemented using a 2-bit saturation counter. The high-order bits of the saturation counter serve as direction prediction bits to indicate whether a jump is possible, while the low-order bits indicate the strength of the prediction. Figure 3 As shown, each 2-bit saturation counter is used to record the historical jump tendency of a conditional branch instruction. Figure 3 In the diagram, T represents a jump and NT represents no jump. Each 2-bit saturation counter has four states: strong jump (11), weak jump (10), weak no jump (00), and strong no jump (01). The BHT can be divided into four physical banks: Bank0, Bank1, Bank2, and Bank3. Each bank contains multiple 2-bit saturation counters. The BHT read index corresponding to the current fetch packet query path is used to read the table data of these four banks from the BHT. The BHT read index corresponding to the adjacent fetch packet query path is used to read the adjacent bank table data required for candidate slot rearrangement from the BHT. The above BHT read results are rearranged according to the 2-byte starting offset of the current fetch address, using the same program order as the BTB hit results, to form the historical jump tendency corresponding to the four candidate slots. This principle will be explained in detail later and will not be elaborated here. In some embodiments, the physical implementation of the BHT adopts a regional clock gating technique, that is, a clock pulse is only provided to the corresponding memory area when a write operation occurs, thereby significantly reducing the static and dynamic power consumption of the predictor.

[0026] RAS is specifically used to push or pop addresses from the stack. For example, RAS has a depth of 4 levels. Specifically, it uses the hardware stack mechanism to push the return address of the CALL instruction onto the stack and pop it from the stack when the corresponding RET instruction is encountered. The CALL instruction represents a function call instruction, and the RET instruction represents a function return instruction.

[0027] Because RISC-V supports 16-bit compressed instructions, the prediction range starting from the current fetch address is, for example, represented in 2-byte granularity as four candidate slots, which can also be called virtual banks. These four candidate slots are not four independent physical storage entities, but rather four logical positions formed by the BTB / BHT read results of the current fetch packet query path and adjacent fetch packet query paths after hit detection, position expansion, and program order reordering. The address bit representing the 2-byte starting offset in the current fetch address is used to determine the starting position of the prediction range within the physical fetch packet; regardless of which 2-byte boundary within the physical fetch packet the current fetch address begins at, the position expansion and reordering module maps four consecutive 2-byte positions starting from the current fetch address sequentially to candidate slots 0 to 3. The specific principles of this part will be explained in detail later.

[0028] In this invention, the parallel hash generation and reading module includes a parallel hash generation module and a data reading and writing module.

[0029] At IF1 level, the fetch control module inputs the current fetch address to the branch predictor. The parallel hash generation module generates adjacent fetch addresses based on the current fetch address. The adjacent fetch address is the address of the next fetch packet adjacent to the current fetch packet. The parallel hash generation module performs hash operations on the current fetch address and the adjacent fetch address respectively, generating the BTB read index, BTB tag, and BHT read index corresponding to the current fetch packet query path and the adjacent fetch packet query path. For example, the width N of the BTB read index is 7 bits, and the width M of the BTB tag is 5 bits. An XOR operation can be performed on the PC[9:3], PC[16:10], and PC[23:17] of the current fetch address and the adjacent fetch address to generate a 7-bit BTB read index hash[9:3] for each of the current fetch packet query path and the adjacent fetch packet query path. An XOR operation can also be performed on PC[24:20], PC[19:15], and PC[14:10] to generate a 5-bit BTB tag hash[4:0] for each of the current fetch packet query path and the adjacent fetch packet query path. PC[9:3] represents the 4th to 10th bits of the current fetch address or the adjacent fetch address, and PC[16:10] represents the 11th to 17th bits of the current fetch address or the adjacent fetch address. The rest are similar and will not be elaborated further here. Furthermore, the parallel hash generation module uses the BTB read index of the current fetch packet query path or the adjacent fetch packet query path as the intermediate input hashin required to generate the BHT read index of the current fetch packet query path or the adjacent fetch packet query path. Then, it obtains the current 7-bit binary code ghr[6:0] of the front-end GHR, and XORs hashin[9:5] with ghr[6:2] to obtain the high 5 bits of the BHT read index, and uses ghr[1:0] as the low 2 bits of the BHT read index. Based on this principle, the 7-bit BHT read index of the current fetch packet query path and the adjacent fetch packet query path can be obtained. In this way, the 7-bit BHT read index is obtained by using the Gshare-type index generation method. Here, Gshare represents the Global Sharedbranch predictor, and Gshare is an abbreviation for Global Sharedbranch predictor. The Gshare-type index generation method refers to the method of mixing global historical information and address index information to generate the BHT index. It should be noted that hashin[9:5] represents the 6th to 10th bits of the intermediate input hashin, ghr[6:2] represents the 3rd to 7th bits of the current 7-bit binary code of the front-end GHR, and ghr[1:0] represents the 1st to 2nd bits of the current 7-bit binary code of the front-end GHR. Thus, IF1 level forms the BTB read index, BTB tag, and BHT read index for the current fetch packet query path and the adjacent fetch packet query path, respectively. Afterwards, BTB and BHT reading can be initiated.It should be noted that N and M are positive integers determined based on the BTB capacity, BHT capacity, and hash configuration, and their specific values ​​can be set according to actual needs.

[0030] In this invention, after obtaining the BTB read index and BHT read index corresponding to the current fetch packet query path and adjacent fetch packet query paths, the data reading and writing module reads data from the BTB and BHT respectively. Taking a BTB using two physical banks (i.e., Bank0 and Bank1) where each physical bank is a two-way grouped association (i.e., both Bank0 and Bank1 include way0 and way1) as an example, the BTB read index of the current fetch packet query path simultaneously accesses way0 and way1 at the corresponding index positions in Bank0 and Bank1, thereby reading four original table entries, called four candidate BTB table entries; adjacent fetch packet query paths read another four candidate BTB table entries in the same way, so the two query paths can read a maximum of eight candidate BTB table entries in total. These eight candidate BTB table entries only represent the original read data of each path under each physical bank in the two query paths. For BHT, the BHT read index of the current fetch packet query path is used to read the table data from Bank0 to Bank3, resulting in four BHT table entries. The BHT read index of the adjacent fetch packet query path is used to read the adjacent Bank table data required to supplement the cross-packet rearrangement. That is, the BHT read index of the adjacent fetch packet query path is also used to read the table data from Bank0 to Bank3, thus also resulting in four BHT table entries. The BHT read data from the two query paths will be rearranged in the same procedural order as BTB to form the historical jump tendency of the four candidate slots.

[0031] In this invention, the hit determination module performs hit determination on the candidate BTB entries read from the current fetch packet query path and adjacent fetch packet query paths at the IF2 level. For each path under each physical bank of each query path, the hit determination module compares the BTB tag corresponding to the query path with the BTB tag recorded in the candidate BTB entry of that path under that physical bank, and determines whether the valid bit in the candidate BTB entry is valid. Only when the BTB tags are consistent and the valid bit is valid is a tag hit result generated for that path under that physical bank, indicating that the candidate BTB entry for that path under that physical bank is a tag hit candidate BTB entry. For example, in a two-way group associativity implementation, the current fetch packet query path performs parallel hit determination on Bank0-way0, Bank0-way1, Bank1-way0, and Bank1-way1 respectively, and adjacent fetch packet query paths also perform corresponding parallel hit determination. The tag hit result obtained in this way still belongs to the tag hit result of the corresponding path under the corresponding physical bank of the current fetch packet query path or the adjacent fetch packet query path.

[0032] After obtaining the above tag hit results, the position expansion and rearrangement module first performs position expansion, and then performs program sequence rearrangement. Position expansion means that for each candidate BTB entry hit by a tag, based on the combination relationship between the slot offset flag boffset and the instruction length information pc4 in the candidate BTB entry hit by the tag, the original 2-byte position of the candidate BTB entry hit by the tag in the corresponding query path (i.e., the current fetch packet query path or the adjacent fetch packet query path) is determined, and the hit results of the physical bank and path corresponding to the candidate BTB entry hit by the tag, as well as the candidate BTB entry hit by the tag, are selected to the determined original 2-byte position. For example, based on the XOR result of boffset and pc4 in the candidate BTB entry hit by the tag, the original 2-byte position corresponding to the candidate BTB entry hit by the tag can be selected between the two original 2-byte positions corresponding to the physical Bank. This expands the tag hit results of each path under Bank0 and Bank1 into four original 2-byte positions in the current fetch packet query path and the adjacent fetch packet query path, and obtains the candidate BTB entries corresponding to the original 2-byte positions. In this way, it can be known which of the four original 2-byte positions covered by the current fetch packet query path and the adjacent fetch packet query path are BTB hits, and which candidate BTB entry the original 2-byte positions of the BTB hits specifically correspond to. It should be noted that the original 2-byte position corresponding to the candidate BTB entry hit by the tag is a BTB hit, while the original 2-byte position of the candidate BTB entry not hit by the tag is a non-BTB hit. Thus, the current fetch packet query path and the adjacent fetch packet query path each form their own original position hit vector and corresponding candidate BTB entries. Specifically, the original position hit vector of the current fetch packet query path or the adjacent fetch packet query path indicates the BTB hit status of each original 2-byte position covered by the current fetch packet query path or the adjacent fetch packet query path, that is, whether each original 2-byte position is a BTB hit. Subsequently, the position expansion and rearrangement module generates the starting position selection result based on the PC[2:1] of the current fetch address (PC[2:1] is the address bit in the current fetch address that represents the 2-byte starting offset), and selects four consecutive original 2-byte positions starting from the current fetch address from all the original 2-byte positions covered by the current fetch packet query path and the adjacent fetch packet query path, and uses these four original 2-byte positions as candidate slot 0, candidate slot 1, candidate slot 2, and candidate slot 3 in sequence, thereby obtaining four rearranged candidate slots.Specifically, when PC[2:1] is 00, the four rearranged candidate slots correspond to the original 2-byte positions 0, 1, 2, and 3 of the current fetch packet query path, respectively; when PC[2:1] is 01, the four rearranged candidate slots correspond to the original 2-byte positions 1, 2, and 3 of the current fetch packet query path, and the original 2-byte position 0 of the adjacent fetch packet query path, respectively; when PC[2:1] is 10, the four rearranged candidate slots correspond to the original 2-byte positions 2 and 3 of the current fetch packet query path, and the original 2-byte positions 0 and 1 of the adjacent fetch packet query path, respectively; when PC[2:1] is 11, the four rearranged candidate slots correspond to the original 2-byte position 3 of the current fetch packet query path, and the original 2-byte positions 0, 1, and 2 of the adjacent fetch packet query path, respectively. It should be noted that, before the reordering, the BTB hit status and candidate BTB entries corresponding to the four original 2-byte positions covered by the current fetch packet query path and adjacent fetch packet query paths are already known based on the candidate BTB entries hit by the tags. Therefore, after obtaining these four candidate slots, the BTB hit status and candidate BTB entries corresponding to each of these four candidate slots are also known. It should be noted that the candidate BTB entries corresponding to candidate slots where BTB is not hit are empty. In addition, since the BHT read indexes of the current fetch packet query path and adjacent fetch packet query paths each read a BHT entry for each original 2-byte position covered by the current fetch packet query path and adjacent fetch packet query paths, the BHT entries corresponding to each candidate slot are also known after obtaining these four candidate slots. This ensures that the BTB hit status, candidate BTB entries, and BHT entries (historical jump tendencies) of each candidate slot correspond to each other.

[0033] In this invention, for each candidate slot obtained by rearrangement, the direction prediction synthesis module determines the direction prediction result of the branch instruction at each candidate slot obtained by rearrangement based on the BTB hit status corresponding to the candidate slot obtained by rearrangement, the instruction type information (i.e., CALL flag, RET flag and unconditional jump flag) in the candidate BTB table entry, and the corresponding historical jump tendency. Specifically, when the candidate slot obtained by the rearrangement does not hit the BTB (Browser-Based Branch) instruction, it indicates that the candidate slot obtained by the rearrangement does not form a valid candidate branch instruction. A valid candidate branch instruction refers to the branch instruction at a candidate slot that has a BTB hit and is valid. When the candidate slot obtained by the rearrangement hits the BTB and the instruction type information indicates that the branch instruction at the candidate slot obtained by the rearrangement is a conditional branch instruction, the direction prediction bit of the historical jump tendency corresponding to the candidate slot obtained by the rearrangement is used as the direction prediction result of the branch instruction at the candidate slot obtained by the rearrangement. When the candidate slot obtained by the rearrangement hits the BTB and the instruction type information indicates that the branch instruction at the candidate slot obtained by the rearrangement is a function call instruction, a function return instruction, or an unconditional jump instruction, the direction prediction result of the branch instruction at the candidate slot obtained by the rearrangement is forcibly set to a jump, without relying on the direction learning result of the BHT. For example, when the instruction type information of the CALL flag, RET flag, and unconditional jump flag does not indicate a deterministic jump, the branch instruction at the candidate slot obtained by the rearrangement can be treated as a conditional branch instruction. The specific values ​​of the CALL flag, RET flag, and unconditional jump flag indicate whether a branch instruction is a conditional branch instruction, function call instruction, function return instruction, or unconditional jump instruction. For example, when the CALL flag is 1 and both the RET and unconditional jump flags are 0, the branch instruction is a CALL instruction; when both the CALL and unconditional jump flags are 0 and the RET flag is 1, the branch instruction is a RET instruction; and when both the CALL and RET flags are 0 and the unconditional jump flag is 1, the branch instruction is an unconditional jump instruction. It should be noted that an unconditional jump instruction refers to a jump instruction whose jump direction does not depend on runtime conditional judgment and whose semantics necessarily change the control flow, such as the jump and link (JAL) instruction in RISC-V. Therefore, in this invention, the branch predictor uses different direction generation methods for conditional branch instructions, unconditional jump instructions, function call instructions, and function return instructions. For deterministic jump instructions marked as CALL, RET, or unconditional jump in the BTB table, this invention forces their direction to "jump" regardless of the BHT prediction, thereby simplifying the learning process and improving the prediction speed of deterministic jumps.

[0034] In this invention, the first jump branch selection module is used to select, from all the candidate slots where the first branch instruction with a jump prediction result is located, from the candidate slots where the direction prediction synthesis module determines the direction prediction result of the branch instruction at each BTB hit candidate slot, thereby obtaining a selection result indicating whether there is a selected candidate slot. For example, the selection result is in one-hot code form.

[0035] In this invention, the target address and instruction mask generation module includes an instruction mask generation module and a target address generation module. The instruction mask generation module is used after the first jump branch selection module generates a selection result. When the selection result indicates the existence of a selected candidate slot, it generates control information to change the next instruction fetch address and generates a first instruction mask based on the position of the selected candidate slot. The first instruction mask indicates that all rearranged candidate slots after the selected candidate slot are invalid, so the IFU no longer processes branch instructions at these invalid rearranged candidate slots, while the selected candidate slot and the rearranged candidate slots before the selected candidate slot are valid. When the selection result indicates the absence of a selected candidate slot, a second instruction mask is generated. The second instruction mask indicates that all rearranged candidate slots are valid, so the IFU can process the entire current instruction fetch packet.

[0036] In this invention, after the first jump branch selection module generates the selection result, the target address generation module generates the predicted target address to be used by the current instruction fetch packet only for the selected candidate slot. Specifically, when the selection result shows that there is a selected candidate slot, the target address generation module reads the target address offset, instruction type information (i.e., CALL flag, RET flag, and unconditional jump flag) and instruction length information from the BTB entry corresponding to the selected candidate slot, and determines the instruction address (i.e., branch PC) of the branch instruction at the selected candidate slot according to the position of the current instruction fetch address and the selected candidate slot in the rearranged program order. It should be noted that the position of the candidate slot in the rearranged program order refers to its number among the four rearranged candidate slots. For example, when the four rearranged candidate slots are: candidate slot 0, candidate slot 1, candidate slot 2, and candidate slot 3, the numbers 0, 1, 2, and 3 here are the numbers of these four candidate slots, respectively. For example, when the selected candidate slot is candidate slot 2, the formula for calculating the branch PC of the branch instruction at candidate slot 2 is: branch PC = current fetch address + (number of the selected candidate slot × 2 bytes). When the branch instruction at the selected candidate slot is a conditional branch instruction, an unconditional jump instruction, or a function call instruction, the branch PC is added to the target address offset to obtain the predicted target address; while when the branch instruction at the selected candidate slot is a function return instruction and the RAS stack top address is valid, the RAS stack top address is used as the predicted target address. It should be noted that when the selection result indicates that there is no selected candidate slot, the target address generation module maintains the sequential instruction fetch path and does not generate a predicted target address for changing the next instruction fetch address.

[0037] In this invention, after obtaining the predicted target address and instruction mask, the branch predictor sends the predicted target address and instruction mask as the front-end prediction result to the back-end so that the back-end execution unit can execute it.

[0038] In this invention, the branch predictor further includes a speculative update module and a prediction error correction module. Specifically, the speculative update module is used to update the front-end GHR according to the rearranged candidate slot order (i.e., program order) when a valid candidate branch instruction exists in the current fetch packet. A valid candidate branch instruction refers to the branch instruction at a valid candidate slot that has been hit by the BTB. Specifically, the branch instruction at the selected candidate slot is called the first jump branch. Therefore, the speculative update module control front-end GHR uses binary code values ​​representing non-jump to record the direction prediction results of each valid candidate branch instruction located before the first jump branch and whose direction prediction result is non-jump. The control front-end GHR uses binary code values ​​representing jump to record the direction prediction result of the first jump branch. The candidate slots after the candidate slot where the first jump branch is located are invalidated by the first instruction mask and do not participate in the update of the status value in the front-end GHR. If there is no first jump branch in the current instruction fetch packet, but there are one or more valid candidate branch instructions, the control front-end GHR uses binary code values ​​representing non-jump to record the non-jump direction prediction results of these valid candidate branch instructions in program order (i.e., the arrangement order of the candidate slots). If there is no valid candidate branch instruction in the current instruction fetch packet, the value recorded in the front-end GHR remains unchanged.

[0039] In this invention, when the selected first jump branch is a CALL instruction, the speculative update module is also used to determine the next sequential address based on the instruction length information of the CALL instruction and push the next sequential address into the RAS; when the selected first jump branch is a RET instruction, the state of the RAS can be speculatively read or adjusted. Since the above updates of the front-end GHR and RAS occur before the actual execution result of the branch is determined, they are considered speculative updates. After the back-end execution unit determines the actual execution result of the corresponding branch instruction, it compares the actual jump direction and the actual target address with the front-end prediction result; if the jump direction or target address is inconsistent, a prediction error feedback packet is generated. The prediction error feedback packet may include the instruction address of the branch instruction or the BTB index, BTB tag, physical bank and path information used to locate the branch instruction, as well as the actual jump result, the correct target address offset, instruction type information, BHT update information, and the correct historical state value used to restore the front-end GHR, etc. It should be noted that the actual jump result indicates whether a jump occurs or not, while strong jump, weak jump, weak no jump, and strong no jump belong to the BHT saturation counter state and are not the actual execution result of the branch instruction.

[0040] In this invention, the prediction error correction module triggers pipeline flushing upon receiving a prediction error feedback packet from the backend execution unit, and corrects the binary code value or table entry content of at least one of the frontend GHR, BTB, BHT, and RAS according to the prediction error feedback packet. For example, when the prediction error feedback packet contains a correct historical state value, the correct historical state value is used to overwrite the historical state value currently recorded in the frontend GHR; when a jump actually occurs but the corresponding BTB table entry does not exist, a new BTB table entry is written according to the instruction address of the branch instruction or the corresponding BTB index, BTB tag, physical bank, path, slot offset flag, instruction length information, target address offset, and instruction type information; when a BTB table entry exists but any one or more of the target address offset, BTB tag, location-related information, and instruction type information are incorrect, the correct information is used for overwriting correction; for conditional branch instructions, the 2-bit saturation counter of the BHT is updated according to the actual jump result; for CALL and RET instructions, the state of the RAS is restored or corrected according to the feedback information.

[0041] In some embodiments, two or more threads may share a portion of the prediction resources. Therefore, the branch predictor further includes a parallel conflict detector, a hardware arbitrator, and an SRAM write-back delay module. The parallel conflict detector determines whether multiple threads (i.e., at least two threads) request to write to the same BTB or BHT entry in the same cycle. When at least two threads request to write to the same BTB or BHT entry in the same cycle, the hardware arbitrator determines the allowed write request from these at least two threads' write requests using a combination of static priority and dynamic polling. Unallowed write requests do not affect the processor architecture state. For BTB implemented using a single-write-port SRAM, when multiple threads generate valid write requests for different BTB entries in the same cycle, the SRAM write-back delay module serializes the allowed write requests (after conflict detection by the parallel conflict detector and arbitration by the hardware arbitrator) into consecutive cycle executions. In some embodiments, the branch predictor further includes a livelock avoidance module. The livelock avoidance module records the correction operations of each thread for the BTB index within a preset period. When a thread requests to write to a BTB index that has been corrected by another thread within the preset period, the write request of that thread is delayed or blocked for several periods. In other words, the livelock avoidance module can record the BTB index that has recently been corrected by each thread due to prediction errors. When it detects that another thread is about to write to a conflicting position that has just been corrected by the current thread, it temporarily blocks the corresponding write operation to avoid different threads repeatedly overwriting the same prediction table position, which would cause the predictor state to become unstable.

[0042] This invention designs a parallel, multi-level hybrid prediction architecture that can process multiple instructions within a single clock cycle, effectively overcoming the performance bottleneck of traditional single-branch prediction and significantly improving the instruction fetch efficiency of superscalar processors. Simultaneously, through built-in multi-threaded conflict detection, hardware arbitration combining priority and polling, and write-back latency and livelock avoidance mechanisms, this invention securely solves the problem of concurrent access to shared prediction resources in a multi-threaded environment, ensuring data consistency and system stability. Furthermore, by combining a closed-loop control method of speculative updates and prediction error correction, the branch predictor can achieve dynamic learning and state correction without sacrificing speed. Specialized optimizations for special instructions such as CALL / RET further improve the overall prediction accuracy.

[0043] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0044] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A branch predictor for a superscalar processor, characterized in that, include: The branch target buffer (BTB) has multiple entries for storing information about different branch instructions; The front-end global history register GHR is used to record the direction history of the latest N valid branch instructions; The branch history table (BHT) is used to record the historical jump trends of conditional branch instructions. The parallel hash generation and reading module is used to generate adjacent fetch addresses based on the current fetch address, and to generate BTB read index, BTB tag and BHT read index corresponding to the current fetch packet query path and the adjacent fetch packet query path in parallel based on the value of the front-end GHR record, and to read data from BTB and BHT using the BTB read index and BHT read index. The hit determination module is used to compare the BTB tag with the BTB tags in the read candidate BTB entries in parallel to determine whether each candidate BTB entry has a tag hit. The position expansion and rearrangement module is used to determine the original 2-byte position of the candidate BTB table entry hit by each tag in the corresponding query path, and use the current fetch address to select consecutive original 2-byte positions from the positions covered by the current fetch packet query path and the adjacent fetch packet query path as candidate slots obtained by multiple rearrangements, and determine the BTB hit status, candidate BTB table entry and read BHT table entry corresponding to each candidate slot; The direction prediction synthesis module is used to determine the direction prediction result of the branch instruction at each BTB-hit candidate slot based on the BTB hit status, BHT entry and candidate BTB entry corresponding to the candidate slot. The first jump branch selection module is used to select the candidate slot where the branch instruction to jump is located, as indicated by the first direction prediction result, and obtain the selection result indicating whether there is a selected candidate slot. The target address and instruction mask generation module is used to generate an instruction mask and the predicted target address to be finally used in the current instruction fetch packet based on the selection result. The position unpacking and rearrangement module is specifically used to determine the original 2-byte position of each candidate BTB entry hit by a tag in the current fetch packet query path or adjacent fetch packet query path based on the physical memory identifier, slot offset flag, and instruction length information in the candidate BTB entry hit by each tag. It obtains the current fetch packet query path and adjacent fetch packet query path by using the original 2-byte position corresponding to the candidate BTB entry hit by the tag in the current fetch packet query path and adjacent fetch packet query paths as the BTB hit position, and the original 2-byte position corresponding to the candidate BTB entry not hit by the tag as the BTB miss position. The query path checks the BTB hit status of each original 2-byte position. Based on the address bit representing the 2-byte start offset in the current fetch address, select multiple consecutive original 2-byte positions from all original 2-byte positions covered by the current fetch packet query path and the adjacent fetch packet query paths. These selected consecutive original 2-byte positions are used as multiple candidate slots obtained through rearrangement. At the same time, the BTB hit status, candidate BTB entries, and read BHT entries corresponding to each selected original 2-byte position are used as the BTB hit status, candidate BTB entries, and read BHT entries corresponding to a candidate slot obtained through rearrangement.

2. The branch predictor for the superscalar processor according to claim 1, characterized in that, A BTB has multiple entries, each of which stores the target address offset of an identified branch instruction, the BTB tag, the valid bit, instruction type information, instruction length information, and location-related information. The instruction type information includes an instruction type flag, and the location-related information includes a physical memory identifier and a slot offset flag. The front-end GHR is used to record the direction history of the latest N valid branch instructions using N-bit binary code. The direction history of a valid branch instruction is used to indicate whether the jump direction of the valid branch instruction is a jump. BHT has multiple entries, each of which stores the historical jump tendencies of a conditional branch instruction. The branch predictor also includes a return address stack (RAS); the RAS is used to push or pop addresses onto or from the stack.

3. The branch predictor for the superscalar processor according to claim 2, characterized in that, The parallel hash generation and reading module includes: A parallel hash generation module is used to perform parallel hash operations on specific bit segments of the current fetch address and adjacent fetch addresses to obtain the N-bit BTB read index and M-bit BTB tag corresponding to the current fetch packet query path and the adjacent fetch packet query path, respectively. The N-bit BTB read index corresponding to the current fetch packet query path and the adjacent fetch packet query path are used as intermediate inputs for generating the BHT index, and hashed with the N-bit binary code recorded by the front-end GHR, respectively, to obtain the N-bit BHT read index corresponding to the current fetch packet query path and the adjacent fetch packet query path, respectively. Here, N and M are both positive integers. When N is 7, the 7-bit BTB read index of the current fetch packet query path is obtained by performing an XOR operation on PC[9:3], PC[16:10] and PC[23:17] of the current fetch address, and the adjacent fetch address is hashed with the PC[9:3], Perform an XOR operation on PC[16:10] and PC[23:17] to obtain the 7-bit BTB read index of the adjacent fetch packet query path; when M is 5, perform an XOR operation on PC[24:20], PC[19:15] and PC[14:10] of the current fetch address to obtain the 5-bit BTB tag of the current fetch packet query path, and perform an XOR operation on PC[24:20], PC[19:15] and PC[14:10] of the adjacent fetch address to obtain the 5-bit BTB tag of the current fetch packet query path. C[14:10] performs an XOR operation to obtain the 5-bit BTB tag of the adjacent fetch packet query path, where PC[9:3] represents the 4th to 10th bits, PC[16:10] represents the 11th to 17th bits, PC[23:17] represents the 18th to 24th bits, PC[24:20] represents the 21st to 25th bits, PC[19:15] represents the 16th to 20th bits, and PC[14:10] represents the 11th to 15th bits; The data reading and writing module is used to read multiple entries from the BTB as multiple candidate BTB entries by using the BTB read index corresponding to the current fetch packet query path and the adjacent fetch packet query path, and to read multiple BHT entries from the BHT by using the BHT read index corresponding to the current fetch packet query path and the adjacent fetch packet query path.

4. The branch predictor for the superscalar processor according to claim 3, characterized in that, The hit determination module is specifically used to perform parallel comparisons between the BTB tag corresponding to the current instruction fetch query path and the BTB tags recorded in each candidate BTB table entry read using the query path for each query path. If the BTB tags are consistent and the valid bit in the candidate BTB table entry is valid, the tag of the candidate BTB table entry is determined to be hit; otherwise, the tag of the candidate BTB table entry is determined to be not hit.

5. The branch predictor for a superscalar processor according to claim 2, characterized in that, The direction prediction synthesis module is specifically used for each candidate slot. When the BTB hit status of the candidate slot indicates that the BTB is hit, it indicates that there is a branch instruction at the candidate slot. When the instruction type information recorded in the candidate BTB entry corresponding to the candidate slot indicates that the branch instruction at the candidate slot is a conditional branch instruction, the historical jump tendency corresponding to the candidate slot is used as the direction prediction result of the branch instruction at the candidate slot. When the BTB hit status of the candidate slot indicates a BTB hit, and the instruction type information recorded in the candidate BTB entry corresponding to the candidate slot indicates that the branch instruction at the candidate slot is an unconditional jump instruction, a function call instruction, or a function return instruction, the direction prediction result of the branch instruction at the candidate slot is predicted as a jump. The first jump branch selection module is specifically used to select the candidate slot where the first direction prediction result is a jump from all the candidate slots hit by BTB, and obtain the selection result indicating whether there is a selected candidate slot.

6. The branch predictor for a superscalar processor according to claim 2, characterized in that, The target address and instruction mask generation module includes: an instruction mask generation module; The instruction mask generation module is used to generate control information to change the next instruction fetch address when the selection result indicates that there is a selected candidate slot, and generate a first instruction mask according to the position of the selected candidate slot, wherein the first instruction mask indicates that all candidate slots after the selected candidate slot are invalid; and to generate a second instruction mask when the selection result indicates that there is no selected candidate slot, wherein the second instruction mask indicates that all rearranged candidate slots are valid.

7. The branch predictor for a superscalar processor according to claim 2, characterized in that, The target address and instruction mask generation module further includes: a target address generation module; The target address generation module is configured to: when the selection result indicates the existence of a selected candidate slot, read the target address offset and instruction type information from the candidate BTB entry corresponding to the selected candidate slot; when the read instruction type information indicates that the branch instruction at the selected candidate slot is a conditional branch instruction, an unconditional jump instruction, or a function call instruction, add the instruction address of the branch instruction at the selected candidate slot to the read target address offset to obtain the predicted target address; when the read instruction type information indicates that the branch instruction at the selected candidate slot is a function return instruction and the stack top address of the RAS is valid, use the stack top address of the RAS as the predicted target address; when the selection result indicates the absence of a selected candidate slot, maintain the sequential instruction fetch path and do not output the predicted target address used to change the next instruction fetch address.

8. The branch predictor for a superscalar processor according to claim 6, characterized in that, The predicted target address and the instruction mask constitute the front-end prediction result generated by the branch predictor; The instruction mask is used to indicate whether each candidate slot obtained from the plurality of rearrangements is valid; the branch predictor further includes: The speculative update module is used to record the direction prediction results of valid candidate branch instructions with non-jump properties before the first jump branch when there are valid candidate branch instructions in the current instruction fetch packet, and to record the direction prediction results of the first jump branch using binary code values ​​representing non-jump properties, and to store the recorded binary code values ​​in the front-end GHR; when there is no first jump branch but there are valid candidate branch instructions, it records the direction prediction results of the valid candidate branch instructions in the current instruction fetch packet using binary code values ​​representing non-jump properties, and stores the recorded binary code values ​​in the front-end GHR; and when the first jump branch is a function call instruction, it pushes the next address into the RAS in the order determined by the instruction length information of the function call instruction, wherein the first jump branch is the branch instruction at the selected candidate slot, and the valid candidate branch instruction refers to the branch instruction at the candidate slot that is hit by BTB and is valid; The prediction error correction module is used to trigger pipeline flushing when it receives a prediction error feedback packet after the execution unit executes the prediction result of the front end, and to correct the binary code value or table entry content of at least one of the front end GHR, BTB, BHT and RAS according to the prediction error feedback packet.

9. The branch predictor for a superscalar processor according to claim 2, characterized in that, The branch predictor also includes: Parallel conflict detectors are used to monitor whether at least two threads initiate write requests to the same BTB or BHT entry within the same period. A hardware arbitrator is used to arbitrate requests when at least two threads initiate write requests to the same BTB or BHT entry within the same cycle, using a combination of static priority and dynamic polling.

10. The branch predictor for a superscalar processor according to claim 9, characterized in that, The branch predictor also includes: The SRAM write-back delay module is used to serialize the write requests that have been reserved after conflict detection and arbitration into write requests in consecutive cycles when at least two threads generate valid write requests for different BTB entries in the same cycle, and the BTB is implemented with a single write port static random access memory.

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