Full-stack adaptation method and system for GIS three-dimensional modeling software based on domestic hardware and software environment

Abstract

The application provides a GIS three-dimensional modeling software full-stack adaptation method and system based on a domestic hardware and software environment, relates to the technical field of software and hardware collaborative design, and comprises the following steps: acquiring a plurality of IO waiting queue depths of an operating system kernel in a preset time period and initial three-dimensional grid data of a target region when a GIS three-dimensional modeling software initiates a loading request for a model of the target region; determining the spatial topological relationship and visibility parameters of a grid unit in the initial three-dimensional grid data to obtain target three-dimensional grid data; performing first-order difference calculation on the IO waiting queue depths to obtain a fluctuation trend and a depth change vector; obtaining a reading instruction sequence of a current scheduling period according to a priority label in the target three-dimensional grid data; obtaining a memory mapping matrix in a preset access delay matrix; and rendering the target region of the GIS three-dimensional modeling software based on the memory mapping matrix. The application improves the loading efficiency and overall rendering performance of GIS data.

Description

Technical Field

[0001] This application relates to the field of software and hardware co-design technology, and in particular to a full-stack adaptation method and system for GIS 3D modeling software based on domestic software and hardware environments. Background Technology

[0002] With the rapid development of digital twins and smart city construction, GIS 3D modeling software is being used more and more widely in fields such as urban planning and disaster prevention and mitigation. Promoting the full-stack migration and adaptation of GIS 3D modeling software to domestically produced processors and operating system platforms has become an inevitable trend in the current industry development.

[0003] Currently, for GIS software adaptation to domestic hardware and software environments, existing technologies mostly focus on recompiling code at the instruction set level or translating the interface of basic graphics APIs to achieve compatibility with the software's basic operating environment. When loading massive amounts of 3D models, existing solutions typically rely directly on the operating system's default general file system reading logic and basic random memory allocation mechanisms for low-level data scheduling.

[0004] However, this generic access mechanism fails to perceive the visual priority of different spatial data within a 3D scene, nor does it consider the differences in physical node distribution under domestic multi-core architectures. This results in a large amount of inefficient random data reads at the disk level, and the overhead of cross-domain memory access is extremely high. This causes frequent congestion bottlenecks when massive spatial data flows through the hardware bus, significantly slowing down the loading speed of the model scene and causing severe stuttering in image rendering. Therefore, existing technologies suffer from the technical problems of low loading efficiency of massive 3D data at the underlying level and excessively high cross-physical node scheduling latency leading to rendering stuttering. Summary of the Invention

[0005] The purpose of this application is to provide a full-stack adaptation method and system for GIS 3D modeling software based on domestic software and hardware environments, so as to solve the technical problems in the existing technology, such as low loading efficiency of massive 3D data at the underlying level and excessive scheduling latency across physical nodes, which leads to rendering lag.

[0006] Firstly, this application provides a full-stack adaptation method for GIS 3D modeling software based on a domestically developed software and hardware environment, including:

[0007] Obtain the depth of multiple I / O wait queues of the operating system kernel within a preset time period and the initial 3D mesh data of the target area when the GIS 3D modeling software initiates a loading request for the model of the target area;

[0008] Determine the spatial topology and visibility parameters of the grid cells in the initial 3D mesh data, and add the visibility parameters to the header bytes of the corresponding grid cells as priority markers to obtain the target 3D mesh data including spatial topology and priority markers;

[0009] The fluctuation trend is obtained by performing first-order difference calculation on the depth of the IO wait queue, and the fluctuation trend is transformed into a depth change vector.

[0010] Based on the priority markers in the target 3D mesh data, the reading path of the mesh cell in the target 3D mesh data is mapped to the logical block address. Based on the slope of the current scheduling cycle in the depth change vector, adjacent logical block addresses are spatially concatenated to obtain the reading instruction sequence of the current scheduling cycle.

[0011] Determine the current computing node used to process the data stream generated by the read instruction sequence, search for the target memory node with the smallest latency to the current computing node in the preset access latency matrix, allocate the data stream to the address space of the target memory node, and obtain the memory mapping matrix. The access latency matrix includes the latency value between any current computing node and any memory node.

[0012] The target area of ​​GIS 3D modeling software is rendered based on a memory mapping matrix.

[0013] Optionally, before rendering the target area of ​​the GIS 3D modeling software based on the memory mapping matrix, the method further includes:

[0014] Based on the starting address and data length in the memory mapping matrix, extract the vertex coordinates and normal vector of each mesh cell from the data stream of the target memory node;

[0015] Determine the data bus width of the graphics processor used to render the target area, and use the data bus width as the access step size to allocate the address of the vertex coordinates and normal vectors in the address space of the target memory node to obtain the aligned data stream.

[0016] The memory mapping matrix is ​​updated based on the starting address and data length occupied by the aligned data stream in the address space to obtain the updated memory mapping matrix.

[0017] Based on a memory-mapped matrix, the target area of ​​a GIS 3D modeling software is rendered, including:

[0018] The target area of ​​the GIS 3D modeling software is rendered based on the updated memory mapping matrix.

[0019] Secondly, this application provides a full-stack adaptation system for GIS 3D modeling software based on a domestically developed software and hardware environment, including:

[0020] The acquisition module is used to acquire the depth of multiple I / O wait queues of the operating system kernel and the initial three-dimensional mesh data of the target area when the GIS 3D modeling software initiates a loading request for the model of the target area within a preset time period.

[0021] The determination module is used to determine the spatial topological relationship and visibility parameters of the grid cells in the initial 3D mesh data, and add the visibility parameters to the header bytes of the corresponding grid cells as priority markers, so as to obtain the target 3D mesh data including spatial topological relationship and priority markers;

[0022] The calculation module is used to perform first-order difference calculation on the depth of the IO wait queue to obtain the fluctuation trend, and then convert the fluctuation trend into a depth change vector.

[0023] The mapping module is used to map the reading path of the grid cell in the target 3D grid data to the logical block address according to the priority mark in the target 3D grid data. Based on the slope of the current scheduling cycle in the depth change vector, adjacent logical block addresses are spatially concatenated to obtain the reading instruction sequence of the current scheduling cycle.

[0024] The determination module is also used to determine the current computing node for processing the data stream generated by the read instruction sequence, query the target memory node with the smallest latency to the current computing node in the preset access latency matrix, allocate the data stream to the address space of the target memory node, and obtain the memory mapping matrix. The access latency matrix includes the latency value between any current computing node and any memory node.

[0025] The rendering module is used to render the target area of ​​GIS 3D modeling software based on a memory-mapped matrix.

[0026] Thirdly, this application provides an electronic device, comprising:

[0027] Memory, used to store computer programs;

[0028] The processor is used to implement the steps of the full-stack adaptation method for GIS 3D modeling software based on the domestic software and hardware environment as described in the first aspect above when executing computer programs.

[0029] Fourthly, this application provides a computer-readable storage medium storing a computer program, which, when executed by a processor, can implement the steps of the full-stack adaptation method for GIS 3D modeling software based on a domestic software and hardware environment as described in the first aspect above.

[0030] The full-stack adaptation method for GIS 3D modeling software based on domestically developed hardware and software environments provided in this application ensures that subsequent scheduling can take into account both hardware status and business needs by simultaneously collecting the depth of multiple I / O wait queues of the underlying operating system kernel and the loading requests of upper-layer 3D mesh data. It achieves hierarchical processing of 3D spatial data, enabling the underlying access mechanism to accurately identify core visual data and breaking through the technical barrier of blind data reading in traditional solutions. It reduces the overhead of disk head seek-through, alleviating congestion during massive data flow on the bus. It achieves physical-level proximity storage, eliminating the high latency overhead caused by cross-node memory access in domestic multi-core architectures. It enables smooth, lag-free 3D scene presentation on a domestically developed hardware and software platform.

[0031] Furthermore, the priority markers determine the order of requests for multiple read paths corresponding to the grid cells. Then, the logical block addresses are obtained through the file mapping table, and a dynamic aggregation threshold is calculated by multiplying the absolute value of the slope in the depth change vector by the base value. Next, the position offsets of adjacent logical block addresses are compared with this aggregation threshold; if the position offset meets the condition, a concatenation operation is performed to generate contiguous address blocks. Finally, these contiguous address blocks are combined to construct the read instruction sequence for the current scheduling cycle. This solves the bus frequency blocking problem caused by random I / O reads, significantly shortens the turnaround time for loading the model scene from disk to memory, and thus eliminates the severe rendering stuttering caused by data supply delays at the source. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 A flowchart illustrating the full-stack adaptation method for GIS 3D modeling software based on a domestic software and hardware environment provided in this application embodiment;

[0034] Figure 2 A flowchart illustrating the method for obtaining the read instruction sequence of the current scheduling period provided in an embodiment of this application;

[0035] Figure 3 A flowchart illustrating the method for obtaining a memory mapping matrix provided in an embodiment of this application;

[0036] Figure 4 A schematic diagram of the structure of a full-stack adaptation system for GIS 3D modeling software based on a domestic software and hardware environment provided in this application embodiment;

[0037] Figure 5 This is a schematic diagram of the hardware structure of the electronic device provided in the embodiments of this application. Detailed Implementation

[0038] To address the technical barriers caused by existing adaptation technologies that only focus on instruction set compatibility, fail to perceive the semantic priority of GIS data, and ignore the physical topology differences of domestic multi-core architectures, this application quantifies the visibility parameters of initial 3D mesh data and transforms them into priority markers. This empowers the underlying access mechanism with the ability to identify core data from a business perspective, thus solving the problem of insufficient perception of 3D scenes by general access mechanisms. Simultaneously, by dynamically analyzing the depth of the operating system kernel IO wait queue, real-time load fluctuations are transformed into depth change vectors, providing quantified pressure feedback for instruction scheduling. Based on this, by coupling the upper-layer priority markers with the lower-layer slope depth, dynamic spatial splicing of logical block addresses is achieved, reconstructing the random IO that originally caused bus congestion into a continuous sequence of read instructions, thereby improving the loading efficiency of the underlying layer. Finally, addressing the pain point of high cross-node access latency in domestic architectures, an access latency matrix is ​​used to guide data flow to allocate memory in the nearest physical layer, establishing an optimal path memory mapping matrix. This achieves end-to-end resource alignment from disk and main memory to graphics rendering, resolving the technical contradiction between the lag in loading massive 3D data and rendering stuttering in domestic hardware and software environments.

[0039] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0040] The core of this application is to provide a full-stack adaptation method for GIS 3D modeling software based on a domestically developed software and hardware environment. A flowchart of one specific implementation method is shown below. Figure 1 As shown, the method includes:

[0041] Step 101: Obtain the depth of multiple I / O wait queues of the operating system kernel within a preset time period and the initial 3D mesh data of the target area when the GIS 3D modeling software initiates a loading request for the model of the target area.

[0042] In this step, the preset time period refers to the time window for high-frequency monitoring of hardware access status, which can be a continuous sampling period. The kernel layer refers to the core layer of software and hardware interaction that interfaces with application software above and manages computing and hardware resources below, providing basic service support. The IO wait queue depth refers to the number of pending read / write requests accumulated in the kernel access program at a specific sampling time, which can include the total number of synchronous read / write tasks and asynchronous pre-read tasks. Spatial information modeling software refers to the application layer program used to construct 3D geographic scenes and render them using the underlying graphics hardware. The target region refers to the geographic spatial range covered by the current viewpoint or specified loading in the 3D scene, which can be a region A enclosed by specific coordinates. Initial 3D mesh data refers to the original model file stored in an external physical medium and not processed by visibility marking, which can include the geometric vertex information, color information, and spatial structure information of the mesh cells.

[0043] In this embodiment, the depths of multiple I / O wait queues are first obtained by calling the kernel performance management interface. Specifically, within a preset time period... Internally, the system monitors the access status of external physical storage media in real time through the block multi-queue layer interface in the kernel, continuously polling and sampling at a fixed sampling period of ten milliseconds. This allows for the low-latency acquisition of multiple discrete values ​​reflecting the current physical access pressure, resulting in a numerical sequence. Simultaneously, it acquires the model loading request initiated by the spatial information modeling software for target region A. Then, based on the loading request, it retrieves the corresponding initial 3D mesh data from the external physical storage medium.

[0044] For example, to obtain the grid cells in target region A With grid cells The original binary file was parsed to obtain vertex coordinates. With normal vector geometric data set Then the numerical sequence With geometric data sets Recorded in the main storage space, it completes the synchronous collection of underlying hardware access load and upper-layer space business data.

[0045] Step 102: Determine the spatial topology and visibility parameters of the grid cells in the initial 3D mesh data, and add the visibility parameters to the header bytes of the corresponding grid cells as priority markers to obtain the target 3D mesh data including spatial topology and priority markers.

[0046] In this step, spatial topology refers to the adjacency and connection status of various mesh units in the 3D model. Visibility parameters refer to the visual importance of each mesh unit to the observer, determined based on the current rendering viewpoint. The header byte refers to the storage area at the beginning of the data structure used to store identification and control information. Priority markers are control markers used to indicate the order of lower-level read operations. The target 3D mesh data refers to the set of data to be accessed, generated after geometric analysis and visual weight calculation, and possessing priority attributes.

[0047] Step 201: Determine the vertex coordinates and normal vector of each grid cell in the initial 3D mesh data, and compare the overlap of the vertex coordinates of all grid cells to determine the spatial topological relationship between different grid cells.

[0048] In this step, vertex coordinates refer to the numerical values ​​of the spatial points in three-dimensional space that determine the geometry. Normal vectors refer to the numerical values ​​of the spatial direction perpendicular to the physical surface and pointing outwards.

[0049] In this embodiment, the underlying structure of the initial 3D mesh data is first parsed to obtain the coordinates of multiple vertices and the corresponding normal vectors for each mesh cell. To overcome the technical deficiency of the native 3D mesh data structure lacking a unified header identifier, when the system loads each mesh cell into memory, a dedicated starting storage area of ​​four bytes with a fixed length is forcibly allocated at the very beginning of the corresponding data block as a header byte, used for subsequent storage of priority markers. For example, to obtain the mesh cells of target region A... vertex coordinate sequence and grid cells vertex coordinate sequence And extract the mesh cells. normal vector .

[0050] Next, extract the coordinates of all vertices from any two different grid cells and perform numerical matching calculations. If two or more vertex coordinates are found to be completely identical, for example, if the comparison reveals a sequence of vertex coordinates... coordinates in With vertex coordinate sequence coordinates in If the values ​​are completely equal, it means that the two mesh cells share vertices in three-dimensional physical space, thus determining the mesh cell. With grid cells There are adjacent spatial topological relationships between them. The numerical matching calculations described above are performed by traversing all mesh cells in the initial 3D mesh data, ultimately yielding a complete spatial topological relationship matrix representing the overall model structure. Specifically, the spatial topological relation matrix An example in the form of a second-order square matrix is ​​shown below:

[0051]

[0052] Among them, matrix elements and The number 1 indicates a grid cell. With grid cells Spatial adjacency; matrix elements and A value of zero indicates that the element has no self-loop connections.

[0053] Step 202: Based on the viewing angle vector of the current rendered screen in the GIS 3D modeling software, calculate the surface area of ​​each grid cell, and multiply the normal vector of each grid cell with the viewing angle vector to obtain the cosine value of the included angle. Based on the cosine value of the included angle, determine the occlusion coefficient of each grid cell.

[0054] In this step, the rendered image refers to the real-time rasterized display of the 3D model on a 2D screen. The viewing angle vector is the numerical value representing the direction of the target's line of sight from the virtual camera's position to the center of the 3D scene. Surface area refers to the actual geometric size of the 2D plane occupied in 3D physical space. The cosine of the angle is the calculated cosine of the relative angle between two spatial vectors. The occlusion coefficient is a quantitative indicator representing the degree to which the back of a target faces the observer, used to determine whether it is occluded by objects in front.

[0055] In this embodiment, the current physical coordinates of the virtual camera and the target viewpoint coordinates are obtained, and the specific viewing angle vector is calculated using spatial vector subtraction. For example, the current viewing angle vector of target region A is calculated. Next, based on the grid cells... vertex coordinate sequence The coordinates of the three vertices are used to calculate the lengths of the three spatial sides of the triangle in the grid cell. , as well as The accurate surface area of ​​the grid cell was calculated using Heron's formula. The specific calculation formulas are shown in formulas (1) and (2):

[0056] (1)

[0057] (2)

[0058] in, This represents the half-perimeter value of the grid cell boundary. Then the grid cell... normal vector With the observation point vector Perform a dot product calculation to obtain the accurate cosine value of the included angle. .

[0059] Based on the cosine value of this included angle The positive or negative attribute determines the occlusion coefficient of each grid cell. Specifically, if the cosine value of the included angle... A value greater than zero indicates that the mesh cell is facing away from the observer, and the corresponding occlusion coefficient is set to a small value, such as the occlusion coefficient. The value range is set to 0 to 0.3; if the cosine value of the included angle is... A value less than or equal to zero indicates that the mesh cell is facing the observer, and the corresponding occlusion coefficient is set to a larger value, such as the occlusion coefficient. The value range is set to 0.7 to 1.0.

[0060] Step 203: Calculate the projected area of ​​each grid cell based on the surface area, the absolute value of the cosine of the included angle, and the preset distance attenuation factor.

[0061] In this step, the preset distance attenuation factor refers to the scaling adjustment value that simulates the visual principle of objects appearing larger when closer and smaller when farther away in real-world perspective projection. The projection area refers to the size of the pixel region occupied by an entity in three-dimensional physical space mapped onto the two-dimensional screen view plane.

[0062] In this embodiment of the application, the mesh cells are first obtained. The spatial straight-line distance between the geometric center 3D coordinates and the physical 3D coordinates of the virtual camera is calculated using the Euclidean distance algorithm. Next, obtain the pre-configured fundamental constants of the view frustum. The constant It is calculated using empirical parameters pre-quantized and converted from the current field of view and near clipping plane distance of the virtual camera during rendering of target area A, and then using the inverse square attenuation algorithm, i.e., through the formula. A mapping is performed to accurately calculate the preset distance attenuation factor corresponding to the spatial depth. .

[0063] Next, extract the cosine value of the included angle calculated in the previous step. And perform mathematical operations on it to obtain the absolute value. Utilizing surface area Multiply by the absolute value of the cosine of the included angle Calculate the orthogonal cross-sectional area of ​​the grid cell in the direction perpendicular to the line of sight, and then multiply the orthogonal cross-sectional area by a preset distance attenuation factor. The perspective projection simulation was completed, and the mesh elements were finally calculated. accurate projected area The specific calculations can be performed using formulas. The projected area sequence of all grid cells is obtained by iterating through the grid. .

[0064] Step 204: Based on preset weights, the occlusion coefficient and projected area of ​​each grid cell are weighted and summed to obtain the visibility parameters of each grid cell.

[0065] In this step, the preset weight refers to the calculated proportion of importance assigned to different indicators when assessing visual importance.

[0066] In this embodiment, the occlusion coefficient and projected area of ​​each grid cell calculated previously are extracted. Since the occlusion coefficient determines whether a grid cell is directly exposed to the field of view, and the projected area determines the visual pixel percentage of the grid cell in the displayed image, a first preset weight and a second preset weight are assigned to each. For example, for a grid cell... Set the first preset weight and the second preset weight First preset weight With the second preset weight The specific value is dynamically allocated based on the current remaining video memory capacity of the domestic graphics processor: when the remaining video memory capacity is lower than the safety threshold, the first preset weight is automatically increased. The proportion of the grid cells is adjusted to prioritize the removal of occluded grid cells in order to save video memory.

[0067] grid cells Occlusion coefficient Multiplied by the first preset weight Obtain the first product value, and then project the area. Multiplied by the second preset weight The second product value is obtained. The first and second product values ​​are then weighted and summed to obtain the visibility parameter, which comprehensively reflects the rendering priority of the mesh cells. The specific calculations can be performed using formulas. The visibility parameter sequence can be obtained through iterative calculation of all grid cells. .

[0068] Step 205: Convert the visibility parameter of each grid cell into a binary value and add the binary value to the header byte of the corresponding grid cell to obtain the priority mark of each grid cell. Combine the spatial topology, priority mark and grid cell to obtain the target 3D grid data.

[0069] In this step, binary values ​​refer to the machine-level basic data form composed of digits zero and one, used for identification by the underlying hardware access logic.

[0070] In this embodiment, the calculated decimal floating-point visibility parameters are numerically normalized and converted to underlying binary values ​​using a base conversion algorithm. For example, the grid cells... Visibility parameters Convert to the underlying binary numerical sequence Next, locate the header byte of the starting memory region of the corresponding grid cell data block, and then retrieve the binary value sequence. Priority marking is completed by directly writing to this memory region. The physical addition. Finally, the spatial topological relation matrix confirmed in the previous steps is added. The attribute description segment attached to the corresponding grid cell data block, combined with the newly written priority flag. The entire sequence is packaged and combined to ultimately generate a target 3D mesh data set carrying complete visual weight features and spatial structure features. .

[0071] Step 103: Perform first-order difference calculation on the depth of the IO wait queue to obtain the fluctuation trend, and transform the fluctuation trend into a depth change vector.

[0072] In this step, the fluctuation trend refers to the direction and severity of change in the underlying access pressure over a continuous time period. The depth change vector refers to the digital control structure generated by combining the time dimension features with the pressure change slope features in a multi-dimensional manner.

[0073] Step 301: Based on the sampling time of the IO wait queue depth, subtract the previous IO wait queue depth from the next IO wait queue depth in the adjacent IO wait queue depth to obtain multiple depth differences.

[0074] In this step, sampling time refers to the specific timestamp value recorded by the kernel performance management module to indicate the underlying access status. Depth difference refers to the difference in the number of underlying access requests queued between two adjacent timestamp values.

[0075] In this embodiment, the entire dynamic adjustment process is controlled by a clear triggering mechanism: whenever the GIS 3D modeling software initiates a batch model loading request for a new geographic region, a new current scheduling cycle is simultaneously triggered. Within this cycle, multiple IO wait queue depth sequences acquired within a preset time period are extracted. and the corresponding sampling time series For example, obtaining a sampling time sequence consisting of three consecutive sampling times. and the corresponding IO wait queue depth sequence The first-order difference algorithm is used to analyze the depth sequence of the I / O wait queue. Perform a step-by-step subtraction calculation. Specifically, subtract the IO wait queue depth corresponding to the previous sampling time from the IO wait queue depth corresponding to the later sampling time in adjacent sampling times to calculate multiple depth differences representing the increase or decrease in pressure. The specific calculation formula is as follows: ,in, Indicates the depth difference. Indicates the depth of the next IO wait queue. This represents the depth of the previous I / O wait queue. The depth difference sequence is calculated after traversing the entire sequence. .

[0076] Step 302: Arrange the depth differences according to the order of sampling time to obtain the fluctuation trend, and calculate the slope of the change of each depth difference in the fluctuation trend.

[0077] In this step, the slope of change refers to the rate at which the number of memory access requests in the queue increases or decreases during a specific time segment.

[0078] In this embodiment, multiple depth differences calculated based on the order of sampling time are aligned and arranged along the time dimension, and integrated into a fluctuation trend sequence representing continuous pressure changes. For example, the depth difference calculated above... Difference with depth Arrange the events in chronological order to generate a fluctuation trend sequence. Next, the time interval between adjacent sampling times is calculated.

[0079] Divide each depth difference by its corresponding time interval and perform the slope calculation step in the differential calculation to accurately obtain the slope of change for each depth difference. The specific calculation formula is as follows: ,in, Indicates the slope of change. Indicates the depth difference. Indicates the next sampling time. This represents the previous sampling time. The change slope sequence is obtained through global calculation. .

[0080] Step 303: Combine each sampling time and the corresponding change slope to obtain the depth change vector.

[0081] In this embodiment of the application, the previously acquired sampling time series is extracted. and the calculated slope sequence A key-value pair data mapping algorithm is used to map and bind each specific sampling time with the corresponding slope of change, forming multi-dimensional data nodes. These multi-dimensional data nodes are then concatenated and merged in chronological order to ultimately construct a depth change vector that guides subsequent dynamic aggregation instructions. .

[0082] For example, time With the first slope of change Bind, and set the time With the second slope of change After binding, splicing and merging, a depth change vector is generated that accurately quantifies the dynamic changes in the underlying physical disk pressure. .

[0083] Step 104: Based on the priority markers in the target 3D mesh data, map the reading path of the mesh cell in the target 3D mesh data to the logical block address. Based on the slope of the current scheduling cycle in the depth change vector, spatially concatenate adjacent logical block addresses to obtain the reading instruction sequence of the current scheduling cycle.

[0084] In this step, the read path refers to the character pointer data used in the application layer program to locate the target file position in the external physical medium. The logical block address is a unified numerical identifier used for data block addressing interactions between the kernel and the underlying storage controller. The current scheduling period refers to the time segment in which the kernel is executing access merging decisions and issuing instructions. The change slope refers to the rate at which the number of memory access request queues increases or decreases within a specific time segment. The read instruction sequence refers to the set of commands generated after contiguous address merging optimization, used to directly drive the underlying storage device to perform continuous read and write operations.

[0085] like Figure 2 As shown, Figure 2 This is a flowchart illustrating a method for obtaining the read instruction sequence of the current scheduling period, as provided in an embodiment of this application.

[0086] Step 401: Determine the request order of grid cells based on the priority markers in the target 3D grid data, and query multiple read paths for each grid cell stored in the GIS 3D modeling software based on the request order.

[0087] In this step, the request order refers to the order in which the underlying physical disk responds to data loading tasks for different grid cells.

[0088] In this embodiment, priority markers of the header bytes of each grid cell in the target 3D mesh data are extracted. A sorting algorithm is used to compare the binary values ​​corresponding to the extracted priority markers, arranging them in descending order of value, thereby accurately determining the request order corresponding to each grid cell. For example, parsing the target 3D mesh data of target region A and extracting the grid cells... With grid cells and grid cells Priority flags are used to determine the order in which requests are loaded, based on the flag values ​​from largest to smallest. .

[0089] Based on the predetermined request sequence The system initiates a retrieval operation to the file management module at the application layer. It sequentially queries and extracts multiple read paths storing the underlying model files of each grid cell to be loaded within the directory structure, and establishes an ordered read index based on visual weights. For example, the query retrieves the corresponding read path sequence. .

[0090] Step 402: Based on the preset file mapping table, map the reading path to the logical block address, multiply the preset base value by the absolute value of the change slope of the current scheduling cycle in the depth change vector to obtain the aggregation threshold, and subtract adjacent logical block addresses to obtain the position offset of adjacent logical block addresses.

[0091] In this step, the preset file mapping table refers to an index data structure that records the correspondence between application layer file paths and underlying physical storage locations, as shown in Table 1:

[0092] Table 1: Preset File Mapping Table

[0093]

[0094] The preset baseline value refers to the basic reference constant pre-configured based on the hardware disk throughput performance for smoothing dynamic calculations. The aggregation threshold is the dynamic boundary value used to determine whether two discrete storage addresses can be merged into a single consecutive read request. The location offset is the difference in distance between two adjacent storage addresses in the physical storage space.

[0095] In this embodiment, a preset file mapping table is invoked for a lookup and translation operation to obtain the read path sequence. Precise mapping translates into a sequence of logical block addresses that the underlying disk controller can recognize. For example, it transforms the read path sequence... Converted into the underlying logical block address sequence Extract depth change vector The slope of change that matches the current scheduling cycle Regarding the slope of this change Perform the absolute value mathematical operation and compare it with the preset base value. Perform multiplication calculations to dynamically generate an aggregation threshold that adapts to the current access pressure. Among them, the preset base values It is directly proportional to the maximum throughput of the underlying physical disk and inversely proportional to the average seek time of the read / write head; when poor seek performance of the storage device is detected, the system automatically increases the base value. This allows for greater tolerance for merging during periods of congestion. The specific calculation formula is as follows: .

[0096] Next in the logical block address sequence Extract the addresses of two adjacent logical blocks, subtract the address of the logical block that is physically earlier from the address of the logical block that is physically later, and calculate the specific offset of the adjacent logical block addresses. The specific calculation formula is as follows: ,in, Indicates the address of the next logical block. This indicates the address of the previous logical block.

[0097] For example, calculating the address of a logical block. With logical block address Obtain the first position offset Calculate the logical block address With logical block address Obtain the second position offset .

[0098] Step 403: If the position offset is less than or equal to the aggregation threshold, then the corresponding adjacent logical block addresses are concatenated to obtain multiple consecutive address blocks.

[0099] In this step, a contiguous address block refers to a large, contiguous physical address range that can be read at once after spatial splicing optimization.

[0100] In this embodiment, a logic judgment unit compares the calculated position offset with a dynamically generated aggregation threshold. If the position offset is less than or equal to the aggregation threshold, it indicates that the physical distance between the two adjacent logical block addresses is within the acceptable range for merging and capturing given the current hardware performance. At this point, an address merging instruction is directly triggered, concatenating the corresponding adjacent logical block addresses at the address space boundary. This concatenation refers to breaking the original discrete fragmentation limitations of the underlying file system, forcibly recombining and encapsulating the two discontinuous logical block address ranges into a single continuous physical read request at the driver level, eliminating the original head seek gap, and ultimately integrating and concatenating the discrete short addresses to obtain multiple continuous address blocks.

[0101] For example, the comparison revealed the first position offset. That is, a value of 50 is less than the aggregation threshold. That is, if the value is 60, then the logical block address will be... With logical block address Concatenate them into a single contiguous address block that includes the addressing ranges of both. If the position offset is greater than the aggregation threshold, the merging operation is not triggered, and the original logical block addresses remain independent. A comparison reveals the second position offset... Greater than the aggregation threshold Therefore, not logical block addresses Perform the splicing operation.

[0102] Step 404: Combine consecutive address blocks into a read instruction sequence for the current scheduling cycle.

[0103] In this embodiment, multiple consecutive address blocks and independent logical block addresses that failed to meet the concatenation conditions are collected. These are then processed according to the initially determined request order sequence. The aforementioned contiguous address blocks and independent logical block addresses are formatted and encapsulated according to the specifications of the underlying storage interface protocol. The encapsulated instruction data is then sequentially appended to the controller's transmit buffer queue, and finally combined to generate a sequence of read instructions specifically designed for direct delivery to the underlying storage hardware for batch fetching during the current scheduling cycle.

[0104] For example, concatenated consecutive address blocks With maintaining independent logical block addresses According to the order of requests The sorting requirements are encapsulated and merged to generate the read instruction sequence for the current scheduling period. It then outputs the data directly to the underlying hardware for efficient data reading.

[0105] Step 105: Determine the current computing node used to process the data stream generated by the read instruction sequence, query the target memory node with the smallest latency to the current computing node in the preset access latency matrix, allocate the data stream to the address space of the target memory node, and obtain the memory mapping matrix. The access latency matrix includes the latency value between any current computing node and any memory node.

[0106] In this step, the preset access latency matrix refers to a two-dimensional data table that has been pre-tested and recorded regarding the data transfer time between each physical processing core and each physical memory module in a multi-core architecture. The data stream refers to the continuous binary model data set returned by the underlying storage device after responding to a sequence of read instructions. The current compute node refers to the specific physical processing core allocated by the kernel to execute read scheduling tasks at the current moment in a multi-core processor architecture. The target memory node refers to the physical memory module that is closest to the current processing core and has the shortest data transfer time at the physical level. The address space refers to a contiguous range of available storage addresses partitioned within the physical memory module. The memory mapping matrix refers to an array structure that records the correspondence between data stream content and specific physical addresses in main memory. The latency value is a measure of the time overhead required for data to be transferred from a specific processing core to a specific memory module.

[0107] like Figure 3 As shown, Figure 3 This is a flowchart illustrating the method for obtaining a memory mapping matrix provided in an embodiment of this application.

[0108] Step 501: Extract the thread identifier of the worker thread used to process the data stream generated by the read instruction sequence from the process control block of the operating system kernel.

[0109] In this step, the process control block refers to the basic data structure in the underlying management program used to record and manage the running state of processes. A worker thread refers to a specific execution sequence that concurrently executes underlying hardware access scheduling tasks in the background of the program. A thread identifier is a unique alphanumeric code assigned to each independent execution sequence.

[0110] In this embodiment, the process control block region managing memory is accessed by calling the underlying core application programming interface. The data structure of this region is parsed to extract the thread identifier corresponding to the worker thread responsible for receiving data from the underlying disk and converting it into a data stream. For example, the worker thread responsible for loading model data in target region A is obtained, and its thread identifier is extracted from it. .

[0111] Step 502: Query the resource scheduling table of the operating system kernel based on the thread identifier, and determine the processor core that is currently processing the worker thread as the current computing node. The processor core is the physical computing core in a multi-core processor.

[0112] In this step, the resource scheduling table refers to the underlying mapping table that records the current allocation status of each physical hardware resource and the task load. The physical computing core refers to the independent silicon chip processing unit in a multi-core processor hardware architecture that actually undertakes instruction computation tasks.

[0113] In this embodiment, the thread identifier obtained previously is used as the retrieval primary key to perform a reverse matching query in the resource scheduling table of the underlying management program. By looking up the table, the physical computing core currently executing the worker thread is located, and this physical computing core is logically identified as the current computing node. For example, using the thread identifier... A query of the resource scheduling table revealed that the thread was running on a physical computing core. The above will be the core of physical calculation. Determined as the current computing node .

[0114] Step 503: Query the latency values ​​from the current computing node to multiple candidate memory nodes in the preset access latency matrix, and determine the candidate memory node corresponding to the minimum latency value as the target memory node.

[0115] In this step, candidate memory nodes refer to multiple independent memory modules on the motherboard that are available for allocation of physical memory space. The minimum latency value refers to the ideal evaluation value that has the shortest latency among multiple transmission time comparisons.

[0116] In this embodiment, based on the current computing node, data corresponding to the row or column of the node is extracted from a preset access latency matrix to obtain multiple latency values ​​from the node to multiple surrounding candidate memory nodes. The preset access latency matrix... During the system boot process, the underlying management program dynamically reads and loads data from the operating system's local information table into memory, accurately recording the microsecond-level transmission latency between hardware nodes in a NUMA architecture. Specifically, the preset access latency matrix... An example in the form of a second-order square matrix is ​​shown below:

[0117]

[0118] Among them, matrix elements arrive These represent the latency parameters between different computing nodes and different candidate memory nodes. A search algorithm is used to iterate and compare the multiple latency values, selecting the smallest latency value, and then identifying the candidate memory node corresponding to this smallest latency value as the target memory node with the fastest physical connection.

[0119] For example, query the current compute node to candidate memory node sequence The latency value was used to identify candidate memory nodes. The delay value is the element If the minimum value is found, then the candidate memory node will be selected. Target memory node identified .

[0120] Step 504: Write the data stream into the address space of the target memory node, and establish the storage correspondence between the data stream and the address space according to the starting address and data length of the address space to obtain the memory mapping matrix.

[0121] In this step, the starting address refers to the absolute memory location of the first byte of a contiguous block of physical memory. The data length refers to the total number of bytes occupied by the allocated memory space. The storage mapping relationship refers to the bidirectional mapping connection between the logical model file and the underlying physical memory location.

[0122] In this embodiment, a direct memory access controller is used to directly and at high speed write the data stream read from the disk into the address space of a defined target memory node. After writing is complete, the starting address of the address space and the length of the data stream are obtained through the memory management unit. The starting address and data length are associated and bound with the corresponding original model file index to establish a storage correspondence between the data stream and the physical hardware, thereby generating a memory mapping matrix to manage the memory region.

[0123] For example, writing a data stream to a target memory node. The address space, recording its starting address and data length Generate a memory mapping matrix that includes these positional parameters. .

[0124] Step 511: Based on the starting address and data length in the memory mapping matrix, extract the vertex coordinates and normal vector of each mesh cell in the data stream of the target memory node.

[0125] In this embodiment, based on the previously generated memory mapping matrix, the specific physical regions of continuous storage within the target memory node are accurately located. The data stream stored in this region is then formatted and parsed according to the recorded starting address and data length. Useless header padding bytes are skipped, and the vertex coordinates and normal vectors belonging to each mesh cell for subsequent graphics pipeline processing are precisely extracted.

[0126] For example, according to the memory mapping matrix The starting address in With data length In the target memory node Accurately extract the data stream and extract the grid cells from it. vertex coordinate sequence and normal vector .

[0127] Step 512: Determine the data bus width of the graphics processor used to render the target area. Using the data bus width as the access step size, allocate addresses for the vertex coordinates and normal vectors in the address space of the target memory node to obtain an aligned data stream.

[0128] In this step, the graphics processing unit (GPU) refers to a dedicated computing chip specifically designed to execute high-concurrency rendering instructions and manage the graphics rendering pipeline. The data bus width refers to the maximum number of bits of data that the GPU can read in parallel from video memory or main memory in a single clock cycle. The access step size refers to the minimum contiguous data block alignment length set during memory address allocation. The aligned data stream refers to an optimized set of data that has been rearranged to perfectly fit the hardware read bit width.

[0129] In this embodiment, the underlying hardware specifications of the graphics processor currently used to perform the rendering task are obtained by calling the hardware diagnostic interface, and its data bus width is determined. This data bus width is directly set as the access step size for memory address arrangement. According to the boundary requirements of this access step size, the extracted vertex coordinates and normal vectors are reallocated as consecutive physical addresses in the address space of the target memory node. By inserting padding bytes or adjusting the order, it is ensured that the starting position of each data block is located at an address that is an integer multiple of the access step size, ultimately resulting in an aligned data stream.

[0130] For example, obtaining the data bus width of the graphics processor. Then, based on the data bus width To access the step size of the vertex coordinate sequence and normal vector The data is rearranged by introducing a boundary padding mechanism during physical address rearrangement. Whitespace padding bytes are automatically calculated and inserted at the end of vertex data packets, forcing that the starting physical memory address of the rearranged data block and the size of a single burst transfer are strictly aligned to the data bus width. This is done by using integer multiples of the specified data type to eliminate bus addressing misalignments and generate aligned data streams that meet hardware throughput requirements. .

[0131] Step 513: Update the memory mapping matrix according to the starting address and data length occupied by the aligned data stream in the address space to obtain the updated memory mapping matrix.

[0132] In this embodiment, by monitoring the physical location changes of the aligned data stream after its rearrangement in the target memory node, the latest starting address and corresponding data length of the aligned data stream in the address space are obtained. These latest location parameters are then used to overwrite the original memory mapping matrix, updating the old mapping records to the aligned storage relationships, ultimately resulting in an updated memory mapping matrix.

[0133] For example, obtaining the aligned data stream The starting address is updated to and data length updated to Using the starting address and data length Refresh memory mapping matrix The updated memory mapping matrix is ​​obtained. .

[0134] Step 514: Based on the memory mapping matrix, render the target area of ​​the GIS 3D modeling software, including:

[0135] The target area of ​​the GIS 3D modeling software is rendered based on the updated memory mapping matrix.

[0136] In this embodiment of the application, rendering the target area of ​​the GIS 3D modeling software based on the memory mapping matrix is ​​replaced by rendering the target area of ​​the GIS 3D modeling software based on the updated memory mapping matrix.

[0137] Step 5141: Based on the starting address and data length in the updated memory mapping matrix, perform spatial projection on the vertex coordinates corresponding to the aligned data stream in the target memory node to obtain multiple screen coordinates.

[0138] In this step, screen coordinates refer to the two-dimensional coordinate values ​​that represent the specific positions of the vertices of the three-dimensional model on the two-dimensional display medium.

[0139] In this embodiment, a graphics processor is used to extract the starting address and data length recorded in the updated memory mapping matrix. For example, the updated memory mapping matrix is ​​extracted. The starting address in and data length According to this starting address and data length From the target memory node Accurately read the aligned data stream And the mesh elements of target region A are extracted from them. vertex coordinate sequence Next, pre-defined view transformation and projection transformation matrices are introduced. The extracted vertex coordinates are then multiplied by the view transformation and projection transformation matrices respectively, completing perspective division and viewport mapping from the world coordinate system to the screen coordinate system, ultimately yielding multiple screen coordinates.

[0140] Specifically, let the view transformation matrix be a fourth-order square matrix. The projection transformation matrix is ​​a fourth-order square matrix. , vertex coordinate sequence Three-dimensional vertex coordinates, such as coordinates Extend to homogeneous coordinates and substitute into the formula: ,in, This represents the transformed two-dimensional screen coordinates. It is achieved through the vertex coordinate sequence. Batch matrix calculations are performed on all vertices to finally output the mesh cells. Corresponding screen coordinate sequence .

[0141] Step 5142: Determine multiple projection areas based on screen coordinates, and divide each projection area into multiple pixel segments based on a preset pixel resolution.

[0142] In this step, the projection area refers to a closed two-dimensional geometric region bounded by multiple screen coordinates connected end-to-end on a two-dimensional display screen. The preset pixel resolution refers to the pre-defined density values ​​of the light-emitting dot array in the horizontal and vertical directions of the display medium. A pixel segment refers to the smallest discrete image unit that constitutes the two-dimensional projection area and awaits illumination and color calculation.

[0143] In this embodiment, the screen coordinates calculated previously are extracted. Multiple screen coordinates belonging to the same grid cell are connected by line segments on a two-dimensional plane to determine the multiple projection areas occupied by each grid cell on the screen. For example, the grid cells... Corresponding screen coordinate sequence Screen coordinates With screen coordinates and screen coordinates Connect the line segments sequentially to define a closed triangular projection area on the screen. Next, the preset pixel resolution of the underlying hardware device is obtained. Based on the pixel grid size determined by this preset pixel resolution, a rasterization discretization operation is performed on the two-dimensional space within the projection area. Each grid cell falling within the projection area is determined as an independent pixel segment, ultimately dividing the continuous projection area into multiple pixel segments.

[0144] For example, obtaining the preset pixel resolution of the current display device. Based on the preset pixel resolution The above projection area Divide into multiple discrete pixel grids to generate a sequence of pixel segments. .

[0145] Step 5143: Calculate the angle between each normal vector in the aligned data stream and the preset ray direction vector, and determine the pixel color value of each pixel segment based on the angle value.

[0146] In this step, the preset light direction vector refers to the three-dimensional spatial vector parameter simulating the direction of light source illumination in the virtual scene. The included angle value is a measure of the spatial angle between the physical surface normal direction and the light illumination direction. The pixel color value is the specific value that determines the brightness of the three primary colors (red, green, and blue) displayed by the final screen pixels.

[0147] In this embodiment, a preset ray direction vector is extracted from the graphics rendering engine, and the normal vector corresponding to each mesh cell is extracted from the alignment data stream. Using vector dot product and the inverse cosine function, the angle between each normal vector in the alignment data stream and the preset ray direction vector is calculated. For example, extracting mesh cells... normal vector and the preset light direction vector provided by the engine. Calculate the normal vector With the preset light direction vector The included angle value The specific calculation formula is shown in formula (3):

[0148] (3)

[0149] in, This represents the magnitude of the normal vector. This represents the magnitude of the ray direction vector. Then, based on the diffuse lighting model, the calculated angle value is used to evaluate the light intensity of the current plane. The model's preset base color value is obtained and multiplied by the light intensity parameter derived from the angle value to determine the specific color and brightness of each pixel segment, generating the pixel color value.

[0150] For example, obtaining grid cells Basic color values Combined with the included angle value The corresponding light intensity is adjusted to determine the brightness of the pixel segment sequence. The pixel color value corresponding to each pixel segment is used to generate the final pixel color value sequence. .

[0151] Step 5144: Write the pixel color values ​​into the frame buffer of the display device to drive the display device to emit light, thus completing the rendering of the target area of ​​the GIS 3D modeling software.

[0152] In this step, the display device refers to the physical terminal that converts electronic signals into visible light signals for output. The frame buffer is a specific high-speed storage area dedicated to storing the full-screen pixel color data waiting to be output to the screen.

[0153] In this embodiment, a physical communication interface is established between the underlying processing hardware and the external display device. All pixel color values ​​calculated in the preceding steps are converted to a format that conforms to the standard data protocol of the digital video interface. Then, these formatted pixel color values ​​are written in batches to the frame buffer inside the display device.

[0154] For example, grid cells Corresponding pixel color value sequence It is converted to the standard communication protocol format and directly written to the frame buffer at the corresponding target area A screen location. Inside, once all the pixel color values ​​of a frame are written to the frame buffer, the display controller reads the data from the frame buffer and generates the corresponding driving electrical signal. This driving signal is then used to directly drive each physical pixel on the display panel to emit light, thus completing the high-frame-rate rendering loop for the target area's 3D model. The hardware display controller reads the frame buffer. The pixel color value sequence stored in This drives the corresponding pixel array on the physical display panel to emit light, ultimately completing the high-speed visual rendering output of the target area A in the GIS 3D modeling software.

[0155] This application embodiment ensures that subsequent scheduling can balance hardware status and business needs by simultaneously collecting the depth of multiple IO wait queues of the underlying operating system kernel and the loading requests of upper-layer 3D mesh data. It achieves hierarchical processing of 3D spatial data, enabling the underlying access mechanism to accurately identify core visual data and breaking through the technical barrier of blind data reading in traditional solutions. It reduces the overhead of disk head seek-through, alleviating congestion during massive data flow on the bus. It achieves physical-level proximity storage, eliminating the high latency overhead caused by cross-node memory access in domestic multi-core architectures. It achieves smooth, lag-free 3D scene presentation on a domestically developed hardware and software platform.

[0156] Figure 4 This is a schematic diagram illustrating a specific implementation of a full-stack adaptation system for GIS 3D modeling software based on a domestically developed software and hardware environment, as provided in this application. (Refer to...) Figure 4 The system may include:

[0157] The acquisition module 21 is used to acquire the depth of multiple I / O wait queues of the operating system kernel within a preset time period and the initial three-dimensional mesh data of the target area when the GIS three-dimensional modeling software initiates a loading request for the model of the target area.

[0158] The determination module 22 is used to determine the spatial topological relationship and visibility parameters of the grid cells in the initial three-dimensional grid data, and add the visibility parameters to the header bytes of the corresponding grid cells as priority markers to obtain target three-dimensional grid data including spatial topological relationship and priority markers;

[0159] Calculation module 23 is used to perform first-order difference calculation on the depth of the IO waiting queue to obtain the fluctuation trend, and convert the fluctuation trend into a depth change vector;

[0160] The mapping module 24 is used to map the reading path of the grid cell in the target three-dimensional grid data to the logical block address according to the priority mark in the target three-dimensional grid data, and to spatially concatenate adjacent logical block addresses according to the change slope of the current scheduling cycle in the depth change vector to obtain the reading instruction sequence of the current scheduling cycle.

[0161] The determination module 22 is also used to determine the current computing node for processing the data stream generated by the read instruction sequence, query the target memory node with the smallest delay to the current computing node in the preset access delay matrix, allocate the data stream to the address space of the target memory node, and obtain the memory mapping matrix. The access delay matrix includes the delay value between any current computing node and any memory node.

[0162] Rendering module 25 is used to render the target area of ​​GIS 3D modeling software based on a memory mapping matrix.

[0163] The GIS 3D modeling software full-stack adaptation system based on domestic software and hardware environment in this application embodiment is used to implement the aforementioned GIS 3D modeling software full-stack adaptation method based on domestic software and hardware environment. Therefore, the specific implementation of the GIS 3D modeling software full-stack adaptation system based on domestic software and hardware environment can be found in the embodiment section of the GIS 3D modeling software full-stack adaptation method based on domestic software and hardware environment above. The specific implementation can be referred to the description of the corresponding embodiment, and will not be repeated here.

[0164] Figure 5 A schematic diagram of the hardware structure of the electronic device provided in an embodiment of this application is shown.

[0165] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for implementing the steps of the above-described full-stack adaptation method for GIS 3D modeling software based on a domestic software and hardware environment when executing the computer program.

[0166] The electronic device may include a processor 510 and a memory 520 storing computer program instructions.

[0167] Specifically, the processor 510 may include a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits that can be configured to implement the embodiments of this application.

[0168] Memory 520 may include mass storage for data or instructions. For example, and not limitingly, memory 520 may include a hard disk drive (HDD), floppy disk drive, flash memory, optical disk, magneto-optical disk, magnetic tape, or Universal Serial Bus (USB) drive, or a combination of two or more of these. Where appropriate, memory 520 may include removable or non-removable (or fixed) media. Where appropriate, memory 520 may be internal or external to the integrated gateway disaster recovery device. In a particular embodiment, memory 520 is non-volatile solid-state memory.

[0169] Memory may include read-only memory (ROM), random access memory (RAM), disk storage media devices, optical storage media devices, flash memory devices, and electrical, optical, or other physical / tangible memory storage devices. Therefore, typically, memory includes one or more tangible (non-transitory) computer-readable storage media (e.g., memory devices) encoded with software including computer-executable instructions, and when the software is executed (e.g., by one or more processors), it is operable to perform the operations described with reference to the method according to the first aspect of this disclosure.

[0170] The processor 510 reads and executes computer program instructions stored in the memory 520 to implement the full-stack adaptation method for any GIS 3D modeling software based on a domestic software and hardware environment in the above embodiments.

[0171] In one example, the electronic device may also include a communication interface 530 and a bus 540. Wherein, such as Figure 5 As shown, the processor 510, memory 520, and communication interface 530 are connected through bus 540 and complete communication with each other.

[0172] The communication interface 530 is mainly used to realize communication between various modules, devices, units and / or equipment in the embodiments of this application.

[0173] Bus 540 includes hardware, software, or both, that couples components of an online data traffic metering device together. For example, and not limitingly, the bus may include an Accelerated Graphics Port (AGP) or other graphics bus, an Enhanced Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), HyperTransport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an Infinite Bandwidth Interconnect, a Low Pin Count (LPC) bus, a memory bus, a Microchannel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local (VLB) bus, or other suitable buses, or combinations of two or more of these. Where appropriate, bus 540 may include one or more buses. Although specific buses are described and illustrated in embodiments of this application, this application contemplates any suitable bus or interconnect.

[0174] This application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of any of the above-described full-stack adaptation methods for GIS 3D modeling software based on a domestic software and hardware environment.

[0175] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as USB flash drives, read-only memory, random access memory, portable hard drives, magnetic disks, or optical disks.

[0176] Embodiments of the present invention also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the embodiments of the full-stack adaptation method for GIS 3D modeling software based on a domestic software and hardware environment.

[0177] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0178] The foregoing has provided a detailed description of the full-stack adaptation method and system for GIS 3D modeling software based on a domestically developed software and hardware environment provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and its core ideas. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of this application.

Claims

1. A full-stack adaptation method for GIS 3D modeling software based on domestically produced software and hardware environment, characterized in that: include: The depth of multiple I / O wait queues of the operating system kernel and the initial three-dimensional mesh data of the target area when the GIS three-dimensional modeling software initiates a loading request for the model of the target area within a preset time period are obtained. The spatial topological relationship and visibility parameters of the grid cells in the initial 3D mesh data are determined, and the visibility parameters are added to the header bytes of the corresponding grid cells as priority markers to obtain target 3D mesh data including the spatial topological relationship and the priority markers; The fluctuation trend is obtained by performing a first-order difference calculation on the depth of the IO waiting queue, and the fluctuation trend is transformed into a depth change vector. Based on the priority markers in the target 3D mesh data, the reading paths of the mesh cells in the target 3D mesh data are mapped to logical block addresses. Based on the slope of the current scheduling cycle in the depth change vector, adjacent logical block addresses are spatially concatenated to obtain the reading instruction sequence of the current scheduling cycle. The current computing node for processing the data stream generated by the read instruction sequence is determined. The target memory node with the smallest latency to the current computing node is queried in the preset access latency matrix. The data stream is allocated to the address space of the target memory node to obtain a memory mapping matrix. The access latency matrix includes the latency value between any current computing node and any memory node. Based on the memory mapping matrix, the target area of ​​the GIS 3D modeling software is rendered.

2. The method according to claim 1, characterized in that, Before rendering the target area of ​​the GIS 3D modeling software based on the memory mapping matrix, the method further includes: Based on the starting address and data length in the memory mapping matrix, extract the vertex coordinates and normal vector of each mesh cell from the data stream of the target memory node; The data bus width of the graphics processor used to render the target region is determined. Using the data bus width as the access step size, the vertex coordinates and the normal vector are allocated in the address space of the target memory node to obtain an aligned data stream. The memory mapping matrix is ​​updated based on the starting address and data length occupied by the aligned data stream in the address space to obtain the updated memory mapping matrix. The rendering of the target area of ​​the GIS 3D modeling software based on the memory mapping matrix includes: Based on the updated memory mapping matrix, the target area of ​​the GIS 3D modeling software is rendered.

3. The method according to claim 2, characterized in that, Based on the updated memory mapping matrix, the target area of ​​the GIS 3D modeling software is rendered, including: Based on the starting address and data length in the updated memory mapping matrix, spatial projection is performed on the vertex coordinates corresponding to the aligned data stream in the target memory node to obtain multiple screen coordinates; Multiple projection areas are determined based on the screen coordinates, and each projection area is divided into multiple pixel segments based on a preset pixel resolution. Calculate the angle between each normal vector in the aligned data stream and the preset ray direction vector, and determine the pixel color value of each pixel segment based on the angle value; The pixel color values ​​are written into the frame buffer of the display device to drive the display device to emit light, thereby completing the rendering of the target area of ​​the GIS 3D modeling software.

4. The method according to claim 1, characterized in that, Determine the spatial topological relationships and visibility parameters of the mesh cells in the initial 3D mesh data, and add the visibility parameters to the header bytes of the corresponding mesh cells as priority markers to obtain target 3D mesh data including the spatial topological relationships and the priority markers, including: The vertex coordinates and normal vector of each grid cell in the initial three-dimensional mesh data are determined, and the overlap of the vertex coordinates of all grid cells is compared to determine the spatial topological relationship between different grid cells. Based on the viewing angle vector of the current rendered image of the GIS 3D modeling software, the surface area of ​​each grid cell is calculated, and the normal vector of each grid cell is multiplied by the viewing angle vector to obtain the cosine value of the included angle. The occlusion coefficient of each grid cell is determined based on the cosine value of the included angle. The projected area of ​​each grid cell is calculated based on the surface area, the absolute value of the cosine of the included angle, and a preset distance attenuation factor. Based on preset weights, the occlusion coefficient and projected area of ​​each grid cell are weighted and summed to obtain the visibility parameters of each grid cell; The visibility parameter of each grid cell is converted into a binary value, and the binary value is added to the header byte of the corresponding grid cell to obtain the priority tag of each grid cell. The spatial topology relationship, the priority tag, and the grid cell are combined to obtain the target three-dimensional grid data.

5. The method according to claim 1, characterized in that, The fluctuation trend is obtained by performing a first-order difference calculation on the depth of the IO waiting queue, and the fluctuation trend is transformed into a depth change vector, including: Based on the sampling time of the IO wait queue depth, the depth of the next IO wait queue in adjacent IO wait queues is subtracted from the depth of the previous IO wait queue to obtain multiple depth differences. The depth differences are arranged in chronological order of the sampling times to obtain the fluctuation trend, and the slope of change of each depth difference in the fluctuation trend is calculated. The depth change vector is obtained by combining each sampling time and the corresponding change slope.

6. The method according to claim 1, characterized in that, Based on the priority markers in the target 3D mesh data, the read paths of the mesh cells in the target 3D mesh data are mapped to logical block addresses. Based on the slope of the current scheduling cycle in the depth change vector, adjacent logical block addresses are spatially concatenated to obtain the read instruction sequence for the current scheduling cycle, including: Based on the priority markers in the target 3D mesh data, the request order of the mesh cells is determined, and based on the request order, multiple read paths for each mesh cell stored in the GIS 3D modeling software are queried. Based on a preset file mapping table, the reading path is mapped to a logical block address. The preset base value is multiplied by the absolute value of the change slope of the current scheduling cycle in the depth change vector to obtain the aggregation threshold. The adjacent logical block addresses are subtracted to obtain the position offset of the adjacent logical block addresses. If the position offset is less than or equal to the aggregation threshold, then the corresponding adjacent logical block addresses are concatenated to obtain multiple consecutive address blocks; The consecutive address blocks are combined into a read instruction sequence for the current scheduling period.

7. The method according to claim 1, characterized in that, The current computing node for processing the data stream generated by the read instruction sequence is determined. A target memory node with the lowest latency to the current computing node is searched in a preset access latency matrix. The data stream is allocated to the address space of the target memory node, resulting in a memory mapping matrix. The access latency matrix includes latency values ​​between any current computing node and any memory node, including: Extract the thread identifier of the worker thread used to process the data stream generated by the read instruction sequence from the process control block of the operating system kernel; Based on the thread identifier, the resource scheduling table of the operating system kernel is queried to determine the processor core that is processing the worker thread as the current computing node. The processor core is the physical computing core in a multi-core processor. The latency values ​​from the current computing node to multiple candidate memory nodes are queried in the preset access latency matrix, and the candidate memory node corresponding to the minimum latency value is determined as the target memory node. The data stream is written into the address space of the target memory node, and a storage correspondence between the data stream and the address space is established based on the starting address and data length of the address space to obtain a memory mapping matrix.

8. A full-stack adaptation system for GIS 3D modeling software based on domestically developed software and hardware environment, characterized in that: include: The acquisition module is used to acquire the depth of multiple I / O wait queues of the operating system kernel and the initial three-dimensional mesh data of the target area when the GIS three-dimensional modeling software initiates a loading request for the model of the target area within a preset time period; The determination module is used to determine the spatial topological relationship and visibility parameters of the grid cells in the initial three-dimensional grid data, and add the visibility parameters to the header bytes of the corresponding grid cells as priority markers to obtain target three-dimensional grid data including the spatial topological relationship and the priority markers; The calculation module is used to perform first-order difference calculation on the depth of the IO waiting queue to obtain the fluctuation trend, and convert the fluctuation trend into a depth change vector. The mapping module is used to map the reading path of the grid cell in the target 3D grid data to a logical block address according to the priority marker in the target 3D grid data, and to spatially concatenate adjacent logical block addresses according to the slope of the current scheduling cycle in the depth change vector to obtain the reading instruction sequence of the current scheduling cycle. The determination module is further configured to determine the current computing node for processing the data stream generated by the read instruction sequence, query the target memory node with the smallest latency to the current computing node in the preset access latency matrix, allocate the data stream to the address space of the target memory node, and obtain a memory mapping matrix. The access latency matrix includes the latency value between any current computing node and any memory node. The rendering module is used to render the target area of ​​the GIS 3D modeling software based on the memory mapping matrix.

9. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the full-stack adaptation method for GIS 3D modeling software based on a domestic software and hardware environment as described in any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, which, when executed by a processor, can implement the full-stack adaptation method for GIS 3D modeling software based on a domestically produced software and hardware environment as described in any one of claims 1 to 7.

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