A pipeline architecture and a method for reducing interrupts for traveling salesman problem reasoning

Abstract

The application provides a pipeline architecture and a method for reducing interruption of travel salesman problem reasoning, comprising: a pipeline execution unit configured to execute multiple iterations in time overlap; an interruption triggering unit configured to monitor state update events of each iteration, and identify a state update event as a pipeline interruption when a state update occurs in any iteration; and a pipeline control unit configured to, in response to the pipeline interruption, sequentially execute suspension of the pipeline, invalidation of a speculative execution result of a subsequent iteration that has been launched, completion of the state update, and relaunch of the subsequent iteration based on the updated state. Under the premise of ensuring correct iteration semantics, the problem that the existing pipeline architecture cannot effectively implement parallel acceleration due to the lack of state update processing mechanism is solved, and unification between serial semantics of state dependence and pipeline parallelism is achieved, thereby providing an architectural foundation for reducing average iteration delay.

Description

Technical Field

[0001] This invention relates to the field of processor architecture technology, and in particular to a pipelined architecture for reasoning about the traveling salesman problem and a method for reducing interruptions. Background Technology

[0002] Annealing processors for the Traveling Salesman Problem (TSP) rely heavily on the state update results of the previous step for their iteration process. Each iteration calculates the energy difference based on the current state and decides whether to accept the state update. If accepted, the state changes, and subsequent iterations must be executed based on the updated state. Traditional implementations use a strictly serial approach, completing all operations (including state updates) for one iteration before launching the next. While this approach guarantees semantic correctness, it cannot leverage pipelined parallelism to improve throughput.

[0003] If a pipelined architecture is introduced into a processor, multiple iterations will be executed concurrently in time. Subsequent iterations will then perform speculative execution based on the current state before the previous iteration has completed its state update. When a state update occurs in any iteration, the state upon which subsequent iterations are based is outdated, rendering all their speculative execution results invalid. This lack of an effective mechanism for handling state update events makes it impossible to correct speculative errors in a timely manner, leading to the accumulation of incorrect speculative results and making it difficult to achieve parallel acceleration while ensuring the correctness of the iterative semantics. Summary of the Invention

[0004] This invention provides a pipelined architecture for reasoning in the Traveling Salesman Problem and a method for reducing interruptions, in order to address the shortcomings of existing pipelined architectures in achieving parallel acceleration while ensuring the correctness of iterative semantics.

[0005] This invention provides a pipeline architecture, comprising: The pipeline execution unit is configured to execute multiple iterations overlapping in time, wherein subsequent iterations are performed speculatively based on the current state before the previous iteration completes its state update; An interrupt triggering unit is configured to monitor the state update event of each iteration, and when a state update occurs in any iteration, the state update event is identified as a pipeline interruption. The pipeline control unit is configured to, in response to the pipeline interruption, sequentially execute the following steps: suspend the pipeline, invalidate the speculative execution results of the already launched subsequent iterations, complete the state update, and relaunch the subsequent iterations based on the updated state.

[0006] According to a pipeline architecture provided by the present invention, the pipeline execution unit is used to decompose a single iteration operation into a site access phase, a weight access phase, an energy difference calculation and annealing acceptance judgment phase, and a conditional spin table update phase, which are executed sequentially. The site access phase is used to determine the path location of the two nearest neighbor exchange based on the pseudo-random number generator, and extract the corresponding site number from the sequence table. The weight access phase is used to read the energy difference from the distance matrix and calculate the required distance using the one-time weighting mechanism of the in-memory computing macro. The energy difference calculation and annealing acceptance judgment stage is used to calculate the energy difference based on the reading distance, and to determine whether to accept the current iteration's state update based on the current temperature using a simulated annealing strategy. The conditional spin table update phase is used to update the corresponding path segment in the order table when the judgment result is accepted.

[0007] According to a pipeline architecture provided by the present invention, the pipeline execution unit is further configured as follows: After the pipeline control unit re-issues subsequent iterations based on the updated state, it uses the updated state as the new current state and continues speculative execution of subsequent iterations.

[0008] According to a pipeline architecture provided by the present invention, the pipeline control unit is further configured as follows: When the interrupt triggering unit does not detect an interrupt, the pipeline execution unit is allowed to continue moving forward without performing any refresh operation; When the interrupt triggering unit detects an interrupt, it introduces a preset number of refresh clock cycles as an interrupt penalty and suspends the transmission of the new iteration during the refresh clock cycles.

[0009] This invention provides a greedy initialization method to reduce interrupts, applied to the traveling salesman problem reasoning in annealing-type processors, including: Before the fine-grained two nearest neighbor swap iteration is executed, a coarse-grained greedy initialization is performed. The greedy nearest neighbor strategy is used to construct an initial path that satisfies the constraints. The initial path is written into the sequence list as the starting state of the fine-grained iteration. Based on the initial path, perform the fine-grained two-nearest neighbor exchange iteration to optimize the path length; The fine-grained two-nearest neighbor swapping iteration is performed on a pipeline architecture as described in any of the preceding claims.

[0010] According to a greedy initialization method for reducing interruptions provided by the present invention, the greedy nearest neighbor strategy includes: Starting from the selected starting station, each step expands the current path to the nearest unvisited station until all stations are visited, forming a closed loop; The greedy initialization is completed within a clock cycle that does not exceed the total number of stations.

[0011] According to a greedy initialization method for reducing interruptions provided by the present invention, the fine-grained two-nearest neighbor swap iteration adopts a simulated annealing strategy. In each step, the path is proposed to perform two-nearest neighbor swaps, the energy difference is calculated, and the swap is accepted or rejected with a preset probability based on temperature. The greedy initialization reduces the number of pipeline interruptions triggered by state update events by lowering the acceptance rate of the fine-grained iteration.

[0012] According to a greedy initialization method for reducing interrupts provided by the present invention, the greedy initialization maintains the acceptance rate of the fine-grained iteration at a level lower than that of random initialization from the initial stage. Compared with random initialization, it reduces the interrupt triggering frequency of the pipeline architecture within a preset number of iteration cycles, thereby reducing the refresh clock cycle overhead introduced by interrupts.

[0013] According to the method for reducing interrupts by greedy initialization provided by the present invention, the proportion of hardware overhead introduced by the greedy initialization is less than the proportion of overhead corresponding to the performance improvement obtained by the greedy initialization by reducing interrupts. The hardware overhead includes at least one of energy overhead, time overhead, and area overhead.

[0014] According to the present invention, a greedy initialization method for reducing interruptions is provided, wherein the initial path constructed by the greedy initialization satisfies the constraint condition of the Traveling Salesman Problem that each station is visited exactly once, and no constraint repair operation is performed.

[0015] This invention provides a pipelined architecture for reasoning in the Traveling Salesman Problem (TSP) and a method for reducing interruptions. By setting up pipelined execution units, interrupt triggering units, and pipelined control units, state update events are explicitly modeled as pipeline interrupts, and a closed-loop control mechanism of speculative execution, interrupt triggering, refresh invalidation, and reissue is constructed. When a state update occurs, the interrupt mechanism promptly corrects speculative errors, preventing error accumulation. When the state is not updated, the pipeline continues to advance, achieving parallel acceleration. While ensuring the correctness of iterative semantics, this invention solves the problem that existing pipelined architectures cannot effectively achieve parallel acceleration due to the lack of a state update handling mechanism. It achieves a unification between state-dependent serial semantics and pipeline parallelism, providing an architectural foundation for reducing average iteration latency. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1 This is a pipeline model diagram provided by the present invention, which uses spin updates as an interruption. Figure 2 This is the greedy initialization cost analysis diagram provided by the present invention; Figure 3 This is a trajectory diagram showing the improvement in solution quality for the PCB442 problem provided by this invention.

[0018] Figure 4 This is a schematic micrograph of the chip of the 28-nanometer complementary metal-oxide-semiconductor process path planning processor provided by the present invention. Figure 5 This is a diagram of the test platform used in the actual test provided by the present invention. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0020] Figure 1 This is a pipeline model diagram provided by the present invention, which uses spin updates as an interruption.

[0021] like Figure 1 As shown, this embodiment provides a pipelined architecture primarily applied to the Traveling Salesman Problem (TSP) reasoning process using annealing-based processors. The core includes three functional units: a pipelined execution unit, an interrupt triggering unit, and a pipelined control unit. These units work collaboratively to achieve iterative parallel execution while ensuring the semantic correctness of the TSP reasoning. For example... Figure 1 As shown, with time on the horizontal axis and pipeline execution stages on the vertical axis, the diagram clearly illustrates the overlapping and parallel execution of the various operation stages in consecutive iteration steps (k, k+1, k+2, etc.) within the pipeline. The vertical axis explicitly marks the core pipeline execution stages as site acquisition, weight acquisition, energy difference calculation and annealing acceptance judgment, and conditional spin table update. It also marks the processes of "accepting the update triggers an interruption and refreshes the pipeline," and the execution branches of "rejecting the update results in no interruption and the pipeline continues to advance." Details are as follows: The pipeline execution unit is configured to perform multiple overlapping annealing iterations in time. Each subsequent iteration performs speculative execution based on the current state before the previous iteration completes its state update. For example... Figure 1As shown, while the conditional spin table update phase in step k is not yet complete, the site acquisition in step k+1 and the weight acquisition in step k+2 are already underway. That is, if the spin table state update operation has not been completed in the previous iteration, subsequent iterations will perform speculative execution based on the current spin table / order table state. This solves the execution limitations of traditional serial iterations, leverages the inter-step overlap characteristics of the pipeline to exploit parallelism, lays the foundation for improving the throughput of annealing-type processors, and avoids single-step iteration delays directly restricting overall processing efficiency.

[0022] The interrupt triggering unit is configured to monitor the state update event for each iteration. When a state update occurs in any iteration, it identifies the state update event as a pipeline interrupt. For example... Figure 1 The interrupt triggering logic, as marked in the diagram, is used in the Traveling Salesman Problem reasoning process. When the annealing acceptance judgment result in a certain iteration is "accept," a spin update of the order table is triggered. At this time, the interrupt triggering unit directly identifies this spin update state update event as a pipeline interrupt, providing a trigger signal for the interrupt response of the pipeline control unit. This achieves accurate monitoring and explicit modeling of state update events, allowing the pipeline architecture to promptly perceive critical events that may lead to the failure of subsequent speculative execution, providing a basis for correcting speculative errors.

[0023] The pipeline control unit is configured to, in response to a pipeline interruption, sequentially execute the following steps: pause the pipeline, invalidate the speculative execution results of already launched subsequent iterations, complete a state update, and relaunch subsequent iterations based on the updated state. The response process executes operations in a fixed order: first, the entire pipeline operation is paused, and subsequent speculative execution steps are no longer advanced. Then, the speculative execution results of all launched subsequent iterations are invalidated, such as... Figure 1 If an interruption is triggered in step k, the speculative operations already executed in steps k+1 and k+2 are invalidated to avoid the accumulation of erroneous results in outdated states. Then, the spin table / order table state corresponding to the current iteration is updated. Finally, subsequent annealing iterations are refired based on the updated state, and the pipeline's overlapping execution continues. This allows the pipeline to correct errors promptly after an interruption, ensuring that each iteration's execution is based on the latest valid state. This makes the pipeline's parallel execution semantically equivalent to traditional serial iteration, achieving a balance between correctness and parallelism.

[0024] Furthermore, based on the above embodiments, the pipeline execution unit in this embodiment is used to decompose a single iteration operation into a site access phase, a weight access phase, an energy difference calculation and annealing acceptance judgment phase, and a conditional spin table update phase, which are executed sequentially. Specifically, the site access phase is used to determine the path position of the two nearest neighbor swap based on a pseudo-random number generator and extract the corresponding site number from the sequence table; the weight access phase is used to read the energy difference from the distance matrix and calculate the required distance using the one-time weighting mechanism of the in-memory computation macro; the energy difference calculation and annealing acceptance judgment phase is used to calculate the energy difference based on the read distance and determine whether to accept the current iteration's state update based on the current temperature using a simulated annealing strategy; and the conditional spin table update phase is used to update the corresponding path segment in the sequence table when the judgment result is acceptance.

[0025] Specifically, all four phases can be hardware-aligned to a single clock cycle delay. The site acquisition phase is... Figure 1 The first execution stage of the pipeline, as marked in the diagram, involves the pipeline execution unit determining the two path locations corresponding to the current two-nearest neighbor swap disturbance based on random numbers generated by a pseudo-random number generator. It then precisely retrieves the four station numbers corresponding to these two locations from the constraint removal order table: left-end station, left inner station, right inner station, and right-end station. This rapid and accurate location of the operation target for the current two-nearest neighbor swap provides fundamental station information for energy difference calculation, and the single-cycle design adapts to the high-speed execution requirements of the pipeline.

[0026] The weight acquisition stage is Figure 1 The second pipeline execution stage after the middle site acquisition involves the pipeline execution unit utilizing a one-time weighting mechanism of an in-memory compute macro to read the four distance data points required for calculating the energy difference from the distance matrix storing the distances between Traveling Salesman Problem (TSP) sites in a single cycle. This achieves efficient distance data retrieval, avoids delays caused by multiple data retrievals, and ensures consistent pipeline rhythm across all stages by completing the weighting process in a single cycle, reducing pipeline bubbles and pauses. Figure 1 The overlapping execution logic of each stage is matched without interruption.

[0027] The energy difference calculation and annealing acceptance judgment stages are as follows: Figure 1 In the third pipeline execution stage after the weights are acquired, the pipeline execution unit sends the four distance data points it has read to a dedicated energy difference calculation unit. This unit calculates the energy difference corresponding to this two-nearest neighbor swap. The calculated energy difference is then divided by the current annealing temperature, and the acceptance probability of this swap is obtained through a simulated annealing lookup table. Finally, this acceptance probability is compared with a uniformly random number generated by a linear feedback shift register. Based on the comparison result, an acceptance or rejection status update signal is output. The judgment result is... Figure 1The core basis for interrupt triggering. The effect of doing this is to complete the energy difference calculation and acceptance judgment in a single cycle, allowing the annealing iteration to be executed efficiently, ensuring the accuracy of the judgment results, and adapting to the single-cycle stage design of the pipeline.

[0028] The conditional spin table update phase is Figure 1 The final execution stage of the pipeline, as marked in the diagram, is also the crucial stage for interrupt triggering. In this stage, the pipeline execution unit performs operations based on the judgment signal output from the previous stage. If the judgment signal is "accept," the corresponding path segment in the sequence table is reversed, completing the state update of the spin table / sequence table. If the judgment signal is "reject," the state of the spin table / sequence table remains unchanged. This achieves conditional and precise state updates, modifying the state only when necessary, providing the interrupt triggering unit with a clear basis for determining state update events, while ensuring pipeline execution efficiency by completing the operation in a single cycle.

[0029] Furthermore, based on the above embodiments, the pipeline execution unit in this embodiment is further configured to: after the pipeline control unit re-issues subsequent iterations based on the updated state, use the updated state as the new current state and continue to perform speculative execution of subsequent iterations.

[0030] Specifically, after the pipeline control unit completes the interrupt response operation and re-launches the subsequent annealing iterations based on the updated state, the pipeline execution unit uses the updated spin table / order table state as the new current state and continues to perform speculative execution on subsequent iterations based on the new current state. Subsequent speculative execution still follows... Figure 1 The step overlap rule shown means that the new (k+1)th step starts from the site retrieval phase and overlaps with the subsequent phases of the new (k)th step. This ensures that the pipeline can quickly return to normal parallel execution after an interruption, and that subsequent iterations are based on the latest valid state. This guarantees the semantic correctness of annealing inference, continuously explores the parallel benefits of the pipeline, and avoids reverting to the inefficient serial execution mode after an interruption.

[0031] Furthermore, based on the above embodiments, the pipeline control unit in this embodiment is further configured to: when the interrupt triggering unit does not detect an interrupt, allow the pipeline execution unit to continue moving forward without performing any refresh operation; when the interrupt triggering unit detects an interrupt, introduce a preset number of refresh clock cycles as an interrupt penalty, and suspend the issuance of the new iteration within the refresh clock cycles.

[0032] Specifically, when the interrupt triggering unit detects a stateless update event in the current iteration, meaning no pipeline interruption is detected, the corresponding... Figure 1 If the execution branch is rejected, the pipeline control unit does not perform any pipeline refresh operation and directly allows the pipeline execution unit to proceed according to the specified path. Figure 1 The original inter-step overlap rule continues to advance iterative speculative execution, with no pauses or overlaps in the site acquisition and weight acquisition stages of each iteration step. This maximizes the parallelism of the pipeline, avoids unnecessary operations without error risk, minimizes the average step latency of the pipeline, and fully leverages the advantages of overlapping execution.

[0033] When the interrupt triggering unit detects a status update event, that is, when a pipeline interrupt is identified, the corresponding... Figure 1 Upon receiving an execution branch, the pipeline control unit introduces a preset number of refresh clock cycles as an interrupt penalty. During these refresh clock cycles, all new iterations of issue operations are paused, and only interrupt response operations such as pipeline pause, invalidating speculative results, state update, and reissue are executed. Figure 1 The pipeline refresh process is consistent with the standardization of the refresh cycle. By standardizing the interrupt handling process of the pipeline through a fixed refresh cycle, the pipeline avoids new speculation errors caused by issuing new iterations during the refresh process, ensuring the stability and orderliness of the pipeline architecture. In actual implementation, a penalty design of about 3 clock cycles is used to keep the time overhead of interrupt handling controllable.

[0034] Figure 2 This is the greedy initialization cost analysis diagram provided by the present invention. Figure 3 This is a trajectory diagram showing the improvement in solution quality for the PCB442 problem provided by this invention.

[0035] The greedy initialization interrupt reduction method provided in this embodiment is applied to the Traveling Salesman Problem reasoning in annealed processors and is used in conjunction with the pipelined architecture in any of the above embodiments. The overall approach is a two-stage iterative scheme, and its overhead characteristics are as follows: Figure 2 As shown, the solution quality improvement effect is due to Figure 3 As shown. Mainly includes: Before the fine-grained two-nearest neighbor swap iteration is executed, a coarse-grained greedy initialization is performed. The greedy nearest neighbor strategy is used to construct an initial path that satisfies the constraints. The initial path is written into the sequence list as the starting state for the fine-grained iteration. Based on the initial path, the fine-grained two-nearest neighbor swap iteration is executed to optimize the path length. The fine-grained two-nearest neighbor swap iteration is executed on the pipeline architecture as described in any of the above embodiments.

[0036] Specifically, Figure 2 The chart shows the cost analysis of the greedy initialization algorithm. The horizontal axis represents the cost type, which includes three categories: energy cost, time cost, and area cost. The vertical axis represents the cost percentage (%), and the chart shows the specific measured values ​​of each type of cost. It also includes the conclusion that the completion period of the greedy initialization algorithm is ≤ the total number of sites N, which clearly demonstrates the characteristics of the greedy initialization algorithm: low cost and fast completion. Figure 3This is a trajectory diagram showing the improvement in solution quality for the PCB442 problem. The vertical axis represents the path ratio, with a scale range of 1.0-1.8, and the horizontal axis represents the number of annealing iterations. The diagram clearly marks two key iteration nodes: 1000 steps and 10000 steps. The diagram includes two comparison curves: one for the baseline test (using only the two nearest neighbor swap algorithm, without greedy initialization) and the other for further adding greedy initialization (using only the two nearest neighbor swap algorithm). Each curve is labeled with a specific path ratio value at the corresponding iteration node, intuitively demonstrating the effect of greedy initialization on improving solution quality.

[0037] Before performing fine-grained two-nearest neighbor swap iterations, a coarse-grained greedy initialization step is first executed. This step uses a greedy nearest neighbor strategy to construct an initial path that satisfies the constraints of the Traveling Salesman Problem. After construction, this initial path is directly written into the sequence list, and the state of the sequence list corresponding to this initial path is used as the starting state for subsequent fine-grained two-nearest neighbor swap iterations. The cost of this step is completely consistent with... Figure 2 The display results are Figure 2 The specific implementation of low-overhead characteristics. The effect of this is to quickly obtain feasible initial paths with lower energy, allowing subsequent fine-grained iterations to start from near-local optima, significantly reducing the acceptance rate of state updates in subsequent iterations, and reducing the probability of pipeline interruptions from the source. Figure 2 The measured data shows that the hardware overhead of this step is minimal, and the benefits far outweigh the costs.

[0038] Starting with the initial path obtained through greedy initialization, a fine-grained two-nearest neighbor (BNN) swap iteration is performed. Through annealing inference with multiple BNN perturbations, the initial path is locally optimized, gradually shortening the path length to approximate the optimal solution to the Traveling Salesman Problem. This fine-grained BNN swap iteration is executed entirely on the pipeline architecture disclosed in the above embodiment. Each step of the iteration is performed according to the following stages: site acquisition, weight acquisition, energy difference calculation and annealing acceptance judgment, and conditional spin table update. Under the condition of using only the BNN swap algorithm, the initial path ratio in the benchmark test is 1.565, and the initial path ratio after adding greedy initialization is 1.451. At 1000 iterations, the path ratio after adding greedy initialization is 1.133, with no corresponding label in the benchmark test. At 10000 iterations, the path ratio after adding greedy initialization further decreases to 1.096, with no corresponding label in the benchmark test. All values ​​are distributed across... Figure 3 Within the vertical axis scale range of 1.0-1.8, fine-grained iteration can fully utilize the parallelism of the pipeline architecture. At the same time, the low acceptance rate caused by the low initial path energy significantly reduces the number of pipeline interruptions, fully demonstrating the advantages of pipeline step overlap and achieving low-interruption, high-throughput inference. Meanwhile, fine-grained optimization of two-nearest neighbor swaps ensures continuous improvement in path quality.

[0039] Furthermore, based on the above embodiments, the greedy nearest neighbor strategy in this embodiment includes: starting from the selected starting station, each step expands the current path end to the unvisited station closest to the current end until all stations are visited, forming a closed loop; wherein, the greedy initialization is completed within a clock cycle not exceeding the total number of stations.

[0040] Specifically, such as Figure 2 As shown, not only are the energy, time, and area costs of the greedy initialization marked, but it also indicates that the number of clock cycles required to complete the greedy initialization is ≤ the total number of stations N. Furthermore, the specific completion cycle range is marked using 32 stations and 442 stations as examples. The specific implementation method and effects of this embodiment are as follows: The greedy nearest neighbor strategy first randomly selects a starting station from all the stations in the Traveling Salesman Problem (TSP). Using this starting station as the origin of the path, each step expands the current path's endpoint to the nearest unvisited station. This expansion is repeated until all stations have been visited exactly once. Finally, the endpoints of the path are connected to the starting station, forming a closed loop. This closed loop is the initial path constructed using the greedy initialization strategy. This constructed initial path naturally satisfies the constraints of the TSP, and its energy is significantly lower than that of a randomly initialized path, laying the foundation for subsequent iterations with low acceptance rates. Furthermore, the strategy's execution logic is simple, easy to implement in hardware, and adaptable to low-overhead design requirements, which is the core reason for its low area and low energy consumption.

[0041] The entire execution process of the greedy nearest neighbor strategy described above, in terms of hardware, completes in no more than the total number of stations N in the Traveling Salesman Problem (TSP). For a TSP with 32 stations, it takes at most 32 clock cycles; for a TSP with 442 stations, it takes at most 442 clock cycles, establishing a linear correspondence between the completion time and the number of stations. This approach keeps the time cost of the greedy initialization process controllable, as this step accounts for only a very small proportion of the total solution time. Figure 2 The time overhead of matching is only 1.1%, which will not negatively affect the overall inference efficiency and enables rapid initialization.

[0042] Furthermore, based on the above embodiments, the fine-grained two-nearest neighbor swap iteration in this embodiment adopts a simulated annealing strategy. In each step, a two-nearest neighbor swap is proposed for the path, the energy difference is calculated, and the swap is accepted or rejected with a preset probability according to the temperature. Greedy initialization reduces the number of pipeline interruptions triggered by state update events by reducing the acceptance rate of fine-grained iteration.

[0043] Specifically, this iteration employs a simulated annealing strategy. Each iteration first proposes a two-nearest neighbor swap perturbation to the current path, then sequentially executes site acquisition, weight acquisition, energy difference calculation, and annealing acceptance judgment. After combining the energy difference with the current annealing temperature, a preset probability is used to determine whether to accept the two-nearest neighbor swap. If the probability determines acceptance, a conditional spin table update is performed; if the probability determines rejection, the path state remains unchanged. The optimization effect of this iterative strategy is... Figure 3 The results clearly demonstrate that after adding greedy initialization, the path ratio continuously decreases from an initial path ratio of 1.451 to 1.133 after 1000 steps, and then to 1.096 after 10000 steps, showing a clear optimization trend. This path ratio consistently outperforms the benchmark initial path ratio of 1.565 without greedy initialization. By employing the probabilistic acceptance rule of simulated annealing, iterative iteration is prevented from getting trapped in local optima. Furthermore, the fine-grained perturbation of two-nearest neighbor swaps gradually optimizes the path length while ensuring path constraints, leading to a continuous improvement in solution quality.

[0044] Greedy initialization constructs low-energy initial paths, ensuring that most two-nearest neighbor swap perturbations in subsequent fine-grained iterations lead to increased path energy. This causes the simulated annealing strategy to reject these perturbations, ultimately reducing the overall state update acceptance rate of the fine-grained iterations. This effect is fundamental to the rapid improvement in solution quality and is the core reason for the reduction in pipeline interruptions. Greedy initialization starts the iteration with a low path ratio of 1.451, rather than a high path ratio of 1.565, reducing interruptions and making the optimization of two-nearest neighbor swaps more efficient. By fundamentally reducing the number of pipeline interruptions triggered by state update events, the pipeline refresh penalty is significantly reduced, allowing the inter-step overlapping parallel advantages of the pipeline architecture to be fully utilized, thus laying the foundation for rapid improvement in solution quality.

[0045] Furthermore, based on the above embodiments, the greedy initialization in this embodiment maintains the acceptance rate of fine-grained iteration at a level lower than that of random initialization from the initial stage. Compared with random initialization, it reduces the interrupt triggering frequency of the pipeline architecture within the preset number of iteration cycles, thereby reducing the refresh clock cycle overhead introduced by interrupts.

[0046] Specifically, the low-energy initialization path constructed by greedy initialization ensures that the acceptance rate of fine-grained two-nearest neighbor swapping iterations remains consistently lower than that of random initialization from the initial stage. This low acceptance rate persists throughout the entire fine-grained iteration process and does not significantly increase with the number of iterations. Within a preset iteration cycle, compared to random initialization, greedy initialization significantly reduces the interrupt triggering frequency of the aforementioned pipeline architecture, thereby reducing the refresh clock cycle overhead introduced by pipeline interruptions. Figure 2As shown, after 10,000 iterations, the number of interrupts decreased by approximately 4.45 times, and the average number of interrupts per cluster in the 442-site benchmark decreased from 786 to 176, with a total latency reduction of 14.8%, clearly demonstrating the effect of reducing the interrupt frequency. This significantly reduces the pipeline's ineffective overhead, resulting in a substantial decrease in the average step latency of the pipeline, fully demonstrating the performance improvement effect of pipeline parallel execution, and verifying that the benefits of this effect far outweigh the hardware overhead of greedy initialization.

[0047] Furthermore, based on the above embodiments, the proportion of hardware overhead introduced by greedy initialization in this embodiment is less than the proportion of overhead corresponding to the performance improvement obtained by greedy initialization by reducing interrupts; wherein, hardware overhead includes at least one of energy overhead, time overhead and area overhead.

[0048] Specifically, such as Figure 2 The diagram shows the cost analysis for the greedy initialization algorithm. The horizontal axis represents the three cost types: energy, time, and area. The vertical axis represents the percentage. The actual measured values ​​for each cost type are clearly marked in bar chart form: energy cost accounts for approximately 4.1% of the total energy, time cost accounts for approximately 1.1% of the total solution time, and area cost accounts for approximately 0.3% of the core area. Figure 4 The image shown is a micrograph of a 28nm complementary metal-oxide-semiconductor (CMOS) process path planning processor chip. The image clearly shows the chip's physical layout, marking the integration areas of core hardware modules such as the pipeline execution unit, interrupt triggering unit, pipeline control unit, greedy initialization module, and in-memory macro, verifying the hardware feasibility of this invention. Figure 5 The diagram shown is a test platform diagram used in the actual test of this technical solution. The diagram shows the complete test environment, including components such as chip carrier board, signal test instruments, data acquisition and analysis module, power supply module, etc., as well as the test purpose used to test pipeline architecture performance, greedy initialization overhead and solution quality.

[0049] In annealed processors, the hardware overhead introduced by greedy initialization is far less than the performance improvement gained by reducing pipeline interrupts. This hardware overhead includes, but is not limited to, at least one of energy, time, and area overheads, with the specific proportions of each type of overhead being... Figure 2 They are completely identical, both representing a very small percentage of the cost.

[0050] All technical solutions described in this invention include Figure 1 The pipeline architecture and greedy initialization module have been implemented. Figure 4 The 28nm complementary metal-oxide-semiconductor process shown is implemented and integrated on the processor, with each core module physically laid out on the chip, and through... Figure 5 The test platform shown completed the entire process of the actual test, and the test results are consistent with... Figure 2 The data perfectly matched, verifying the low-overhead characteristics of greedy initialization and the hardware feasibility of this invention. Greedy initialization achieves an extremely high cost-effectiveness ratio, requiring only a small investment of hardware resources, time, and energy costs to obtain significant pipeline performance improvements, making it suitable for implementation in actual hardware chips.

[0051] Furthermore, based on the above embodiments, in this embodiment, the initial path constructed by greedy initialization satisfies the constraint that each station in the Traveling Salesman Problem is visited exactly once, and no constraint repair operation is performed.

[0052] Specifically, the greedy initialization, using a greedy nearest neighbor strategy, constructs an initial path that naturally satisfies the core constraints of the Traveling Salesman Problem: each station is visited exactly once, forming a closed loop. Throughout the greedy initialization process, no additional constraint correction operations are required; the constructed initial path directly satisfies the constraints. This characteristic is consistent with... Figure 2 Completely identical. The advantage of this approach is that it eliminates the hardware circuit design and clock cycle overhead required for constraint repair operations. It eliminates the need for a separate hardware module for constraint repair and avoids the need for additional iteration cycles for path correction. This is... Figure 2 A key reason why the area overhead of the greedy initialization algorithm is only 0.3% and the time overhead is only 1.1% is that it further reduces the hardware and time costs of greedy initialization. Figure 2 This aligns with the characteristics of greedy initialization, which offers low time and area overhead. Simultaneously, this characteristic ensures the validity of the initial path, preventing invalid operations in subsequent two-nearest neighbor swap iterations due to unmet constraints. This ensures the entire reasoning process of the Traveling Salesman Problem is in a valid path state from the initial stage, guaranteeing the effectiveness of iteration and also providing... Figure 3 The rapid improvement in the quality of solution provides a legitimate initial basis.

[0053] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0054] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0055] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A pipeline architecture, characterized in that, include: The pipeline execution unit is configured to execute multiple iterations overlapping in time, wherein subsequent iterations are performed speculatively based on the current state before the previous iteration completes its state update; An interrupt triggering unit is configured to monitor the state update event of each iteration, and when a state update occurs in any iteration, the state update event is identified as a pipeline interruption. The pipeline control unit is configured to, in response to the pipeline interruption, sequentially execute the following steps: suspend the pipeline, invalidate the speculative execution results of the already launched subsequent iterations, complete the state update, and relaunch the subsequent iterations based on the updated state.

2. The pipeline architecture according to claim 1, characterized in that, The pipeline execution unit is used to decompose a single iteration operation into a site access phase, a weight access phase, an energy difference calculation and annealing acceptance judgment phase, and a conditional spin table update phase, which are executed sequentially. The site access phase is used to determine the path location of the two nearest neighbor exchange based on the pseudo-random number generator, and extract the corresponding site number from the sequence table. The weight access phase is used to read the energy difference from the distance matrix and calculate the required distance using the one-time weighting mechanism of the in-memory computing macro. The energy difference calculation and annealing acceptance judgment stage is used to calculate the energy difference based on the reading distance, and to determine whether to accept the current iteration's state update based on the current temperature using a simulated annealing strategy. The conditional spin table update phase is used to update the corresponding path segment in the order table when the judgment result is accepted.

3. The pipeline architecture according to claim 1, characterized in that, The pipeline execution unit is further configured as follows: After the pipeline control unit re-issues subsequent iterations based on the updated state, it uses the updated state as the new current state and continues speculative execution of subsequent iterations.

4. The pipeline architecture according to claim 1, characterized in that, The production line control unit is further configured as follows: When the interrupt triggering unit does not detect an interrupt, the pipeline execution unit is allowed to continue moving forward without performing any refresh operation; When the interrupt triggering unit detects an interrupt, it introduces a preset number of refresh clock cycles as an interrupt penalty and suspends the transmission of the new iteration during the refresh clock cycles.

5. A greedy initialization method to reduce interrupts, applied to the traveling salesman problem reasoning in annealing-type processors, characterized in that, include: Before the fine-grained two nearest neighbor swap iteration is executed, a coarse-grained greedy initialization is performed. The greedy nearest neighbor strategy is used to construct an initial path that satisfies the constraints. The initial path is written into the sequence list as the starting state of the fine-grained iteration. Based on the initial path, perform the fine-grained two-nearest neighbor exchange iteration to optimize the path length; The fine-grained two-nearest neighbor exchange iteration is performed on the pipeline architecture described in any one of claims 1 to 4.

6. The greedy initialization method for reducing interrupts according to claim 5, characterized in that, The greedy nearest neighbor strategy includes: Starting from the selected starting station, each step expands the current path to the nearest unvisited station until all stations are visited, forming a closed loop; The greedy initialization is completed within a clock cycle that does not exceed the total number of stations.

7. The greedy initialization method for reducing interrupts according to claim 5, characterized in that, The fine-grained two-nearest neighbor swapping iteration adopts a simulated annealing strategy. In each step, the proposal performs two-nearest neighbor swapping on the path, calculates the energy difference, and accepts or rejects the swap according to the temperature with a preset probability. The greedy initialization reduces the number of pipeline interruptions triggered by state update events by lowering the acceptance rate of the fine-grained iteration.

8. The greedy initialization method for reducing interrupts according to claim 7, characterized in that, The greedy initialization keeps the acceptance rate of the fine-grained iteration below the level of random initialization from the beginning stage. Compared with random initialization, it reduces the interrupt triggering frequency of the pipeline architecture within the preset number of iteration cycles, thereby reducing the refresh clock cycle overhead introduced by interrupts.

9. The greedy initialization method for reducing interrupts according to claim 8, characterized in that, The proportion of hardware overhead introduced by the greedy initialization is less than the proportion of overhead corresponding to the performance improvement obtained by the greedy initialization by reducing interrupts. The hardware overhead includes at least one of energy overhead, time overhead, and area overhead.

10. The greedy initialization method for reducing interrupts according to claim 5, characterized in that, The initial path constructed by the greedy initialization satisfies the constraint of the Traveling Salesman Problem that each station is visited exactly once, and no constraint repair operation is performed.

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