A mode switching method and device of an ARM Cortex-R processor in a ThreadX system

Abstract

The application discloses a mode switching method of an ARM Cortex-R processor in a ThreadX system. When an application thread is first scheduled by a ThreadX system kernel, the ARM Cortex-R processor is forced to be switched to a SYS mode, a memory address pre-assigned to the application thread is written into a stack pointer register, and then general registers and link registers are cleared. Then, the ThreadX system kernel changes the ARM Cortex-R processor to a USR mode to execute the application thread. When the application thread needs to execute a high-privilege operation, an SVC assembly instruction is executed. The ThreadX system kernel reads an address of the SVC assembly instruction, reads binary machine code of the SVC assembly instruction back and extracts the same, and automatically corresponds and transfers the immediate number to a C language API function address in the ThreadX system kernel to execute. The application uses the SYS mode as a springboard, and combines machine code interception of the SVC assembly instruction to realize zero switching overhead of the ARM Cortex-R processor hardware mode switching.

Description

Technical Field

[0001] This invention relates to a method for switching application threads in a real-time operating system between different modes of an ARM Cortex-R processor. Background Technology

[0002] In a real-time operating system (RTOS), applications are divided into independent threads, and the system kernel is responsible for scheduling and managing these threads. A thread, also commonly referred to as a task, is the smallest unit of computation scheduling performed by the real-time operating system.

[0003] The ARM Cortex-R processor (R stands for Real-time) does not support a dual stack pointer mechanism—the MSP (Main Stack Pointer) and PSP (Process Stack Pointer). The ARM Cortex-R processor has multiple hardware modes, including a low-privilege USR (User) mode, a high-privilege SYS (System) mode, and the highest-privilege SVC (Administrator) mode, switching between different hardware modes via the CPSR (Current Program Status Register). The system kernel runs in SVC mode, while application threads run in USR mode. When an application thread needs to perform a high-privilege operation, it executes an SVC assembly instruction. The real-time operating system forces the ARM Cortex-R processor to switch to SVC mode and jumps to the system kernel to complete the high-privilege operation requested by the application thread. After the kernel finishes processing, the real-time operating system switches the ARM Cortex-R processor back to USR mode, returning control to the application thread.

[0004] ThreadX is a real-time operating system. In the official ThreadX architecture, application code is tightly integrated with the system kernel by default, running in the same address space and SVC mode. To address security isolation issues, ThreadX provides ThreadX Modules technology, which uses an MPU (Memory Protection Unit) to separate module code (i.e., application code) from the system kernel, allowing it to run in different hardware modes of the processor.

[0005] ThreadX Modules technology has the following drawbacks. First, it has high engineering complexity, requiring complete separation of application code from system kernel code, and compilation using separate projects and linker scripts. Second, it incurs significant performance and memory overhead; using ThreadX Modules leads to additional performance degradation and memory penalties. Third, communication between modules and the kernel, and between modules themselves, is forcibly transformed into complex cross-domain calls, creating communication barriers. Summary of the Invention

[0006] The technical problem to be solved by this invention is: how to implement safe switching of application threads between USR mode and SVC mode of ARM Cortex-R processor in ThreadX system.

[0007] To address the aforementioned technical problems, this invention proposes a mode switching method for the ARM Cortex-R processor in the ThreadX system, comprising the following steps: Step S1: When the ThreadX system kernel schedules the application thread for the first time, it forcibly switches the ARM Cortex-R processor to SYS mode and writes the memory address pre-allocated to the application thread into the stack pointer register. Step S2: While the ARM Cortex-R processor is in SYS mode, the ThreadX system kernel clears the general-purpose registers and link registers. Step S3: The ThreadX system kernel switches the ARM Cortex-R processor to USR mode, enables hardware interrupts, and bypasses the ThreadX system kernel shell layer through a jump and state-switching BX instruction, transferring control to the application thread. The entire execution process from steps S1 to S3 is continuous and cannot be interrupted by any interrupts. Step S4: The ARM Cortex-R processor executes the application thread in USR mode. When the application thread needs to perform a high-privilege operation, it executes the SVC assembly instruction, generating a software interrupt. The ARM Cortex-R processor automatically backs up the current program status register (CPSR) from its current non-privileged state to the backup program status register (SPSR_svc) in SVC mode, and simultaneously saves the breakpoint address to the link register. Step S5: The ThreadX system kernel reads the address of the SVC assembly instruction, backtracks to read the binary machine code of the SVC assembly instruction, extracts it, and automatically maps the immediate value to the address of the C language API function in the ThreadX system kernel for execution. The ARM Cortex-R processor automatically enters SVC mode. Step S6: After the ThreadX system kernel processes the high-privilege operation requested by the application thread, it switches the ARM Cortex-R processor back to USR mode, returning control to the application thread, and simultaneously restores the SPSR_svc to the CPSR.

[0008] Furthermore, in step S1, the ARM Cortex-R processor is forcibly switched to SYS mode by modifying the mode control bit in the CPSR inside the ARM Cortex-R processor.

[0009] Furthermore, in step S1, the SYS mode and USR mode of the ARM Cortex-R processor physically share the stack pointer register.

[0010] Furthermore, in step S5, the C language API functions in the ThreadX system kernel refer to the ThreadX native system services, which are core API functions provided by the Thread system kernel for task management, synchronization, communication, and time control.

[0011] Furthermore, step S5 does not modify the source code of the ThreadX system kernel; it simply calls the native ThreadX system service after recognizing the immediate value, which is a non-intrusive mapping method.

[0012] Furthermore, in step S6, the MOVS pc, lr exception return instruction is used; MOV indicates that data transfer is performed, S indicates that SPSR_svc is automatically copied to CPSR, pc indicates that the destination register is the program counter, and lr indicates that the source register is the link register.

[0013] This invention also proposes a mode switching device for the ARM Cortex-R processor in the ThreadX system, including a SYS mode switching unit, a clearing unit, a hardware interrupt unit, and a software interrupt unit. The SYS mode switching unit is used to force the ARM Cortex-R processor to switch to SYS mode when the ThreadX system kernel first schedules the application thread, and writes the memory address pre-allocated to the application thread into the stack pointer register. The clearing unit is used to clear the general-purpose registers and link registers in the SYS mode of the ARM Cortex-R processor. The hardware interrupt unit is used to switch the ARM Cortex-R processor to USR mode, enable hardware interrupts, and bypass the ThreadX system kernel shell layer through the BX instruction to transfer control to the application thread. The entire execution process from the SYS mode switching unit to the clearing unit to the hardware interrupt unit is continuous and cannot be interrupted by any interrupt. The software interrupt unit is used to execute the application thread in the USR mode of the ARM Cortex-R processor. When the application thread needs to perform a high-privilege operation, it executes the SVC assembly instruction to generate a software interrupt. The ARM Cortex-R processor automatically backs up the current program status register (CPSR) of the current non-privileged state to the backup program status register (SPSR_svc) in SVC mode, and saves the breakpoint address to the link register. The SVC mode switching unit is used to read the address of the SVC assembly instruction, backtrack to read the binary machine code of the SVC assembly instruction, extract the immediate value, and automatically transfer the immediate value to the address of the C language API function in the ThreadX system kernel for execution; the ARM Cortex-R processor automatically enters SVC mode. The USR mode rollback unit is used to switch the ARM Cortex-R processor back to USR mode after the ThreadX system kernel has processed the high-privilege operation requested by the application thread, returning control to the application thread, and restoring SPSR_svc to CPSR.

[0014] The technical effect achieved by this invention is as follows: In response to the hardware defects of the lack of MSP and PSP in ARM Cortex-R processors, the SYS mode is used as a springboard to initialize the stack pointer register and clean the registers. Combined with machine code interception using SVC assembly instructions and mapping to ThreadX native system services, a completely different zero-switching overhead ARM Cortex-R processor hardware mode switching method is realized, which is completely different from the ThreadX Modules solution, and user-mode security isolation is achieved. Attached Figure Description

[0015] Figure 1This is a flowchart illustrating the mode switching method of the ARM Cortex-R processor in the ThreadX system of this invention.

[0016] Figure 2 This is a schematic diagram of the mode switching device for the ARM Cortex-R processor in the ThreadX system of this invention.

[0017] The attached diagrams are labeled as follows: SYS mode switching unit 1, clearing unit 2, hardware interrupt unit 3, software interrupt unit 4, SVC mode switching unit 5, and USR mode rollback unit 6. Detailed Implementation

[0018] Please see Figure 1 The mode switching method for the ARM Cortex-R processor in the ThreadX system proposed in this invention includes the following steps.

[0019] Step S1: When the ThreadX system kernel schedules the application thread for the first time, it forces the ARM Cortex-R processor to switch to SYS mode by modifying the mode control bit in the Current Program Status Register (CPSR) inside the ARM Cortex-R processor. SYS mode is a privileged state, but it physically shares the stack pointer register (R13) with USR mode. In SYS mode, the ThreadX system kernel writes the memory address pre-allocated to the application thread into the stack pointer register.

[0020] Step S2: In SYS mode, the ThreadX system kernel of the ARM Cortex-R processor performs a zeroing operation on the general-purpose registers (R2-R12) and the link register. This completely cuts off any bypass paths that could allow sensitive kernel contexts (such as kernel stack addresses and keys) to leak to the isolation sandbox.

[0021] Step S3: The ThreadX system kernel switches the ARM Cortex-R processor to USR mode, enables hardware interrupts, and bypasses the general ThreadX system kernel shell layer (Shell Bypass) through the BX (Branch and Exchange) instruction, transferring control to the application thread.

[0022] The entire execution process from step S1 to step S3 includes switching to SYS mode, writing to the stack pointer register, clearing multiple registers, switching to USR mode, and transferring control. The entire execution process is continuous and cannot be interrupted by any interrupt.

[0023] Step S4: The ARM Cortex-R processor executes the application thread in USR mode. When the application thread needs to perform a high-privilege operation, it executes an SVC assembly instruction. The SVC assembly instruction generates a software interrupt, and the ARM Cortex-R processor automatically backs up the current program status register (CPSR) of the current non-privileged state to the saved program status register for SVC mode (SPSR_svc), while saving the breakpoint address to the link register.

[0024] Step S5: The ThreadX system kernel reads the address of the SVC assembly instruction, backtracks to read the binary machine code of the SVC assembly instruction, extracts the immediate number from the binary machine code, and automatically assigns the immediate number to the corresponding address of a C language API (Application Programming Interface) function in the ThreadX system kernel for execution. The ARM Cortex-R processor automatically enters SVC mode.

[0025] Machine code is the final form of a program stored in memory; it's a binary sequence that the CPU can directly recognize and execute. Immediate values ​​are constants directly embedded within the instruction machine code. The C language API functions in the ThreadX system kernel refer to ThreadX native system services, which are core API functions provided by the ThreadX system kernel for task management, synchronization, communication, and time control. This step does not modify the core source code of the ThreadX system kernel at all; it simply calls the ThreadX native system services after recognizing the immediate value, thus it's a non-intrusive mapping method. For example, the SVC assembly instruction is SVC #0, which extracts the immediate value 0 from its binary machine code. The immediate value 0 is statically mapped to the tx_thread_sleep function in the ThreadX system kernel.

[0026] Step S6: After the ThreadX system kernel processes the high-privilege operation requested by the application thread, the ThreadX system switches the ARM Cortex-R processor back to USR mode, returning control to the application thread. This step simultaneously completes the transfer of control and the restoration of SPSR_svc to the CPSR, thus completely eliminating privilege escalation vulnerabilities during context switching. For example, this step uses the MOVS pc, lr instruction, which is an exception return instruction. MOV indicates performing a data transfer, S indicates automatically copying SPSR_svc to the CPSR, pc indicates the destination register is the program counter, and lr indicates the source register is the link register (LR). The execution result is: loading the address in the link register into the program counter, forcing the ARM Cortex-R processor to jump back to the breakpoint address before the software interrupt, and simultaneously restoring SPSR_svc completely to the CPSR.

[0027] Please see Figure 2 The mode switching device for the ARM Cortex-R processor in the ThreadX system proposed in this invention includes a SYS mode switching unit 1, a clearing unit 2, a hardware interrupt unit 3, a software interrupt unit 4, an SVC mode switching unit 5, and a USR mode rollback unit 6. Figure 2 The device shown corresponds to Figure 1 The method shown.

[0028] The SYS mode switching unit 1 is used to force the ARM Cortex-R processor to switch to SYS mode when the ThreadX system kernel schedules the application thread for the first time, and write the memory address pre-allocated to the application thread into the stack pointer register.

[0029] The clearing unit 2 is used to clear the general-purpose registers and link registers in the SYS mode of the ARM Cortex-R processor.

[0030] The hardware interrupt unit 3 is used to switch the ARM Cortex-R processor to USR mode, enable hardware interrupts, and bypass the general ThreadX system kernel shell layer through the BX instruction to transfer control to the application thread.

[0031] The entire execution process from the SYS mode switching unit 1 to the clearing unit 2 to the hardware interrupt unit 3 is continuous and cannot be interrupted by any interruption.

[0032] The software interrupt unit 4 is used to execute application threads in the USR mode of the ARM Cortex-R processor. When the application thread needs to perform high-privilege operations, it executes an SVC assembly instruction, generates a software interrupt, and the ARM Cortex-R processor automatically backs up the CPSR completely to SPSR_svc, while saving the breakpoint address to the link register.

[0033] The SVC mode switching unit 5 is used to read the address of the SVC assembly instruction, backtrack to read the binary machine code of the SVC assembly instruction, extract the immediate value from it, and automatically map the immediate value to the address of the C language API function in the ThreadX system kernel for execution. The ARM Cortex-R processor automatically enters SVC mode.

[0034] The USR mode rollback unit 6 is used to switch the ARM Cortex-R processor back to USR mode after the ThreadX system kernel has finished processing the high-privilege operation requested by the application thread, return control to the application thread, and restore SPSR_svc to CPSR.

[0035] The ARM Cortex-R processor lacks a dual-stack pointer mechanism. This invention does not employ ThreadX Modules technology, nor does it modify the native ThreadX core scheduling algorithm, enabling application threads to safely call ThreadX system kernel services via software interrupts. Compared to ThreadX Modules technology, this invention has extremely low performance and memory overhead, incurring only a few assembly instruction interception overheads. Furthermore, this invention does not separate the system kernel from the application; the two are linked, compiled, and communicate uniformly, eliminating cross-domain calls.

[0036] The above are merely preferred embodiments of the present invention and are not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A mode switching method for an ARM Cortex-R processor in a ThreadX system, characterized in that, Includes the following steps; Step S1: When the ThreadX system kernel schedules the application thread for the first time, it forces the ARM Cortex-R processor to switch to SYS mode and writes the memory address pre-allocated to the application thread into the stack pointer register. Step S2: In SYS mode, the ThreadX system kernel of the ARM Cortex-R processor clears the general-purpose registers and link registers; Step S3: The ThreadX system kernel switches the ARM Cortex-R processor to USR mode, enables hardware interrupts, and bypasses the ThreadX system kernel shell by using the jump and state switching BX instruction to transfer control to the application thread. The entire execution process from step S1 to step S3 is continuous and cannot be interrupted in any way. Step S4: The ARM Cortex-R processor executes the application thread in USR mode; when the application thread needs to perform high-privilege operations, it executes the SVC assembly instruction to generate a software interrupt. The ARM Cortex-R processor automatically backs up the current program status register CPSR in the current non-privileged state to the backup program status register SPSR_svc in SVC mode, and saves the breakpoint address to the link register. Step S5: The ThreadX system kernel reads the address of the SVC assembly instruction, backtracks to read the binary machine code of the SVC assembly instruction and extracts it, automatically assigns the immediate value to the corresponding address of the C language API function in the ThreadX system kernel for execution; the ARM Cortex-R processor automatically enters SVC mode; Step S6: After the ThreadX system kernel finishes processing the high-privilege operation requested by the application thread, it switches the ARM Cortex-R processor back to USR mode, returns control to the application thread, and simultaneously performs the restoration of SPSR_svc to CPSR.

2. The mode switching method for the ARM Cortex-R processor in the ThreadX system according to claim 1, characterized in that, In step S1, the ARM Cortex-R processor is forcibly switched to SYS mode by modifying the mode control bit in the CPSR inside the ARM Cortex-R processor.

3. The mode switching method for the ARM Cortex-R processor in the ThreadX system according to claim 1, characterized in that, In step S1, the SYS mode and USR mode of the ARM Cortex-R processor physically share the stack pointer register.

4. The mode switching method for the ARM Cortex-R processor in the ThreadX system according to claim 1, characterized in that, In step S5, the C language API functions in the ThreadX system kernel refer to the native ThreadX system services, which are core API functions provided by the Thread system kernel for task management, synchronization, communication, and time control.

5. The mode switching method for the ARM Cortex-R processor in the ThreadX system according to claim 4, characterized in that, Step S5 does not modify the source code of the ThreadX system kernel; it simply calls the native ThreadX system service after recognizing the immediate value, which is a non-intrusive mapping method.

6. The mode switching method for the ARM Cortex-R processor in the ThreadX system according to claim 4, characterized in that, In step S6, the MOVS pc, lr exception return instruction is used; MOV indicates that data transfer is performed, S indicates that SPSR_svc is automatically copied to CPSR, pc indicates that the destination register is the program counter, and lr indicates that the source register is the link register.

7. A mode switching device for an ARM Cortex-R processor in a ThreadX system, characterized in that, Includes a SYS mode switching unit, a clearing unit, a hardware interrupt unit, and a software interrupt unit; The SYS mode switching unit is used to force the ARM Cortex-R processor to switch to SYS mode when the ThreadX system kernel schedules the application thread for the first time, and write the memory address pre-allocated to the application thread into the stack pointer register. The clearing unit is used to clear the general-purpose registers and link registers in the SYS mode of the ARM Cortex-R processor; The hardware interrupt unit is used to switch the ARM Cortex-R processor to USR mode, enable hardware interrupts, and bypass the ThreadX system kernel shell layer through the BX instruction to transfer control to the application thread. The entire execution process from the SYS mode switching unit to the clearing unit to the hardware interrupt unit is continuous and cannot be interrupted by any interruption. The software interrupt unit is used to execute the application thread in the USR mode of the ARM Cortex-R processor. When the application thread needs to perform high-privilege operations, it executes the SVC assembly instruction to generate a software interrupt. The ARM Cortex-R processor automatically backs up the current program status register CPSR in the current non-privileged state to the backup program status register SPSR_svc in the SVC mode, and saves the breakpoint address to the link register. The SVC mode switching unit is used to read the address of the SVC assembly instruction, backtrack to read the binary machine code of the SVC assembly instruction and extract the immediate value from it, and automatically match and transfer the immediate value to the address of the C language API function in the ThreadX system kernel for execution; the ARM Cortex-R processor automatically enters SVC mode; The USR mode rollback unit is used to switch the ARM Cortex-R processor back to USR mode after the ThreadX system kernel has finished processing the high-privilege operation requested by the application thread, return control to the application thread, and restore SPSR_svc to CPSR.

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