A data processing method

Abstract

The present disclosure provides a data processing method, each power domain in an electronic device is provided with a comparator, the method comprises: in response to the first comparator determining that the voltage of the first power domain is less than the voltage threshold of the first power domain, outputting a first interrupt signal to the field programmable gate array (FPGA); in response to receiving the first interrupt signal, the FPGA interrupts the service program; determining the target power domain based on the time stamp corresponding to all power domains and the state information of the comparator corresponding to all power domains; determining the target fault cause based on the feature value corresponding to the frequency domain waveform of the electromagnetic interference magnetic field signal in the first time interval of the time stamp corresponding to the first power domain; determining the target operation based on the target power domain and the target fault cause.

Description

Technical Field

[0001] This disclosure relates to the field of server technology, and in particular to a data processing method. Background Technology

[0002] When servers perform tasks that cause sudden load changes, the Central Processing Unit (CPU) or Graphics Processing Unit (GPU) can generate peak currents within hundreds of microseconds. According to the fundamental laws of power integrity, extremely high current changes can cause voltage drops in the power supply network on the order of microseconds to nanoseconds, potentially leading to system crashes or computational errors. Although modern high-performance accelerator cards have some power management and emergency braking capabilities, their design goals are macroscopic power capping and hardware protection after severe faults, with response delays typically on the order of hundreds of microseconds to milliseconds. Such mechanisms cannot effectively handle power supply voltage transients on the order of microseconds to nanoseconds, nor can they achieve early prediction, fault type diagnosis, and precise location of such events. Summary of the Invention

[0003] This disclosure provides a data processing method to at least solve the above-mentioned technical problems existing in the prior art.

[0004] According to a first aspect of this disclosure, a data processing method is provided, wherein a comparator is provided in each power domain of an electronic device, the method comprising: In response to the first comparator determining that the voltage of the first power supply domain is less than the voltage threshold of the first power supply domain, a first interrupt signal is output to the field programmable gate array. In response to receiving a first interrupt signal, the field-programmable gate array (FPGA) then responds by determining the timestamp corresponding to the first power domain, the timestamp corresponding to at least one second power domain in the electronic device, the status information of at least one second comparator, and the frequency domain waveform of the electromagnetic interference magnetic field signal in a first time interval including the timestamp corresponding to the first power domain, collected by at least one sampling point. The target power domain is determined based on the timestamps corresponding to all power domains and the state information of the comparators corresponding to all power domains. Based on the characteristic values ​​corresponding to the frequency domain waveform of the electromagnetic interference magnetic field signal in the first time interval corresponding to the timestamp of the first power domain, the cause of the target fault is determined. The target operation is determined based on the target power domain and the target fault cause.

[0005] In the above scheme, the inverting input of each comparator is connected in parallel to the voltage acquisition point on the corresponding power domain through a filter network; the non-inverting input of each comparator is connected to the voltage threshold. The output of each comparator is connected to the first pin of the field-programmable gate array; the first pin is the input of the interrupt service routine.

[0006] The method in the above scheme further includes: Real-time acquisition of the average voltage and standard deviation of voltage for each power domain; Based on the smoothed real-time average voltage, real-time voltage standard deviation, upper voltage limit, lower voltage limit, regulation coefficient, and real-time load rate of each power domain, the voltage threshold of each power domain is determined. The voltage thresholds for each power domain are updated based on the real-time average voltage and real-time standard deviation of each power domain, which are collected in real time.

[0007] In the above scheme, determining the target power domain based on the timestamps corresponding to all power domains and the state information of the comparators corresponding to all power domains includes: Traverse the topology of each power domain and determine the power domain corresponding to the timestamp that satisfies the first condition, which is the target power domain.

[0008] In the above scheme, the power domain corresponding to the timestamp that satisfies the first condition includes: Traverse the topological relationships of each power domain and determine the rules corresponding to any two power domains with topological relationships. Based on the timestamps and propagation delays of the two power domains included in each rule, the target power domain is determined, specifically including: If, in any rule, the timestamp of the upstream power domain is earlier than the timestamp of the downstream power domain, and the difference between the timestamp of the downstream power domain and the timestamp of the upstream power domain is less than the propagation delay, and the state information representation of the comparator corresponding to the upstream power domain is abnormal, then the upstream power domain is determined to be the target power domain.

[0009] In the above scheme, determining the cause of the target fault based on the characteristic values ​​corresponding to the frequency domain waveform of the electromagnetic interference magnetic field signal in the first time interval corresponding to the timestamp of the first power domain includes: Based on the spectral data corresponding to the waveform of the electromagnetic interference magnetic field signal in the first time interval, the characteristic values ​​corresponding to the frequency domain waveform of the electromagnetic interference magnetic field signal are determined. The cause of the target fault is determined based on the characteristic values ​​corresponding to the frequency domain waveform of the electromagnetic interference magnetic field signal.

[0010] In the above scheme, determining the cause of the target fault based on the characteristic values ​​corresponding to the frequency domain waveform of the electromagnetic interference magnetic field signal includes: The energy of a preset frequency band in the spectral data of the waveform of an electromagnetic interference magnetic field signal is the characteristic value corresponding to the signal waveform; If the characteristic value is greater than the product of the historical energy baseline and the first coefficient, the cause of the target fault is determined to be capacitor aging. Alternatively, in response to the characteristic value being greater than the product of the historical energy baseline and the second coefficient, the cause of the target fault is determined to be capacitor failure; wherein the second coefficient is greater than the first coefficient; Alternatively, if the harmonic energy in the spectral data is greater than the product of the third coefficient and the switching coefficient, the cause of the target fault is determined to be a distortion of the switching characteristics. Alternatively, if the energy of the ultra-wideband in the spectrum data is greater than the product of the energy of the wideband noise generated by the arc discharge and the fourth coefficient, then the cause of the target fault is determined to be a short circuit. Alternatively, if the peak value of the subharmonic of the switching frequency in the spectral data is greater than the mean value of the subharmonic, then the cause of the target fault is determined to be inductor saturation.

[0011] The method in the above scheme further includes: The confidence level of the target power domain is determined based on the timestamp corresponding to the target power domain and the timestamps of all downstream power domains of the target power domain. Based on the characteristic values ​​and baseline values ​​corresponding to the frequency domain waveform of the electromagnetic interference magnetic field signal, the confidence level of the target fault cause is determined. The total confidence level is determined based on the confidence level of the target power domain and the confidence level of the target fault cause.

[0012] In the above scheme, determining the confidence level of the target power domain based on the timestamp corresponding to the target power domain and the timestamps of all downstream power domains of the target power domain includes: Determine the timestamp of the target power domain and the difference between the timestamps of all downstream power domains; If the difference between each timestamp is less than the first preset threshold, then the confidence level of the target power domain is the first threshold. If the difference between any timestamp and the first preset threshold is less than the second preset threshold, then the confidence level of the target power domain is the second threshold. If the difference between any timestamp and the first preset threshold is greater than or equal to the second preset threshold, or if the timestamp of the upstream power domain is later than the timestamp of the downstream power domain, then the confidence level of the target power domain is the third threshold. Among them, the first threshold is greater than the second threshold, and the second threshold is greater than the third threshold.

[0013] In the above scheme, determining the target operation based on the target power domain and the target fault cause includes one of the following: Reduce the parameters of the cooling system to reduce its power consumption; The output voltage of the power converter can be fine-tuned via the bus interface; The field-programmable gate array transmits the timestamp, the identifier of the target power domain, the cause of the target fault, and the total confidence level to the board management controller, which then reports to the server.

[0014] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0015] The above and other objects, features, and advantages of this disclosure will become readily apparent from the following detailed description of exemplary embodiments, taken in conjunction with the accompanying drawings. Several embodiments of this disclosure are illustrated in the drawings by way of example and not limitation, in which: In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts.

[0016] Figure 1 A schematic diagram of a first optional flow of the data processing method provided in this embodiment of the present disclosure is shown; Figure 2 A schematic diagram of a second optional flow of the data processing method provided in an embodiment of this disclosure is shown; Figure 3 A schematic diagram of a third optional flow of the data processing method provided in this embodiment of the present disclosure is shown; Figure 4 A schematic diagram of a first optional structure of the data processing apparatus provided in this disclosure embodiment is shown; Figure 5 A schematic diagram of a second optional structure of the data processing apparatus provided in an embodiment of this disclosure is shown; Figure 6 A schematic diagram of the composition structure of an electronic device according to an embodiment of the present disclosure is shown. Detailed Implementation

[0017] To make the objectives, features, and advantages of this disclosure more apparent and understandable, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0018] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0019] In the following description, the terms "first" and "second" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first" and "second" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0020] Unless otherwise defined, all technical and scientific terms used in this disclosure have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in this disclosure is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0021] It should be understood that in the various embodiments of this disclosure, the sequence number of each implementation process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure.

[0022] In related technologies, power health monitoring of high-performance computing servers, especially artificial intelligence (AI) servers, may pose three major industry-wide technical challenges due to nanosecond / microsecond-level voltage transient events: 1) Early failures caused by missed detection of nanosecond-level transient events When AI servers perform tasks with sudden load changes, such as inference computation, the CPU or GPU can generate peak currents within hundreds of microseconds (e.g., 100A / 1200W for an NVIDIA H20 card). According to the fundamental law of power integrity (ΔV=L×di / dt), extremely high di / dt can cause voltage drops in the power supply network on the order of microseconds to nanoseconds, potentially leading to system crashes or computational errors. Although modern high-performance accelerator cards (such as the NVIDIA H20) have some power management and emergency braking functions (such as Power Brake), their design goals are macroscopic power capping and hardware protection after severe faults, with response delays typically on the order of hundreds of microseconds to milliseconds. Such mechanisms cannot effectively cope with power supply voltage transient drops on the order of microseconds to nanoseconds, let alone achieve early prediction, fault type diagnosis, and precise location of such events. Traditional monitoring solutions are limited by the physical sampling rate of the analog-to-digital converter (ADC) (current power monitoring ADC chips have a sampling rate of only 82Hz) and the processing delay of the baseboard management controller (BMC). Such events are beyond the capabilities of traditional monitoring solutions. On the other hand, the equivalent series inductance (ESL) of capacitors creates a fatal blind spot in their high-frequency response. For instantaneous current demands caused by di / dt in the microsecond to nanosecond range, the inductance of the capacitor itself will prevent the instantaneous release of current, causing it to be unable to respond to high-frequency transients. As a result, it cannot provide early warning of hardware failures such as degradation of the equivalent series resistance (ESR) of capacitors and gate breakdown of metal-oxide-semiconductor field-effect transistors (MOSFETs).

[0023] 2) High false alarm rate leads to ineffective operation and maintenance. Existing solutions rely on fixed threshold criteria (e.g., alarming when voltage <11.4V), which cannot distinguish between compliant load transients (e.g., peak values ​​during AI training, conforming to processor power consumption (Embedded Dynamic Power Management, EDPp) specifications) and genuine hardware faults (e.g., micro-short circuits on printed circuit boards (PCBs)). This results in a high false alarm rate, leading to ineffective maintenance and downtime losses.

[0024] 3) The fault propagation chain across power domains is broken. Multi-level power supply networks (such as the CPU / GPU voltage regulator module (VRM) of the 12V main power supply and the Non-Volatile Memory Express (NVMe) solid-state drive (SSD)) exhibit strict temporal causal relationships. A nanosecond-level drop in upstream 12V power supply may manifest as a microsecond (µs)-level anomaly on downstream NVMe devices. Current technologies lack nanosecond-level timestamp synchronization capabilities, making it impossible to construct this fault propagation chain, leading to root cause analysis failures.

[0025] In view of the deficiencies existing in the related technologies, this disclosure provides a data processing method to at least solve some or all of the above-mentioned technical problems.

[0026] Figure 1 A schematic diagram of a first alternative flow of the data processing method provided in this disclosure is shown, and the steps will be described accordingly.

[0027] In step S101, in response to the first comparator determining that the voltage of the first power supply domain is less than the voltage threshold of the first power supply domain, a first interrupt signal is output to the field programmable gate array.

[0028] In some embodiments, the electronic device can be a server, computer host, laptop, or other device capable of providing high-performance computing; the power domain (or power rail) of the electronic device includes at least one of the following: 3.3V standby power domain, DDR memory power domain, PCIe power domain, VRM multi-stage converter power domain, and CPU / GPU power domain, and a comparator is set for each power domain; wherein, the inverting input terminal of the comparator corresponding to each power domain is connected in parallel to the voltage acquisition point on the corresponding power domain through a filter network; the non-inverting input terminal of each comparator is connected to the voltage threshold (i.e., voltage threshold); the output terminal of each comparator is connected to the first pin of the field-programmable gate array; the first pin is the input of the interrupt service routine.

[0029] In some embodiments, the voltage threshold corresponding to each power domain is different.

[0030] In some embodiments, the first power domain is any power domain in an electronic device; the first comparator acquires the voltage of the first power domain based on the inverting input terminal; the non-inverting input terminal of the first comparator acquires the voltage threshold of the first power domain, i.e., the voltage threshold, and compares the voltage of the first power domain with the voltage threshold. In response to the voltage of the first power domain being greater than or equal to the voltage threshold of the first power domain, step S101 is repeated, indicating that the first power domain is normal at this time.

[0031] If the voltage of the first power domain is less than the voltage threshold of the first power domain, indicating a voltage transient event in the first power domain, a first interrupt signal is output to the FPGA. The first interrupt signal is used to latch the current timestamp to determine the target power domain where the fault occurred.

[0032] In step S102, in response to receiving the first interrupt signal, the field-programmable gate array (FPGA) responds by determining the timestamp corresponding to the first power domain, the timestamp corresponding to at least one second power domain in the electronic device, the status information of at least one second comparator, and the frequency domain waveform of the electromagnetic interference magnetic field signal in the first time interval including the timestamp corresponding to the first power domain, collected by at least one sampling point.

[0033] In some embodiments, after the FPGA receives the first interrupt signal, an interrupt service response is initiated, the current timestamp is latched, and the current timestamp is determined to be the timestamp corresponding to the first power domain. The interrupt service is software logic implemented based on the FPGA, used to determine the cause of the fault and the target power domain.

[0034] In some embodiments, the FPGA further determines the timestamp of the most recent triggering of at least one second power domain in the electronic device, i.e., the timestamp corresponding to the second power domain; and the status information of at least one second comparator. The second power domain is any power domain in the electronic device other than the first power domain; the second comparator is the comparator corresponding to the second power domain; the status information of the second comparator includes the current output level state of the second comparator, the purpose of which is to determine whether the power domain corresponding to it is currently experiencing an abnormal voltage transient drop.

[0035] The comparator has two inputs: the voltage of the power supply domain and the voltage threshold of the power supply domain. The output of the comparator is the result of the voltage of the power supply domain and the voltage threshold of the power supply domain, which is usually a high level or a low level. Specifically, if the voltage of the power supply domain is greater than the voltage threshold of the power supply domain, the comparator outputs a low level; if the voltage of the power supply domain is greater than or equal to the voltage threshold of the power supply domain, the comparator outputs a high level, that is, the comparator flips to generate a rising edge.

[0036] In some embodiments, the FPGA further acquires the frequency domain waveform of the electromagnetic interference magnetic field signal in the first power domain during the first time interval. Optionally, the FPGA can acquire the waveform of the electromagnetic interference magnetic field signal in the first power domain and transform the waveform to the frequency domain using a fast Fourier transform to obtain the frequency domain waveform.

[0037] The first time interval is the time interval that includes the timestamp of the first power domain; that is, the time interval consisting of a period of time before and after the first power domain triggers the first interrupt signal.

[0038] Step S103: Determine the target power domain based on the timestamps corresponding to all power domains and the state information of the comparators corresponding to all power domains.

[0039] In some embodiments, upstream and downstream relationships, i.e., rules, exist among all power domains of an electronic device. The topological relationships of each power domain can be determined based on the ROM, and then the rules between any two power domains with a topological relationship can be determined based on the topological relationships of each power domain. The rules include two power domains with an upstream and downstream relationship, and the relative positions of the two power domains.

[0040] The target power domain is determined based on the timestamps and propagation delays of the two power domains included in each rule. The target power domain is the power domain that causes the abnormal transient voltage drop in the first power domain.

[0041] Step S104: Determine the cause of the target fault based on the characteristic value corresponding to the frequency domain waveform of the electromagnetic interference magnetic field signal in the first time interval of the timestamp corresponding to the first power domain.

[0042] In some embodiments, step S103 can be executed in parallel with step S104, that is, step S103 determines the fault location and step S104 determines the fault cause.

[0043] In some embodiments, different fault causes can lead to different characteristics in the frequency domain waveform of electromagnetic interference magnetic field signals, and the target fault cause can be determined based on the characteristic values ​​corresponding to the frequency domain waveform.

[0044] The characteristic values ​​corresponding to the frequency domain waveform include the energy of a preset frequency band in the spectrum data, and the preset frequency band can be determined according to actual needs or experimental results.

[0045] Step S105: Determine the target operation based on the target power domain and the target fault cause.

[0046] In some embodiments, the FPGA takes corresponding actions to repair the fault based on the target power domain and the target fault cause. The target actions may include at least one of adjusting the heat dissipation system parameters, reducing system power consumption, and adjusting the bus interface output voltage.

[0047] In some alternative embodiments, the FPGA may also send at least one of the timestamp corresponding to the first power domain, the identifier of the target power domain, and the target fault cause to the BMC, so that the BMC reports to the server.

[0048] In some embodiments, the FPGA can determine the confidence level of the target power domain based on the target power domain and the target fault cause, that is, determine the confidence level of the target power domain in generating the target fault cause; and determine the target operation based on the confidence level of the target power domain.

[0049] Thus, through the data processing method provided in this embodiment, voltage transient drop events can be detected by a comparator, and the source of the fault can be located to a specific power domain through time-series causal analysis. Furthermore, the fault type can be analyzed through EMI spectrum analysis, simplifying the operation and maintenance action from replacing the entire board to checking or replacing specific components in a specific area, which greatly improves the operation and maintenance efficiency and reduces costs.

[0050] Figure 2 A second alternative flowchart of the data processing method provided in this disclosure embodiment is shown, and will be described according to each step.

[0051] Step S201: Determine the voltage threshold for each power domain.

[0052] In some embodiments, the real-time average voltage and real-time standard deviation of each power domain are collected in real time.

[0053] In practice, the following operations can be performed on each power domain: the voltage of the power domain is collected within a second time interval based on a preset sampling frequency, and the real-time voltage mean and real-time voltage standard deviation of the power domain are determined based on the multiple voltages collected within the second time interval.

[0054] In some embodiments, the real-time average voltage and real-time voltage standard deviation of each power domain are smoothed, and the voltage threshold of each power domain is determined based on the smoothed real-time average voltage, smoothed real-time voltage standard deviation, upper voltage limit, lower voltage limit, adjustment coefficient, and real-time load rate.

[0055] The upper and lower voltage limits may include voltage limits preset according to industry safety specifications for the power domain.

[0056] In specific implementation, the voltage threshold It can be determined based on the following formula: (1) in, This is a clamping function used to restrict a value to between a specified minimum and maximum value. In this embodiment of the disclosure, the purpose of the clamping function is to... Limited to and between. The average real-time voltage after smoothing; The standard deviation of the real-time voltage after smoothing; This is the upper limit of voltage; This is the lower limit of voltage. For adjustment coefficient and This represents the real-time load rate.

[0057] In some alternative embodiments, a multi-channel DAC (such as the TI DAC5311, I2C interface, 12-bit precision) can be used. The FPGA executes the above formula (1) in real time and refreshes the calculation result to the corresponding channel of the DAC via the I2C bus. The DAC output then generates a precise analog voltage corresponding to the digital value. And input it to the non-inverting input of the comparator.

[0058] In some alternative embodiments, a PWM wave can be generated using a GPIO pin of the FPGA, and converted into a smooth analog voltage through an RC low-pass filter (e.g., a 10kΩ resistor + a 1μF capacitor). The dynamic threshold calculation module within the FPGA executes the above formula (1) in real time to calculate the voltage threshold. By dynamically adjusting the duty cycle of the PWM wave, the average value of the output analog voltage is precisely controlled. The relationship is as follows: .

[0059] Where N is the maximum value of the PWM counter, This is the collector power supply voltage.

[0060] To ensure the final output Absolutely no less than After the output of the RC filter, a voltage clamping circuit consisting of a precision reference source (such as an LM4040) and an operational amplifier is added. This circuit will clamp the final output voltage. The lower voltage limit is hard-limited at This eliminates the risk of an excessively low reference voltage due to software logic errors at the hardware level.

[0061] In step S202, the comparator corresponding to each power domain compares the voltage of the power domain with the voltage threshold in real time.

[0062] In some embodiments, the inverting input of each comparator is connected in parallel to the voltage acquisition point on the corresponding power domain through a filter network; the non-inverting input of each comparator is connected to the voltage threshold; and the output of each comparator is connected to the first pin of the field-programmable gate array (FPGA); the first pin is the input of the interrupt service routine.

[0063] In some embodiments, the comparator compares the power supply voltage with a voltage threshold, and outputs a high level in response to the power supply voltage being less than the voltage threshold; and outputs a low level in response to the power supply voltage being greater than or equal to the voltage threshold.

[0064] In some embodiments, step S203 is executed in response to a high level output from the comparator. Step S202 is repeated in response to a low level output from the comparator.

[0065] Step S203: Determine the timestamps of all power domains, and the frequency domain waveforms of electromagnetic interference magnetic field signals collected at at least one sampling point, including the timestamps corresponding to the first power domain, for a first time interval.

[0066] In some embodiments, when the power supply voltage drops, the comparator output toggles, generating a rising edge. The FPGA's interrupt service routine (a high-priority state machine) responds immediately, latching the current timestamp. Optionally, the interrupt service can latch the current timestamp from an internal 64-bit high-speed counter (driven by a 200MHz clock with 5ns accuracy).

[0067] In some embodiments, the FPGA reads the status information of all second comparators via GPIO, as well as the timestamp of the last time all second comparators generated a high level.

[0068] Step S204: Determine the target power domain based on the timestamps corresponding to all power domains and the state information of the comparators corresponding to all power domains.

[0069] In some embodiments, the FPGA queries the topology of each power domain in the ROM to determine the rules corresponding to any two power domains with a topological relationship. A topological relationship between power domains can include an upstream and downstream relationship between the two power domains.

[0070] In some embodiments, the FPGA traverses all rules, and for a rule (A, B, T_max), it checks whether its timestamp meets a first condition. If the first condition is met, the power domain corresponding to the timestamp that meets the first condition is determined to be the target power domain.

[0071] In practice, in the rule (A, B, T_max), A represents power domain A, B represents power domain B, and power domain B is the power domain upstream of power domain A. This represents the propagation delay between power domain A and power domain B.

[0072] In specific implementation, the first condition may include: the timestamp of the upstream power domain is earlier than the timestamp of the downstream power domain, and the difference between the timestamp of the downstream power domain and the timestamp of the upstream power domain is less than the propagation delay, and the state information representation of the comparator corresponding to the upstream power domain is abnormal, then the upstream power domain is determined to be the target power domain.

[0073] Among them, the timestamp of the upstream power domain Earlier timestamps than downstream power domains ,include The difference between the timestamp of the downstream power domain and the timestamp of the upstream power domain is less than the propagation delay. .

[0074] Step S205: Determine the cause of the target fault based on the characteristic value corresponding to the frequency domain waveform of the electromagnetic interference magnetic field signal in the first time interval corresponding to the timestamp of the first power domain.

[0075] In some embodiments, the characteristic values ​​corresponding to the frequency domain waveform of the electromagnetic interference magnetic field signal are determined based on the spectral data corresponding to the waveform of the electromagnetic interference magnetic field signal in the first time interval.

[0076] In specific implementation, the energy of a preset frequency band in the spectral data of the electromagnetic interference magnetic field signal waveform of the FPGA is the characteristic value corresponding to the signal waveform.

[0077] In some embodiments, in response to the characteristic value being greater than the product of the historical energy baseline and a first coefficient, the cause of the target fault is determined to be capacitor aging. In this case, the preset frequency band is the low-frequency band.

[0078] In practice, the main characteristic of capacitor aging or increased ESR is a significant increase in energy in the low-frequency range (100kHz - 2MHz), leading to a degradation in filter performance due to increased ESR. Therefore, if E_low_measured> E_low_baseline determines the cause of the target fault as capacitor aging. Here, E_low_measured is the characteristic value, and E_low_baseline is the historical energy baseline in the low-frequency band. The first coefficient is 1.5; optionally, the first coefficient can be 1.5.

[0079] In some embodiments, in response to the characteristic value being greater than the product of the historical energy baseline and a second coefficient, the cause of the target fault is determined to be capacitor failure; wherein the second coefficient is greater than the first coefficient. In this case, the radio frequency band is the mid-to-high frequency band.

[0080] In practice, the main characteristics of MLCC capacitor failure (reduced capacitance / short circuit) are increased energy in the mid-to-high frequency range (10MHz-50MHz) and decreased high-frequency noise suppression capability due to decoupling network failure. If E_mid_measured> If E_mid_baseline is selected, the cause of the target fault is determined to be the failure of the MLCC capacitor.

[0081] Where E_mid_measured is the eigenvalue and E_mid_baseline is the historical energy baseline of the mid-frequency band. This is the second coefficient; optionally, the second coefficient can be 2.

[0082] In some embodiments, in response to the harmonic energy in the spectral data being greater than the product of the third coefficient and the fundamental frequency of the switching coefficient, the cause of the target fault is determined to be a distortion of the switching characteristics.

[0083] In practical implementation, the main characteristic of MOSFET switching characteristic distortion is an abnormal increase in the energy amplitude of the fundamental frequency and its harmonics (such as the 300kHz fundamental frequency and its 600kHz, 900kHz, etc. harmonics), caused by intensified ringing of the switching waveform. If any major harmonic energy E_sw_n_measured> If E_sw_n_baseline is used, the cause of the target fault is determined to be a MOSFET fault.

[0084] Where E_sw_n_measured represents the eigenvalues, and E_sw_n_baseline represents the fundamental frequency of the switching coefficients. This is the third coefficient. Optionally, the third coefficient can be 2.

[0085] In some embodiments, in response to the energy of the ultra-wideband in the spectrum data being greater than the product of the energy of the wideband noise generated by the arc discharge and the fourth coefficient, the cause of the target fault is determined to be a short circuit.

[0086] In practice, the main characteristic of PCB arc / partial short circuits is a significant increase in overall background noise energy across an ultra-wideband (50MHz - 200MHz) due to the wide-spectrum noise generated by arc discharge, which may be more pronounced at higher frequencies. If E_wideband_baseline is selected, the cause of the target fault is determined to be a suspected short circuit. In this case, the preset frequency band is the ultra-wideband.

[0087] Where E_wideband_measured is the eigenvalue, and E_wideband_baseline is the energy of the wideband noise generated by the arc discharge. The fourth coefficient is optional and can be 3.

[0088] In some embodiments, in response to the peak value of the subharmonic of the switching frequency in the spectrum data being greater than the mean value of the subharmonic, the cause of the target fault is determined to be inductor saturation.

[0089] In practical implementation, the main characteristic of inductor saturation is a significant energy peak at the subharmonic of the switching frequency (e.g., 150kHz for a 300kHz switching frequency), caused by subharmonic oscillations. If E_subharmonic_measured> If ×E_subharmonic_baseline is used, then the cause of the target fault is determined to be inductor saturation.

[0090] Where E_subharmonic_measured is the eigenvalue, i.e., the peak value of the subharmonic at the switching frequency, and E_subharmonic_baseline is the mean value of the subharmonic. The fifth coefficient can be 2.5.

[0091] In some embodiments, if the energy of the spectrum data increases uniformly across the entire frequency band without any abnormal spikes, the cause of the target fault is determined to be a normal load change characteristic.

[0092] It should be noted that multiple dimensions of the target fault cause may be determined based on the feature value, that is, one target fault cause or multiple target fault causes may be determined.

[0093] In some embodiments, the baseline value in the rule base that is compared with the feature value can be a relative threshold (such as 1.5 times, 2.0 times, etc.) relative to the baseline energy. This baseline value is obtained by self-learning its historical energy data of each frequency band under normal conditions. This method based on relative change has good adaptability and resistance to individual differences. All judgment rules can be executed in parallel, thereby realizing the synchronous diagnosis and identification of multiple fault modes.

[0094] Step S206: Determine the total confidence level based on the target power domain and the target fault cause.

[0095] In some embodiments, the confidence level of the target power domain is determined based on the timestamp corresponding to the target power domain and the timestamps of all downstream power domains of the target power domain.

[0096] In specific implementation, the timestamp of the target power domain and the difference between the timestamps of all downstream power domains are determined. If the difference between each timestamp is less than a first preset threshold, the confidence level of the target power domain is the first threshold. If the difference between any timestamp and the first preset threshold is less than a second preset threshold, the confidence level of the target power domain is the second threshold. If the difference between any timestamp and the first preset threshold is greater than or equal to the second preset threshold, or if the timestamp of the upstream power domain is later than the timestamp of the downstream power domain, the confidence level of the target power domain is the third threshold. Wherein, the first threshold is greater than the second threshold, and the second threshold is greater than the third threshold.

[0097] Specifically, check whether the actual measured event time difference conforms to the preset power topology dependency rules. If the difference Δt = |t1 - t0| between the 12V dropout time t0 and the CPU VCORE dropout time t1 is within the preset rule range (e.g., 1μs < Δt < 2μs), then the confidence score for this item is very high (e.g., preset 95%). Partial match: If Δt is close to the range boundary (e.g., 2.1μs), then the score is reduced (e.g., 70%). No match: If the event order is completely reversed or the time difference is huge, then the score for this item is extremely low (e.g., 10%).

[0098] Among them, 1μs<Δt<2μs can be the first preset threshold; 2.1μs is the second preset threshold.

[0099] In some embodiments, the confidence level of the target fault cause is determined based on the ratio between the feature value E_measured and the baseline value E_baseline.

[0100] In practice, the ratio = E_measured / E_baseline; the confidence level of the target fault cause is determined based on the range of the ratio. A higher ratio results in a higher confidence level C_spectrum for the target fault cause.

[0101] For example, if the ratio is greater than 3.0, then C_spectrum = 100% (severely exceeding the limit, definitely a fault); if 2.0 < ratio < 3.0, then C_spectrum = 75%; if the 1.5 rule threshold < ratio < 2.0, then C_spectrum = 50% (just exceeding the limit, suspicious).

[0102] In some embodiments, the confidence levels of the target power domain and the target fault cause are weighted and summed to determine the total confidence level.

[0103] In some embodiments, it is determined whether to take the target action based on the total confidence level. For example, if the total confidence level is greater than or equal to a preset confidence threshold, it is determined that the target action should be taken.

[0104] In some embodiments, the target operation may include: Collaborative power consumption management: By adjusting the operating status of high-power auxiliary loads such as liquid cooling pumps and fans, the total power consumption of the system can be reduced instantaneously, relieving power supply pressure and improving the system's survivability under fault conditions.

[0105] Parameter compensation adjustment: Preventive and compensatory fine-tuning of the output voltage of the power converter (VRM) is performed through bus interfaces such as PMBus to optimize power quality after a drop event or compensate for device aging.

[0106] Accurate fault reporting: The FPGA encapsulates the diagnostic results into a data frame of a specific format (e.g., format: [start character][timestamp][fault source ID][fault type][confidence level][end character]), and sends it to the BMC via UART or I2C interface. The BMC then reports the data to the cloud operation and maintenance platform through its standard Redfish interface, enabling predictive maintenance.

[0107] Thus, the data processing method provided in this disclosure solves the nanosecond-level missed detection problem caused by insufficient sampling rate of traditional ADCs by using a dedicated hardware comparator, and introduces an adaptive dynamic voltage threshold to suppress false alarms; through time-series causal and spectrum analysis, the target power domain of the fault can be located and the cause of the target fault can be diagnosed, improving operation and maintenance efficiency; all processing logic is implemented based on FPGA, with an end-to-end delay of <10μs, and existing ADCs are reused, resulting in low addition costs; combined with multi-physics field fusion analysis, it can solve the problem of transient power fault detection and diagnosis in high-performance servers.

[0108] Figure 3 A third alternative flowchart of the data processing method provided in this disclosure embodiment is shown, and will be described according to each step.

[0109] Step S301: Determine the voltage threshold for each power domain, and at least one rule.

[0110] In some embodiments, after the electronic device is powered on, the initial voltage baselines of each power domain, which are obtained in advance through factory calibration, are loaded from non-volatile memory, i.e., the mean and variance of the initial voltage and the adjustment factor K.

[0111] In some embodiments, after the electronic device system enters the operating state, the FPGA runs an online adaptive algorithm based on equation (1) to recursively and smoothly update the real-time average voltage of each power domain. ) and standard deviation ( The algorithm employs exponential smoothing averaging with a smoothing factor set close to 1 (e.g., 0.999) to ensure that the baseline only reflects the long-term, slow trend of voltage change and is insensitive to instantaneous drop events, thus effectively preventing the threshold from being contaminated by abnormal events. The same method is used to obtain the spectral energy characteristics and establish and update the dynamic energy baseline values ​​for each frequency band.

[0112] In some embodiments, the FPGA programs the power domain topology (e.g., 12V-5V-Vcore) into the FPGA's Block ROM in the form of a lookup table. The table entry format is: {Upstream power domain ID, Downstream power domain ID, Maximum allowable propagation delay}.

[0113] Step S302: Real-time monitoring of the voltage of each power domain based on the comparator.

[0114] In some embodiments, formula (1) is calculated periodically (e.g., once per second) to obtain the latest voltage threshold.

[0115] In some embodiments, when the voltage of the power domain drops, the output of the comparator flips and generates a rising edge. The interrupt service program of the FPGA (a high-priority state machine) responds immediately and latches the current timestamp from the internal 64-bit high-speed counter (driven by a 200MHz clock, with an accuracy of 5ns).

[0116] Step S303, determining the target power domain.

[0117] In some embodiments, after the interrupt service program latches the timestamp, the current states output by all the second comparators and their timestamps of the last trigger are read through GPIO. Subsequently, the topology in the ROM is queried to determine a plurality of rules. All rules are traversed, and for a rule (A, B, T_max), it is checked whether (t_B - t_A>0)&&(t_B - t_A<T_max) is satisfied. If satisfied, it is determined that the fault originates from power domain A, that is, power domain A is the target power domain. This process processes all rules in parallel and outputs the result within 1μs.

[0118] Step S304, determining the target fault cause.

[0119] In some embodiments, while the interrupt service program latches the timestamp, the FPGA subsequently reads the complete data segment including a specific number of sampling points before and after the trigger point from the cache, and then the FFT IP core automatically starts working and outputs spectrum data.

[0120] Calculating the sum of energy in predefined frequency bands. For example, the sum of the squared amplitudes of frequency points with indexes 100-200 (corresponding to about 1-2MHz) is calculated as the "low-frequency band energy" feature.

[0121] Fault matching: comparing the feature value with a pre-stored threshold. The characteristic frequency bands and energy thresholds in the fault rule base need to be finally determined and calibrated through experiments on known faulty components (such as fault injection tests) or collecting spectrum data of a large number of on-site fault cases. If the collected values of "low-frequency band energy" exceed 150% of the historical baseline for 3 consecutive times, the diagnosis result is "Bulk capacitor aging". It specifically includes: The main characteristic of Bulk capacitor aging (increased ESR) is that the energy in the low-frequency band (100kHz - 2MHz) increases significantly, because the increased ESR leads to degradation of filtering performance. The judgment rule is: if E_low_measured>1.5 is satisfied E_low_baseline, then it is determined that the target fault cause is capacitor aging.

[0122] The main characteristics of MLCC capacitor failure (reduced capacitance / short circuit) are increased energy in the mid-to-high frequency range (10MHz - 50MHz) and decreased high-frequency noise suppression capability due to decoupling network failure. The judgment rule is: if E_mid_measured > 2.0... If E_mid_baseline is used, then the cause of the target fault is determined to be the failure of the MLCC capacitor.

[0123] The main characteristic of MOSFET switching distortion is an abnormally increased energy amplitude of the fundamental frequency and its harmonics (e.g., the 300kHz fundamental and its 600kHz, 900kHz, etc. harmonics) due to intensified ringing in the switching waveform. The criterion is: if the energy of any major harmonic E_sw_n_measured > 2.0... If E_sw_n_baseline is used, the cause of the target fault is determined to be a MOSFET fault.

[0124] The main characteristics of PCB arc / partial short circuits are a significant increase in overall background noise energy across an ultra-wideband (50MHz - 200MHz) range, caused by broadband noise generated by arc discharge, which may be more pronounced at higher frequencies. The criterion is: if E_wideband_measured > 3.0... If E_wideband_baseline is selected, the cause of the target fault is determined to be a suspected short circuit.

[0125] The main characteristic of inductor saturation is the presence of subharmonic oscillations at the switching frequency, such as a significant energy peak at a switching frequency of 150kHz versus 300kHz, caused by subharmonic oscillations. The criterion is: if E_subharmonic_measured > 2.5... If E_subharmonic_baseline is used, the cause of the target fault is determined to be inductor saturation.

[0126] The normal load mutation is characterized by a uniform increase in energy across the entire frequency band without any abnormal spikes.

[0127] The energy threshold in the rule base can preferably be a relative threshold (e.g., 1.5 times, 2.0 times, etc.) relative to the baseline energy. This baseline is obtained by the system self-learning its historical energy data for each frequency band under normal conditions. This method based on relative change has good adaptability and resistance to individual differences. All judgment rules can be executed in parallel, thereby realizing the synchronous diagnosis and identification of multiple fault modes.

[0128] Step S305: Determine the total confidence level.

[0129] In some embodiments, the total confidence level is derived by weighted fusion of the confidence level of the target power domain and the confidence level of the target fault cause.

[0130] The method for determining the confidence level of the target power domain includes checking whether the actual measured event time difference conforms to preset power topology dependency rules. If the difference Δt = |t1-t0| between the 12V dropout time t0 and the CPU VCORE dropout time t1 is within the preset rule range (e.g., 1μs < Δt < 2μs), the confidence score for this item is very high (e.g., preset 95%). Partial match: If Δt is close to the range boundary (e.g., 2.1μs), the score is reduced (e.g., 70%). Mismatch: If the event order is completely reversed or the time difference is huge, the score for this item is extremely low (e.g., 10%).

[0131] Methods for determining the confidence level of the target fault cause include: calculation formula: ratio = E_measured / E_baseline; calculating the spectral confidence level based on the range of exceedance multiples. If the ratio is greater than 3.0, then C_spectrum = 100% (severely exceeding the limit, definitely a fault); if 2.0 < ratio < 3.0, then C_spectrum = 75%; if 1.5 (rule threshold) < ratio < 2.0, then C_spectrum = 50% (just exceeding the limit, suspicious).

[0132] In some embodiments, the total confidence level = C_timing × W1 + C_spectrum × W2; W1 and W2 can be set according to actual needs or experimental results. Wherein, C_timing is the confidence level of the target power domain; C_spectrum is the confidence level of the target fault cause.

[0133] For example, if the confidence level of the target power domain is 80% and the confidence level of the target fault cause is 90%, with each having a weight of 0.5, then the overall confidence level is 0.8 × 0.5 + 0.9 × 0.5 = 0.85 (i.e., 85%).

[0134] In some embodiments, rules based on fuzzy logic may be introduced, but the multiplication model is the simplest and most efficient to implement in FPGAs.

[0135] Step S306: Take the target action based on the confidence level.

[0136] In some embodiments, it is determined whether to take the target action based on the total confidence level. For example, if the total confidence level is greater than or equal to a preset confidence threshold, it is determined that the target action should be taken.

[0137] In some embodiments, after detecting a voltage transient drop event and performing EMI diagnostics, a dynamic response can be executed based on the diagnostic results, including but not limited to: Collaborative power consumption management: "By adjusting the operating status of high-power auxiliary loads such as liquid cooling pumps and fans, the total power consumption of the system can be reduced instantaneously, relieving power supply pressure and improving the system's survivability under fault conditions."

[0138] Parameter compensation adjustment: Preventive and compensatory fine-tuning of the output voltage of the power converter (VRM) is performed through bus interfaces such as PMBus to optimize power quality after a drop event or compensate for component aging. Accurate fault reporting: The FPGA encapsulates the diagnostic results into a data frame of a specific format (format: [start character][timestamp][fault source ID][fault type][confidence level][end character]), and sends it to the BMC via UART or I2C interface. The BMC then reports the data to the cloud operation and maintenance platform through its standard Redfish interface, enabling predictive maintenance.

[0139] Thus, the data processing method provided in this disclosure solves the nanosecond-level missed detection problem caused by insufficient sampling rate of traditional ADCs by using a dedicated hardware comparator, and introduces an adaptive dynamic voltage threshold to suppress false alarms; through time-series causal and spectrum analysis, the target power domain of the fault can be located and the cause of the target fault can be diagnosed, improving operation and maintenance efficiency; all processing logic is implemented based on FPGA, with an end-to-end delay of <10μs, and existing ADCs are reused, resulting in low addition costs; combined with multi-physics field fusion analysis, it can solve the problem of transient power fault detection and diagnosis in high-performance servers.

[0140] Figure 4 A schematic diagram of a first alternative structure of the data processing apparatus provided in an embodiment of this disclosure is shown, and will be described in terms of each part.

[0141] like Figure 4 As shown in the embodiments of this disclosure, the data processing apparatus includes at least a monitoring unit and an FPGA.

[0142] The monitoring unit includes a comparator, an SMD magnetic ring probe, and a high-speed amplifier; the FPGA includes an analog-to-digital converter, a processing module, and an edge processing module.

[0143] The processing module includes a timestamp engine, a time-series causal engine, a dynamic threshold calculation engine, and a spectrum analysis engine.

[0144] In some embodiments, the comparator of the monitoring unit is communicatively connected to the power path of the electronic device's motherboard. The inverting input (-) of the comparator is directly connected in parallel to the target power test point on the server motherboard through a filter network to prevent high-frequency oscillation. The non-inverting input (+) of the comparator is connected to a voltage threshold Vref. The output of the comparator is directly connected to a dedicated high-speed GPIO pin (configured as an interrupt input) on the FPGA carrier board, and the GPIO pin is communicatively connected to the edge processing module.

[0145] In some embodiments, the FPGA may include a digital-to-analog converter (DAC) for executing the above formula (1) and refreshing the calculation result to the corresponding channel of the DAC via the I2C bus. The DAC output then generates a precise analog voltage corresponding to the digital value. And input it to the non-inverting input of the comparator.

[0146] In other embodiments, the FPGA can generate a PWM wave using a GPIO pin, which is then converted into a smooth analog voltage through an RC low-pass filter (e.g., a 10kΩ resistor + a 1μF capacitor). The dynamic threshold calculation module within the FPGA executes the above formula (1) in real time to calculate the voltage threshold. By dynamically adjusting the duty cycle of the PWM wave, the average value of the output analog voltage is precisely controlled. The relationship is as follows: .

[0147] In some embodiments, an SMD magnetic ring probe, a high-speed amplifier, and a magic converter head constitute the EMI signal acquisition channel. Specifically, an SMD magnetic ring probe (such as Texas Instruments (TI)-TMC S1100 / TMCS1101, etc.) is mounted on the board. The signal is conditioned by a high-speed amplifier (such as AD8001) and then sampled by a medium-speed ADC (such as AD9213, 100MSPS). The ADC continuously writes data to a loop buffer, and the data is locked for FFT analysis upon triggering.

[0148] The ADC continuously samples and writes data to a fixed-depth buffer in the FPGA. When the write pointer reaches the end of the buffer, it automatically returns to the starting address, overwriting the old data. When the FPGA determines that the comparator has triggered a rising edge, it immediately stops sampling and locks the current buffer contents by configuring the ADC register or directly controlling the ADC output. The FPGA then reads the complete data segment from the buffer, containing specific sampling points before and after the trigger point, thus ensuring that the complete EMI signal waveform before and after the voltage drop event is captured for FFT spectrum analysis. If computational resources are sufficient, wavelet decomposition and energy analysis can also be used to distinguish fault types by identifying energy changes in characteristic frequency bands, such as capacitor aging corresponding to a rise in low-frequency energy and MOSFET failure corresponding to a sudden change in high-frequency ringing energy.

[0149] In some embodiments, the FPGA reads data such as CPU / GPU utilization and power consumption from the BMC via I2C / SPI.

[0150] In some embodiments, the edge processor may be a Xilinx Artix-7, such as an XC7A35T FPGA. This chip provides sufficient logic cells, DSP slices (for FFT calculations), and Block RAM (for data caching).

[0151] In some embodiments, if the target operation is to adjust the parameters of the cooling system, a GPIO pin of the FPGA is configured in PWM output mode. This pin is connected to the PWM control line of the liquid cooling pump via a level shifting chip (such as TXS0108E). The pump speed is directly controlled by modifying the duty cycle register value of the FPGA's internal PWM generator.

[0152] In other embodiments, if the target operation is to adjust the output voltage of the power converter via the bus interface, the FPGA communicates with the CPU VRM controller via the PMBus protocol, sending an "OPERATION" command to finely adjust the output voltage offset. The physical layer of the PMBus protocol is I2C, and the protocol layer is implemented as a state machine within the FPGA.

[0153] Figure 5 A schematic diagram of a second alternative structure of the data processing apparatus provided in an embodiment of this disclosure is shown, and will be described in terms of each part.

[0154] In some embodiments, the data processing apparatus includes a comparison unit, a data acquisition unit, a positioning unit, a fault cause determination unit, and a repair unit.

[0155] The comparison unit is configured to output a first interrupt signal to the data acquisition unit in response to the first comparator determining that the voltage of the first power supply domain is less than the voltage threshold of the first power supply domain. The data acquisition unit is configured to respond to receiving a first interrupt signal, and then the interrupt service routine responds to determine the timestamp corresponding to the first power domain, the timestamp corresponding to at least one second power domain in the electronic device, the status information of at least one second comparator, and the frequency domain waveform of the electromagnetic interference magnetic field signal including the timestamp corresponding to the first power domain collected by at least one sampling point in the first time interval. The positioning unit is used to determine the target power domain based on the timestamps corresponding to all power domains and the state information of the comparators corresponding to all power domains. The fault cause determination unit is used to determine the target fault cause based on the characteristic value corresponding to the frequency domain waveform of the electromagnetic interference magnetic field signal in the first time interval corresponding to the timestamp of the first power domain. The repair unit is used to determine the target operation based on the target power domain and the target fault cause.

[0156] In some embodiments, the inverting input of each comparator is connected in parallel to the voltage acquisition point on the corresponding power domain through a filter network; the non-inverting input of each comparator is connected to the voltage threshold. The output of each comparator is connected to the first pin of the field-programmable gate array; the first pin is the input of the interrupt service routine.

[0157] In some embodiments, the comparison unit is further configured to: Real-time acquisition of the average voltage and standard deviation of voltage for each power domain; Based on the smoothed real-time average voltage, real-time voltage standard deviation, upper voltage limit, lower voltage limit, regulation coefficient, and real-time load rate of each power domain, the voltage threshold of each power domain is determined. The voltage thresholds for each power domain are updated based on the real-time average voltage and real-time standard deviation of each power domain, which are collected in real time.

[0158] The positioning unit is specifically used to traverse the topological relationships of each power domain and determine the power domain corresponding to the timestamp that satisfies the first condition, which is the target power domain.

[0159] The positioning unit is specifically used to traverse the topological relationships of each power domain and determine the rules corresponding to any two power domains with topological relationships. Based on the timestamps and propagation delays of the two power domains included in each rule, the target power domain is determined, specifically including: If, in any rule, the timestamp of the upstream power domain is earlier than the timestamp of the downstream power domain, and the difference between the timestamp of the downstream power domain and the timestamp of the upstream power domain is less than the propagation delay, and the state information representation of the comparator corresponding to the upstream power domain is abnormal, then the upstream power domain is determined to be the target power domain.

[0160] The fault cause determination unit is used to determine the characteristic value corresponding to the frequency domain waveform of the electromagnetic interference magnetic field signal based on the spectrum data corresponding to the waveform of the electromagnetic interference magnetic field signal in the first time interval. The cause of the target fault is determined based on the characteristic values ​​corresponding to the frequency domain waveform of the electromagnetic interference magnetic field signal.

[0161] The fault cause determination unit is used to determine the characteristic value corresponding to the signal waveform based on the energy of a preset frequency band in the spectral data of the waveform of the electromagnetic interference magnetic field signal. If the characteristic value is greater than the product of the historical energy baseline and the first coefficient, the cause of the target fault is determined to be capacitor aging. Alternatively, in response to the characteristic value being greater than the product of the historical energy baseline and the second coefficient, the cause of the target fault is determined to be capacitor failure; wherein the second coefficient is greater than the first coefficient; Alternatively, if the harmonic energy in the spectral data is greater than the product of the third coefficient and the switching coefficient, the cause of the target fault is determined to be a distortion of the switching characteristics. Alternatively, if the energy of the ultra-wideband in the spectrum data is greater than the product of the energy of the wideband noise generated by the arc discharge and the fourth coefficient, then the cause of the target fault is determined to be a short circuit. Alternatively, if the peak value of the subharmonic of the switching frequency in the spectral data is greater than the mean value of the subharmonic, then the cause of the target fault is determined to be inductor saturation.

[0162] The repair unit is also used to determine the confidence level of the target power domain based on the timestamp corresponding to the target power domain and the timestamps of all downstream power domains of the target power domain. Based on the characteristic values ​​and baseline values ​​corresponding to the frequency domain waveform of the electromagnetic interference magnetic field signal, the confidence level of the target fault cause is determined. The total confidence level is determined based on the confidence level of the target power domain and the confidence level of the target fault cause.

[0163] The repair unit is specifically used to determine the timestamp of the target power domain and the difference between the timestamps of all downstream power domains. If the difference between each timestamp is less than the first preset threshold, then the confidence level of the target power domain is the first threshold. If the difference between any timestamp and the first preset threshold is less than the second preset threshold, then the confidence level of the target power domain is the second threshold. If the difference between any timestamp and the first preset threshold is greater than or equal to the second preset threshold, or if the timestamp of the upstream power domain is later than the timestamp of the downstream power domain, then the confidence level of the target power domain is the third threshold. Among them, the first threshold is greater than the second threshold, and the second threshold is greater than the third threshold.

[0164] The repair unit is specifically used for one of the following: Reduce the parameters of the cooling system to reduce its power consumption; The output voltage of the power converter can be fine-tuned via the bus interface; The field-programmable gate array transmits the timestamp, the identifier of the target power domain, the cause of the target fault, and the total confidence level to the board management controller, which then reports to the server.

[0165] According to embodiments of this disclosure, this disclosure also provides an electronic device and a readable storage medium.

[0166] Figure 6A schematic block diagram of an example electronic device 800 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0167] like Figure 6 As shown, the electronic device 800 includes a computing unit 801, which can perform various appropriate actions and processes based on a computer program stored in a read-only memory (ROM) 802 or a computer program loaded from a storage unit 808 into a random access memory (RAM) 803. The RAM 803 may also store various programs and data required for the operation of the electronic device 800. The computing unit 801, ROM 802, and RAM 803 are interconnected via a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.

[0168] Multiple components in electronic device 800 are connected to I / O interface 805, including: input unit 806, such as keyboard, mouse, etc.; output unit 807, such as various types of displays, speakers, etc.; storage unit 808, such as disk, optical disk, etc.; and communication unit 809, such as network card, modem, wireless transceiver, etc. Communication unit 809 allows electronic device 800 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0169] The computing unit 801 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 801 performs the various methods and processes described above, such as data processing methods. For example, in some embodiments, the data processing method may be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 808. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 800 via ROM 802 and / or communication unit 809. When the computer program is loaded into RAM 803 and executed by the computing unit 801, one or more steps of the data processing method described above may be performed. Alternatively, in other embodiments, the computing unit 801 may be configured to perform data processing methods by any other suitable means (e.g., by means of firmware).

[0170] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0171] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0172] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0173] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0174] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0175] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.

[0176] It should be understood that the various forms of processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0177] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means two or more, unless otherwise explicitly specified.

[0178] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A data processing method, wherein a comparator is provided in each power domain of an electronic device, the method comprising: In response to the first comparator determining that the voltage of the first power supply domain is less than the voltage threshold of the first power supply domain, a first interrupt signal is output to the field programmable gate array. In response to receiving a first interrupt signal, the field-programmable gate array (FPGA) then responds by determining the timestamp corresponding to the first power domain, the timestamp corresponding to at least one second power domain in the electronic device, the status information of at least one second comparator, and the frequency domain waveform of the electromagnetic interference magnetic field signal in a first time interval including the timestamp corresponding to the first power domain, collected by at least one sampling point. The target power domain is determined based on the timestamps corresponding to all power domains and the state information of the comparators corresponding to all power domains. Based on the characteristic values ​​corresponding to the frequency domain waveform of the electromagnetic interference magnetic field signal in the first time interval corresponding to the timestamp of the first power domain, the cause of the target fault is determined. The target operation is determined based on the target power domain and the target fault cause.

2. The method according to claim 1, The inverting input of each comparator is connected in parallel to the voltage acquisition point on the corresponding power domain through a filter network; the non-inverting input of each comparator is connected to the voltage threshold. The output of each comparator is connected to the first pin of the field-programmable gate array; the first pin is the input of the interrupt service routine.

3. The method according to claim 1, further comprising: Real-time acquisition of the average voltage and standard deviation of voltage for each power domain; Based on the smoothed real-time average voltage, real-time voltage standard deviation, upper voltage limit, lower voltage limit, regulation coefficient, and real-time load rate of each power domain, the voltage threshold of each power domain is determined. The voltage thresholds for each power domain are updated based on the real-time average voltage and real-time standard deviation of each power domain, which are collected in real time.

4. The method according to claim 1, wherein determining the target power domain based on the timestamps corresponding to all power domains and the state information of the comparators corresponding to all power domains includes: Traverse the topology of each power domain and determine the power domain corresponding to the timestamp that satisfies the first condition, which is the target power domain.

5. The method according to claim 4, wherein the power domain corresponding to the timestamp satisfying the first condition includes: Traverse the topological relationships of each power domain and determine the rules corresponding to any two power domains with topological relationships. Based on the timestamps and propagation delays of the two power domains included in each rule, the target power domain is determined, specifically including: If, in any rule, the timestamp of the upstream power domain is earlier than the timestamp of the downstream power domain, and the difference between the timestamp of the downstream power domain and the timestamp of the upstream power domain is less than the propagation delay, and the state information representation of the comparator corresponding to the upstream power domain is abnormal, then the upstream power domain is determined to be the target power domain.

6. The method according to claim 1, wherein determining the cause of the target fault based on the characteristic value corresponding to the frequency domain waveform of the electromagnetic interference magnetic field signal in the first time interval corresponding to the timestamp of the first power domain includes: Based on the spectral data corresponding to the waveform of the electromagnetic interference magnetic field signal in the first time interval, the characteristic values ​​corresponding to the frequency domain waveform of the electromagnetic interference magnetic field signal are determined. The cause of the target fault is determined based on the characteristic values ​​corresponding to the frequency domain waveform of the electromagnetic interference magnetic field signal.

7. The method according to claim 6, wherein determining the cause of the target fault based on the characteristic value corresponding to the frequency domain waveform of the electromagnetic interference magnetic field signal includes: The energy of a preset frequency band in the spectral data of the waveform of an electromagnetic interference magnetic field signal is the characteristic value corresponding to the signal waveform; If the characteristic value is greater than the product of the historical energy baseline and the first coefficient, the cause of the target fault is determined to be capacitor aging. Alternatively, in response to the characteristic value being greater than the product of the historical energy baseline and the second coefficient, the cause of the target fault is determined to be capacitor failure; wherein the second coefficient is greater than the first coefficient; Alternatively, if the harmonic energy in the spectral data is greater than the product of the third coefficient and the switching coefficient, the cause of the target fault is determined to be a distortion of the switching characteristics. Alternatively, if the energy of the ultra-wideband in the spectrum data is greater than the product of the energy of the wideband noise generated by the arc discharge and the fourth coefficient, then the cause of the target fault is determined to be a short circuit. Alternatively, if the peak value of the subharmonic of the switching frequency in the spectral data is greater than the mean value of the subharmonic, then the cause of the target fault is determined to be inductor saturation.

8. The method according to claim 1, further comprising: The confidence level of the target power domain is determined based on the timestamp corresponding to the target power domain and the timestamps of all downstream power domains of the target power domain. Based on the characteristic values ​​and baseline values ​​corresponding to the frequency domain waveform of the electromagnetic interference magnetic field signal, the confidence level of the target fault cause is determined. The total confidence level is determined based on the confidence level of the target power domain and the confidence level of the target fault cause.

9. The method according to claim 8, wherein determining the confidence level of the target power domain based on the timestamp corresponding to the target power domain and the timestamps of all downstream power domains of the target power domain includes: Determine the timestamp of the target power domain and the difference between the timestamps of all downstream power domains; If the difference between each timestamp is less than the first preset threshold, then the confidence level of the target power domain is the first threshold. If the difference between any timestamp and the first preset threshold is less than the second preset threshold, then the confidence level of the target power domain is the second threshold. If the difference between any timestamp and the first preset threshold is greater than or equal to the second preset threshold, or if the timestamp of the upstream power domain is later than the timestamp of the downstream power domain, then the confidence level of the target power domain is the third threshold. Among them, the first threshold is greater than the second threshold, and the second threshold is greater than the third threshold.

10. The method according to claim 1 or 8, wherein determining the target operation based on the target power domain and the target fault cause includes one of the following: Reduce the parameters of the cooling system to reduce its power consumption; The output voltage of the power converter can be fine-tuned via the bus interface; The field-programmable gate array transmits the timestamp, the identifier of the target power domain, the cause of the target fault, and the total confidence level to the board management controller, which then reports to the server.

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