Verification information generation method, verification method and device for register configuration combination

Abstract

The application discloses a register configuration combination verification information generation method, a verification method and a device, and relates to the technical field of chip verification. First, the bit width and the value range of a domain segment are obtained by analyzing a register description file, and then the value range is divided according to the bit width, and verification points are automatically obtained, so that the generation efficiency and consistency of the verification points are improved. Secondly, the value range of a random variable corresponding to the domain segment is determined according to one or more verification points, and the diversity of the test configuration is increased. Thirdly, each verification point is mapped into a corresponding coverage bin of a coverage point, so that each coverage bin corresponds to a corresponding verification point, and whether the corresponding verification point is covered can be determined according to the hit condition of the coverage bin in the subsequent process. Finally, the test constraint condition and the coverage rate model are both generated according to the same set of verification points, so that the generation efficiency, completeness and accuracy of the verification information are improved. When the register configuration combination verification is performed, the efficiency, completeness and accuracy of the register configuration combination verification are ensured.

Description

Technical Field

[0001] This invention relates to the field of chip verification technology, and in particular to a method, verification method and apparatus for generating verification information based on register configuration combinations. Background Technology

[0002] In the design of complex System-on-Chips (SoCs), the operating modes, performance parameters, and interactive behaviors of hardware functional modules are typically controlled by a large number of software-programmable configuration registers. Verifying all hardware behavior scenarios triggered by these register configuration combinations is crucial to ensuring the correctness of chip functionality. Currently, verification of register configuration combinations usually requires engineers to extract verification points based on experience and write test constraints and coverage models (used to measure the completeness of verification). In this method, verification points, test constraints, and coverage models are developed completely independently, which can easily lead to a lack of correlation between verification points and test constraints, resulting in some verification scenarios not being covered, or the actual test content deviating from the preset verification target; and a mismatch between verification points and coverage models, causing coverage metrics to fail to accurately reflect verification progress. Moreover, it is susceptible to human factors, leading to reduced verification efficiency and accuracy.

[0003] Therefore, how to efficiently, comprehensively, and accurately verify register configuration combinations is a technical problem that urgently needs to be solved by those in this field. Summary of the Invention

[0004] The purpose of this invention is to provide a method, verification method, and apparatus for generating verification information based on register configuration combinations, in order to solve the problems of low efficiency, incompleteness, and low accuracy in manually developing verification points, test constraints, and coverage models.

[0005] In a first aspect, to solve the above-mentioned technical problems, the present invention provides a method for generating verification information of register configuration combinations, comprising: Obtain the register description file and parse the register description file to obtain the register field information; wherein the field information includes at least the bit width and value range; The value range is divided according to the bit width in the domain segment information to obtain one or more verification points corresponding to the domain segment; Obtain the random variable corresponding to the domain segment, and determine the value range of the random variable based on the one or more verification points to generate test constraints; Obtain the coverage points corresponding to the domain segment, map the one or more verification points to the coverage bins corresponding to the coverage points, and generate a coverage model based on the coverage points and the coverage bins; The test constraints and the coverage model are used as the verification information corresponding to the register configuration combination.

[0006] On the other hand, the value range is divided according to the bit width in the segment information to obtain one or more verification points corresponding to the segment, including: If the bit width in the field segment information is detected to be less than or equal to the preset bit width, the values ​​within the value range corresponding to the field segment are traversed. Each value obtained through traversal is determined as a verification point corresponding to the domain segment.

[0007] On the other hand, it also includes: If the bit width in the domain segment information is detected to be greater than the preset bit width, a boundary value is determined from the value range corresponding to the domain segment, and the boundary value is determined as the verification point corresponding to the domain segment; Remove the boundary values ​​from the value range to obtain the non-boundary value range; The non-boundary value range is divided into multiple equivalent intervals, and each of the equivalent intervals is determined as the verification point corresponding to the domain segment.

[0008] On the other hand, the non-boundary value range is divided into multiple equivalent intervals, including: The number of values ​​in each interval is determined based on the preset number of intervals and the number of values ​​within the non-boundary value range; wherein, if the number of values ​​cannot be evenly distributed according to the preset number of intervals, the remaining values ​​are allocated to some intervals. Based on the number of values ​​in each interval, the values ​​within the non-boundary value range are divided to obtain multiple equivalent intervals.

[0009] On the other hand, after obtaining one or more verification points corresponding to the domain segment, and before obtaining the random variable corresponding to the domain segment, the method further includes: When the bit width in the domain segment information is less than or equal to the preset bit width, each value in the value range is written into the verification point description string in the order of the values ​​in the value range to obtain the verification point description string corresponding to the domain segment. If the bit width in the domain segment information is greater than the preset bit width, obtain the boundary value and equivalent interval corresponding to the domain segment; according to the preset description rules, write the boundary value into the boundary value field, write the start value and end value of the equivalent interval into the interval field, and obtain the verification point description string corresponding to the domain segment based on the boundary value field and the interval field.

[0010] On the other hand, after obtaining the verification point description string corresponding to the domain segment, the method further includes: Determine if there is a field segment without a verification point description string; If so, return to the step of determining whether the bit width in the field segment information is less than or equal to the preset bit width; If not, the verification point description strings of multiple domain segments will be summarized and sorted according to preset rules, and the summarized description information will be written into the verification point description file.

[0011] On the other hand, obtaining the random variable corresponding to the domain segment includes: A random variable with random attributes is generated based on the bit width in the field segment information; wherein the storage bits of the random variable are the same as the bit width of the field segment.

[0012] On the other hand, determining the range of values ​​for the random variable based on the one or more verification points to generate test constraints includes: When the bit width in the domain segment information is less than or equal to the preset bit width, each value is converted into an independent weighted value item; the same weight is set for each weighted value item, and the test constraint is generated based on the weighted value item; If the bit width in the domain segment information is greater than the preset bit width, the boundary value is converted into an independent weighted value item, and the equivalent interval is converted into a weighted range item; the same weight is set for the weighted value item and the weighted range item, and the test constraint is generated based on the weighted value item and the weighted range item.

[0013] On the other hand, after generating test constraints, the following is also included: Obtain the test constraints corresponding to different domain segments; The test constraints corresponding to different domain segments are encapsulated into a unified constraint class.

[0014] On the other hand, mapping the one or more verification points to the coverage bins corresponding to the coverage points includes: When the bit width in the domain segment information is less than or equal to the preset bit width, a corresponding independent overlay bin is created for each value within the value range, and each independent overlay bin is associated with the overlay point; If the bit width in the domain segment information is greater than the preset bit width, a corresponding independent coverage bin is created for the boundary value, and a corresponding range coverage bin is created for the equivalent interval. The independent coverage bin and the range coverage bin are then associated with the coverage point.

[0015] On the other hand, after mapping the one or more verification points to coverage bins corresponding to the coverage points, and before generating a coverage model based on the coverage points and the coverage bins, the method further includes: Generate readable tags for the covered compartment; Add annotation information to the coverage point or the coverage group to which the coverage point belongs; wherein, the annotation information includes at least the source register, the domain segment information, and the verification point description information corresponding to the coverage repository.

[0016] Secondly, in order to solve the above-mentioned technical problems, the present invention also provides a method for verifying register configuration combinations, comprising: Obtain the test cases and the test constraints and coverage models corresponding to the register configuration combinations; wherein the test constraints and coverage models are obtained through the above-mentioned method for generating verification information of register configuration combinations; During the execution of the test cases, the random variables corresponding to the domain segments of the target register are randomized based on the test constraints to obtain the register configuration values; The register configuration value is written to the register configuration port of the hardware module to which the target register belongs, so as to drive the hardware module to run in the configuration scenario corresponding to the register configuration value; The actual value of the target register is obtained during the operation of the hardware module, and the actual value is sampled through the coverage points in the coverage model; Determine the coverage area where the actual value is hit, and based on the hit status of the coverage area, determine the coverage status of the verification point corresponding to the coverage area.

[0017] On the other hand, it also includes: The test cases are executed repeatedly, and the random variables are re-randomized during each execution of the test cases; The register configuration value obtained through randomization is written to the register configuration port, and the actual value of the target register is sampled through the coverage point; If the number of times the test case is executed reaches the threshold, the hit rate of each coverage repository is statistically analyzed, and a coverage report is generated based on the statistical results.

[0018] Thirdly, the present invention also provides a verification apparatus for register configuration combinations, comprising: Memory, used to store computer programs; A processor, configured to implement the steps of the method for generating verification information of the above-described register configuration combination when executing the computer program, or to implement the steps of the method for verifying the above-described register configuration combination.

[0019] Fourthly, the present invention also provides a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, it implements the steps of the above-described method for generating verification information of register configuration combinations, or the steps of the above-described method for verifying register configuration combinations.

[0020] The beneficial effects of this invention are as follows: First, by parsing the register description file to obtain the bit width and value range of the domain segment, and then dividing the value range according to the bit width to automatically obtain the verification point, the process of manually extracting verification points based on engineer experience is reduced, which is conducive to improving the efficiency and consistency of verification point generation. Second, by obtaining the random variable corresponding to the domain segment and determining the value range of the random variable according to one or more verification points, the random variable can generate different register configuration values ​​within the range defined by the verification point, increasing the diversity of test configurations, increasing the possibility of testing configuration scenarios corresponding to different verification points, and reducing the omission of verification scenarios caused by the independent writing of verification points and test constraints, as well as the problem of actual test content deviating from the preset verification target. Third, each verification point is mapped to a coverage module corresponding to the coverage point, so that each coverage module in the coverage model establishes a corresponding relationship with the corresponding verification point. Therefore, in subsequent verification processes, the hit status of the coverage bins can be used to determine whether the corresponding verification points are covered, reducing the mismatch between the coverage model and the verification points, and enabling the coverage metric to more accurately reflect the degree of completion of the preset verification objectives. Finally, both the test constraints and the coverage model are generated based on the same set of verification points, reducing inconsistencies and human errors caused by separate manual development, and improving the efficiency, completeness, and accuracy of verification information generation. When register configuration combination verification is performed based on this verification information, the efficiency, completeness, and accuracy of register configuration combination verification are guaranteed.

[0021] Furthermore, by traversing all values ​​within the range of the domain segment when the bit width is less than or equal to the preset bit width, and determining each value as a verification point, full value coverage of the small bit width domain segment is achieved. At the same time, since the verification points are automatically generated by traversing the value range, there is no need for engineers to manually extract them item by item, which can improve the generation efficiency and consistency of verification points, and provide an accurate data foundation for the subsequent generation of test constraint items and coverage bins value by value.

[0022] By extracting boundary values ​​as verification points when the domain segment width exceeds a preset width, and dividing the non-boundary value range after removing boundary values ​​into multiple equivalent intervals as verification points, this approach can address both boundary and non-boundary scenarios without traversing all values ​​within a large value range. This avoids a sharp increase in the number of verification points due to an excessive number of values ​​in a large-width domain segment, reducing verification resource consumption, improving verification efficiency, and maintaining comprehensive coverage of different configuration scenarios within the complete value range.

[0023] In one possible implementation, by sequentially writing the values ​​of the smaller bit-width segment into the verification point description string according to the value range order, the verification point description string corresponding to the smaller bit-width segment is obtained. By writing the boundary values ​​of the larger bit-width segment into the boundary value field according to a preset description rule, and writing the start and end values ​​of the equivalent interval into the interval field, single-value verification points and range verification points can be accurately represented in a structured manner. This allows internally generated verification points to be converted into description information with a unified format that is easy for machines to read and for manual inspection, reducing parsing errors caused by inconsistent description formats or unclear interval boundaries. Simultaneously, test constraints and coverage models can be generated based on the same verification point description string, which enhances the traceability between verification points and subsequent verification information and improves the reproducibility and maintainability of the verification information generation process.

[0024] In one possible implementation, by converting each value into an independent weighted value item and assigning the same weight within a small bit-width range, the configuration scenario corresponding to each single-value verification point has an equal chance of being selected, reducing the likelihood that some discrete values ​​will remain untested for a long time due to uneven random distribution. In a large bit-width range, by converting boundary values ​​into independent weighted value items and equivalent intervals into weighted range items, and assigning the same weight to each value item and range item, boundary scenarios and different interval scenarios can be selected with a more balanced probability. This avoids intervals with a large number of values ​​occupying too high a proportion during the random process, making it difficult to hit boundary values ​​or other intervals, thus increasing the probability that scenarios corresponding to different verification points will be tested, and thereby improving the efficiency of random verification.

[0025] In one possible implementation, by obtaining the test constraints corresponding to different domain segments and encapsulating these test constraints into a unified constraint class, the random variables and their value rules of multiple domain segments in the combination can be configured using the same constraint object management register. This is beneficial for the constraint class to be reused in different test cases or verification components, thereby improving the modularity, reusability, and maintenance efficiency of test constraints.

[0026] In one possible implementation, by creating independent coverage bins for each value within the range in a small-width segment, the accuracy of determining whether a value has been validated can be determined based on the hit status of the specific coverage bins. By creating independent coverage bins for boundary values ​​and range coverage bins for equivalent intervals in a large-width segment, the partitioning structure of the coverage bins is consistent with the validation point structure formed by the boundary values ​​and equivalent intervals. This ensures that each validation point can be mapped to the corresponding coverage bin, reducing issues such as missing or multiple coverage bins or inconsistent range boundaries, and enabling the coverage statistics to more accurately represent the actual completion status of each validation point.

[0027] In one possible implementation, by generating readable tags for coverage pods, coverage reports can directly display the boundary values, individual values, or equivalent ranges represented by the coverage pods, facilitating engineers' rapid identification of the specific configuration scenarios corresponding to missed coverage pods. By adding annotations to coverage points or coverage groups, including at least the source register, domain information, and verification point description, a clear association can be established between coverage pods and register specifications, target domains, and verification points. Therefore, when coverage gaps or verification anomalies occur, the corresponding registers and verification points can be quickly traced back based on the coverage pod tags and annotations, improving the readability of coverage reports, the efficiency of problem localization, and the traceability of the verification process.

[0028] In addition, the present invention also provides a method for verifying register configuration combinations, a device for verifying register configuration combinations, and a computer-readable storage medium, which have the same or corresponding technical features as the aforementioned method for generating verification information of register configuration combinations, and have the same effects. Attached Figure Description

[0029] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 A schematic diagram of a basic hardware interaction architecture for simulation verification provided in an embodiment of the present invention; Figure 2 A flowchart illustrating a method for generating verification information for register configuration combinations provided in an embodiment of the present invention; Figure 3 A flowchart of a verification point extraction method provided in an embodiment of the present invention; Figure 4 A flowchart illustrating a method for generating test constraints based on verification points, provided in an embodiment of the present invention; Figure 5 A flowchart illustrating an automatic method for creating a coverage model based on verification points, provided in an embodiment of the present invention; Figure 6 This is an overall flowchart of a method for automatically generating register random test constraints and coverage models based on verification points, provided by an embodiment of the present invention. Figure 7 A flowchart illustrating a method for verifying register configuration combinations provided in an embodiment of the present invention; Figure 8 This is a structural diagram of a verification device for register configuration combinations provided in an embodiment of the present invention. Detailed Implementation

[0031] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0032] The core of this invention is to provide a method, verification method, and apparatus for generating verification information based on register configuration combinations, in order to solve the problems of low efficiency, incompleteness, and low accuracy that exist in manually developing verification points, test constraints, and coverage models.

[0033] Currently, verifying register configuration combinations typically requires engineers to manually interpret design specifications, identify valid values ​​and combinations of register configuration fields, manually extract verification points, and develop test cases based on targeted or random testing methods. Finally, the verification completion is evaluated using a functional coverage model. Verification points represent "what to verify," test constraints represent "how to verify," and the coverage model represents "how well the verification was done." Currently, verification points, test constraints, and the coverage model (also known as the functional coverage model) are developed completely independently, which presents the following problems: 1. There is a problem of synchronization and consistency among the three: the lack of automated link between verification points and test cases can easily lead to incomplete coverage or inaccurate implementation; the coverage model may not match the actual verification points, causing the coverage metric to fail to accurately reflect the verification progress.

[0034] Definition and implementation are disconnected: Manually defined "verification points" (requirements) and manually written "test cases" (implementations) are conducted independently, without any mandatory or automated link between them. This easily leads to test cases failing to fully cover the preset verification points, or vague definitions of verification points resulting in inaccurate test implementations.

[0035] Inaccurate Coverage Metrics: The coverage model, as a metric, is also independently and manually written. It may not match the actual "verification points" that need to be verified (missing or multiple definitions), or it may be inconsistent with the scope covered by the implemented "test cases." This causes the coverage metric to fail to accurately reflect the completion of the preset verification goals, generating false signals such as "high coverage but no defects found" or "scenario verified but low coverage," rendering the coverage metric meaningless.

[0036] 2. Low work efficiency and high labor costs: For the decomposition and verification of the legal values ​​of each register, verification engineers need to manually extract verification points, write test cases and coverage models, which leads to repetitive work, low efficiency and waste of resources.

[0037] 3. Validation quality depends on personal experience, and consistency and completeness are difficult to guarantee: The extraction of validation points, the construction of test constraints and the definition of coverage models are highly dependent on engineers' experience, which can easily lead to inconsistent validation scope, omission of key scenarios or overvalidation.

[0038] It is evident that manually developing verification points, test constraints, and coverage models suffers from low efficiency, incompleteness, and low accuracy.

[0039] To address the inefficiencies, poor consistency, and maintenance difficulties caused by the disconnect between verification points, test cases, and coverage models in the aforementioned related technologies, this invention proposes a systematic and automated solution. Specifically, by parsing register description files, formalized verification points (VPs) are automatically extracted as the unique trusted source; and based on these verification points, strictly corresponding randomized test constraints and coverage models are automatically and synchronously generated.

[0040] Figure 1 This is a schematic diagram of a basic hardware interaction architecture for simulation verification provided in an embodiment of the present invention. Figure 1 As shown, the system includes a verification platform 1 and a unit under test 2 (hardware under test). Verification platform 1 stores verification information (including test constraints and coverage models). Unit under test 2 integrates multiple registers. Verification platform 1 generates register configuration values ​​based on the verification information and distributes them to each register. Simultaneously, it collects the actual values ​​taken by the registers to complete coverage statistics, thus achieving automated verification of register configuration combinations.

[0041] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Figure 2 A flowchart of a method for generating verification information for register configuration combinations provided in an embodiment of the present invention is shown below. Figure 2 As shown, the method includes: S10: Obtain the register description file and parse it to obtain the register field information; the field information includes at least the bit width and value range. S11: Divide the value range according to the bit width in the domain segment information to obtain one or more verification points corresponding to the domain segment; S12: Obtain the random variable corresponding to the domain segment, and determine the range of values ​​of the random variable based on one or more verification points to generate test constraints; S13: Obtain the coverage points corresponding to the domain segment, map one or more verification points to the coverage bins corresponding to the coverage points, and generate a coverage model based on the coverage points and coverage bins; S14: Use the test constraints and coverage model as the verification information corresponding to the register configuration combination.

[0042] The register description file records the register name, address, attributes (such as read-only, read-write, etc.), and information about different fields. The field information includes at least the bit width and value range.

[0043] After obtaining the domain segment information, the value range is divided according to the bit width in the domain segment information to obtain one or more verification points corresponding to the domain segment. The verification point is a structured and formal description of the register configuration item at the verification level, which includes value range classification and semantic labels.

[0044] In implementation, the value range is divided according to the bit width in the domain segment information, resulting in one or more verification points corresponding to the domain segment, including: If the bit width in the field segment information is less than or equal to the preset bit width, iterate through each value in the value range corresponding to the field segment. Each value obtained through the traversal is determined as a verification point corresponding to the domain segment.

[0045] There is no limit to the preset bit width, such as a preset bit width of 4 bits.

[0046] In this method, when the bit width of a domain segment is less than or equal to a preset bit width, each value within the range of the domain segment's value range is traversed, and each value is determined as a verification point, thereby achieving full value coverage of the small bit width domain segment. At the same time, since the verification points are automatically generated by traversing the value range, there is no need for engineers to manually extract them item by item, which can improve the generation efficiency and consistency of verification points, and provide an accurate data foundation for the subsequent generation of test constraint items and coverage bins value by value.

[0047] In addition, if the bit width in the detected field segment information is greater than the preset bit width, the boundary value is determined from the value range corresponding to the field segment, and the boundary value is determined as the verification point corresponding to the field segment; Remove boundary values ​​from the range of values ​​to obtain the range of non-boundary values; The non-boundary value range is divided into multiple equivalent intervals, and each equivalent interval is determined as the verification point corresponding to the domain segment.

[0048] By extracting boundary values ​​as verification points when the domain segment width exceeds a preset width, and dividing the non-boundary value range after removing boundary values ​​into multiple equivalent intervals as verification points, this approach can address both boundary and non-boundary scenarios without traversing all values ​​within a large value range. This avoids a sharp increase in the number of verification points due to an excessive number of values ​​in a large-width domain segment, reducing verification resource consumption, improving verification efficiency, and maintaining comprehensive coverage of different configuration scenarios within the complete value range.

[0049] Specifically, the range of non-boundary values ​​is divided into multiple equivalent intervals, including: The number of values ​​in each interval is determined based on the preset number of intervals and the number of values ​​in the non-boundary value range; where the number of values ​​cannot be evenly distributed according to the preset number of intervals, the remaining values ​​are allocated to some intervals. Based on the number of values ​​in each interval, the values ​​outside the boundary value range are divided to obtain multiple equivalent intervals.

[0050] In this method, the number of values ​​in each interval is determined based on the number of preset intervals and the number of values ​​in the range of non-boundary values. When the values ​​cannot be evenly distributed, the remaining values ​​are allocated to some intervals so that the number of values ​​contained in multiple equivalent intervals is as balanced as possible.

[0051] In some embodiments, after obtaining one or more verification points corresponding to a domain segment and before obtaining the random variable corresponding to the domain segment, the method further includes: If the bit width in the domain segment information is less than or equal to the preset bit width, the values ​​in the value range are written into the verification point description string in sequence according to the value order in the value range to obtain the verification point description string corresponding to the domain segment. If the bit width in the domain segment information is greater than the preset bit width, obtain the boundary value and equivalent interval corresponding to the domain segment; according to the preset description rules, write the boundary value into the boundary value field, write the start value and end value of the equivalent interval into the interval field, and obtain the verification point description string corresponding to the domain segment based on the boundary value field and the interval field.

[0052] The preset description rules are not limited and are determined according to the actual situation. In this method, by writing the values ​​of the smaller bit-width segment into the verification point description string in the order of value range, the verification point description string corresponding to the smaller bit-width segment is obtained. By writing the boundary values ​​of the larger bit-width segment into the boundary value field according to the preset description rules, and writing the start and end values ​​of the equivalent interval into the interval field, single-value verification points and range verification points can be accurately represented in a structured manner. Thus, the internally generated verification points can be converted into description information with a unified format that is easy for machines to read and for manual inspection, reducing parsing errors caused by inconsistent description formats or unclear interval boundaries. At the same time, test constraints and coverage models can be generated based on the same verification point description string, which helps to enhance the traceability between verification points and subsequent verification information, and improves the reproducibility and maintainability of the verification information generation process.

[0053] To form a complete verification point data source, in some embodiments, after obtaining the verification point description string corresponding to the domain segment, the following is also included: Determine if there is a field segment without a verification point description string; If so, return to the step of determining whether the bit width in the field segment information is less than or equal to the preset bit width; If not, the verification point description strings of multiple domain segments will be summarized and sorted according to preset rules, and the summarized description information will be written into the verification point description file.

[0054] This method ensures that all target segments in the register description file are processed by determining whether there are any segments for which verification point description strings have not yet been generated, and returns the corresponding bit width determination and verification point generation steps when such segments exist. This reduces the risk of segment omissions caused by incomplete loop processing. After all segments have been processed, the verification point description strings of multiple segments are summarized and sorted according to preset rules and written into the verification point description file, forming a complete and stable verification point data source.

[0055] The automated extraction process of verification points has been described above. To enable those skilled in the art to better understand the above process, specific embodiments are described below.

[0056] The automatic verification point extraction process of this invention is universal and applicable to various types of registers. To clearly illustrate the method, this embodiment uses a read-write register (register access attribute of read-write (RW)) as the main example. This is because in typical hardware module designs, read-write registers not only account for the largest proportion but are also the key part that directly controls the module's operating mode, configuration parameters, and functional scenarios, making their verification point extraction representative. For other types of registers such as read-only and write-only, their verification point extraction follows the same core rules and automated process, requiring only adaptation processing based on their specific access attributes and functional semantics.

[0057] Figure 3 A flowchart of a verification point extraction method provided in an embodiment of the present invention is shown below. Figure 3 As shown, the method includes: S15: Register description file parsing; S16: Extract the field segments of all readable and writable registers; S17: Initialization, set the list of verification point descriptions to empty; S18: Traverse the register field list; S19: Obtain information about the current segment, including bit width, value range, etc. S20: Determine if the current field segment width is greater than 4; if not, proceed to step S21; if yes, proceed to step S22. S21: Generate a list of all possible values; S22: Extract boundary values: maximum and minimum values; S23: Determine the range of non-boundary values: from minimum value +1 to maximum value -1; S24: Divide the range of non-boundary values ​​into 4 equivalence class intervals; S25: Construct the overlay description string; S26: Determine if there are any unprocessed segments; if yes, return to step S19; if no, proceed to step S27. S27: Summarize and sort the verification point description strings of all domain segments according to the rules; S28: Write the summarized description into the verification point description file.

[0058] Specifically, the system first reads and parses the register description file to extract basic information about all register fields. Then, it selects fields with an access type of "Read-Write (RW)" as the objects for verification point extraction. The entire process can be divided into two main stages: verification point extraction and verification point description generation. These are explained below.

[0059] 1) Validation point extraction: Validation point extraction employs a differentiated strategy based on the different domain segment widths. a. Small bit-width segment strategy (e.g., bit width ≤ 4): Since the value range is limited (no more than 16 possible values), a full coverage strategy is adopted, that is, all possible values ​​of the range (from 0 to 2^bit width - 1) are extracted as verification points. This method is based on the idea of ​​exhaustive testing to ensure complete coverage of the small value range configuration.

[0060] b. Large bit-width segment strategy (e.g., bit width > 4): When the field width exceeds 4 bits, the value range space grows exponentially (e.g., 8 bits have 256 values, 16 bits have 65536 values). To balance verification efficiency and coverage, a hybrid strategy combining boundary value detection and equivalence class partitioning is adopted. The specific implementation steps are as follows: Step 1: Boundary value extraction: Extract two key boundary values ​​for the range of this segment: minimum value: 0; maximum value: 2^bit width - 1; Step 2: Determine the range of non-boundary values: Excluding the extracted boundary values ​​(0 and the maximum value) from the complete value range, we get the non-boundary value range: [1, maximum value - 1]. For example, for a 5-bit range (value range 0-31), the non-boundary value range is [1, 30].

[0061] Step 3: Equivalence class partitioning: The system divides the non-boundary value range [1, maximum value - 1] into 4 equivalence classes, each represented by a continuous interval: Partitioning principle: Use a uniform partitioning algorithm to ensure that each interval contains as many values ​​as possible; Partitioning algorithm: Calculate the total number of non-boundary values: N = (maximum value - 1) - 1 + 1 = maximum value - 1; Divide N into 4 parts as evenly as possible; If N is not divisible by 4, the first few intervals can contain one more value.

[0062] Interval representation: Each equivalence class is represented as a closed interval [start, end], which contains all integer values ​​from start to end.

[0063] The following is an example: Taking a 5-bit field as an example: Bit width: 5 bits; Value range: 0-31 (32 values ​​in total); Boundary values: 0, 31; Non-boundary value range: [1, 30] (30 values ​​in total); Equivalence class partitioning (evenly divided into 4 segments): First segment: [1,8] (8 values); Second segment: [9,16] (8 values); Third segment: [17,24] (8 values); Fourth segment: [25,30] (6 values).

[0064] Coverage integrity description: Boundary values ​​(2) and equivalence class range (covering 30 values) together cover all 32 possible values.

[0065] 2) Verification point description generation process: The system generates a standardized verification point description string for each domain segment, in the following format: Cover: Boundary value 1, Boundary value 2, ..., [range 1], [range 2], [range 3], [range 4].

[0066] Among them, boundary values ​​are represented by specific numerical values, such as 0, 255, 65535, etc. Equivalence class ranges are represented in the format [starting value: ending value], such as [1:8], [9:16], etc.; Example description: 5-bit field: cover: 0, 31, [1:8], [9:16], [17:24], [25:30]; 8-bit field: cover: 0, 255, [1:64], [65:127], [128:191], [192:254].

[0067] 16-bit field: cover: 0, 65535, [1:16383], [16384:32767], [32768:49151], [49152:65534].

[0068] This method enables the automated extraction of validation points. After the validation points are extracted, test constraints and a coverage model are generated based on them. The following section first explains the generation of test constraints based on validation points.

[0069] In some embodiments, obtaining the random variable corresponding to the domain segment includes: Based on the bit width in the field segment information, a random variable with random properties is generated; wherein the storage bits of the random variable are the same as the bit width of the field segment.

[0070] If the bit width of a field is 16 bits, then the storage bits for a random variable are also 16 bits.

[0071] Determining the range of values ​​for a random variable based on one or more validation points to generate test constraints includes: When the bit width in the domain segment information is less than or equal to the preset bit width, each value is converted into an independent weighted value item; the same weight is set for each weighted value item, and test constraints are generated based on the weighted value items; If the bit width in the domain segment information is greater than the preset bit width, the boundary values ​​are converted into independent weighted value items, and the equivalent intervals are converted into weighted range items. The same weight is set for the weighted value items and the weighted range items, and test constraints are generated based on the weighted value items and the weighted range items.

[0072] This method converts each value into an independent weighted value item within a small bit-width range and assigns them the same weight. This ensures that the configuration scenarios corresponding to each single-value verification point have an equal chance of being selected, reducing the likelihood that some discrete values ​​will remain untested due to uneven random distribution. Within a large bit-width range, boundary values ​​are converted into independent weighted value items, and equivalent intervals are converted into weighted range items. Assigning the same weight to each value item and range item ensures that boundary scenarios and different interval scenarios are selected with a more balanced probability. This avoids intervals with a large number of values ​​occupying an excessively high proportion during the random process, making it difficult to hit boundary values ​​or other intervals. This increases the probability that scenarios corresponding to different verification points will be tested, thereby improving the efficiency of random verification.

[0073] After generating test constraints, the following is also included: Obtain the test constraints corresponding to different domain segments; The test constraints corresponding to different domain segments are encapsulated into a unified constraint class.

[0074] In this method, by obtaining the test constraints corresponding to different domain segments and encapsulating these test constraints into a unified constraint class, the random variables and their value rules of multiple domain segments in the combination can be configured using the same constraint object to manage the register. This is beneficial for the repeated use of the constraint class in different test cases or verification components, thereby improving the modularity, reusability, and maintenance efficiency of the test constraints.

[0075] This process describes the establishment of test constraints based on verification points. To enable those skilled in the art to better understand the above process, the following description will continue with specific embodiments.

[0076] The process of automatically generating random test constraints based on verification points includes: After the automated extraction of verification points is completed, the automatic generation stage of random test constraints begins. The goal of this stage is to automatically convert the formalized verification points into register configuration constraint codes that conform to the randomized constraint verification specification and can be directly used in simulation, ensuring that the generated randomized test stimuli can efficiently and comprehensively cover all preset verification scenarios.

[0077] Figure 4 A flowchart illustrating a method for generating test constraints based on verification points, as provided in an embodiment of the present invention, is shown below. Figure 4 As shown, the method includes: S29: Declaration of constraint variables; S30: Constraint transformation and generation of the range; S31: Constraint class encapsulates the output of the domain.

[0078] Specifically, regarding the constraint variable declaration in step S29: The system iterates through the list of verification point descriptions and automatically declares a variable with a random attribute (rand) for each register field segment whose access attributes are readable and writable. The number of bits stored in the variable strictly corresponds to the bit width of the field segment. For example, for a 16-bit wide baud rate divider field segment, it will be declared as rand bit [15:0] baud_rate_div.

[0079] For the constraint transformation and generation of the value range in step S30: The register domain segmentation information (boundary values, equivalence class ranges) defined in the verification points is translated into SystemVerilog weighted distribution constraints (dist). The system assigns equal weights (usually 1) to each item to ensure that values ​​of all types are sampled uniformly during randomization, avoiding coverage bias caused by uneven weighting.

[0080] The constraint generation rules are as follows: Boundary value handling: Each boundary value is treated as an independent weighted term. For example, boundary values ​​0 and 65535 are represented as 0: / 1 and 65535: / 1, respectively. Taking 0: / 1 as an example, it means that the weight of 0 is set to 1.

[0081] Equivalence class range processing: Each continuous interval divided by the verification point is treated as a weighted range term. For example, the range [1:16383] is represented as [1:16383]: / 1.

[0082] Small bit-width full coverage processing: For a field with a bit width ≤ 4, its verification point includes all possible values. The constraint will directly list all values, with each value as an independent item and a weight of 1.

[0083] For the constraint class encapsulation domain output in step S31: All constraints generated for different domain segments are systematically organized and encapsulated in a unified SystemVerilog constraint class. This constraint class maintains good modularity and reusability, can be directly instantiated, and integrated into Universal Verification Methodology (UVM) test sequences or other test components to drive the configuration port of the Design Under Test (DUT), thereby automatically generating random stimuli that meet the requirements of the verification scenario.

[0084] The output of this stage is a ready-to-use System Verilog constraint class file that can be directly embedded into existing UVM verification environments or test platforms to drive the generation of random test sequences.

[0085] Test constraints were generated based on the validation points, establishing a relationship between the validation points and the test constraints. The process of generating a coverage test model based on validation points is described in more detail below.

[0086] In some embodiments, mapping one or more verification points to coverage bins corresponding to coverage points includes: If the bit width in the domain segment information is less than or equal to the preset bit width, create a corresponding independent overlay bin for each value within the value range, and associate each independent overlay bin with the overlay point; If the bit width in the domain segment information is greater than the preset bit width, create a corresponding independent cover bin for the boundary value and a corresponding range cover bin for the equivalent interval, and associate the independent cover bin and the range cover bin with the cover point.

[0087] This method creates independent coverage bins for each value within the range of values ​​in a small-width segment, allowing for accurate determination of whether a value has been validated based on the hit status of the specific coverage bins. By creating independent coverage bins for boundary values ​​and range coverage bins for equivalent intervals in a large-width segment, the structure of the coverage bins is consistent with the validation point structure formed by the boundary values ​​and equivalent intervals. This ensures that each validation point can be mapped to a corresponding coverage bin, reducing issues such as missing or multiple coverage bins or inconsistent range boundaries. This allows the coverage statistics to more accurately represent the actual completion status of each validation point.

[0088] In addition, after mapping one or more validation points to coverage bins corresponding to coverage points, and before generating the coverage model based on the coverage points and coverage bins, the following steps are also included: Generate readable tags for the overlay repository; Add annotation information to the coverage point or the coverage group to which the coverage point belongs; the annotation information shall include at least the source register, the domain segment information and the verification point description information corresponding to the coverage repository.

[0089] The information includes field segment information such as bit width and reset value.

[0090] This method generates readable tags for coverage modules, enabling coverage reports to directly display the boundary values, individual values, or equivalent ranges represented by the coverage modules. This facilitates engineers' rapid identification of the specific configuration scenarios corresponding to missed coverage modules. By adding annotations to coverage points or coverage groups, including at least the source register, domain information, and verification point description, a clear association can be established between coverage modules and register specifications, target domains, and verification points. Therefore, when coverage gaps or verification anomalies occur, the corresponding registers and verification points can be quickly traced back based on the coverage module tags and annotations, improving the readability of coverage reports, the efficiency of problem localization, and the traceability of the verification process.

[0091] The process of generating a coverage model based on validation points has been described above. To enable those skilled in the art to better understand this process, the following section will further illustrate the process of automatically creating a coverage model based on validation points with specific embodiments.

[0092] Coverage model is a core metric for measuring validation completeness. This phase automatically creates a coverage model that is fully synchronized with validation points and random constraints, ensuring that the coverage collection accurately and unambiguously reflects the achievement of the preset validation objectives. Figure 5 A flowchart of an automatic method for creating a coverage model based on verification points provided in an embodiment of the present invention is shown below. Figure 5 As shown, the method includes: S32: Creation of coverage points for coverage groups; S33: Automatic mapping of cover compartments; S34: Tag field annotation generation; S35: Coverage model encapsulation.

[0093] The specific implementation steps are as follows: For step S32, coverage group domain coverage points are created: The system automatically instantiates a covergroup for each register field segment containing a verification point. Each covergroup contains a coverpoint, which directly corresponds to the verification point of that field segment.

[0094] For step S33, the bins are automatically mapped: Map each value class in the verification point (including each boundary value and each equivalence class range) to a bin under the coverpoint.

[0095] Boundary values: Each boundary value creates a separate bin and automatically generates labels with clear semantics (such as baud_rate_div_boundary_0).

[0096] Equivalence class range: Create a range bin for each consecutive interval (e.g., binsrange_1={[1:16383]}).

[0097] Small-bit wide-domain segment: Each possible value is assigned to an independent bin, achieving precise coverage.

[0098] For step S34, tag field annotations are generated: Each bin is automatically generated with readable labels, and annotations can be added at the covergroup or coverpoint level, indicating the source register, bit width, reset value, and corresponding VP description, greatly enhancing the readability and traceability of coverage reports.

[0099] For step S35, the coverage model is encapsulated as follows: The generated coverage model is encapsulated in a separate SystemVerilog file, which can be directly instantiated and integrated into the verification environment. Coverage sampling is typically triggered in the monitor to ensure that data is collected after each register configuration transaction.

[0100] The output of this stage is the complete coverage model code. Data is collected in real time during the simulation process, and a coverage report is finally generated to accurately reflect the coverage of the test stimuli at the verification points, thus realizing closed-loop measurement and management of the verification process.

[0101] Before including the test constraints and coverage model as verification information corresponding to the register configuration combination, the following is also included: Generate unique identifiers for one or more verification points respectively; Determine the constraint terms corresponding to each verification point in the test constraints, and the coverage bins corresponding to each verification point in the coverage model; Based on the unique identifier, establish the mapping relationship between each verification point, the corresponding constraint item, and the corresponding coverage module; Based on the mapping relationship, consistency checks are performed on the verification points, constraint terms, and coverage binaries; If each verification point has corresponding constraints and coverage repositories, the consistency check is considered successful.

[0102] This method generates unique identifiers for one or more verification points and identifies the corresponding constraint terms in the test constraints and the corresponding coverage modules in the coverage model, thus clarifying the correspondence between each verification point and its constraint terms and coverage modules. Furthermore, a mapping relationship is established between each verification point, its corresponding constraint terms, and its corresponding coverage modules based on the unique identifiers. Consistency checks are then performed on these mapping relationships to determine whether each verification point has its corresponding constraint terms and coverage modules. Therefore, this method can promptly detect verification points lacking corresponding constraint terms or coverage modules, reducing the problems of mismatches between test constraints and verification points, and between the coverage model and verification points, thereby improving the completeness and accuracy of the verification information corresponding to register configuration combinations.

[0103] Figure 6 A flowchart illustrating the overall process of a method for automatically generating register random test constraints and coverage models based on verification points, as provided in this embodiment of the invention, is shown below. Figure 6 As shown, the method includes: S36: Register description file parsing; S37: Extract information from each field segment of the register; S38: Verification point extraction; S39: Verification point data structure storage; S40: Generate register configuration constraints; S41: Output the file containing the constrained register configuration class; S42: Generate coverage model; S43: Output register function coverage model file.

[0104] This invention establishes a fully automated process from design description to asset verification by automatically extracting register configuration verification points and automatically generating random test constraints and functional coverage models. This method unifies the previously fragmented and manually completed definitions of verification objectives (verification points), implementation of verification methods (constraints), and measurement of verification effectiveness (coverage) at the data source, fundamentally changing the traditional verification model and bringing the following significant benefits: 1. Fundamentally improves verification efficiency and quality consistency: The manual coding and debugging work that traditionally takes days or even weeks is compressed into an automated generation process that takes only minutes, greatly improving the efficiency of setting up the verification environment. At the same time, since all verification assets originate from the same VP data model, inconsistencies such as definition conflicts and omissions that may occur with manual coding are fundamentally eliminated, ensuring the accurate realization of the verification intent.

[0105] 2. Systematically Enhanced Verification Completeness and Scientific Rigor: During the verification point extraction stage, systematic testing theories and algorithms such as equivalence class partitioning and boundary value analysis are embedded, replacing arbitrary extraction based on personal experience. This makes the verification scenario coverage more comprehensive and scientific, significantly reducing the risk of missing key scenarios due to human negligence, and improving the depth and credibility of the verification.

[0106] 3. Achieve end-to-end traceability and rapid debugging in the verification process: Every automatically generated constraint and every coverage collection point (bin) can be automatically traced back to a specific verification point in the verification plan. When a test fails or a coverage gap occurs, the original unmet verification scenario can be quickly located, greatly simplifying the problem analysis and debugging process and achieving precise backtracking from the problem phenomenon to the verification target.

[0107] 4. Achieve zero-cost synchronization and low-maintenance of verification assets: When design specifications change, only the register description file needs to be updated and this automated process re-executed. All associated test constraints and coverage models will be automatically synchronized and updated. This completely solves the tedious and error-prone problem of manually maintaining multiple sets of files, reducing maintenance costs to near zero and ensuring real-time synchronization between the verification environment and design iterations.

[0108] The above describes a method for generating verification information for register configuration combinations. This embodiment also provides a method for verifying register configuration combinations. Figure 7 A flowchart of a verification method for register configuration combinations provided in an embodiment of the present invention is shown below. Figure 7 As shown, the method includes: S44: Obtain the test constraints and coverage model corresponding to the test cases and register configuration combinations; S45: During the execution of test cases, the random variables corresponding to the domain segments of the target register are randomized based on the test constraints to obtain the register configuration values; S46: Write the register configuration value to the register configuration port of the hardware module to which the target register belongs, so as to drive the hardware module to run in the configuration scenario corresponding to the register configuration value; S47: Obtain the actual value of the target register during the operation of the hardware module, and sample the actual value through the coverage points in the coverage model; S48: Determine the coverage bins that the actual values ​​hit, and based on the hit status of the coverage bins, determine the coverage status of the verification points corresponding to the coverage bins.

[0109] In the register configuration combination verification method provided in this embodiment, the test constraints and coverage model are obtained through the above-described register configuration combination verification information generation method. The process of obtaining the test constraints and coverage model has been described in detail above, and the generation process of the test constraints and coverage model will not be repeated here.

[0110] In this method, during test case execution, the random variables corresponding to the target register domain are randomized based on test constraints. This generates register configuration values ​​that satisfy the value range defined by the verification point, ensuring that the test stimulus remains consistent with the preset verification target. Writing the configuration values ​​to the register configuration port of the hardware module enables the hardware module to actually run under the corresponding configuration scenario.

[0111] Furthermore, by acquiring the actual values ​​of the target registers during the operation of the hardware module and sampling these actual values ​​using coverage points in the coverage model, the coverage statistics are based on the actual configuration state received or presented by the hardware module. The coverage status of the corresponding verification points is determined according to the coverage bins hit by the actual values. Therefore, this approach improves the automation level of register configuration combination verification while making the coverage results more realistic and accurate, and enhances the consistency between the test execution process and the preset verification targets.

[0112] In some embodiments, the verification method for register configuration combinations further includes: Repeatedly execute the test cases, and re-randomize the random variables during each execution of the test cases; The register configuration value obtained through randomization is written to the register configuration port, and the actual value of the target register is sampled through the overlay point; If the number of times a test case is executed reaches the threshold, the hit rate of each coverage repository is statistically analyzed, and a coverage report is generated based on the statistical results.

[0113] There is no limit to the number of times; it is determined based on the actual situation.

[0114] This method repeatedly executes test cases, re-randomizing the random variables during each execution to continuously generate different register configuration values, thereby increasing the testing opportunities for different verification points and their corresponding hardware configuration scenarios. Each time, the randomized configuration value is written to the register configuration port, and the actual value of the target register is sampled through the coverage point. This continuously accumulates hit data for each coverage module, allowing the coverage to gradually converge with the number of test executions. After the number of executions reaches a threshold, the hit status of each coverage module is uniformly statistically analyzed and a coverage report is generated. This enables a quantitative evaluation of the coverage status of each verification point and clearly identifies the missed coverage modules and their corresponding uncovered verification points.

[0115] The register configuration combination verification method provided in this embodiment has the same or corresponding technical features as the register configuration combination verification information generation method described above, and the effect is the same.

[0116] In the above embodiments, the method for generating verification information for register configuration combinations, or the method for verifying register configuration combinations, has been described in detail. This invention also provides embodiments corresponding to a verification device and a verification apparatus for register configuration combinations. It should be noted that this invention describes the embodiments of the apparatus from two perspectives: one based on functional modules, and the other based on hardware.

[0117] An embodiment of the present invention provides a verification device for register configuration combinations. This embodiment, based on functional modules, includes: The acquisition module is used to acquire the register description file and parse the register description file to obtain the register field information; wherein the field information includes at least the bit width and value range; The partitioning and obtaining module is used to partition the value range based on the bit width in the domain segment information and obtain one or more verification points corresponding to the domain segment; The first generation module is used to obtain the random variables corresponding to the domain segment and determine the range of values ​​of the random variables based on one or more verification points in order to generate test constraints. The second generation module is used to obtain the coverage points corresponding to the domain segment, map one or more verification points to the coverage bins corresponding to the coverage points, and generate a coverage model based on the coverage points and coverage bins. As a module, it is used to combine test constraints and coverage models as register configurations to form corresponding verification information.

[0118] Since the embodiments of the apparatus and the embodiments of the method correspond to each other, please refer to the description of the embodiments of the method for the embodiments of the apparatus, which will not be repeated here.

[0119] Figure 8 This is a structural diagram of a verification device for register configuration combinations provided in an embodiment of the present invention. This embodiment is based on a hardware perspective, such as... Figure 8 As shown, the verification device for register configuration combination includes: Memory 20 is used to store computer programs; The processor 21 is configured to implement the steps of the method for generating verification information of register configuration combinations, or the method for verifying register configuration combinations, as mentioned in the above embodiments when executing a computer program.

[0120] The processor 21 may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor 21 may be implemented using at least one of the following hardware forms: Digital Signal Processor (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). The processor 21 may also include a main processor and a coprocessor. The main processor, also known as the Central Processing Unit (CPU), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 21 may integrate a Graphics Processing Unit (GPU), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, the processor 21 may also include an Artificial Intelligence (AI) processor, which handles computational operations related to machine learning.

[0121] The memory 20 may include one or more computer-readable storage media, which may be non-transitory. The memory 20 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In this embodiment, the memory 20 is used to store at least the following computer program 201, which, after being loaded and executed by the processor 21, is capable of implementing the register configuration combination verification information generation method disclosed in any of the foregoing embodiments, or related steps of the register configuration combination verification method. In addition, the resources stored in the memory 20 may also include an operating system 202 and data 203, etc., and the storage method may be temporary storage or permanent storage. The operating system 202 may include Windows, Unix, Linux, etc. The data 203 may include, but is not limited to, the data involved in the register configuration combination verification information generation method mentioned above, or the data involved in the register configuration combination verification method.

[0122] In some embodiments, the verification device for register configuration combination may further include a display screen 22, an input / output interface 23, a communication interface 24, a power supply 25, and a communication bus 26.

[0123] Those skilled in the art will understand that Figure 8 The structure shown does not constitute a limitation on the verification device for register configuration combinations and may include more or fewer components than shown.

[0124] The register configuration combination verification device provided in this embodiment of the invention includes a memory and a processor. When the processor executes a program stored in the memory, it can implement the following methods: a register configuration combination verification information generation method, or a register configuration combination verification method, with the same effect as above.

[0125] In addition, the present invention also provides a computer program product, including a computer program / instruction, which, when executed by a processor, implements the above-described method for generating verification information of register configuration combinations, or the steps of a method for verifying register configuration combinations.

[0126] Finally, the present invention also provides an embodiment corresponding to a computer-readable storage medium. The computer-readable storage medium stores a computer program, which, when executed by a processor, performs the steps described in the above method embodiments.

[0127] It is understood that if the methods in the above embodiments are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0128] The computer-readable storage medium provided by this invention includes the aforementioned method for generating verification information of register configuration combinations, or a method for verifying register configuration combinations, with the same effect.

[0129] The foregoing has provided a detailed description of the method for generating verification information for register configuration combinations, the verification method, and the apparatus provided by this invention. The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section. It should be noted that those skilled in the art can make several improvements and modifications to this invention without departing from the principles of this invention, and these improvements and modifications also fall within the protection scope of this invention.

[0130] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A method for generating verification information for register configuration combinations, characterized in that, include: Obtain the register description file and parse the register description file to obtain the register field information; wherein the field information includes at least the bit width and value range; The value range is divided according to the bit width in the domain segment information to obtain one or more verification points corresponding to the domain segment; Obtain the random variable corresponding to the domain segment, and determine the value range of the random variable based on the one or more verification points to generate test constraints; Obtain the coverage points corresponding to the domain segment, map the one or more verification points to the coverage bins corresponding to the coverage points, and generate a coverage model based on the coverage points and the coverage bins; The test constraints and the coverage model are used as verification information corresponding to the register configuration combination; The value range is divided according to the bit width in the segment information, and one or more verification points corresponding to the segment are obtained, including: If the bit width in the field segment information is detected to be less than or equal to the preset bit width, the values ​​within the value range corresponding to the field segment are traversed. Each value obtained through traversal is determined as a verification point corresponding to the domain segment; If the bit width in the domain segment information is detected to be greater than the preset bit width, a boundary value is determined from the value range corresponding to the domain segment, and the boundary value is determined as the verification point corresponding to the domain segment; Remove the boundary values ​​from the value range to obtain the non-boundary value range; The non-boundary value range is divided into multiple equivalent intervals, and each of the equivalent intervals is determined as the verification point corresponding to the domain segment; Obtaining the random variable corresponding to the domain segment includes: Based on the bit width in the field segment information, a random variable with random attributes is generated; wherein the storage bits of the random variable are the same as the bit width of the field segment; Determining the range of values ​​for the random variable based on one or more verification points to generate test constraints includes: When the bit width in the domain segment information is less than or equal to the preset bit width, each value is converted into an independent weighted value item; the same weight is set for each weighted value item, and the test constraint is generated based on the weighted value item; If the bit width in the domain segment information is greater than the preset bit width, the boundary value is converted into an independent weighted value item, and the equivalent interval is converted into a weighted range item; the same weight is set for the weighted value item and the weighted range item, and the test constraint is generated based on the weighted value item and the weighted range item.

2. The method for generating verification information for register configuration combinations according to claim 1, characterized in that, The non-boundary value range is divided into multiple equivalent intervals, including: The number of values ​​in each interval is determined based on the preset number of intervals and the number of values ​​within the non-boundary value range; wherein, if the number of values ​​cannot be evenly distributed according to the preset number of intervals, the remaining values ​​are allocated to some intervals. Based on the number of values ​​in each interval, the values ​​within the non-boundary value range are divided to obtain multiple equivalent intervals.

3. The method for generating verification information for register configuration combinations according to claim 1, characterized in that, After obtaining one or more verification points corresponding to the domain segment, and before obtaining the random variable corresponding to the domain segment, the process further includes: When the bit width in the domain segment information is less than or equal to the preset bit width, each value in the value range is written into the verification point description string in the order of the values ​​in the value range to obtain the verification point description string corresponding to the domain segment. If the bit width in the domain segment information is greater than the preset bit width, obtain the boundary value and equivalent interval corresponding to the domain segment; according to the preset description rules, write the boundary value into the boundary value field, write the start value and end value of the equivalent interval into the interval field, and obtain the verification point description string corresponding to the domain segment based on the boundary value field and the interval field.

4. The method for generating verification information for register configuration combinations according to claim 3, characterized in that, After obtaining the verification point description string corresponding to the domain segment, the following is also included: Determine if there is a field segment without a verification point description string; If so, return to the step of determining whether the bit width in the field segment information is less than or equal to the preset bit width; If not, the verification point description strings of multiple domain segments will be summarized and sorted according to preset rules, and the summarized description information will be written into the verification point description file.

5. The method for generating verification information for register configuration combinations according to claim 1, characterized in that, After generating test constraints, the following is also included: Obtain the test constraints corresponding to different domain segments; The test constraints corresponding to different domain segments are encapsulated into a unified constraint class.

6. The method for generating verification information for register configuration combinations according to claim 1, characterized in that, Mapping the one or more verification points to the coverage bins corresponding to the coverage points includes: When the bit width in the domain segment information is less than or equal to the preset bit width, a corresponding independent overlay bin is created for each value within the value range, and each independent overlay bin is associated with the overlay point; If the bit width in the domain segment information is greater than the preset bit width, a corresponding independent coverage bin is created for the boundary value, and a corresponding range coverage bin is created for the equivalent interval. The independent coverage bin and the range coverage bin are then associated with the coverage point.

7. The method for generating verification information for register configuration combinations according to claim 6, characterized in that, After mapping the one or more verification points to coverage bins corresponding to the coverage points, and before generating a coverage model based on the coverage points and coverage bins, the method further includes: Generate readable tags for the covered compartment; Add annotation information to the coverage point or the coverage group to which the coverage point belongs; wherein, the annotation information includes at least the source register, the domain segment information, and the verification point description information corresponding to the coverage repository.

8. A method for verifying register configuration combinations, characterized in that, include: Obtain test cases and corresponding test constraints and coverage models for register configuration combinations; wherein, the test constraints and coverage models are obtained by the verification information generation method for register configuration combinations as described in any one of claims 1 to 7; During the execution of the test cases, the random variables corresponding to the domain segments of the target register are randomized based on the test constraints to obtain the register configuration values; The register configuration value is written to the register configuration port of the hardware module to which the target register belongs, so as to drive the hardware module to run in the configuration scenario corresponding to the register configuration value; The actual value of the target register is obtained during the operation of the hardware module, and the actual value is sampled through the coverage points in the coverage model; Determine the coverage area where the actual value is hit, and based on the hit status of the coverage area, determine the coverage status of the verification point corresponding to the coverage area.

9. The verification method for register configuration combinations according to claim 8, characterized in that, Also includes: The test cases are executed repeatedly, and the random variables are re-randomized during each execution of the test cases; The register configuration value obtained through randomization is written to the register configuration port, and the actual value of the target register is sampled through the coverage point; If the number of times the test case is executed reaches the threshold, the hit rate of each coverage repository is statistically analyzed, and a coverage report is generated based on the statistical results.

10. A verification device for register configuration combinations, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement, when executing the computer program, the steps of the method for generating verification information of register configuration combinations as described in any one of claims 1 to 7, or the steps of the method for verifying register configuration combinations as described in claim 8 or 9.

11. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the method for generating verification information of register configuration combinations as described in any one of claims 1 to 7, or the steps of the method for verifying register configuration combinations as described in claim 8 or 9.

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