Hardware behavior description method, apparatus, electronic device, and program product

Abstract

The application is suitable for the technical field of computers, and provides a hardware behavior description method and device, electronic equipment and program product, comprising: collecting execution behaviors of hardware under different running conditions during hardware running to obtain a set of execution characteristic information of hardware under different running conditions; performing abstract processing on each execution characteristic information in each set of execution characteristic information to obtain an execution characteristic description vector of hardware under different running conditions; and packaging and storing each execution characteristic description vector to obtain execution characteristic description data of hardware. The application perceives, abstracts and organizes execution behaviors of hardware under different running conditions during real running processes, constructs an execution characteristic description system capable of describing execution characteristics of the same hardware under multiple execution modes, can not only reflect execution behaviors of hardware under real running conditions, but also is convenient for direct calling during subsequent model deployment, operator mapping or execution strategy determination.

Description

Technical Field

[0001] This application belongs to the field of computer technology, and in particular relates to a hardware behavior description method, apparatus, electronic device and program product. Background Technology

[0002] In practical applications, computing hardware is used to carry various computational algorithms, complete data processing, logical judgment, instruction execution, and service scheduling, and can encompass main control chips, digital signal processors, programmable logic devices, and various dedicated computing power processing units. Therefore, the description of computing hardware is extremely important. However, current descriptions of computing hardware (such as Neural Processing Units, NPUs) typically focus on peak computing power, theoretical bandwidth, and static benchmark test results, which are not comprehensive enough and fail to meet actual needs. Summary of the Invention

[0003] This application provides a hardware behavior description method, apparatus, electronic device, and program product to address the problem that existing technologies lack comprehensive consideration and fail to meet practical needs.

[0004] In a first aspect, embodiments of this application provide a hardware behavior description method, including: During hardware operation, the execution behavior of the hardware under different operating conditions is collected to obtain a set of execution characteristic information of the hardware under different operating conditions; The execution characteristic information in each execution characteristic information set is abstracted to obtain the execution characteristic description vector of the hardware under different operating conditions; the abstraction process includes the process of extracting core features from each execution characteristic information; Each execution characteristic description vector is encapsulated and stored to obtain execution characteristic description data of the hardware under multiple execution modes.

[0005] Optionally, different operating conditions include: different operator types, different computing scales, and different resource usage conditions; each execution characteristic information includes: execution response characteristic information of computing units, storage access path and access behavior characteristic information, and operator scheduling and resource contention behavior characteristic information.

[0006] Optionally, the execution characteristic information in each execution characteristic information set is abstracted to obtain the execution characteristic description vector of the hardware under different operating conditions, including: For each set of execution characteristic information, feature extraction is performed on each execution characteristic information in each set of execution characteristic information to obtain multiple corresponding feature information; Normalize each feature information to obtain the feature vector corresponding to each execution characteristic information; By concatenating the various feature vectors, we obtain the execution characteristic description vector corresponding to each execution characteristic information set.

[0007] Optionally, each execution characteristic description vector is encapsulated and stored to obtain execution characteristic description data of the hardware under multiple execution modes, including: Each execution characteristic description vector is encapsulated to obtain an execution characteristic description unit; the execution characteristic description unit includes the subject of the corresponding execution characteristic description vector, the runtime condition label, and the applicable scope description. Each execution characteristic description unit is stored to obtain execution characteristic description data.

[0008] Optionally, each execution characteristic description unit is stored to obtain execution characteristic description data, including: The execution characteristic description units are classified and stored based on the preset running condition dimension to obtain the execution characteristic description data; the preset running condition dimension includes at least one of operator type, computing scale and resource consumption conditions.

[0009] Optionally, after obtaining the execution characteristic description data of the hardware in multiple execution modes, the method further includes: In response to a retrieval request, extract the current execution characteristics of the current task from the retrieval request; Target execution characteristic description units that match the current execution characteristics are obtained from the execution characteristic description data; Under the current task, control the hardware reuse target execution characteristic description unit.

[0010] Optionally, the control hardware multiplexing target execution characteristic description unit includes: The operator mapping method is determined based on the target execution characteristic description unit; And / or, The execution unit allocation method is determined based on the target execution characteristic description unit; And / or, The scheduling order and parallel strategy are determined based on the target execution characteristic description unit.

[0011] Secondly, embodiments of this application provide a hardware behavior description device, including: The acquisition unit is used to collect the execution behavior of the hardware under different operating conditions during the hardware operation process, and obtain a set of execution characteristic information of the hardware under the different operating conditions. The abstract processing unit is used to abstract each execution characteristic information in each execution characteristic information set to obtain the execution characteristic description vector of the hardware under the different operating conditions; the abstract processing includes the process of extracting core features from each execution characteristic information. The data determination unit is used to encapsulate and store each execution characteristic description vector to obtain execution characteristic description data of the hardware under multiple execution modes.

[0012] Thirdly, embodiments of this application provide an electronic device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the hardware behavior description method as described in any one of the first aspects above.

[0013] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the hardware behavior description method as described in any one of the first aspects above.

[0014] Fifthly, embodiments of this application provide a computer program product that, when run on an electronic device, enables the electronic device to execute the hardware behavior description method described in any one of the first aspects.

[0015] The beneficial effects of the embodiments in this application compared with the prior art are: This application provides a hardware behavior description method. During hardware operation, the method collects the execution behavior of the hardware under different operating conditions to obtain a set of execution characteristic information under these conditions. Each execution characteristic information in each set is abstracted to obtain an execution characteristic description vector under different operating conditions. These vectors are then encapsulated and stored to obtain the hardware's execution characteristic description data. This application constructs an execution characteristic description system capable of characterizing the same hardware under multiple execution modes by perceiving, abstracting, and organizing the execution behavior of hardware during real-world operation under different conditions. This system not only reflects the hardware's execution behavior under different real-world operating conditions but also facilitates direct invocation during subsequent model deployment, operator mapping, or execution strategy determination. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a flowchart illustrating the implementation of a hardware behavior description method provided in an embodiment of this application; Figure 2 This is a flowchart illustrating the implementation of a hardware behavior description method provided in another embodiment of this application; Figure 3 This is a flowchart illustrating the implementation of a hardware behavior description method provided in another embodiment of this application; Figure 4 This is a schematic diagram of the structure of a hardware behavior description device provided in an embodiment of this application; Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0018] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0019] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0020] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0021] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0022] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0023] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0024] In practical applications, computing hardware is used to carry various computational algorithms, complete data processing, logical judgment, instruction execution, and business scheduling, and can encompass main control chips, digital signal processors, programmable logic devices, and various dedicated computing power processing units. Therefore, the description of computing hardware is extremely important. However, current descriptions of computing hardware (such as Neural Processing Units, NPUs) typically focus on peak computing power, theoretical bandwidth, and static benchmark test results, but do not define: what the actual execution behavior of computing hardware is under specific operator types, specific input sizes, and specific resource usage conditions.

[0025] In other words, existing technologies cannot reflect the performance behavior of computing hardware under real-world operating conditions, such as: How are computing units occupied? How is the storage access path triggered? How do scheduling conflicts arise and evolve?

[0026] Meanwhile, existing technologies typically describe the performance of computing hardware using uniform metrics, but do not: Distinguish between the execution differences of convolution operators and vector operators on the same computing hardware; Distinguish the execution characteristics of computationally intensive operators from those of memory-access intensive operators.

[0027] Therefore, the behavioral differences of the same computing hardware when executing different operators are averaged or masked, making it impossible for existing technologies to systematically describe the multiple execution modes exhibited by the same computing hardware under different operator types.

[0028] To address the aforementioned issues, this application provides a hardware behavior description method. By perceiving, abstracting, and organizing the execution behavior of computing hardware during actual operation, a description system capable of characterizing the execution characteristics of the same computing hardware in multiple execution modes can be constructed, thereby enabling the systematic description and reuse of hardware execution characteristics.

[0029] Please see Figure 1 , Figure 1 This is a flowchart illustrating the implementation of a hardware behavior description method according to an embodiment of this application. In this embodiment, the executing entity of the hardware behavior description method is an electronic device.

[0030] Among them, electronic devices can be field-programmable gate arrays (FPGAs), microcontroller units (MCUs), or computing devices (such as desktop computers, servers, etc.), which will not be elaborated here.

[0031] like Figure 1 As shown, a hardware behavior description method provided in one embodiment of this application may include S101~S103, which are detailed below: In S101, during the hardware operation, the execution behavior of the hardware under different operating conditions is collected to obtain a set of execution characteristic information of the hardware under different operating conditions.

[0032] It should be noted that the hardware mentioned above can be computing hardware, such as an NPU.

[0033] In this embodiment of the application, during the operation of the hardware, the electronic device collects real-time data on the actual execution behavior of the hardware under different operating conditions, that is, the execution behavior of the hardware is collected, thereby obtaining a set of execution characteristic information of the hardware under different operating conditions.

[0034] It should be noted that the execution characteristic information set includes data on the actual execution behavior of the hardware collected under certain operating conditions.

[0035] In one embodiment of this application, different operating conditions may include: different operator types, different computational scales, and different resource consumption conditions, etc.

[0036] It should be noted that different operator types are used to describe various operational instructions and models supported by the hardware, which may include convolution, matrix multiplication and addition, activation functions, pooling, logical operations, floating-point operations, etc., to switch between different operational tasks to test hardware behavior.

[0037] Different computing scales are used to describe the data volume, number of tasks, and number of iterations in a single operation. They can include small-batch, medium-batch, and large-batch data operations to distinguish between light-load and heavy-load computing scenarios.

[0038] Different resource occupancy conditions are used to describe the occupancy ratio of hardware resources such as hardware computing cores, on-chip cache, bus bandwidth, and memory channels. They can include three resource states: simulated idle, medium occupancy, and high preemption contention.

[0039] In this embodiment, the execution characteristic information may include: execution response characteristic information of the computing unit, storage access path and access behavior characteristic information, and operator scheduling and resource contention behavior characteristic information, etc.

[0040] It should be noted that the execution response characteristic information of the computing unit is used to describe the actual operating performance of the computing core, including but not limited to indicators such as computing time, processing throughput, instruction cycle, computing power consumption, computing accuracy and task response latency.

[0041] Storage access path and access behavior characteristics information are used to describe data access-related behaviors, including but not limited to read and write address flow, access order, read and write frequency, cache hit misses, on-chip / off-chip storage jumps, and data movement patterns.

[0042] Operator scheduling and resource contention behavior characteristics are used to describe the task arrangement and resource contention status, including but not limited to operator queuing scheduling order, task switching interval, number of resource contention conflicts among multiple tasks, resource allocation priority, and scheduling blocking status.

[0043] In this embodiment, after the electronic device starts up and enters a stable operating state, it can systematically configure and traverse the above three types of operating conditions, namely, traversing different operator types, different computing scales, and different resource usage conditions.

[0044] It should be noted that different operator types, different computational scales, and different resource usage conditions can each type of operating condition constitute a single operating condition, or they can be combined to form a single operating condition by combining at least two types of operating conditions from different operator types, different computational scales, and different resource usage conditions.

[0045] Compared with existing technologies that only know how fast the hardware can run, but not how the hardware is running, the embodiments of this application do not use chip specifications or static benchmarks as the object of description. Instead, they perceive the execution response behavior of the computing unit, the memory access path and access mode, and the operator scheduling and resource contention behavior during the actual operation of the model or operator.

[0046] Therefore, through step S101, the embodiments of this application change the described object from hardware capabilities to hardware execution behavior, which can effectively make up for the gap in the invisible execution form in the prior art.

[0047] In S102, the execution characteristic information in each execution characteristic information set is abstracted to obtain the execution characteristic description vector of the hardware under different operating conditions; the abstraction process includes the process of extracting core features from each execution characteristic information.

[0048] In this embodiment, the electronic device can abstract each execution characteristic information in each execution characteristic information set, that is, filter each execution characteristic information in each execution characteristic information set to remove redundancy, thereby obtaining each valid characteristic information in each execution characteristic information set. Then, the electronic device can perform structured encoding on each valid characteristic information in each execution characteristic information set to convert each execution characteristic information set into a fixed-dimensional, computable, and comparable numerical vector, that is, the execution characteristic description vector corresponding to each execution characteristic information set, thereby obtaining the execution characteristic description vector of the hardware under different operating conditions.

[0049] It should be noted that each running condition can correspond to an execution characteristic description vector.

[0050] It should be understood that each execution characteristic description vector is used to characterize the execution pattern of the hardware under the corresponding operating conditions, including but not limited to: computation response characteristics, memory access characteristics, and scheduling behavior characteristics.

[0051] In one embodiment of this application, the electronic device may specifically implement step S102 according to the following steps, as detailed below: For each set of execution characteristic information, feature extraction is performed on each execution characteristic information in each set of execution characteristic information to obtain multiple corresponding feature information; Normalize each feature information to obtain the feature vector corresponding to each execution characteristic information; By concatenating the various feature vectors, we obtain the execution characteristic description vector corresponding to each execution characteristic information set.

[0052] In this embodiment, for each set of execution characteristic information, the electronic device can determine the key indicator that best characterizes the hardware behavior from each execution characteristic information in the set, for example: The execution response characteristics information of the computing unit includes execution cycle, computing power utilization, and latency, etc. Store access path and access behavior characteristics information, such as hit rate, bandwidth, and number of hops in the access path; The queuing time, number of resource conflicts, and switching overhead are among the characteristics of operator scheduling and resource contention behavior.

[0053] Then, the electronic device can extract features from each execution characteristic information in the above execution characteristic information set to obtain the above key indicators, thereby obtaining multiple feature information corresponding to each execution characteristic information in the execution characteristic information set.

[0054] In this embodiment, the electronic device can uniformly map indicators of different units and magnitudes (such as period, bandwidth, time, and number of times) in the above-mentioned feature information to [0, 1] or standard numerical range to eliminate the difference in dimensions, thereby realizing the normalization processing of each feature information and obtaining the feature vector corresponding to each execution feature information in the above-mentioned execution feature information set.

[0055] Then, the electronic device can arrange the feature vectors in the above-mentioned execution characteristic information set in a preset order and concatenate them to form an execution characteristic description vector. The preset order can be determined according to actual needs and is not limited here.

[0056] For example, the execution characteristic description vector = [computation response feature vector 1, computation response feature vector 2, ..., storage access feature vector 1, storage access feature vector 2, ..., scheduling behavior feature vector 1, scheduling behavior feature vector 2, ...]. Here, the computation response feature vector refers to the feature vector corresponding to the execution response characteristic information of the computation unit; the storage access feature vector refers to the feature vector corresponding to the storage access path and access behavior characteristic information; and the scheduling behavior feature vector refers to the feature vector corresponding to the operator scheduling and resource contention behavior characteristic information.

[0057] Compared with the existing technology where the differences in execution under different operators and different loads cannot be uniformly expressed, the embodiments of this application do not directly use the original execution data, but abstract the perceived execution behavior and map the computation response characteristics, storage access characteristics and scheduling behavior characteristics into a unified structured execution characteristic description vector.

[0058] Therefore, through step S102, in this embodiment of the application, convolution operators, vector operators, light load and heavy load conditions, etc., can all be expressed by the same descriptive structure, only with different values, thereby effectively solving the problem that diverse execution behaviors cannot be uniformly described.

[0059] In S103, each execution characteristic description vector is encapsulated and stored to obtain execution characteristic description data of the hardware under multiple execution modes.

[0060] In this embodiment, the electronic device can attach a label to each execution characteristic description vector. The attached label includes, but is not limited to, operator type, computational scale, resource consumption conditions, data collection timestamp, and hardware version, forming a structured entry consisting of runtime conditions and a description vector.

[0061] Subsequently, the electronic device can encapsulate and store each execution characteristic description vector according to a preset data structure, thereby obtaining execution characteristic description data of the hardware under multiple execution modes.

[0062] The preset data structures include, but are not limited to, binary format (for efficient storage), JSON / XML (for easy parsing), data table format (for easy retrieval), and custom protocol format (for hardware specific use).

[0063] Compared to existing technologies where the same hardware is treated as having only one performance characteristic, the embodiments of this application clarify that the same hardware will essentially exhibit multiple execution modes under different operator types, different computing scales, and different resource consumption conditions. Therefore, the embodiments of this application do not attempt to cover all situations with a single description, but rather generate corresponding execution characteristic description vectors under different execution conditions, and organize these vectors into a set of hardware execution characteristic description vectors, that is, execution characteristic description data of hardware under multiple execution modes.

[0064] Through step S103, a vector can be approximately equal to an execution mode, and a set of execution characteristic description vectors can be equal to the execution characteristic of a piece of hardware. This can effectively solve the problem that multiple execution modes cannot be systematically characterized.

[0065] In one embodiment of this application, the electronic device can specifically be implemented via, as follows: Figure 2 Steps S201 to S202 shown implement step S103, as detailed below: In S201, each execution characteristic description vector is encapsulated to obtain each execution characteristic description unit; the execution characteristic description unit includes the subject of the corresponding execution characteristic description vector, the running condition label, and the applicable scope description.

[0066] In this embodiment, for each execution characteristic description vector corresponding to a running condition, the electronic device can directly write the execution characteristic description vector as the core data ontology of the description unit, and accurately bind the corresponding acquisition running condition to the execution characteristic description vector to generate structured tag data, namely, running condition tags. Finally, based on the running conditions and hardware execution behavior characteristics corresponding to the execution characteristic description vector, the electronic device can generate an applicable scope description combining natural language and standardized fields to clarify the effective applicable scenarios, boundary conditions, and usage limitations of this set of execution characteristic vector data.

[0067] The runtime condition tags can include three core tags: operator type tags, computation scale tags, and resource usage tags.

[0068] It should be noted that the operator type label is used to indicate the type of hardware operator under the corresponding operating conditions, such as convolution operator, matrix multiplication operator, activation operator, pooling operator, logical operation operator, etc.

[0069] The computation scale label is used to quantify the computational load level and specific parameters under corresponding operating conditions, including small / medium / large load levels, input data tensor size, number of computation iterations, number of parallel tasks, etc.

[0070] Resource usage tags are used to indicate the hardware resource usage and contention status under corresponding operating conditions, including computing core utilization, on-chip cache utilization, bus bandwidth utilization, memory channel utilization, etc.

[0071] The scope of application description may include three aspects: applicable business scenarios, effective operating boundaries, and feature adaptation instructions.

[0072] It should be noted that the applicable business scenarios are used to label the actual hardware business scenarios under the corresponding operating conditions, such as lightweight inference, large-scale model training, multi-task concurrent operation, and high-frequency data migration.

[0073] The effective operating boundary is used to define the effective parameter range of the execution characteristic description vector under the corresponding operating conditions, such as data volume threshold, resource consumption threshold, operator combination limit, etc. If the boundary is exceeded, the set of characteristic data will be invalid.

[0074] Feature adaptation descriptions are used to indicate the adaptability of the core behavioral characteristics of the hardware under corresponding operating conditions, such as whether it is suitable for high-throughput scenarios, low-latency scenarios, resource-constrained scenarios, etc.

[0075] In this embodiment, the electronic device can structurally concatenate, format-validate, and complete the three parts of the execution characteristic description vector: the ontology, the running condition label, and the applicable scope description, thereby generating the smallest independent data unit of the execution characteristic description vector, namely the execution characteristic description unit.

[0076] Through step S201, the electronic device associates and encapsulates the execution characteristic description vector with its corresponding operator type, computational scale, and resource consumption conditions to form an execution characteristic description unit that can be called independently.

[0077] In S202, each execution characteristic description unit is stored to obtain execution characteristic description data.

[0078] In this embodiment, the electronic device can encapsulate all execution characteristic description units as a whole, unify the data storage protocol and file format, and add global attributes such as unique hardware identifier, data acquisition version, generation timestamp, and checksum to form a complete data packet. Finally, the encapsulated data packet is persistently stored in the hardware firmware, local storage, or a dedicated database. The stored data is the complete execution characteristic description data of the hardware under multiple different execution modes.

[0079] In one embodiment of this application, the electronic device may specifically implement step S202 according to the following steps, as detailed below: Each execution characteristic description unit is classified and stored based on a preset operating condition dimension to obtain execution characteristic description data; the preset operating condition dimension includes at least one of operator type, computation scale, and resource consumption conditions.

[0080] It should be noted that the preset operating conditions include at least one of the following: operator type, computation scale, and resource consumption conditions.

[0081] In this embodiment, the electronic device can traverse all execution feature description units, extract the running condition tags built into each execution feature description unit, match the running condition tags with different preset running condition dimensions one by one, determine the operator type, computing scale and resource consumption conditions of each execution feature description unit, and complete the multi-dimensional attribute labeling of each execution feature description unit.

[0082] Subsequently, the electronic device can perform structured partitioning and storage of all execution characteristic description units based on the multi-dimensional attribute annotations of each matched execution characteristic description unit.

[0083] For example, electronic devices can adopt a hierarchical storage architecture of major categories, subdivided intervals, and independent units: firstly, the first-level major category partitioning is completed according to the operator type; within each operator partitioning, the second-level sub-partitioning is completed according to the computing scale; finally, within the corresponding scale sub-partitions, fine-grained classification and storage are completed according to resource usage conditions, thereby achieving ordered storage with multi-dimensional hierarchical nesting.

[0084] In this embodiment, the electronic device can uniformly and persistently store all execution characteristic description units that have completed multi-dimensional classification, hierarchical organization, and attribute encapsulation in hardware firmware, local storage medium, or dedicated database, and finally obtain execution characteristic description data that is organized based on multiple operating conditions and covers all execution forms of hardware.

[0085] As can be seen from the above, the hardware behavior description method provided in this application collects the execution behavior of the hardware under different operating conditions during hardware operation, obtaining a set of execution characteristic information of the hardware under different operating conditions; abstracts each execution characteristic information in each execution characteristic information set to obtain an execution characteristic description vector of the hardware under different operating conditions; and encapsulates and stores each execution characteristic description vector to obtain the execution characteristic description data of the hardware. This application, by perceiving, abstracting, and organizing the execution behavior of hardware during actual operation under different operating conditions, constructs an execution characteristic description system capable of characterizing the same hardware under multiple execution modes. This system not only reflects the execution behavior of the hardware under real operating conditions but also facilitates direct invocation during subsequent model deployment, operator mapping, or execution strategy determination.

[0086] Please see Figure 3 , Figure 3 This is a flowchart illustrating the implementation of a hardware behavior description method provided in another embodiment of this application. Compared to... Figure 1 In a corresponding embodiment, this embodiment may further include S301~S303 after S103, as detailed below: In S301, in response to the retrieval request, the current execution characteristics of the current task are extracted from the retrieval request.

[0087] It should be noted that electronic devices can establish retrieval entry points for the aforementioned execution characteristic description data for subsequent calls.

[0088] In this embodiment, when the hardware scheduling system issues a new model deployment, a new operator mapping, or generates a hardware resource scheduling requirement, the hardware platform can automatically generate a corresponding retrieval request. Subsequently, the electronic device can respond to the retrieval request in real time and analyze and extract the current task's operational characteristics to obtain the current execution characteristics of the current task.

[0089] Among them, the current execution characteristics correspond one-to-one with the aforementioned running condition dimensions, and are multi-dimensional combined features. The specific extracted content may include: current operator characteristics, current computation scale characteristics, and current resource usage characteristics, etc.

[0090] It should be noted that the current operator characteristics are used to identify the type of operator that the current task needs to execute.

[0091] The current computational scale characteristics are used to analyze the input data volume, tensor size, number of parallel tasks, and number of iterations of the current task to determine the computational scale of the current task.

[0092] The current resource usage characteristics are used to count the computing cores, on-chip cache, bus bandwidth, and memory channel resources currently occupied by the hardware where the current task is running, and to predict the resource usage level and resource contention level during the execution of the current task.

[0093] In S302, target execution characteristic description units that match the current execution characteristics are selected from the execution characteristic description data.

[0094] In this embodiment, the electronic device can use the extracted current execution characteristics as search conditions to traverse and search the classified and stored execution characteristic description data and perform similarity matching to filter out target execution characteristic description units that are highly suitable for the current task.

[0095] The specific steps can be as follows: Step 1: Multi-dimensional indexing for rapid location: In conjunction with step S202, the electronic device can, based on the aforementioned hierarchical storage architecture of operator type, computing scale, and resource usage conditions, lock the corresponding storage partition in the execution characteristic description data according to the current operator type, current computing scale, and current resource usage characteristics, thereby narrowing the search scope, avoiding full data traversal, and improving search efficiency.

[0096] Step 2: Calculation of similarity between operating conditions and features: Within the locked storage partition, the electronic device can compare the current execution characteristics of the current task with the running condition labels and execution characteristic description vectors of each execution characteristic description unit one by one, calculate the operating condition matching similarity, and filter out multiple candidate description units with the highest feature similarity.

[0097] Step 3: Filter and execute feature description units based on applicable scope verification. For the multiple candidate description units obtained from the initial screening, the electronic device can perform boundary verification based on the applicable scope description built into each candidate description unit, and eliminate candidate description units that are beyond the scope of business scenario adaptation, exceed the valid parameter boundaries, or are not suitable for the current task running environment, and finally select the unique or optimal target execution characteristic description unit.

[0098] In S303, under the current task, the control hardware reuse target execution characteristic description unit is used.

[0099] In this embodiment, after the electronic device determines the target execution characteristic description unit, the hardware can directly call and reuse the complete data of the unit to support the efficient execution of the current task and the adaptive adaptation of hardware behavior.

[0100] Specifically, the above-mentioned reuse implementation methods may include: I. Reusing quantized feature vectors: Electronic devices can control hardware to directly reuse the ontology of the execution characteristic description vector in the target execution characteristic description unit, obtain quantitative data on the hardware computing response latency, storage access patterns, and scheduling competition characteristics under the current working conditions, and provide accurate data basis for the computing power allocation, latency prediction, and bandwidth scheduling of the current task.

[0101] II. Reuse Operating Condition Adaptation Rules: Electronic devices can control the running condition labels and applicable scope descriptions of the hardware reuse target execution characteristic description unit to quickly determine the optimal resource scheduling strategy, data access path, and operator arrangement for the current task, thereby effectively avoiding problems such as resource conflicts, memory access congestion, and task blocking.

[0102] III. Achieving Dynamic Adaptive Scheduling and Reuse: Throughout the entire runtime of the current task, the electronic device can control the hardware to dynamically adjust the hardware resource allocation ratio, task scheduling sequence, and cache read / write strategy in real time according to the hardware behavior characteristics described by the target execution characteristic description unit, so that the execution state of the current task matches the optimal operating characteristics of the hardware.

[0103] In one embodiment of this application, when the current task is a new operator mapping, the electronic device may specifically determine the operator mapping method based on the target execution characteristic description unit.

[0104] In this embodiment, since the target execution characteristic description unit records the computation response characteristic vector, storage access characteristic vector and scheduling behavior characteristic vector of different operators under the corresponding working conditions, the electronic device can control the hardware to complete the mapping and adaptation of the operator corresponding to the current task based on the target execution characteristic description unit.

[0105] Specifically, the electronic device can control the hardware to first read the operator type label and computation response feature vector within the target execution characteristic description unit, obtaining the optimal computation mapping rules for that type of operator under the corresponding computational scale and resource consumption state, including operator computation level mapping, tensor dimension mapping, and operator segmented execution mapping relationship. Secondly, the electronic device can control the hardware to match the standard memory access mapping paths for data input, intermediate cache, and result write-back during operator computation based on the memory access feature vector built into the target execution characteristic description unit. Finally, the electronic device can control the hardware to effectively avoid conflicting operator combination mapping methods based on the scheduling behavior feature vector in the target execution characteristic description unit, generating a dedicated operator mapping relationship adapted to the current hardware's actual behavior. This achieves dynamic adaptation between business operators and the hardware computing and storage architectures, reducing performance losses caused by operator execution redundancy, memory access mismatch, and mapping misalignment.

[0106] In one embodiment of this application, when the current task is to deploy a new model, the electronic device can specifically determine the execution unit allocation method based on the target execution characteristic description unit.

[0107] It should be noted that execution unit allocation mainly refers to the allocation and binding of hardware computing cores, on-chip caches, storage channels, and bus resources.

[0108] In this embodiment, the electronic device can control the hardware to achieve refined, non-excessive, and conflict-free resource allocation based on the scheduling behavior feature vector and calculation response feature vector of the target execution characteristic description unit, i.e., the execution unit allocation method.

[0109] Specifically, electronic devices can control hardware to parse the scheduling behavior feature vector in the target execution characteristic description unit, obtain the optimal occupancy ratio, idle threshold, and conflict-prone resource points of each execution unit under the current task; and combine it with the computation response feature vector in the target execution characteristic description unit to match the number and working frequency of computational execution units with the optimal computing power matching degree for the current task; and allocate cache partitions, memory channels, and bus bandwidth resources that are suitable for the current data scale and access patterns according to the storage access feature vector in the target execution characteristic description unit; and finally form a targeted execution unit allocation method, which can effectively avoid problems such as resource idle waste, excessive resource preemption, frequent conflicts, and memory access blocking, and realize the stable and efficient operation of the current task under the appropriate resource allocation.

[0110] In one embodiment of this application, when the current task is determined by a new execution strategy, the electronic device may specifically determine the scheduling order and parallel strategy based on the target execution characteristic description unit.

[0111] It should be noted that, since the target execution characteristic description unit fixes the operator queuing scheduling order, task switching interval, number of resource contention conflicts, resource allocation priority and scheduling blocking status under the current task, in this embodiment, the electronic device can control the hardware to dynamically generate the optimal scheduling order and parallel execution strategy based on the scheduling behavior feature vector in the target execution characteristic description unit.

[0112] Specifically, the electronic device can control the hardware to read the scheduling behavior feature vector in the target execution characteristic description unit, and obtain the task queuing latency, switching overhead, and resource preemption probability under different operator combinations and different computing scales. Based on the measured characteristics corresponding to the task queuing latency, switching overhead, and resource preemption probability under different operator combinations and different computing scales, the device prioritizes the sub-operators and sub-tasks of the current task, determines the serial execution order, pre-dependencies, and post-execution logic, and combines the multi-task parallel operation characteristics of the execution units in the hardware to determine the maximum safe parallelism, parallelizable task combinations, and conflicting task combinations that are prohibited from parallelization under the current hardware resource conditions. The device dynamically configures the task parallel granularity, time slice allocation, and context switching timing to generate a scheduling order strategy and parallel execution strategy that adapt to the actual operating behavior of the current hardware. This can effectively reduce scheduling blocking, task starvation, and parallel conflict problems, and improve the overall task throughput and execution stability.

[0113] As can be seen from the above, the hardware behavior description method provided in this embodiment, in response to a retrieval request, extracts the current execution characteristics of the current task from the retrieval request; filters the execution characteristic description data to obtain a target execution characteristic description unit that matches the current execution characteristics; and controls the hardware to reuse the target execution characteristic description unit under the current task. After matching a suitable execution characteristic description unit to the current task, this embodiment can directly reuse the content in that execution characteristic description unit. That is, the execution characteristics at this time are no longer debugging results, but rather long-term usable hardware cognitive assets. Therefore, this embodiment not only effectively solves the problem of unreusable debugging results, but also eliminates the need for a complete hardware execution state perception process and repeated benchmark testing, thus improving work efficiency.

[0114] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0115] Corresponding to the hardware behavior description method described in the above embodiments, Figure 4 A schematic diagram of a hardware behavior description device according to an embodiment of this application is shown. For ease of explanation, only the parts related to the embodiment of this application are shown. (Refer to...) Figure 4 The hardware behavior description device 400 includes: a data acquisition unit 41, an abstract processing unit 42, and a data determination unit 43. Wherein: The acquisition unit 41 is used to acquire the execution behavior of the hardware under different operating conditions during the hardware operation process, and obtain a set of execution characteristic information of the hardware under the different operating conditions.

[0116] Abstraction processing unit 42 is used to abstract each execution characteristic information in each execution characteristic information set to obtain the execution characteristic description vector of the hardware under the different operating conditions; the abstraction processing includes the process of extracting core features from each execution characteristic information.

[0117] The data determination unit 43 is used to encapsulate and store each execution characteristic description vector to obtain execution characteristic description data of the hardware under multiple execution modes.

[0118] In one embodiment of this application, different operating conditions include: different operator types, different computing scales, and different resource occupancy conditions; each execution characteristic information includes: execution response characteristic information of computing units, storage access path and access behavior characteristic information, and operator scheduling and resource contention behavior characteristic information.

[0119] In one embodiment of this application, the abstract processing unit 42 specifically includes: a feature extraction unit, a normalization unit, and a splicing unit. Wherein: The feature extraction unit is used to extract features from each execution characteristic information set for each execution characteristic information set, thereby obtaining multiple corresponding feature information.

[0120] The normalization unit is used to normalize each feature information to obtain the feature vector corresponding to each execution characteristic information.

[0121] The concatenation unit is used to concatenate the various feature vectors to obtain the execution feature description vector corresponding to each execution feature information set.

[0122] In one embodiment of this application, the data determination unit 43 specifically includes: an encapsulation unit and a first storage unit. Wherein: The encapsulation unit is used to encapsulate each execution characteristic description vector to obtain each execution characteristic description unit; the execution characteristic description unit includes the subject of the corresponding execution characteristic description vector, the runtime condition label, and the applicable scope description.

[0123] The first storage unit is used to store each execution characteristic description unit to obtain execution characteristic description data.

[0124] In one embodiment of this application, the first storage unit specifically includes: a second storage unit.

[0125] The second storage unit is used to classify and store each execution characteristic description unit based on a preset operating condition dimension to obtain execution characteristic description data; the preset operating condition dimension includes at least one of operator type, computing scale, and resource usage conditions.

[0126] In one embodiment of this application, the hardware behavior description device 400 further includes: a feature extraction unit, a filtering unit, and a multiplexing unit. Wherein: The feature extraction unit is used to extract the current execution features of the current task from the retrieval request in response to the retrieval request.

[0127] The filtering unit is used to filter out target execution characteristic description units that match the current execution characteristics from the execution characteristic description data.

[0128] The multiplexing unit is used to control the execution characteristic description unit of the hardware multiplexing target under the current task.

[0129] In one embodiment of this application, the multiplexing unit specifically includes: a mapping method determination unit, and / or an allocation method determination unit, and / or an order determination unit. Wherein: The mapping method determination unit is used to determine the operator mapping method based on the target execution characteristic description unit.

[0130] The allocation method determination unit is used to determine the allocation method of the execution unit based on the target execution characteristic description unit.

[0131] The sequence determination unit is used to determine the scheduling order and parallel strategy based on the target execution characteristic description unit.

[0132] It should be noted that the information interaction and execution process between the above-mentioned devices / units are based on the same concept as the method embodiments of this application. For details on their specific functions and technical effects, please refer to the method embodiments section, and they will not be repeated here.

[0133] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0134] Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Figure 5As shown, the electronic device 5 of this embodiment includes: at least one processor 50 ( Figure 5 Only one is shown in the diagram), memory 51, and computer program 52 stored in said memory 51 and executable on said at least one processor 50, wherein said processor 50 executes said computer program 52 to implement the steps in any of the above hardware behavior description method embodiments.

[0135] The electronic device 5 may include, but is not limited to, a processor 50 and a memory 51. Those skilled in the art will understand that... Figure 5 This is merely an example of electronic device 5 and does not constitute a limitation on electronic device 5. It may include more or fewer components than shown in the figure, or combine certain components, or different components. For example, it may also include input / output devices, network access devices, etc.

[0136] The processor 50 may be a Central Processing Unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.

[0137] In some embodiments, the memory 51 may be an internal storage unit of the electronic device 5, such as the RAM of the electronic device 5. In other embodiments, the memory 51 may be an external storage device of the electronic device 5, such as a plug-in hard drive, Smart Media Card (SMC), Secure Digital (SD) card, or Flash Card equipped on the electronic device 5. Furthermore, the memory 51 may include both internal and external storage units of the electronic device 5. The memory 51 is used to store the operating system, applications, boot loader, data, and other programs, such as the program code of the computer program. The memory 51 can also be used to temporarily store data that has been output or will be output.

[0138] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps described in the various method embodiments above.

[0139] This application provides a computer program product that, when run on an electronic device, enables the electronic device to perform the steps described in the various method embodiments above.

[0140] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments of this application can be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include at least: any entity or device capable of carrying computer program code to an electronic device, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium. Examples include USB flash drives, portable hard drives, magnetic disks, or optical disks.

[0141] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0142] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A hardware behavior description method, characterized in that, include: During hardware operation, the execution behavior of the hardware under different operating conditions is collected to obtain a set of execution characteristic information of the hardware under different operating conditions; The execution characteristic information in each of the execution characteristic information sets is abstracted to obtain the execution characteristic description vector of the hardware under different operating conditions; the abstraction process includes the process of extracting core features from each of the execution characteristic information. Each of the execution characteristic description vectors is encapsulated and stored to obtain the execution characteristic description data of the hardware under multiple execution modes.

2. The hardware behavior description method as described in claim 1, characterized in that, The different operating conditions include: different operator types, different computing scales, and different resource occupancy conditions; each of the execution characteristic information includes: execution response characteristic information of computing units, storage access path and access behavior characteristic information, and operator scheduling and resource contention behavior characteristic information.

3. The hardware behavior description method as described in claim 1, characterized in that, The step of abstracting each execution characteristic information in each execution characteristic information set to obtain the execution characteristic description vector of the hardware under different operating conditions includes: For each set of execution characteristic information, feature extraction is performed on each execution characteristic information in each set of execution characteristic information to obtain multiple corresponding feature information; The feature information is normalized to obtain the feature vector corresponding to each of the execution characteristic information; The feature vectors are concatenated to obtain the execution characteristic description vector corresponding to each execution characteristic information set.

4. The hardware behavior description method as described in claim 1, characterized in that, The process of encapsulating and storing each of the execution characteristic description vectors to obtain execution characteristic description data of the hardware under multiple execution modes includes: Each execution characteristic description vector is encapsulated to obtain an execution characteristic description unit; the execution characteristic description unit includes the subject, runtime condition label, and applicable scope description of the corresponding execution characteristic description vector; Each of the execution characteristic description units is stored to obtain the execution characteristic description data.

5. The hardware behavior description method as described in claim 4, characterized in that, The step of storing each of the execution characteristic description units to obtain the execution characteristic description data includes: The execution characteristic description units are classified and stored based on a preset operating condition dimension to obtain the execution characteristic description data; the preset operating condition dimension includes at least one of operator type, computation scale, and resource consumption conditions.

6. The hardware behavior description method as described in any one of claims 1-5, characterized in that, After obtaining the execution characteristic description data of the hardware in multiple execution modes, the method further includes: In response to a retrieval request, the current execution characteristics of the current task are extracted from the retrieval request; Target execution characteristic description units that match the current execution characteristic are obtained by filtering the execution characteristic description data; Under the current task, the hardware is controlled to reuse the target execution characteristic description unit.

7. The hardware behavior description method as described in claim 6, characterized in that, The reuse of the target execution characteristic description unit includes: The operator mapping method is determined based on the target execution characteristic description unit; And / or, The execution unit allocation method is determined based on the target execution characteristic description unit; And / or, The scheduling order and parallel strategy are determined based on the target execution characteristic description unit.

8. A hardware behavior description device, characterized in that, include: The acquisition unit is used to acquire the execution behavior of the hardware under different operating conditions during hardware operation, and obtain a set of execution characteristic information of the hardware under different operating conditions. An abstract processing unit is used to abstract each execution characteristic information in each execution characteristic information set to obtain an execution characteristic description vector of the hardware under different operating conditions; the abstract processing includes the process of extracting core features from each execution characteristic information. The data determination unit is used to encapsulate and store each of the execution characteristic description vectors to obtain the execution characteristic description data of the hardware under multiple execution modes.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the hardware behavior description method as described in any one of claims 1 to 7.

10. A computer program product, characterized in that, It includes a computer program that, when run, implements the hardware behavior description method as described in any one of claims 1 to 7.

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