Data output method and device, equipment, storage medium and program product

Abstract

The present disclosure provides a data output method and device, equipment, storage medium and program product. The device comprises a data mapping module configured to: in the case that first return data of a target cache line request is received in a current input period, determine, from the first return data, second return data of a target sub-request included in the target cache line request according to identification information in the target cache line request; and output the second return data of the target sub-request through at least one output period according to an output data bit width of the data mapping module in one output period; wherein the output data bit width is less than a maximum return data length of a data access request supported by a system. According to embodiments of the present disclosure, hardware resource waste caused by an excessively large output data bit width of the data mapping module can be avoided.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a data output method and apparatus, electronic equipment, computer-readable storage medium, and computer program product. Background Technology

[0002] In computer architecture, especially in systems involving caching and memory access, when processing read-type data access requests, it is usually necessary to split the instruction data access request into multiple sub-requests according to the multiple access addresses contained in the data access request. In the data packing stage, the returned data read from the multiple sub-requests is organized according to a specific return format and returned to the sender who sent the data access request.

[0003] In the current data assembly stage, a data mapping module (data xbar) is typically used to output the return data read from multiple sub-requests in the data access request. To ensure that the hardware can flexibly route and combine return data from different sources and meet the return format requirements, the output data width of the data mapping module is usually set according to the number of multiple sub-requests and the maximum return data length of each sub-request. However, in practical applications, due to considerations of hardware area and power consumption, the actual output data width agreed upon between the data mapping module and the upstream module is often set to be small, and the actual return data length is often smaller than the output data width. If the output data width of the data mapping module is still set according to the maximum return data length, the output data width of the data mapping module will be designed to be too large in practical applications, resulting in a waste of hardware resources. Summary of the Invention

[0004] This disclosure provides a data output method and apparatus, an electronic device, a computer-readable storage medium, and a computer program product.

[0005] In a first aspect, this disclosure provides a data output device, including a data mapping module, the data mapping module being configured to: upon receiving first return data of a target cache line request in the current input cycle, determine second return data of a target sub-request included in the target cache line request from the first return data based on identification information in the target cache line request; wherein the target cache line request is at least one of a cache line request obtained by packaging multiple sub-requests of a data access request, the target sub-request is at least one of multiple sub-requests, and each cache line request includes at least one sub-request; and output the second return data of the target sub-request through at least one output cycle according to the output data bit width of the data mapping module in one output cycle; wherein the output data bit width is less than the maximum return data length of the data access request supported by the system.

[0006] Secondly, this disclosure provides a data output method applied to a data mapping module in a data output device. The method includes: upon receiving first return data of a target cache line request in the current input cycle, determining second return data of a target sub-request included in the target cache line request from the first return data based on identification information in the target cache line request; wherein the target cache line request is at least one of a cache line request obtained by packaging multiple sub-requests of a data access request, and the target sub-request is at least one of multiple sub-requests, with each cache line request including at least one sub-request; and outputting the second return data of the target sub-request through at least one output cycle based on the output data bit width of the data mapping module in one output cycle; wherein the output data bit width is less than the maximum return data length of a data access request supported by the system.

[0007] Thirdly, this disclosure provides an electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores one or more computer programs executable by the at least one processor, the one or more computer programs being executed by the at least one processor to enable the at least one processor to perform the data output method described above.

[0008] Fourthly, this disclosure provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the above-described data output method.

[0009] Fifthly, this disclosure provides a computer program product including computer-readable code, which, when executed in a processor of an electronic device, causes the processor in the electronic device to perform the aforementioned data output method.

[0010] The embodiments provided in this disclosure, upon receiving first return data of a target cache line request in the current input cycle, can determine second return data of a target sub-request from the first return data based on the identification information in the target cache line request, and output the second return data of the target sub-request through at least one output cycle according to the output data bit width of the data mapping module in one output cycle. Since the output data bit width is less than the maximum return data length of the data access request supported by the system, the second return data is output in cycles according to the output data bit width of the data mapping module. This ensures that the return data output by the data mapping module in each cycle matches the output data bit width, avoiding the waste of hardware resources caused by an excessively large output data bit width of the data mapping module.

[0011] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0012] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the embodiments of the present disclosure to explain the disclosure and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0013] Figure 1 This is a block diagram of a data output device provided in an embodiment of the present disclosure.

[0014] Figure 2 This is a schematic diagram of a data output device provided in an embodiment of the present disclosure.

[0015] Figure 3 This is a schematic diagram illustrating the determination of target sector data according to an embodiment of the present disclosure.

[0016] Figure 4 This is a schematic diagram of the routing of target sector data provided in an embodiment of this disclosure.

[0017] Figure 5 This is a flowchart illustrating the processing of a data output device when it is executed, as provided in an embodiment of this disclosure.

[0018] Figure 6 A flowchart of a data output method provided in an embodiment of this disclosure.

[0019] Figure 7 This is a block diagram of an electronic device provided in an embodiment of the present disclosure. Detailed Implementation

[0020] To enable those skilled in the art to better understand the technical solutions of this disclosure, exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments of this disclosure to aid understanding. These should be considered merely exemplary. Therefore, those skilled in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0021] Where there is no conflict, the various embodiments of this disclosure and the features thereof in the embodiments may be combined with each other.

[0022] As used herein, the term “and / or” includes any and all combinations of one or more related enumerated entries.

[0023] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “made of” are used in this specification, the presence of the stated feature, integral, step, operation, element, and / or component is specified, but the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof is not excluded. Words such as “connected” or “linked” are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect.

[0024] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined herein.

[0025] As mentioned above, the data assembly stage is typically implemented in hardware using a data mapping module. The input to this module is generally cached line data from N storage units (banks), with a total data width usually designed to be N × R bytes, where R is the size of the cached line data. Its output must support the data required by M sub-requests within the data access request, with a total output width typically designed to be M × the maximum return data length (MAX_REQ_LEN) for each sub-request. This design aims to ensure that the hardware can flexibly route and combine data from different sources to meet the requirements of the return format.

[0026] In actual hardware logic design, due to considerations of hardware area and power consumption, the actual output data bit width agreed upon between the data mapping module and the upstream module is often set to a relatively small value. Typically, the output data bit width is set to a fixed value, usually a positive power of 2. The maximum return data length is often less than the output data bit width, and the data request length of sub-requests within the data access request to be output is often less than the maximum return data length. Under this constraint, if the data width of the input and output ends of the data mapping module is still designed according to the theoretical maximum width, the data request length of the output data will be less than the output data bit width, resulting in a waste of hardware resources at the output end of the data mapping module. The allocation of hardware resources and the complexity of the backend implementation are closely related to the data width of the data mapping module; the larger the width, the more hardware resources are usually required, and the higher the complexity of the backend implementation. Therefore, in systems with limited output data bit width, continuing to use a full-width output design will result in a waste of hardware resources.

[0027] According to the data output device of this disclosure, based on the mask identifiers of multiple sub-requests in a data access request, the device can filter the second return data of sub-requests whose mask identifiers are valid from the first return data of the target cache line request. Within the limitation of the output data bit width of the data mapping module, the second return data is output through at least one output cycle. Since the output data bit width of the data mapping module is designed to be relatively small, the amount of data output during the output of the second return data is matched as closely as possible to the output data bit width of the data mapping module, thereby reducing hardware resource waste. In addition, embodiments of this disclosure can also filter target sector data with valid flag bits from the first return data based on the flag bits of multiple sector data in the first return data. By using a pre-set number of sector data that the data mapping module can output in one output cycle, the filtered target sector data is output through at least one output cycle. Since the number of sector data that the data mapping module can output in one output cycle is determined by the output data bit width of the data mapping module, the data length of the target sector data output in one output cycle is equal to or less than the output data bit width of the data mapping module. In other words, the input and output bit widths of the data mapping module are made as equal as possible, further reducing the waste of hardware resources caused by excessively large input bit widths.

[0028] Figure 1 This is a block diagram of a data output device provided according to an embodiment of the present disclosure. See also... Figure 1 The device includes a data mapping module, which is configured to:

[0029] When the first return data of the target cache line request is received in the current input cycle, the second return data of the target sub-request included in the target cache line request is determined from the first return data according to the identification information in the target cache line request; wherein, the target cache line request is at least one of the cache line requests obtained by packaging multiple sub-requests of the data access request, the target sub-request is at least one of the multiple sub-requests, and each cache line request includes at least one sub-request.

[0030] Based on the output data bit width of the data mapping module in one output cycle, the second return data of the target sub-request is output through at least one output cycle; wherein, the output data bit width is less than the maximum return data length of the data access request supported by the system.

[0031] The data output device provided in this disclosure can be deployed and applied to processing devices (such as CPUs, GPUs, etc.). In practical applications, to reduce the number of accesses to system memory, a cache is usually set up to temporarily store data. When a data access request is received, data is first retrieved from the cache. If the data is not found in the cache, it is then retrieved from memory. Since a data access request often contains multiple different access addresses, before accessing the cache, the data access request is usually split into multiple sub-requests according to different access addresses. Each sub-request retrieves data from the cache according to its corresponding access address, and the retrieved data is assembled and returned to the sender of the data access request.

[0032] The current input cycle refers to the cycle in which the data mapping module receives the first returned data; the output cycle refers to the cycle in which the data mapping module outputs the second returned data. The target cache line request refers to the request received by the data mapping module in the current input cycle, which is a package of at least one sub-request from the data access request; that is, the target cache line request includes at least one sub-request. The first returned data is the data retrieved from the cache in response to at least one sub-request. Identification information is used to characterize whether the sub-requests in the target cache line request are valid, or whether the data in the first returned data is valid. The second returned data refers to the data determined from the first returned data that can be output by the data mapping module. The output data bit width characterizes the data width output by the data mapping module in one cycle.

[0033] Specifically, when the data mapping module receives the first return data of the target cache line request in the current input cycle, it can obtain the identification information in the target cache line request and determine the second return data of the target sub-request included in the target cache line request from the first return data based on the identification information. Then, according to the preset output data bit width of the data mapping module, the determined second return data is output through at least one output cycle.

[0034] Specifically, the output data width of the data mapping module is smaller than the maximum return data length (M×MAX_REQ_LEN) supported by the system for data access requests. MAX_REQ_LEN represents the maximum request length (i.e., the length of the return data of a single sub-request) supported by the system, and M represents the number of sub-requests in a data access request. This approach reduces bandwidth waste on the output interface of the data mapping module, decreases the hardware resources occupied by the data mapping module, and improves chip area utilization.

[0035] See Figure 2 , Figure 2 This is a schematic diagram of a data output device provided in an embodiment of the present disclosure, such as... Figure 2 As shown, the sender sends multiple sub-requests from the data access request to the merging module of the data output device. The merging module merges the multiple sub-requests, specifically merging sub-requests that access the same access address, or merging multiple sub-requests that fall within the address range of the same cache line into a single cache line request. By merging multiple sub-requests, the number of requests sent to memory can be reduced, thus decreasing the number of memory accesses. After merging multiple sub-requests, the merging module sends the merged cache line request to the cache, so that the cache line request can retrieve data from the cache according to the access address. If the cache does not have the data required by the cache line request, the cache sends the cache line request to memory, so that the cache line request can retrieve data from memory. The retrieved return data is sent to the data mapping module in the data assembly stage. At this time, the cache sends the return data to the data mapping module. In the data assembly stage, the data mapping module assembles the return data of multiple cache line requests, and after the data assembly is completed, the return data is output to the sender. The data output device provided in this embodiment is applied to applications such as... Figure 2 The following section provides a detailed explanation of the data output device during the data assembly stage.

[0036] In this embodiment, the data mapping module includes a first mapping module and / or a second mapping module. Both the first and second mapping modules can map and output data, but their output methods for the received return data differ. Specifically, the first mapping module can determine the second return data of the target sub-request based on the identification information of the received first return data and output the second return data; the second mapping module can determine the second return data of the target sub-request based on the identification information of the sub-request in the received target cache line request and output the second return data. In practical applications, the data mapping module can be only the first mapping module, or only the second mapping module, or it can be composed of both the first and second mapping modules. The type and composition of the data mapping module are determined according to the actual application situation, and this disclosure does not limit them.

[0037] The following explanation addresses the case where the data mapping module is the first mapping module.

[0038] In one specific embodiment provided in this disclosure, the first returned data is cache line data corresponding to the target cache line request, each cache line data includes multiple sector data, and the identification information includes flag bits of multiple sector data; the step of determining the second returned data of the target sub-request included in the target cache line request from the first returned data based on the identification information in the target cache line request includes: filtering target sector data from the multiple sector data corresponding to the target cache line request based on the flag bits of each sector data; and determining the second returned data based on the target sector data.

[0039] In practical applications, caches are typically divided into multiple storage units (banks), each storage unit is further divided into multiple cache lines (cachelines), and each cache line includes multiple sectors. Therefore, the first returned data obtained from multiple sub-requests within a single data access request is actually cache line data from multiple storage units, with each cache line containing multiple sectors. Based on this, the identification information in the target cache line request includes flags for multiple sectors. Each sector's flag indicates whether it is valid and is then output. The target sector data refers to at least one valid sector among the multiple sectors corresponding to the target cache line request.

[0040] Specifically, based on the flag bit of each sector data, valid target sector data is filtered from the multiple sector data corresponding to the target cache line request. Since a sector may contain the return data of sub-requests in different data access requests, after determining the target sector data, it is also necessary to further determine the return data of the target sub-request in the data access request based on the target sector data, that is, to determine the second return data.

[0041] This embodiment of the present disclosure filters valid second returned data belonging to the target sub-request in the data access request from multiple sector data corresponding to the target cache line request based on the flag bits of these multiple sector data, thereby improving the accuracy of determining the second returned data.

[0042] As described above, the data mapping module (i.e., the first mapping module) is pre-set with a data output bit width in this embodiment. Therefore, the number of sector data that the data mapping module can output in one output cycle is limited. When filtering target sector data, it is also necessary to filter according to the number of sector data that the data mapping module can output in one output cycle.

[0043] In one specific embodiment provided in this disclosure, the step of filtering target sector data from multiple sector data corresponding to the target cache line request based on the flag bit of each sector data includes: filtering a second number of target sector data with valid flag bits from the multiple sector data based on a first number of sector data output by the data mapping module in each output cycle, wherein the second number is less than or equal to the first number.

[0044] After receiving the first returned data of the target cache line request, i.e. multiple cache line data, since the data size of multiple cache line data may be greater than the output data bit width of the data mapping module, in order to make the data size output by the data mapping module in one output cycle reach the output data bit width as much as possible, the determined second returned data can be divided and output through at least one cycle.

[0045] Specifically, based on the first number of sector data that the data mapping module can output in each cycle, the corresponding number of target sector data is selected from the second returned data of the target sub-request. However, in the last cycle of the data output by the data mapping module, there may be a situation where the number of remaining sector data is insufficient, that is, the number of target sector data to be output is less than the first number. In this case, the remaining sector data can be directly determined as the target sector data.

[0046] Furthermore, as mentioned above, each sector data is assigned a corresponding flag bit. The value of the flag bit indicates whether the sector data is valid. A valid value (e.g., 1) indicates that the sector data is valid, and an invalid value (e.g., 0) indicates that the sector data is invalid. In practical applications, invalid sector data may exist in the cache line data. These invalid sector data cannot be used as output data of the data mapping module. Therefore, filtering a second number of target sector data from the multiple sector data included in the cache line data is actually filtering from valid sector data to avoid outputting invalid sector data. When filtering the second return data from the first return data, the sector data with a valid flag bit in the first return data is filtered. If the number of sectors with a valid flag bit is less than or equal to the first number, these sectors are all determined as target sector data; if the number of sectors with a valid flag bit is greater than the first number, a second number of sectors are selected from the multiple sector data to determine as target sector data. When filtering target sector data, you can filter them sequentially according to the order of each sector data in the cache line.

[0047] See Figure 3 , Figure 3 This is a schematic diagram illustrating the determination of target sector data provided in an embodiment of the present disclosure, such as... Figure 3 As shown, the first returned data of the target cache line request includes four cache line data: cache line data for storage unit 0, cache line data for storage unit 1, cache line data for storage unit 2, and cache line data for storage unit 3. Each cache line data includes four sector data: sector data 0, sector data 1, sector data 2, and sector data 3. Taking the number of sector data that the data mapping module can output in each cycle as an example, four target sector data are selected from the 16 sector data included in the four cache line data. For example, from sector data 0 of storage unit 0, sector data 1 of storage unit 0, ..., sector data 2 of storage unit 3, sector data 3 of storage unit 3, four target sector data with valid flag bits are selected, namely target sector data 0, target sector data 1, target sector data 2, and target sector data 3.

[0048] In the first returned data of the target cache line request, the valid target sector data is filtered out according to the sector data flag bit and the first data. On the basis of ensuring that the data length of the second returned data output by the data mapping module is as consistent as possible with the output data bit width, the second returned data is further guaranteed to be valid data, so as to realize the periodic output of valid sector data.

[0049] In this embodiment of the disclosure, the first quantity is determined based on the output data bit width of the data mapping module and a first ratio, wherein the first ratio is determined based on the ratio of the size of each cache line data to the number of sector data included in each cache line data.

[0050] The first ratio refers to the ratio of the size of the cache line data to the number of sectors included in the cache line data, used to characterize the size of each sector data. The first quantity refers to the ratio of the output data bit width to the first ratio, used to characterize the amount of sector data that the data mapping module can output in each cycle.

[0051] Specifically, a first ratio is determined between the size of the cache line data and the number of sectors included in the cache line data to determine the size of each sector data. Furthermore, a ratio between the output data bit width and the first ratio is determined to determine the number of sectors data output by the data mapping module in each cycle. Further, when both the size of the cache line data and the number of sectors included in the cache line data are positive integer powers of 2, the determined first number is a positive integer. The determination of the first number can be specifically referred to in Formula 1 below:

[0052] main_data_xbar_input_sector_num=(return data width) / (R / S) Formula 1.

[0053] Wherein, main_data_xbar_input_sector_num is the first quantity, return data width is the output data bit width of the data mapping module, R is the size of the cache line data, and S is the number of sectors included in the cache line data.

[0054] If the size of the cache line data and the number of sectors included in the cache line data are not positive integer powers of 2, the determined first quantity may not be a positive integer. In this case, the first quantity can be rounded according to the actual application situation, and the rounded value can be determined as the first quantity.

[0055] For example, if the output data width is 128 bytes, the cache line data size is 128 bytes, the cache line data includes 4 sectors, and the first return data of the target cache line request includes 4 cache lines, then the first number is 128 / (128 / 4) = 4. In this case, the input to the data mapping module, i.e., the first return data of the target cache line request, has a data length of 128 × 4 = 512 bytes, and includes a total of 4 × 4 = 16 sectors. Therefore, the output data length of the data mapping module is (128 / 4) × 4 = 128 bytes.

[0056] In this embodiment of the disclosure, the size of each sector data is determined based on the size of the cache line data and the number of sector data included in each cache line data. Furthermore, based on the output data bit width and the size of each sector data, the number of target sector data that the data mapping module can output in each output cycle is determined. By controlling the number of target sector data output by the data mapping module, the data length of the output data of the data mapping module is controlled so as to maximize the output data bit width and avoid waste of hardware resources.

[0057] Furthermore, after determining the target sector data, each target sector data needs to be routed to its corresponding output sector channel to form the second return data for each output cycle based on the target sector data, and the second return data is then output.

[0058] Based on this, in a specific embodiment provided in this disclosure, the output side of the data mapping module includes a first number of sector channels. Determining the second return data based on the target sector data includes: determining the target sector channels corresponding to the second number of target sector data in the first number of sector channels; routing the second number of target sector data to their corresponding target sector channels; and determining the second return data of the data mapping module in each output cycle. Outputting the second return data of the target sub-request through at least one output cycle based on the output data bit width of the data mapping module in one output cycle includes: outputting the corresponding second return data in each output cycle.

[0059] In this embodiment of the disclosure, the output side of the data mapping module includes multiple sector channels. The sector channels are used to output the determined second return data. The number of sector channels is a first number. In practical applications, after the first number is determined in advance, the first number can be directly set to the data mapping module. Thus, when the data is encapsulated and output based on the data mapping module, the second return data can be output according to the first number.

[0060] Among them, the target sector channel refers to the sector channel used to output target sector data among multiple sector channels, and each target sector data can be assigned a corresponding target sector channel.

[0061] Specifically, after determining the second number of target sector channels, among the first number of sector channels on the output side of the data mapping module, the target sector channel corresponding to each target sector data is determined, and each target sector data is routed to its corresponding target sector channel, thereby constituting the second return data to be output by the data mapping module in one output cycle, and the second return data is output in the corresponding output cycle. In the process of determining and routing the target sector channel corresponding to each target sector data, the channels can be determined and routed sequentially according to the return order among multiple cache line data. It should be noted that the data mapping module provided in this embodiment is a non-fully interconnected mapping module.

[0062] See Figure 4 , Figure 4 This is a schematic diagram of the routing of target sector data provided in an embodiment of the present disclosure. Figure 4 Continue Figure 3 Examples are provided to illustrate this, such as Figure 4 As shown, the input side of the data mapping module receives four cache lines of data: cache lines from storage unit 0, storage unit 1, storage unit 2, and storage unit 3. Each cache line includes four sectors: sector 0, sector 1, sector 2, and sector 3. The output side of the data mapping module includes four sector channels: sector channel 0, sector channel 1, sector channel 2, and sector channel 3. The data mapping module provided in this embodiment sets a fixed sector channel for each sector of the returned first cache line, ensuring that each sector in the first cache line can only be routed to a fixed sector channel. Therefore, in... Figure 4 In the context of cache line data for storage unit 0, sector data 0 can only be routed to sector channel 0, sector data 1 can only be routed to sector channel 0 or sector channel 1, sector data 2 can only be routed to sector channel 0, sector channel 1, or sector channel 2, and sector data 3 can be routed to any one of sector channel 0, sector channel 1, sector channel 2, and sector channel 3. For subsequent returned cache line data, each sector data can be routed to any one of the four sector channels on the output side.

[0063] The embodiments disclosed herein design the data mapping module as a non-fully interconnected mapping module, which further reduces the area of ​​the data mapping module while ensuring that each sector data in the second returned data is routed to the corresponding sector channel for output.

[0064] The following explanation addresses the case where the data mapping module is the second mapping module.

[0065] In one specific embodiment provided in this disclosure, the identification information includes the mask identifiers of the plurality of sub-requests; the step of determining the second return data of the target sub-request included in the target cache line request from the first return data based on the identification information in the target cache line request includes: filtering sub-requests with mask identifiers that are valid values ​​as the target sub-requests based on the mask identifiers of the plurality of sub-requests; and determining the second return data of the target sub-request from the first return data based on the sub-request index of the target sub-request.

[0066] When the data mapping module is the second mapping module, it can determine the second return data of the target sub-request from the first return data based on the identification information of multiple sub-requests in the target cache line request. In practical applications, a cache line request carries mask identifiers of its multiple sub-requests. The mask identifier of each sub-request is used to characterize whether the sub-request is valid or has been returned. The mask identifier includes valid and invalid values; a valid value can be 1, and an invalid value can be 0, etc. The sub-request index is used to uniquely identify each sub-request. For example, for sub-request 0, 0 is the sub-request index.

[0067] Specifically, based on the mask identifiers of multiple sub-requests in the target cache line request, target sub-requests with mask identifiers of valid values ​​(e.g., 1) are filtered out from the multiple sub-requests, and the second return data of the target sub-request is determined from the first return data of the target cache line request based on the sub-request index of the target sub-request.

[0068] For example, the mask identifiers of multiple sub-requests in the target cache line request are [0:0], [1:1], [2:0], ..., [M-1:0], where M is the number of sub-requests, and the two identifiers in the square brackets from left to right are the sub-request index and the mask identifier, respectively. That is, the mask identifier of sub-request 0 is 0, the mask identifier of sub-request 1 is 1, the mask identifier of sub-request 2 is 0, ..., the mask identifier of sub-request M-1 is 0. If, among these M-1 sub-requests, only sub-request 1, sub-request 4, sub-request 5, sub-request 17, and sub-request 20 have a mask identifier of 1, then in the first returned data, the returned data of sub-request 1, sub-request 4, sub-request 5, sub-request 17, and sub-request 20 will be determined as the second returned data.

[0069] This embodiment of the disclosure can quickly identify a valid target sub-request among multiple sub-requests by using the mask identifier of multiple sub-requests in the cache line request, and determine the second return data of the target sub-request from the first return data based on the sub-request index of the target sub-request, thereby improving the efficiency of determining the second return data from the first return data.

[0070] After determining the second return data from the first return data, the second return data is output in at least one output cycle according to the output data bit width of the data mapping module.

[0071] Based on this, in a specific embodiment provided in this disclosure, the step of outputting the second return data of the target sub-request through at least one output cycle according to the output data bit width of the data mapping module in one output cycle includes: in the current output cycle, if there is a target sub-request in the i-th sub-request group, outputting the second return data of the target sub-request in the i-th sub-request group through the current output cycle, where i is an integer greater than or equal to 1; if there is no target sub-request in the i-th sub-request group and there is a target sub-request in the (i+j)-th sub-request group, outputting the second return data of the target sub-request in the (i+j)-th sub-request group through the current output cycle, where j is an integer greater than or equal to 1; wherein, the data mapping module presets the sub-request groups of the plurality of sub-requests, and the sub-request groups are determined according to the return data length of the sub-requests, the number of requests of the plurality of sub-requests, and the output data bit width.

[0072] In this embodiment of the disclosure, multiple sub-requests of the data access request are grouped to obtain multiple sub-request groups, so as to output the determined second return data through a corresponding number of output cycles.

[0073] As mentioned above, the sub-requests included in the target cache line request may contain invalid sub-requests. Therefore, for multiple sub-request groups in the data access request, there may be sub-request groups that do not include the target sub-request. Specifically, in the current output cycle, if the target sub-request exists in the i-th sub-request group, the second return data of the target sub-request is output in the current output cycle; if the target sub-request does not exist in the i-th sub-request group, it means that there is no return data to be output in the i-th sub-request group, so the output of the i-th sub-request group is skipped until the target sub-request exists in the (i+j)-th sub-request group, at which point the second return data of the target sub-request in the (i+j)-th sub-request group is output in the current output cycle.

[0074] In the embodiments of this disclosure, when outputting the second return data of the target sub-request according to the sub-request group, it determines whether the corresponding sub-request group needs to be output in the output cycle by judging whether there is a target sub-request in each sub-request group, thereby avoiding the output of invalid sub-requests and improving the accuracy and output efficiency of the second return data of the target sub-request.

[0075] Furthermore, the upper limit of the output period for multiple sub-request groups in the data access request is determined based on the output data bit width of the data mapping module. In this embodiment, the number of multiple sub-request groups in the data access request and the upper limit of the output period are determined in advance based on the output data bit width of the data mapping module, and the data mapping module is configured so that in actual application, the data mapping module outputs the second return data of the target sub-request in stages according to the determined sub-request groups and the upper limit of the output period.

[0076] Specifically, based on the pre-set output data bit width of the data mapping module and the number of requests for multiple sub-requests, the amount of data that the data mapping module can output for each sub-request in one cycle is determined, i.e., the baseline request length. This baseline request length is then used to determine the maximum number of output cycles required to output the return data from multiple sub-requests in subsequent processes, i.e., the upper limit of the output cycle, which is also the number of sub-request groups. The baseline request length characterizes the amount of data that the data mapping module can output for each sub-request in one output cycle.

[0077] In this embodiment of the disclosure, after obtaining the first returned data of the target cache line request, the number of sub-requests in its data access request is determined, and the ratio of the output data bit width to the number of requests is determined. This ratio is then used as the baseline request length, as shown in Formula 2 below:

[0078] base_req_length=(return data width) / M Formula 2

[0079] Where base_req_length is the base request length, return data width is the output data bit width, and M is the number of sub-requests in a data access request.

[0080] In this embodiment of the disclosure, the ratio between the output data bit width of the data mapping module and the number of requests of the sub-requests is determined, and the determined ratio is used as the base request length. This is used to measure the number of output cycles required to output the second return data of multiple target sub-requests, so that the actual amount of second return data output is as close as possible to the output data bit width, thereby improving the utilization of hardware resources.

[0081] After determining the baseline request length, the data request length of the second return data carried by multiple sub-requests can be further determined. Based on the data request length and the baseline request length, the number of output cycles required for the data mapping module to output the second return data of multiple sub-requests can be determined; that is, how many output cycles the data mapping module needs to output the second return data of multiple sub-requests. Here, the data request length is used to characterize the amount of data in the second return data of each sub-request.

[0082] In this embodiment of the disclosure, since the data request length of each sub-request is the same, the data request length of any sub-request can be compared with the base request length. If it is determined that the data request length is less than or equal to the base request length, the total data request length of multiple sub-requests can be determined to be less than or equal to the output data bit width of the data mapping module. That is, if request length (data request length of a single sub-request) ≤ base_req_length, then M×(request length) ≤ return data width, indicating that the data mapping module can output all the second return data of multiple sub-requests to the sender in one output cycle. At this time, the number of output cycles is 1, and the number of sub-request groups is also 1. If the data request length of a single sub-request is greater than the base request length, then the total data request length of multiple sub-requests is greater than the output data width of the data mapping module. That is, if requestlength > base_req_length, then M × request length > return data width. This indicates that the data mapping module cannot output all the second return data of multiple sub-requests to the sender in one output cycle. In this case, the number of output cycles is greater than or equal to 1, and the number of sub-request groups is greater than 1. Therefore, it is necessary to further determine the number of output cycles and the number of sub-request groups. Determine the ratio of the data request length to the baseline request length, and then determine the number of output cycles based on this ratio. Specifically, if both the data request length and the request quantity are positive integer powers of 2, the determined number of output cycles will be a positive integer, and the ratio of the data request length to the baseline request length can be used as the number of output cycles. If either the data request length or the request quantity is not a positive integer power of 2, the determined number of output cycles may not be a positive integer. In this case, the ratio of the data request length to the baseline request length can be rounded according to the actual application, and the rounded value can be used as the number of output cycles.

[0083] For example, if the output data width of the data mapping module is 128 bytes, the number of sub-requests is 32, and the maximum return data length of a single sub-request is 16 bytes (the data request length of each sub-request must be less than or equal to the maximum return data length), then the base request length can be determined to be 128 / 32 = 4 bytes. When the data request length of a single sub-request is 1, 2, or 4 bytes, it can be determined that the data request length of a single sub-request is less than or equal to the base request length. In this case, the data mapping module can output all the second return data of these 32 sub-requests to the sender in one output cycle, and the number of output cycles is 1. When the data request length of a single sub-request is 8 bytes, it can be determined that the data request length of a single sub-request is greater than the base request length. In this case, the data mapping module cannot output all the second return data of these 32 sub-requests to the sender in one output cycle. Therefore, the number of output cycles is further determined to be 8 / 4 = 2, meaning that the data mapping module may need to output the second return data of these 32 sub-requests to the sender in 2 output cycles. When the data request length of a single sub-request is 16 bytes, it can be determined that the data request length of a single sub-request is greater than the base request length. In this case, the data mapping module also cannot output all the second return data of these 32 sub-requests to the sender in one output cycle. The number of output cycles is determined to be 16 / 4 = 4, meaning that the data mapping module needs to output the second return data of these 32 sub-requests to the sender in 4 output cycles.

[0084] In this embodiment of the disclosure, after determining the baseline request length, the data request length of each sub-request is compared with the baseline request length, and the number of output cycles required for the data mapping module to output the second return data is further determined based on the comparison result. This enables the output of the second return data of multiple sub-requests in a cycle-by-cycle manner, so that the length of the output second return data during the output process is as close as possible to the output data bit width, which is beneficial to improving the utilization of hardware resources.

[0085] Furthermore, after determining the number of output cycles required for the data mapping module to output the second return data, each sub-request can be mapped to a different output cycle according to the execution order of the sub-requests, thereby determining the output cycle corresponding to each sub-request, and mapping the second return data of each sub-request to the corresponding output cycle, so that the second return data of the sub-request can be output in the corresponding output cycle.

[0086] Continuing with the previous example, when the data request lengths are 1, 2, and 4 bytes respectively, the number of output cycles required for the data mapping module to output the second return data is 1. Therefore, the output cycles corresponding to all 32 sub-requests are the same cycle, and the second return data for all 32 sub-requests is output within that cycle. When the data request length is 8 bytes, the number of output cycles required for the data mapping module to output the second return data is 2. The output cycles for sub-requests 0 to 15 are determined as the first output cycle, and the output cycles for sub-requests 16 to 31 are determined as the second output cycle. Based on this, the output of the data mapping module in the first output cycle is mapped to the second return data of sub-requests 0 to 15, and the output of the second output cycle is mapped to the second return data of sub-requests 16 to 31. The second return data for sub-requests 0 to 15 is output in the first output cycle, and the second return data for sub-requests 16 to 31 is output in the second output cycle. When the data request length is 16 bytes, the data mapping module outputs the second... The required number of output cycles for returning data is 4. The output cycles for sub-requests 0 to 7 are determined as the first output cycle, the output cycles for sub-requests 8 to 15 as the second output cycle, the output cycles for sub-requests 16 to 23 as the third output cycle, and the output cycles for sub-requests 24 to 31 as the fourth output cycle. Based on this, the output of the data mapping module in the first output cycle is mapped to the second returned data for sub-requests 0 to 7, the output of the second output cycle is mapped to the second returned data for sub-requests 8 to 15, the output of the third output cycle is mapped to the second returned data for sub-requests 16 to 23, and the output of the fourth output cycle is mapped to the second returned data for sub-requests 24 to 31. The second returned data for sub-requests 0 to 7 is output in the first output cycle, the second returned data for sub-requests 8 to 15 is output in the second output cycle, the second returned data for sub-requests 16 to 23 is output in the third output cycle, and the second returned data for sub-requests 24 to 31 is output in the fourth output cycle.

[0087] It should be noted that the number of output cycles determined above is the upper limit of the output cycle, that is, the maximum number of cycles that the data mapping module can use to output the second return data. The actual number of output cycles used in actual applications needs to be determined according to the actual application situation.

[0088] Continuing with the previous example, when the data request length is 16 bytes, the data mapping module requires 4 output cycles to output the second return data. In this case, the output cycles for sub-requests 0 to 7 are the first output cycle, those for sub-requests 8 to 15 are the second, those for sub-requests 16 to 23 are the third, and those for sub-requests 24 to 31 are the fourth. If the data mapping module determines that the second return data only corresponds to sub-requests 1, 4, 5, 17, and 20, since there are no corresponding sub-requests 8 to 15 and 24 to 31 in the second return data, it is determined that there is no corresponding second return data to output in the second and fourth output cycles. Therefore, during data mapping output, the data mapping module only needs two output cycles to output the second return data.

[0089] In this embodiment of the disclosure, the second return data of multiple sub-requests can be mapped to the corresponding output cycles according to the determined number of output cycles. This allows the data mapping module to output the second return data carried by the sub-request in the corresponding output cycle, thereby realizing the output of the second return data in multiple cycles and improving the utilization of hardware resources.

[0090] Furthermore, as described above, the data mapping module may also include a first mapping module and a second mapping module. In this case, the first mapping module performs the operation of determining the second return data from the first return data, and inputs the determined second return data into the second mapping module, which then outputs the second return data through at least one output cycle.

[0091] In a specific embodiment provided in this disclosure, the data mapping module includes a first mapping module and a second mapping module. The first returned data is cache line data corresponding to the target cache line request. Each cache line data includes multiple sector data, and the identification information includes flag bits of the multiple sector data. The step of determining the second returned data of the target sub-request included in the target cache line request from the first returned data based on the identification information in the target cache line request includes: filtering target sector data from the multiple sector data corresponding to the target cache line request by the first mapping module according to the flag bits of each sector data; determining the second returned data of the second mapping module in each output cycle based on the target sector data; and outputting the second returned data of the target sub-request in at least one output cycle according to the output data bit width of the data mapping module in one output cycle includes: outputting the corresponding second returned data in each output cycle by the second mapping module.

[0092] The operation of the first mapping module to determine the second return data from the first return data, and the implementation of the second mapping module to output the second return data through at least one output cycle are the same as described above. For specific implementation methods, please refer to the above content. This disclosure will not repeat them here.

[0093] This embodiment of the disclosure implements the following: when the first return data of a target cache line request is received in the current input cycle, the second return data of the target sub-request is determined from the first return data based on the identification information in the target cache line request. Then, based on the output data bit width of the data mapping module in one output cycle, the second return data of the target sub-request is output in at least one output cycle. Since the output data bit width is less than the maximum return data length of the data access request supported by the system, the second return data is output in cycles according to the output data bit width of the data mapping module. This ensures that the return data output by the data mapping module in each cycle matches the output data bit width as closely as possible, avoiding the waste of hardware resources caused by an excessively large output data bit width of the data mapping module.

[0094] The following is in conjunction with the appendix Figure 5 Taking the data mapping module, which includes a first mapping module and a second mapping module, as an example, the data output device provided in the embodiments of this disclosure will be further explained and described. Figure 5 A flowchart illustrating the processing of a data output device as provided in this embodiment of the present disclosure includes the following steps:

[0095] Step 502: Upon receiving the first return data of the target cache line request in the current input cycle, the first mapping module determines the number of target sector data to be used to input the second mapping module.

[0096] Specifically, the first returned data includes multiple cache line data, each cache line data includes multiple sector data, a first ratio is determined between the size of the cache line data and the number of sector data included in each cache line data, and the ratio between the output data bit width of the second mapping module and the first ratio is further determined, that is, the number of target sector data used to input the first mapping module.

[0097] For example, the first returned data of the target cache line request includes 4 cache line data, each cache line data includes 4 sectors, the output data bit width is 128 bytes, and the size of the cache line data is 128 bytes. It can be determined that the number of target sector data used to input the second mapping module is 128 / (128 / 4) = 4.

[0098] Step 504: Filter the corresponding number of target sector data from the first returned data and input the target sector data into the second mapping module.

[0099] Specifically, from the multiple sectors included in multiple cache lines, valid sectors with valid flag values ​​are determined. If the number of valid sectors is less than or equal to the number of target sectors determined for input to the second mapping module, all valid sectors are directly designated as target sectors. If the number of valid sectors exceeds the number of target sectors determined for input to the second mapping module, a corresponding number of target sectors are sequentially selected from the multiple valid sectors. The selected target sectors are the second return data that the first mapping module needs to input to the second mapping module.

[0100] Using the previous example, we can determine that the number of sector data included in the first returned data is 4×4=16. Assuming that all 16 sector data are valid sector data, we need to select 4 target valid sector data from these 16 valid sector data in turn. In other words, these 16 valid sector data will be divided into 4 cycles and input into the second mapping module respectively.

[0101] Step 506: Upon receiving the second return data input from the first mapping module, the second mapping module outputs the corresponding second return data in each output cycle.

[0102] Specifically, in each output cycle, the second return data of each target sub-request is mapped to the corresponding output cycle, and the second return data of the target sub-request is output in the corresponding output cycle.

[0103] This embodiment of the disclosure implements a method whereby the first mapping module preprocesses the first returned data, ensuring that the length of the preprocessed second returned data in each output cycle is equal to the output data bit width of the second mapping module. This achieves equal input and output bit widths for the second mapping module, and the second returned data is input to the second mapping module in cycles. This reduces hardware resource waste caused by excessively large input bit widths. Furthermore, by outputting the second returned data in cycles according to at least one output cycle, the amount of second returned data output in each output cycle is matched as closely as possible to the output data bit width, further reducing hardware resource waste.

[0104] It is understood that the configuration steps of the various embodiments of the apparatus mentioned in this disclosure can be combined with each other to form combined embodiments without violating the principle and logic. Due to space limitations, this disclosure will not elaborate further. Those skilled in the art will understand that in the apparatus of the specific implementation, the specific execution order of each configuration step should be determined by its function and possible internal logic.

[0105] According to an embodiment of this disclosure, a data output method is also provided, which is applied to the data mapping module in the above-described data output device.

[0106] Figure 6 A flowchart illustrating a data output method provided in an embodiment of this disclosure. See also... Figure 6 The method specifically includes the following steps:

[0107] Step 602: If the first return data of the target cache line request is received in the current input cycle, determine the second return data of the target sub-request included in the target cache line request from the first return data according to the identification information in the target cache line request.

[0108] The target cache line request is at least one of the cache line requests obtained by packaging multiple sub-requests of the data access request. The target sub-request is at least one of the multiple sub-requests, and each cache line request includes at least one sub-request.

[0109] Step 604: Based on the output data bit width of the data mapping module in one output cycle, output the second return data of the target sub-request through at least one output cycle; wherein the output data bit width is less than the maximum return data length of the data access request supported by the system.

[0110] The steps of the data output method can be found in the configuration of the data mapping module in the above-mentioned data output device, and will not be repeated here.

[0111] The embodiments disclosed herein achieve the following: by presetting the output data bit width of the data mapping module, the returned data output by the data mapping module in each cycle is matched as closely as possible to the output data bit width, thereby avoiding the waste of hardware resources caused by an excessively large output data bit width of the data mapping module.

[0112] In addition, this disclosure also provides electronic devices and computer-readable storage media, all of which can be used to implement the data output method provided in this disclosure. The corresponding technical solutions and descriptions are described in the corresponding descriptions in the method section, and will not be repeated here.

[0113] Figure 7 This is a block diagram of an electronic device provided in an embodiment of the present disclosure.

[0114] See Figure 7 This disclosure provides an electronic device 700, which includes: at least one processor 701; at least one memory 702; and one or more I / O interfaces 703 connected between the processor 701 and the memory 702; wherein the memory 702 stores one or more computer programs that can be executed by the at least one processor 701, and the one or more computer programs are executed by the at least one processor 701 to enable the at least one processor 701 to perform the above-described data output method.

[0115] This disclosure also provides a computer-readable storage medium storing a computer program thereon, wherein the computer program, when executed by a processor, implements the above-described data output method. The computer-readable storage medium may be volatile or non-volatile.

[0116] This disclosure also provides a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code, wherein when the computer-readable code is run in a processor of an electronic device, the processor in the electronic device executes the above-described data output method.

[0117] Those skilled in the art will understand that all or some of the steps, systems, and apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software can be distributed on a computer-readable storage medium, which may include computer storage media (or non-transitory media) and communication media (or transient media).

[0118] As is known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, such as computer-readable program instructions, data structures, program modules, or other data. Computer storage media includes, but is not limited to, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), static random access memory (SRAM), flash memory or other memory technologies, portable compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, it is known to those skilled in the art that communication media typically contain computer-readable program instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0119] The computer-readable program instructions described herein can be downloaded from computer-readable storage media to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage media in the respective computing / processing device.

[0120] Computer program instructions used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), is personalized by utilizing the status information of the computer-readable program instructions to implement various aspects of this disclosure.

[0121] The computer program product described herein can be implemented specifically through hardware, software, or a combination thereof. In one alternative embodiment, the computer program product is specifically embodied in a computer storage medium; in another alternative embodiment, the computer program product is specifically embodied in a software product, such as a software development kit (SDK), etc.

[0122] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0123] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0124] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0125] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0126] Example embodiments have been disclosed herein, and while specific terminology has been used, it is for illustrative purposes only and should be construed as such, and is not intended to be limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in connection with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this disclosure as set forth by the appended claims.

Claims

1. A data output device, characterized in that, Includes a data mapping module, which is configured as follows: If the first return data of the target cache line request is received in the current input cycle, the second return data of the target sub-request included in the target cache line request is determined from the first return data based on the identification information in the target cache line request; The target cache line request is at least one of the cache line requests obtained by packaging multiple sub-requests of the data access request. The target sub-request is at least one of the multiple sub-requests, and each cache line request includes at least one sub-request. Based on the output data bit width of the data mapping module in one output cycle, the second return data of the target sub-request is output through at least one output cycle; wherein, the output data bit width is less than the maximum return data length of the data access request supported by the system.

2. The apparatus as claimed in claim 1, characterized in that, The identification information includes the mask identifiers of the multiple sub-requests; The step of determining the second returned data of the target sub-request included in the target cache line request from the first returned data based on the identification information in the target cache line request includes: Based on the mask identifiers of the multiple sub-requests, the sub-requests with valid mask identifiers are selected as the target sub-requests; Based on the sub-request index of the target sub-request, the second return data of the target sub-request is determined from the first return data.

3. The apparatus as described in claim 1, characterized in that, The step of outputting the second return data of the target sub-request through at least one output cycle, based on the output data bit width of the data mapping module in one output cycle, includes: In the current output cycle, if there is a target sub-request in the i-th sub-request group, the second return data of the target sub-request in the i-th sub-request group is output through the current output cycle, where i is an integer greater than or equal to 1; If there is no target sub-request in the i-th sub-request group and there is a target sub-request in the (i+j)-th sub-request group, the second return data of the target sub-request in the (i+j)-th sub-request group is output through the current output cycle, where j is an integer greater than or equal to 1; The data mapping module includes a pre-defined sub-request grouping for the multiple sub-requests. The sub-request grouping is determined based on the return data length of the sub-request, the number of requests for the multiple sub-requests, and the output data bit width.

4. The apparatus as claimed in claim 1, characterized in that, The first returned data is the cache line data corresponding to the target cache line request, and each cache line data includes multiple sector data. The identification information includes flag bits of multiple sector data. The step of determining the second returned data of the target sub-request included in the target cache line request from the first returned data based on the identification information in the target cache line request includes: Based on the flag bit of each sector data, filter the target sector data from the multiple sector data corresponding to the target cache line request; The second returned data is determined based on the target sector data.

5. The apparatus as described in claim 4, characterized in that, The step of filtering target sector data from multiple sector data corresponding to the target cache line request based on the flag bit of each sector data includes: Based on the first number of sector data output by the data mapping module in each output cycle, a second number of target sector data with valid flag bits are selected from the plurality of sector data, wherein the second number is less than or equal to the first number.

6. The apparatus as claimed in claim 5, characterized in that, The output side of the data mapping module includes a first number of sector channels, and the step of determining the second returned data based on the target sector data includes: In the first number of sector channels, determine the target sector channels corresponding to the second number of target sector data respectively; The second number of target sector data are routed to their corresponding target sector channels, and the second return data of the data mapping module in each output cycle is determined. The step of outputting the second return data of the target sub-request through at least one output cycle, based on the output data bit width of the data mapping module in one output cycle, includes: Output the corresponding second return data in each output cycle.

7. The apparatus as claimed in claim 1, characterized in that, The data mapping module includes a first mapping module and a second mapping module. The first returned data is the cache line data corresponding to the target cache line request. Each cache line data includes multiple sector data, and the identification information includes flag bits of multiple sector data. The step of determining the second returned data of the target sub-request included in the target cache line request from the first returned data based on the identification information in the target cache line request includes: The first mapping module filters target sector data from multiple sector data corresponding to the target cache line request based on the flag bit of each sector data; and determines the second return data of the second mapping module in each output cycle based on the target sector data. The step of outputting the second return data of the target sub-request through at least one output cycle, based on the output data bit width of the data mapping module in one output cycle, includes: The second mapping module outputs the corresponding second return data in each output cycle.

8. The apparatus as described in claim 5 or 6, characterized in that, The first quantity is determined based on the output data bit width of the data mapping module and a first ratio, which is determined based on the ratio of the size of each cache line data to the number of sector data included in each cache line data.

9. A data output method, characterized in that, The method, applied to a data mapping module in a data output device, includes: If the first return data of the target cache line request is received in the current input cycle, the second return data of the target sub-request included in the target cache line request is determined from the first return data based on the identification information in the target cache line request; The target cache line request is at least one of the cache line requests obtained by packaging multiple sub-requests of the data access request. The target sub-request is at least one of the multiple sub-requests, and each cache line request includes at least one sub-request. Based on the output data bit width of the data mapping module in one output cycle, the second return data of the target sub-request is output through at least one output cycle; wherein, the output data bit width is less than the maximum return data length of the data access request supported by the system.

10. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores one or more computer programs that can be executed by the at least one processor, the one or more computer programs being executed by the at least one processor to enable the at least one processor to perform the method as described in claim 9.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that, The computer program, when executed by a processor, implements the method as described in claim 9.

12. A computer program product, characterized in that, Includes computer-readable code, which, when executed in a processor of an electronic device, causes the processor in the electronic device to perform the method of claim 9.

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