Method and system for MCU to interactively control fast charging chip

Abstract

The application discloses an MCU and fast-charging chip interaction control method and system. The method comprises the following steps: when power is on and initialized, the MCU writes configuration mapping data into the register unit of the fast-charging chip through a protocol, for the first time, the instruction mapping table for query is written into the fast-charging chip through an external interface, and the fundamental constraint that the instruction logic of the fast-charging chip is fixed and cannot be defined by writing an instruction in the prior art is broken; when the physical layer module of the fast-charging chip detects that a load device is connected, the access information is transmitted back to the MCU through a pin; the MCU sends an operation instruction to the fast-charging chip according to the access information, the digital control core dynamically analyzes the operation instruction by inquiring the written mapping table, and the corresponding protocol circuit is driven to fast charge the load device. The application fundamentally changes the MCU and fast-charging chip interaction mode by writing the instruction mapping table for query into the fast-charging chip through a protocol.

Description

Technical Field

[0001] This invention relates to the field of fast charging chip integrated circuit technology, and in particular to a method and system for interactive control between an MCU and a fast charging chip. Background Technology

[0002] With the continued growth in demand for fast charging in mobile devices, various fast charging protocols are widely deployed in the consumer electronics field. Fast charging systems typically consist of an MCU and a dedicated fast charging chip working together. The MCU is responsible for charging strategy decisions, while the fast charging chip is responsible for protocol detection, voltage regulation, and power output. The two generally establish a communication connection through a protocol.

[0003] In existing fast charging control schemes, the instruction execution logic of the fast charging chip is fixed within the chip during the chip design phase: the mapping relationship between register addresses and corresponding protocol circuits is stored in the chip's internal architecture at the factory in the form of hardware logic or read-only memory, and the MCU cannot write or modify this mapping relationship through an external interface. Communication between the MCU and the fast charging chip is limited to reading or writing predefined register addresses to trigger the pre-fixed functions within the chip—that is, the MCU can only use the instructions already present in the chip and cannot write new instruction definitions to the chip.

[0004] The above architecture leads to the following technical limitations: when the fast charging protocol is iterated and upgraded or new protocol support is required, the chip hardware must be redesigned because the internal instruction mapping relationship of the chip is fixed and cannot be written, resulting in a long development cycle and high cost.

[0005] In summary, there is an urgent need for a technical solution that can write a queryable instruction mapping table to the fast charging chip via a protocol, thereby fundamentally changing the interaction mode between the MCU and the fast charging chip. Summary of the Invention

[0006] This invention provides a method and system for interactive control between an MCU and a fast charging chip, which solves the problem that the instruction execution logic of existing fast charging chips is fixed inside the chip during the chip design stage, resulting in the protocol routing behavior of the fast charging chip being unconfigurable after leaving the factory, thus restricting the flexible response capability of the fast charging system to protocol upgrades and multi-scenario adaptation.

[0007] In a first aspect, the present invention provides an interactive control method for an MCU and a fast charging chip. The method is applied to an interactive control system including an MCU, a fast charging chip, and at least one load device. The MCU and the fast charging chip establish a communication connection via a communication protocol. The fast charging chip integrates a top-level module, a physical layer module, and a protocol circuit. The top-level module includes a communication interface unit and a digital control core. The digital control core integrates a register unit. The communication interface unit is connected to both the MCU and the digital control core. The method includes:

[0008] During power-on initialization, the MCU sends configuration mapping data to the fast charging chip via the communication protocol, so that the configuration mapping data is written into the register unit of the fast charging chip;

[0009] The physical layer module of the fast charging chip continuously detects the access status of the load device, and sends access information to the MCU when the load device is detected to be connected;

[0010] The MCU sends an operation command to the fast charging chip based on the access information, so that the digital control core of the fast charging chip queries the configuration mapping data in the register unit and parses the operation command, driving the corresponding protocol circuit to fast charge the load device.

[0011] Preferably, the configuration mapping data is a register address mapping table, which records the mapping relationship between each register address and the corresponding protocol circuit, as well as the protocol status or control function definition corresponding to each field in each register address;

[0012] The MCU sends the register address mapping table to the fast charging chip through the data transmission channel of the communication protocol, so that the communication interface unit of the fast charging chip synchronously receives the register address mapping table based on the communication clock signal and writes the register address mapping table into the register unit.

[0013] Preferably, when the load device is connected, the physical layer module of the fast charging chip drives the interrupt detection circuit in the interrupt unit to pull the interrupt signal high, so that the communication interface unit can detect the level change of the interrupt unit;

[0014] After the communication interface unit detects the level transition, it initiates a read operation to the control area where the interrupt detection circuit is located in the top-level module, so that the digital control core can obtain the interrupt level status currently output by the interrupt detection circuit.

[0015] In response to the interrupt level state, the digital control core queries the configuration mapping data in the register unit to determine the access status of the load device, so that the fast charging chip can transmit the access information back to the MCU based on the access status through the communication protocol.

[0016] Preferably, the MCU sends an operation command to the fast charging chip according to the access information, so that the digital control core of the fast charging chip queries the configuration mapping data in the register unit and parses the operation command, driving the corresponding protocol circuit to fast charge the load device, including:

[0017] The MCU sends the operation instruction to the fast charging chip according to the access information. The operation instruction carries the target register address and the corresponding control parameters.

[0018] After receiving the operation instruction, the communication interface unit of the fast charging chip forwards the operation instruction to the digital control core. The digital control core retrieves the corresponding protocol circuit identifier from the configuration mapping data in the register unit using the target register address as the lookup key.

[0019] The digital control core locates and activates the corresponding protocol circuit based on the protocol circuit identifier, and transmits the control parameters to the protocol circuit so that the protocol circuit can implement fast charging control on the load device based on the control parameters.

[0020] Preferably, the digital control core starts the CC / CV module according to the protocol circuit identifier and transmits the target charging voltage and target charging current contained in the control parameters to the CC / CV module;

[0021] During the constant current charging phase, the CC / CV module dynamically adjusts the input voltage at the VIN input terminal to maintain the charging current output to the load device at the target charging current. During the constant voltage charging phase, the CC / CV module adjusts the input voltage at the VIN input terminal to a level corresponding to the target charging voltage to maintain the charging voltage at the target charging voltage, thereby implementing constant current and constant voltage fast charging control for the load device.

[0022] Preferably, the physical layer module includes a PD physical layer module and a DPDM physical layer module. The PD physical layer module carries the access detection and fast charging protocol interaction of the load device based on the PD protocol, and the DPDM physical layer module carries the access detection and fast charging protocol interaction of the load device based on the DPDM protocol. The two correspond to different fast charging protocol communication paths.

[0023] After the fast charging chip completes protocol negotiation with the load device, it writes the locked protocol type into the corresponding register address field in the register unit, so that the MCU can obtain the locking status of the protocol type by reading the register address field and monitor the fast charging process in real time.

[0024] The MCU monitors the level status of the interrupt unit in real time via polling, so that the MCU can detect the connection and disconnection events of the load device.

[0025] Preferably, the communication protocol includes the SPI protocol and the I2C protocol;

[0026] When the communication protocol is SPI, the communication interface unit receives data sent by the MCU through the MOSI pin, sends data back to the MCU through the MISO pin, and uses the SCLK signal generated by the MCU as a clock reference for synchronous sampling.

[0027] When the communication protocol is I2C, the communication interface unit performs bidirectional data transmission with the MCU through the data line;

[0028] Under any communication protocol, the communication interface unit carries out the writing of the configuration mapping data, the issuance of the operation instructions, and the return of the access information.

[0029] Secondly, a control system for interaction between an MCU and a fast charging chip, the system comprising:

[0030] The MCU is used to write configuration mapping data to the fast charging chip via communication protocol during power-on initialization, and to send operation commands to the fast charging chip after receiving access information from the load device.

[0031] The fast charging chip integrates a top-level module, a physical layer module, and protocol circuitry. The top-level module includes a communication interface unit and a digital control core. The digital control core integrates a register unit. The communication interface unit communicates with the MCU and receives configuration mapping data and operation instructions, forwarding them to the digital control core. The register unit stores the configuration mapping data and receives the operation instructions. The digital control core queries the register unit for the configuration mapping data to parse the operation instructions and drives the corresponding protocol circuitry. The physical layer module detects the access status of the load device and sends the access information to the MCU when the load device is detected.

[0032] The MCU and the fast charging chip work together through the communication protocol to control the fast charging of at least one of the load devices.

[0033] Preferably, the physical layer module includes at least one of a PD physical layer module and a DPDM physical layer module. The PD physical layer module carries the access detection and fast charging protocol interaction of the load device based on the PD protocol, and the DPDM physical layer module carries the access detection and fast charging protocol interaction of the load device based on the DPDM protocol.

[0034] The fast charging chip also includes an interrupt unit electrically connected to the communication interface unit. The interrupt unit includes an interrupt detection circuit, which is used to output a high-level signal when the load device is detected to be connected.

[0035] In response to the level transition of the interrupt unit, the communication interface unit initiates a read operation to the top-level module to obtain the interrupt level status of the interrupt detection circuit. The digital control core determines the access status of the load device by combining the configuration mapping data stored in the register unit, generates the access information based on the access status, and sends the access information back to the MCU through the communication protocol.

[0036] After the fast charging chip completes protocol negotiation with the load device, it writes the locked protocol type into the corresponding register address field in the register unit. The MCU obtains the locking status of the protocol type by reading the register address field in order to monitor the fast charging process in real time.

[0037] Preferably, multiple load devices can be connected to the system simultaneously, and each load device is connected to the fast charging chip through its own independent VBUS path;

[0038] At least two of the load devices share the same VIN input terminal, the same physical layer module, the same CC / CV module, and the same discharge circuit.

[0039] The MCU distinguishes the protocol circuits corresponding to each load device through the register address mapping relationship stored in the configuration mapping data, and sends operation instructions to the corresponding protocol circuits respectively to realize independent fast charging control of each load device.

[0040] The technical solutions provided in the embodiments of the present invention have the following advantages compared with the prior art:

[0041] First, during the power-on initialization phase, the MCU can write configuration mapping data into the register unit of the fast charging chip through protocol-related parameters. The chip's digital control core can then dynamically parse operation instructions and route them to the corresponding protocol circuits based on this written table. This fundamentally changes the one-way interaction mode between the MCU and the fast charging chip, which can only trigger predefined functions, and gives the fast charging chip the ability to dynamically define instruction routing behavior externally without changing the hardware.

[0042] Secondly, since the instruction mapping table can be written by the MCU during the initialization phase, the same fast charging chip hardware can adapt to different fast charging protocol combinations by writing different configuration mapping data, without having to redesign the chip for each application scenario, which significantly reduces the hardware development cost and iteration cycle of multi-protocol fast charging solutions.

[0043] Third, the protocol routing mechanism based on register address mapping table naturally supports concurrent access of multiple load devices. Multiple devices can share the same physical layer module, CC / CV module and discharge circuit, which reduces system hardware costs while maintaining independent fast charging control for each device and has good scalability. Attached Figure Description

[0044] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0045] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0046] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0047] Figure 1 This is a schematic diagram of the overall architecture of the MCU and fast charging chip interaction control system in an embodiment of the present invention;

[0048] Figure 2 This is a schematic diagram of the architecture of the MCU and fast charging chip interaction control system when a single load device is connected in an embodiment of the present invention. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0050] The following disclosure provides numerous different embodiments or examples for implementing various structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of the invention. Furthermore, reference numerals and / or letters may be repeated in different examples. Such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed.

[0051] like Figure 1 and Figure 2 As shown, this embodiment describes a complete three-stage interactive control method between the MCU and the fast charging chip, which is the core framework of this invention. Subsequent embodiments are all refined based on this.

[0052] Phase 1 Power-On Initialization: After the system powers on, the MCU first sends the configuration mapping data to the fast-charging chip via the protocol, so that the configuration mapping data is written into the fast-charging chip's register units. The configuration mapping data is essentially a register address mapping table, recording the correspondence between each register address of the fast-charging chip and its internal protocol circuitry, as well as the functional definition of each field within each register address, such as which bit fields correspond to the lock state and which correspond to CC pin detection. Once written during the initialization phase, this mapping table becomes the protocol routing basis for all subsequent interactive operations, essentially establishing a configurable protocol routing table within the fast-charging chip. The MCU does not need to transmit register address logic during runtime, effectively decoupling the protocol configuration from the charging control logic.

[0053] Phase Two Device Access Detection: After initialization, the physical layer module of the fast charging chip enters a continuous detection state, monitoring the level changes of the CC pin or D+ / D- lines of the load device in real time. When a load device is detected, the physical layer module triggers the interrupt detection circuit to pull up the interrupt signal through the internal signal link. After the protocol unit senses the level change of the interrupt unit, it actively initiates a read operation to the top-level module of the digital control core to obtain the interrupt level status. The digital control core then queries the configuration mapping data in the register unit to confirm the device access status and generates access information based on this, which is then transmitted back to the MCU via the pin.

[0054] The third stage of fast charging control: After receiving the access information, the MCU sends an operation command carrying the target register address and control parameters to the fast charging chip according to the charging strategy logic. The digital control core of the fast charging chip queries the configuration mapping data in the register unit to obtain the protocol circuit identifier corresponding to the target register address, and then drives the corresponding protocol circuit (such as the CC / CV module) to implement fast charging for the load device. In this process, the MCU only needs to know the target register address and does not need to know the details of the protocol circuit inside the fast charging chip, which greatly reduces the firmware complexity on the MCU side.

[0055] By writing configuration mapping data during the power-on initialization phase, the MCU is able to write an instruction mapping table to the fast charging chip via SPI for subsequent queries for the first time. This breaks through the fundamental constraint of existing technologies where instruction logic is fixed in the chip and external interfaces cannot write instruction definitions. Subsequently, each operation instruction is dynamically routed by querying the written mapping table, truly realizing the MCU's externally configurable control over the protocol behavior of the fast charging chip.

[0056] Preferably, this embodiment details the specific composition and writing mechanism of the configuration mapping data during the power-on initialization phase, revealing the design principles of the register address mapping table and the protocol writing timing.

[0057] In this embodiment, the register address mapping table adopts a two-layer mapping structure. The first layer is a coarse-grained mapping between register addresses and protocol circuits. For example, address 0x79 corresponds to the CC pin detection circuit, address 0x78 corresponds to the protocol lock status register, and address 0x7A corresponds to the USB DFP lock status register. The second layer defines the function of each field within each register address. For example, bits 7 to 6 of register 0x78 (vooc_note field) use 2 bits to represent the VOOC protocol lock version (00 = unlocked, 01 = VOOC 2.0, 10 = VOOC 4.0, 11 = VOOC 6.0), bits 5 to 3 (pe_note field) use 3 bits to represent the PE protocol version, and bits 2 to 0 (fcp_note field) use 3 bits to represent the FCP / SCP / AFC protocol type. This two-layer structure design enables the digital control core not only to locate the target protocol circuit through register addresses but also to precisely read and write the protocol status through bit field definitions, providing a fine-grained information foundation for subsequent protocol lock status monitoring.

[0058] In terms of writing timing, the MCU serially sends the register address mapping table byte by byte to the fast charging chip via pins. The protocol unit of the fast charging chip uses the clock signal generated by the MCU as the sampling trigger reference, synchronously sampling the data bits on the pin on each valid clock edge. After receiving one byte, the protocol unit writes it to the corresponding address area of ​​the register unit. After the full table is written within the power-on initialization window, there is no longer a need to transmit the mapping relationship data. The communication bandwidth of the bus can be dedicated to instruction issuance and status reading, effectively improving the communication efficiency during operation.

[0059] The key value of this writing mechanism lies in the fact that the contents of the register address mapping table are dynamically determined by the MCU during initialization, rather than being fixed at the chip factory. Therefore, when the register specifications of the fast charging chip are adjusted with version upgrades, only the contents of the mapping table need to be updated in the MCU initialization code. There is no need to change the logical architecture of the interaction between the MCU and the fast charging chip, thus achieving decoupling between hardware upgrades and software logic.

[0060] Preferably, this embodiment refines the complete link from the generation of the interrupt signal during the device access detection phase to its awareness by the MCU.

[0061] When a load device is plugged into the charging port of the fast charging chip, its CC pin (PD protocol device) or D+ / D- pin (DPDM protocol device) forms a level change with the corresponding detection network inside the fast charging chip. After the physical layer module senses the above level change, it drives the interrupt detection circuit in the interrupt unit to pull the interrupt signal high through the internal signal link. The interrupt detection circuit then outputs a high-level signal to the protocol unit.

[0062] The protocol unit continuously polls to monitor the output level of the interrupt unit. Upon detecting a low-to-high transition, it immediately initiates a read operation to the control area of ​​the interrupt detection circuit in the top-level module to obtain the real-time output status of the interrupt detection circuit, i.e., the interrupt level status. The top-level module aggregates key signals such as the interrupt detection circuit output and the status registers of each port. The protocol unit can obtain the required interrupt level status by reading the top-level module without the need for an additional communication path.

[0063] After acquiring the interrupt level status, the digital control core uses it as a query key to retrieve configuration mapping data in the register unit, determine the access port and device access status corresponding to the interrupt, and generate access information containing port identifier and access type. Finally, the fast charging chip transmits the access information back to the MCU in the form of data frames via pins. The MCU can then read the data on the pins to obtain the complete context of the device access event.

[0064] This embodiment integrates the interrupt detection logic into the protocol unit of the fast charging chip, enabling both interrupt detection and access information reporting to be completed through a single bus path. This eliminates the dependence on dedicated INT pins and allows access information to carry rich contextual content in the data frame, providing better information expression capabilities than dedicated interrupt pins that can only transmit high and low levels.

[0065] Preferably, this embodiment details the core interaction process of the fast charging control stage, and elaborates on the complete mechanism from the MCU issuing operation instructions to the digital control core of the fast charging chip completing table lookup parsing and activating the target protocol circuit.

[0066] After confirming the load device type and charging requirements based on the device access information, the MCU sends an operation command to the fast charging chip. The frame structure of the operation command carries two key fields: a target register address field, whose value points to a specific protocol circuit index in the configuration mapping data written to the register unit during the initialization phase; and a control parameter field, containing specific control quantities required for charging adjustment, such as the target charging voltage level and target charging current value. The MCU only needs to know the target register address and does not need to understand the physical structure of the protocol circuit inside the fast charging chip; the details of the protocol routing are handled by the configuration mapping data on the chip side.

[0067] After receiving the operation command, the communication interface unit of the fast charging chip forwards it completely to the digital control core. The digital control core uses the target register address carried in the operation command as the lookup key to retrieve the configuration mapping data in the register unit, obtaining the protocol circuit identifier corresponding to that address. The protocol circuit identifier is an index value uniquely identified by the MCU during the initialization phase, identifying a specific protocol processing module within the fast charging chip. Based on this identifier, the digital control core accurately locates and activates the corresponding protocol circuit, simultaneously transmitting the control parameters carried in the operation command to the activated protocol circuit, enabling the protocol circuit to implement fast charging control on the load device according to the charging parameters specified by the MCU.

[0068] The table lookup routing mechanism disclosed in this embodiment is a direct manifestation of the core breakthrough of this invention at the instruction execution level. In the prior art, which protocol circuit the digital control core drives based on the operation instruction is determined by the internal logic fixed at the chip factory. The MCU can neither change this routing rule nor extend support for new protocols through external configuration. However, in this invention, the routing rule is entirely determined by the mapping relationship established by the configuration mapping data written by the MCU during the initialization phase. When it is necessary to support a new protocol or adjust the protocol routing strategy, only the updated mapping table needs to be written during the initialization phase, and the digital control core can execute instructions according to the new routing rule without making any changes to the chip hardware, thus achieving complete external configurability of the instruction routing logic.

[0069] Preferably, this embodiment provides a detailed explanation of the specific mechanism by which the CC / CV module implements fast charging control of the load device in a constant current and constant voltage manner after the protocol circuit is activated.

[0070] After the digital control core activates the CC / CV module based on the protocol circuit identifier, it extracts the control parameters carried in the operation command into the target charging voltage and target charging current, and transmits them to the CC / CV module as the target reference values ​​for charging regulation. The CC / CV module is the core power regulation unit of the fast charging system, which automatically switches between two operating modes according to the current charging status of the load device.

[0071] During the constant current (CC) charging phase, the battery's state of charge (SOC) is low. The CC / CV module uses the target charging current as the control target and dynamically adjusts the input voltage at the VIN input terminal to maintain the charging current output to the load device at the target charging current value, preventing overcurrent damage to the battery or charging cable. During the constant voltage (CV) charging phase, the battery voltage approaches the rated full charge voltage. The CC / CV module switches to using the target charging voltage as the control target and adjusts the input voltage at the VIN input terminal to a level corresponding to the target charging voltage. The charging current naturally decays to the trickle-off threshold as the SOC increases, completing the full charge process.

[0072] At the hardware implementation level, the VIN input is connected to an external ACDC adapter, which converts AC mains power into DC input power. The CC / CV module dynamically adjusts the VIN input through an external closed-loop voltage regulation circuit: the CC / CV module generates an error control signal based on the current charging stage. This signal is then used by a sampling resistor network to sense the VBUS output voltage or charging current in real time and compare it with the target value to generate an adjustment drive signal. This adjustment drive signal is fed into the light-emitting side of the optocoupler, which establishes an electrically isolated feedback path between the secondary side of the fast-charging chip and the primary control circuit of the ACDC adapter via photoelectric conversion. The PWM controller on the primary side of the ACDC adapter receives the feedback signal from the optocoupler and adjusts the duty cycle accordingly, thereby changing the output voltage of the ACDC adapter, i.e., adjusting the actual voltage value of the VIN input.

[0073] Through the aforementioned closed-loop adjustment mechanism, the CC / CV module can dynamically switch between charging levels specified by different fast charging protocols, such as PD (up to 20V / 5A), VOOC (proprietary current grading), PE (5V / 9V / 12V), and FCP (5V / 9V / 12V), based on the target charging voltage and target charging current issued by the MCU, achieving unified and precise fast charging control across multiple protocols. The target parameters of the CC / CV module are dynamically issued by the MCU through operation commands, and the routing of these commands is determined by the configuration mapping data written during the initialization phase. The charging parameter configurations for different protocols are all issued and executed through the same lookup table routing framework, eliminating the need to solidify adjustment logic separately for each protocol. This fully demonstrates the core value of the writable command mapping table mechanism of this invention at the charging adjustment level.

[0074] Preferably, this embodiment provides a detailed explanation of the specific composition of the physical layer module involved, the fast charging protocol negotiation process, and the real-time monitoring mechanism for the protocol lock status.

[0075] The physical layer module is divided into two independent sub-modules in terms of hardware: the PD physical layer module and the DPDM physical layer module. The PD physical layer module establishes a physical connection with the CC pin of the load device through the CC1 and CC2 pins. It confirms the access of devices that conform to the USB PD specification by detecting the presence of the 5.1kΩ pull-down resistor on the CC pin, and after the access is confirmed, it starts the BMC codec engine to complete the negotiation process based on the PD protocol.

[0076] The DPDM physical layer module establishes a connection with the data lines of the load device through the D+ and D- pins. It identifies the device access type by detecting the voltage levels of the D+ / D- lines and completes fast charging protocol negotiation based on the data lines using the handshake voltage sequence specified by each protocol. The two sub-modules correspond to different fast charging protocol communication paths, and are scheduled by the digital control core system through the protocol path selection field in the configuration mapping data.

[0077] After the protocol negotiation is completed and the final fast charging protocol type is determined, the digital control core writes the locked protocol type into the corresponding register address field in the register unit according to the predefined encoding rules in the register address mapping table. For example, when VOOC 4.0 is locked, the encoded value 10 is written to the vooc_note field (bits 7 to 6) of register 0x78; when FCP 9V is locked, the encoded value 001 is written to the fcp_note field (bits 2 to 0) of register 0x78. By reading the current encoded value in the above register address field, the MCU can know the current fast charging protocol locking status, realizing real-time monitoring of the entire fast charging process without polling multiple scattered status registers.

[0078] In addition, the MCU continuously monitors the level status of the interrupt unit in real time through polling to ensure that the connection and disconnection events of the load device can be captured in real time under either the PD or DPDM protocol communication path, providing a reliable event-driven basis for fast charging status management.

[0079] The write-back and monitoring mechanism for the protocol lock state described in this embodiment relies on the writable register address mapping table established during the initialization phase of this invention. The functional semantics of each register address bit field are defined by the configuration mapping data written by the MCU, rather than being fixed at the chip factory. In existing technical solutions, the register bit field semantics of the protocol lock state are read-only and cannot be redefined for the MCU; however, this invention empowers the MCU to flexibly define the semantics of each bit field by writing configuration mapping data during the initialization phase. This allows the protocol coverage and granularity of fast charging monitoring to be determined by actual application requirements, which is the specific manifestation of the core breakthrough of this invention in multi-protocol monitoring scenarios.

[0080] Preferably, this embodiment provides a detailed description of the specific types of communication protocols, clarifying that the technical solution of the present invention includes multiple interaction protocols. Only the SPI protocol and I2C protocol are illustrated in the specific implementation. In the actual implementation, it is not limited to these two methods and is not limited here. Other communication protocol methods can be implemented by referring to the same interaction process of this application.

[0081] When the communication protocol uses SPI, the communication interface unit is configured in SPI slave mode. The MCU serially sends configuration mapping data and operation commands to the fast charging chip via the MOSI (Master Output, Slave Input) pin. The communication interface unit synchronously samples the data on the MOSI pin on each valid clock edge, using the SCLK signal generated by the MCU as the clock reference. The communication interface unit also sends access information and protocol lock status back to the MCU via the MISO (Master Input, Slave Output) pin. The full-duplex nature of the SPI protocol allows data transmission on both MOSI and MISO to occur simultaneously within the same SCLK clock cycle. The MCU can receive the preceding query results from the fast charging chip while issuing operation commands, enabling parallel read and write operations with high communication efficiency, making it suitable for fast charging monitoring scenarios requiring high-frequency register read and write operations.

[0082] When the communication protocol adopts the I2C protocol, the communication interface unit is configured to operate in I2C slave mode, transmitting data bidirectionally with the MCU via the SDA data line, and using the SCL signal generated by the MCU as the clock reference. The I2C protocol uses an address addressing mechanism. The communication interface unit responds to read and write transactions initiated by the MCU with a preset slave address; the MCU, acting as the master, actively initiates write transactions (issuing configuration mapping data or operation instructions) and read transactions (obtaining access information or protocol lock status).

[0083] Under any communication protocol, the communication interface unit carries the transmission of three types of core data: writing configuration mapping data during the power-on initialization phase, issuing operation commands during the fast charging control phase, and transmitting access information during the device access detection phase. The choice of communication protocol only affects the implementation at the physical signal level and does not change the core interaction logic of this invention, namely the fundamental breakthrough of the MCU writing a queryable instruction mapping table to the fast charging chip through the communication protocol, and the dynamic instruction routing mechanism based on the mapping table, which is equally applicable under both SPI and I2C protocols.

[0084] This invention also provides an MCU and fast charging chip interactive control system. Since the MCU and fast charging chip interactive control method is applied to the interactive control system, specific embodiments are described in the method category. In one embodiment, this embodiment describes the specific implementation of the system simultaneously supporting concurrent access and independent fast charging control of multiple load devices, illustrating the design principles of the multi-device hardware resource sharing and independent control coordination mechanism.

[0085] In scenarios with multiple devices accessing concurrently, each load device connects to the fast charging chip through its own independent VBUS path. Taking three devices accessing simultaneously as an example, the three paths VBUS0, VBUS1, and VBUS2 are each connected to the VIN input terminal through their respective MOSFETs. The gate of the MOSFET in each VBUS path is independently driven by the digital control core of the fast charging chip. The MCU can control the enable timing and power output of each VBUS path by issuing operation instructions to different target register addresses, thereby achieving completely independent charging start / stop and parameter adjustment for each load device.

[0086] Regarding hardware resource sharing, at least two load devices share the same VIN input, the same physical layer module, the same CC / CV module, and the same bleeder circuit (which can be understood as the bleeder circuit being connected to both the VBUS and VIN ports to charge the load devices). Sharing the VIN input allows multiple outputs to draw power from the same power input, simplifying the power management structure. The shared physical layer module supports protocol detection and negotiation for multiple ports in a time-division or channel-multiplexed manner through an internal protocol channel switching mechanism, saving on-chip silicon resources. The shared CC / CV module performs voltage and current regulation for each port sequentially through a time-division multiplexing scheduling strategy. Under the premise of reasonable multi-port working timing arrangement, one CC / CV regulation circuit can serve multiple load devices. The shared bleeder circuit quickly discharges the residual voltage of the corresponding VBUS path when a load device is disconnected, preventing voltage surges during hot-plugging from damaging subsequently connected devices and improving the safety of multi-port dynamic access.

[0087] In terms of protocol routing for multiple devices, the MCU matches the target register address carried in the operation instruction with the register address mapping relationship in the configuration mapping data written during initialization. Based on this, the digital control core determines which protocol circuit channel corresponding to the load device the instruction should be routed to and sends a charging control signal to that channel. In existing technologies that solidify instructions, the multi-port routing logic must be fully pre-stressed in the chip, resulting in extremely poor flexibility. In contrast, this invention implements the external definition of routing logic by writing to a mapping table. This allows for the expansion of multi-device management simply by adding corresponding entries to the mapping table. The system complexity does not increase linearly with the number of ports, exhibiting excellent scalability.

[0088] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0089] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed in this invention can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0090] In the embodiments provided by this invention, it should be understood that the disclosed circuits / terminal devices and methods can be implemented in other ways. For example, the circuit / terminal device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, indirect coupling or communication connection of circuits or units, and may be electrical, mechanical, or other forms.

[0091] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0092] If the integrated module / unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or circuit capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium can be appropriately added or removed according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.

[0093] The present invention can implement all or part of the processes in the methods of the above embodiments, or it can be accomplished by a computer program product. When the computer program product is run on a terminal device, the terminal device can implement the steps in the various method embodiments described above.

[0094] The embodiments described above are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A method for interactive control between an MCU and a fast charging chip, characterized in that, The method is applied to an interactive control system including an MCU, a fast charging chip, and at least one load device. The MCU and the fast charging chip establish a communication connection via a communication protocol. The fast charging chip integrates a top-level module, a physical layer module, and protocol circuitry. The top-level module includes a communication interface unit and a digital control core. The digital control core integrates a register unit. The communication interface unit is connected to both the MCU and the digital control core. The method includes: During power-on initialization, the MCU sends configuration mapping data to the fast charging chip via the communication protocol, so that the configuration mapping data is written into the register unit of the fast charging chip; The physical layer module of the fast charging chip continuously detects the access status of the load device, and sends access information to the MCU when the load device is detected to be connected; The MCU sends an operation command to the fast charging chip based on the access information, so that the digital control core of the fast charging chip queries the configuration mapping data in the register unit and parses the operation command, driving the corresponding protocol circuit to fast charge the load device.

2. The method according to claim 1, characterized in that, The configuration mapping data is a register address mapping table, which records the mapping relationship between each register address and the corresponding protocol circuit, as well as the protocol status or control function definition corresponding to each field in each register address. The MCU sends the register address mapping table to the fast charging chip through the data transmission channel of the communication protocol, so that the communication interface unit of the fast charging chip synchronously receives the register address mapping table based on the communication clock signal and writes the register address mapping table into the register unit.

3. The method according to claim 1, characterized in that, When the load device is connected, the physical layer module of the fast charging chip drives the interrupt detection circuit in the interrupt unit to pull the interrupt signal high, so that the communication interface unit can detect the level change of the interrupt unit. After the communication interface unit detects the level transition, it initiates a read operation to the control area where the interrupt detection circuit is located in the top-level module, so that the digital control core can obtain the interrupt level status currently output by the interrupt detection circuit. In response to the interrupt level state, the digital control core queries the configuration mapping data in the register unit to determine the access status of the load device, so that the fast charging chip can transmit the access information back to the MCU based on the access status through the communication protocol.

4. The method according to claim 1, characterized in that, The MCU sends an operation command to the fast charging chip based on the access information, so that the digital control core of the fast charging chip queries the configuration mapping data in the register unit and parses the operation command, driving the corresponding protocol circuit to fast charge the load device, including: The MCU sends the operation instruction to the fast charging chip according to the access information. The operation instruction carries the target register address and the corresponding control parameters. After receiving the operation instruction, the communication interface unit of the fast charging chip forwards the operation instruction to the digital control core. The digital control core retrieves the corresponding protocol circuit identifier from the configuration mapping data in the register unit using the target register address as the lookup key. The digital control core locates and activates the corresponding protocol circuit based on the protocol circuit identifier, and transmits the control parameters to the protocol circuit so that the protocol circuit can implement fast charging control on the load device based on the control parameters.

5. The method according to claim 4, characterized in that, The digital control core starts the CC / CV module according to the protocol circuit identifier and transmits the target charging voltage and target charging current contained in the control parameters to the CC / CV module; During the constant current charging phase, the CC / CV module dynamically adjusts the input voltage at the VIN input terminal to maintain the charging current output to the load device at the target charging current. During the constant voltage charging phase, the CC / CV module adjusts the input voltage at the VIN input terminal to a level corresponding to the target charging voltage, thereby maintaining the charging voltage at the target charging voltage and implementing constant current and constant voltage fast charging control for the load device.

6. The method according to claim 3, characterized in that, The physical layer module includes a PD physical layer module and a DPDM physical layer module. The PD physical layer module carries the access detection and fast charging protocol interaction of the load device based on the PD protocol, and the DPDM physical layer module carries the access detection and fast charging protocol interaction of the load device based on the DPDM protocol. The two correspond to different fast charging protocol communication paths. After the fast charging chip completes protocol negotiation with the load device, it writes the locked protocol type into the corresponding register address field in the register unit, so that the MCU can obtain the locking status of the protocol type by reading the register address field and monitor the fast charging process in real time. The MCU monitors the level status of the interrupt unit in real time through polling, so that the MCU can detect the connection and disconnection events of the load device.

7. The method according to claim 1, characterized in that, The communication protocols include the SPI protocol and the I2C protocol; When the communication protocol is SPI, the communication interface unit receives data sent by the MCU through the MOSI pin, sends data back to the MCU through the MISO pin, and uses the SCLK signal generated by the MCU as a clock reference for synchronous sampling. When the communication protocol is I2C, the communication interface unit performs bidirectional data transmission with the MCU through the data line; Under any communication protocol, the communication interface unit carries out the writing of the configuration mapping data, the issuance of the operation instructions, and the return of the access information.

8. A control system for interaction between an MCU and a fast charging chip, characterized in that, The system includes: The MCU is used to write configuration mapping data to the fast charging chip via communication protocol during power-on initialization, and to send operation commands to the fast charging chip after receiving access information from the load device. The fast charging chip integrates a top-level module, a physical layer module, and protocol circuitry. The top-level module includes a communication interface unit and a digital control core. The digital control core integrates a register unit. The communication interface unit communicates with the MCU and receives configuration mapping data and operation instructions, forwarding them to the digital control core. The register unit stores the configuration mapping data and receives the operation instructions. The digital control core queries the register unit for the configuration mapping data to parse the operation instructions and drives the corresponding protocol circuitry. The physical layer module detects the access status of the load device and sends the access information to the MCU when the load device is detected. The MCU and the fast charging chip work together through the communication protocol to control the fast charging of at least one of the load devices.

9. The system according to claim 8, characterized in that, The physical layer module includes at least one of a PD physical layer module and a DPDM physical layer module. The PD physical layer module carries the access detection and fast charging protocol interaction of the load device based on the PD protocol, and the DPDM physical layer module carries the access detection and fast charging protocol interaction of the load device based on the DPDM protocol. The fast charging chip also includes an interrupt unit electrically connected to the communication interface unit. The interrupt unit includes an interrupt detection circuit, which is used to output a high-level signal when the load device is detected to be connected. In response to the level transition of the interrupt unit, the communication interface unit initiates a read operation to the top-level module to obtain the interrupt level status of the interrupt detection circuit. The digital control core determines the access status of the load device by combining the configuration mapping data stored in the register unit, generates the access information based on the access status, and sends the access information back to the MCU through the communication protocol. After the fast charging chip completes protocol negotiation with the load device, it writes the locked protocol type into the corresponding register address field in the register unit. The MCU obtains the locking status of the protocol type by reading the register address field in order to monitor the fast charging process in real time.

10. The system according to claim 8, characterized in that, Multiple load devices can be connected to the system simultaneously, and each load device is connected to the fast charging chip through its own independent VBUS path; At least two of the load devices share the same VIN input terminal, the same physical layer module, the same CC / CV module, and the same discharge circuit; The MCU distinguishes the protocol circuits corresponding to each load device through the register address mapping relationship stored in the configuration mapping data, and sends operation instructions to the corresponding protocol circuits respectively to realize independent fast charging control of each load device.

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