Data arrangement conversion device, method, medium, apparatus, and neural network processor

Abstract

Disclosed are a data arrangement conversion device, method, medium, equipment and neural network processor. In response to a type of a write cycle being a first cycle type, a plurality of data elements are written into a same storage row in a storage array; in response to the type of the write cycle being a second cycle type, the plurality of data elements are written into a plurality of storage rows in the storage array based on a first data arrangement mode and configuration parameters. In response to a type of a read cycle being the second cycle type, the plurality of data elements are respectively read from the plurality of storage rows in the storage array based on the first data arrangement mode to obtain an intermediate data block; the plurality of data elements are read from the same storage row in the storage array to obtain the intermediate data block, and the plurality of data elements in the intermediate data block are subjected to data rearrangement to obtain an output data block arranged according to a second data arrangement mode. Thus, data arrangement conversion is realized by a storage array with a smaller size, cache overhead is reduced, and data arrangement conversion efficiency is improved.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to a data layout conversion device, method, readable storage medium, electronic device, and neural network processor. Background Technology

[0002] Neural network inference computations in integrated circuits typically involve a large amount of data processing. During data processing by a neural network processor, the data to be processed needs to be rearranged to change its arrangement. The data to be processed is divided into multiple data blocks according to a predetermined data arrangement. During the rearrangement process, the data elements in these multiple data blocks need to be recombinated. Currently, most methods rely on cache circuits for this rearrangement, resulting in significant cache resource consumption and thus impacting the efficiency of the data rearrangement process. Summary of the Invention

[0003] To address the aforementioned technical problems, this disclosure provides a data layout conversion apparatus, method, readable storage medium, electronic device, and neural network processor to solve the problems of high cache resource consumption and low efficiency in the neural network processor layout conversion process.

[0004] The first aspect of this disclosure provides a data arrangement conversion apparatus, comprising: a storage array including a plurality of storage blocks, each storage block including a plurality of storage cells; an input rearrangement circuit configured to acquire an input data block arranged according to a first data arrangement method, and select data elements corresponding to a plurality of storage blocks from a plurality of data elements in the input data block based on configuration parameters of a function operator and the position of the input data block in the data to be converted; and a data writing circuit configured to write the plurality of data elements into the same storage row in the storage array in response to a writing cycle of a first cycle type; and to respond to a writing cycle of a second cycle type. The system comprises: a data reading circuit configured to, in response to a second cycle type, read multiple data elements from multiple storage rows in the storage array based on the first data arrangement, to obtain an intermediate data block; and an output rearrangement circuit configured to rearrange the multiple data elements in the intermediate data block to obtain an output data block arranged according to the second data arrangement.

[0005] A second aspect of this disclosure provides a data arrangement transformation method, comprising: acquiring an input data block arranged according to a first data arrangement method; selecting data elements corresponding to multiple storage banks from multiple data elements in the input data block based on configuration parameters of a function operator and the position of the input data block in the data to be transformed; writing multiple data elements to the same storage row in a storage array in response to a write cycle of a first cycle type; writing multiple data elements to multiple storage rows in a storage array based on the first data arrangement method and configuration parameters in response to a write cycle of a second cycle type; reading multiple data elements from multiple storage rows in the storage array based on the first data arrangement method in response to a read cycle of a second cycle type to obtain an intermediate data block; reading multiple data elements from the same storage row in the storage array in response to a read cycle of a first cycle type to obtain an intermediate data block; and rearranging the multiple data elements in the intermediate data block to obtain an output data block arranged according to the second data arrangement method.

[0006] A third aspect of this disclosure provides a neural network processor, including a data layout conversion device and a memory; wherein the data layout conversion device includes a data layout conversion device for implementing the first aspect of this disclosure.

[0007] A fourth aspect of this disclosure provides a computer-readable storage medium storing a computer program for implementing the data arrangement conversion method of the second aspect of this disclosure.

[0008] A fifth aspect of this disclosure provides an electronic device comprising: a processor; a memory for storing processor-executable instructions; and a processor for reading executable instructions from the memory and executing the instructions to implement the data arrangement conversion method of the second aspect of this disclosure.

[0009] The data arrangement conversion apparatus provided in this disclosure acquires an input data block arranged according to a first data arrangement method through an input rearrangement circuit. Based on the configuration parameters of the function operator and the position of the input data block in the data to be converted, it selects data elements corresponding to multiple storage banks from multiple data elements in the input data block. A data writing circuit, responding to a first cycle type, writes multiple data elements into the same storage row in the storage array; responding to a second cycle type, it writes multiple data elements into multiple storage rows in the storage array based on the first data arrangement method and configuration parameters. A data reading circuit, responding to a second cycle type, reads multiple data elements from multiple storage rows in the storage array based on the first data arrangement method to obtain an intermediate data block; responding to a first cycle type, it reads multiple data elements from the same storage row in the storage array to obtain an intermediate data block. An output rearrangement circuit rearranges the multiple data elements in the intermediate data block to obtain an output data block arranged according to the second data arrangement method.

[0010] The data layout conversion apparatus disclosed herein, in a first cycle type, uses a data writing circuit to write multiple data elements to the same storage row, and a data reading circuit to read multiple data elements from the same storage row. In a second cycle type, multiple data elements are written to multiple storage rows using a data writing circuit, and multiple data elements are read from multiple storage rows using a data reading circuit. This allows the two cycle types to employ different storage row write and read relationships, enabling data elements written to the storage array in the previous cycle type to be read and combined in the subsequent cycle type or a later corresponding cycle. The storage array can simultaneously store data elements corresponding to different cycle types. Therefore, data layout conversion can be achieved using a storage array smaller than the size of the data to be converted, improving the utilization rate of the storage array, reducing the hardware overhead of caching, thereby reducing hardware area and cost, and improving data layout conversion efficiency. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of the structure of a data layout conversion device provided in an exemplary embodiment of this disclosure.

[0012] Figure 2 This is a schematic diagram of the data arrangement of the data to be converted before and after transposition, provided by an exemplary embodiment of this disclosure.

[0013] Figure 3 This is a circuit diagram of a data layout conversion device provided in an exemplary embodiment of the present disclosure.

[0014] Figure 4 This is a flowchart illustrating a data arrangement and conversion method provided in an exemplary embodiment of this disclosure.

[0015] Figure 5 This is a flowchart illustrating a data input rearrangement method provided in an exemplary embodiment of this disclosure.

[0016] Figure 6 This is a flowchart illustrating a method for outputting target data elements provided in an exemplary embodiment of this disclosure.

[0017] Figure 7 This is a flowchart illustrating a data element selection method provided in an exemplary embodiment of this disclosure.

[0018] Figure 8 This is a flowchart illustrating a method for determining the shift value provided in an exemplary embodiment of this disclosure.

[0019] Figure 9 This is a flowchart illustrating a data element writing method provided in an exemplary embodiment of this disclosure.

[0020] Figure 10 This is a flowchart illustrating a method for writing data elements into the same storage row, as provided in an exemplary embodiment of this disclosure.

[0021] Figure 11 This is a flowchart illustrating a method for writing data elements into multiple storage rows according to an exemplary embodiment of this disclosure.

[0022] Figure 12 This is a flowchart illustrating another data element writing method provided by an exemplary embodiment of this disclosure.

[0023] Figure 13 This is a flowchart illustrating a method for determining the same storage row address provided in an exemplary embodiment of this disclosure.

[0024] Figure 14 This is a flowchart illustrating a method for determining multiple storage row addresses provided in an exemplary embodiment of this disclosure.

[0025] Figure 15 This is a flowchart illustrating a data element output method provided in an exemplary embodiment of this disclosure.

[0026] Figure 16 This is a flowchart illustrating a data element reading method provided in an exemplary embodiment of this disclosure.

[0027] Figure 17 This is a flowchart illustrating another data element reading method provided by an exemplary embodiment of this disclosure.

[0028] Figure 18 This is a flowchart illustrating another data reading method provided by an exemplary embodiment of this disclosure.

[0029] Figure 19 This is a flowchart illustrating a method for determining multiple row addresses provided in an exemplary embodiment of this disclosure.

[0030] Figure 20 This is a flowchart illustrating a method for determining the same storage row address provided in an exemplary embodiment of this disclosure.

[0031] Figure 21 This is a flowchart illustrating a data element output rearrangement method provided in an exemplary embodiment of this disclosure.

[0032] Figure 22 This is a flowchart illustrating a data element output method provided in an exemplary embodiment of this disclosure.

[0033] Figure 23 This is a flowchart illustrating a data rearrangement method provided in an exemplary embodiment of this disclosure.

[0034] Figure 24 This is a flowchart illustrating a method for determining the shift value provided in an exemplary embodiment of this disclosure.

[0035] Figure 25 This is a flowchart illustrating an exemplary embodiment of the present disclosure of an access address generation method.

[0036] Figure 26 This is a schematic diagram of the structure of an electronic device provided in an exemplary embodiment of this disclosure.

[0037] Figure 27 This is a schematic diagram of the structure of a neural network processor provided in an exemplary embodiment of the present disclosure. Detailed Implementation

[0038] To explain this disclosure, exemplary embodiments of the disclosure will now be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the disclosure, and not all of them. It should be understood that the disclosure is not limited to exemplary embodiments.

[0039] It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of this disclosure.

[0040] Those skilled in the art will understand that the terms "first," "second," "third," and "fourth" in this disclosure are used only to distinguish different objects and are not used to limit the order, quantity, or importance of the objects. For example, the first data arrangement method and the second data arrangement method are used to distinguish the arrangement methods of input data blocks and output data blocks; the first selection signal, the second selection signal, the third selection signal, and the fourth selection signal are used to distinguish the selection signals that act on different circuit stages.

[0041] In this disclosure, "data element" can be understood as the smallest data processing granularity in an input data block, output data block, or data to be transformed. For example, a data element can be a single byte of data, or it can be other data granularities processed by the neural network processor according to its internal data bit width. For ease of explanation, this disclosure uses an example where the input data block includes 64 data elements and the storage array includes 64 memory blocks. This example is used to illustrate the circuit structure and data mapping logic and does not limit the number of data elements, the number of memory blocks, or the data bit width in this disclosure.

[0042] In this disclosure, the data to be transformed can be understood as data that needs to be arranged and transformed according to the constraints of the data arrangement transformation operator. The data to be transformed can be a multidimensional array, such as tensor data, or one or more data blocks in tensor data. The data arrangement transformation operator can be the transpose operator, or other operators that require equivalent transposition or data arrangement transformation during execution; this disclosure does not limit the specific operators.

[0043] Application Overview With the rapid development of neural network technology, neural network models have been widely used in fields such as image recognition and natural language processing. The inference computation of neural network models typically involves a large amount of data processing, such as tensor computation, matrix multiplication, and attention mechanisms. During the computation process, the neural network processor usually needs to perform arrangement transformation operations on the data to be processed to adjust the position of data elements within the transformed data. The data to be transformed can be feature data, intermediate activation data, weight data, or other data organized according to a multi-dimensional structure in the neural network model. The data to be transformed can be divided into multiple input data blocks according to a predetermined data arrangement method. The data arrangement method is used to indicate the order of each dimension within the data block and the block size (or block dimension) of each dimension.

[0044] Neural network processors can change the position of data elements in the data to be transformed based on data arrangement transformation operators. These operators can be two-dimensional or multi-dimensional transpose operators. For example, if the data to be transformed is a two-dimensional tensor, the data arrangement transformation operation can be a row and column swap. If the data to be transformed is a multi-dimensional tensor (e.g., the data includes H, W, and C dimensions), the data arrangement transformation operation can adjust the order of data elements in different dimensions.

[0045] For example, if the data to be converted is divided into multiple data blocks according to the 1H1W64C data arrangement, and the data arrangement of the data blocks in the data to be converted is converted to 64H1W1C, it is necessary to first write the data elements of the 64 data blocks in the data to be converted to the cache array, and then read the data blocks from the cache array in the form of 64H1W1C. In one data arrangement conversion cycle, the neural network processor can only write data elements to or read data elements from the cache array. When the size of the data to be converted is larger than the size of the cache array (for example, the data to be converted includes 256 data blocks), the data arrangement conversion efficiency is low.

[0046] Currently, data routing transformations are performed using larger cache arrays to reduce latency. For example, this can be achieved using 128... 1 A 64-level cache array performs data layout transformation operations. The first 64 levels of the cache array and the last 64 levels of the cache array are used to process different data blocks in the data to be transformed. However, this approach results in higher hardware area and cost, and more complex cache read / write scheduling, which in turn affects the efficiency of data layout transformation.

[0047] To address the issues of high cache area and cost, as well as low data layout conversion efficiency, resulting from increasing the size of the cache array for data layout conversion, the data layout conversion device disclosed herein employs different storage row write and read relationships in two types of cycles. Data elements written to the storage array in the previous cycle type can be read and combined in the subsequent cycle type or a later corresponding cycle. The storage array can simultaneously store data elements corresponding to different cycle types. Therefore, data layout conversion is achieved using a storage array smaller than the size of the data to be converted, improving the utilization of the storage array, reducing cache hardware overhead, thereby reducing hardware area and cost, and improving data layout conversion efficiency.

[0048] Exemplary device Figure 1This is a schematic diagram of a data layout conversion device provided in this disclosure. The data layout conversion device 100 of this disclosure can be a hardware circuit in a neural network processor, a brain processing unit (BPU), a graphics processing unit (GPU), or other chips with tensor processing capabilities. It can also be a neural network processor, a brain processing unit (BPU), a graphics processing unit (GPU), or other integrated circuits with neural network processing capabilities. In this embodiment, the data layout conversion device 100 is exemplarily described as a hardware circuit disposed in a neural network processor. The data layout conversion device 100 of this disclosure can be coupled to one or more devices such as memory, on-chip cache, and direct memory access controller (DMA) in the neural network processor.

[0049] like Figure 1 As shown, the data arrangement conversion device 100 includes a storage array 110, an input rearrangement circuit 120, a data writing circuit 130, a data reading circuit 140, and a data rearrangement circuit 150.

[0050] Storage array 110 includes multiple banks, each containing multiple storage units. These banks can each correspond to multiple data element positions within an output data block. For example, storage array 110 may include 64 banks: Bank0, Bank1, ..., Bank63. Each bank may contain multiple rows or multiple storage units, where the row address represents the corresponding cache location within the bank for different data collection stages. Element positions indicate coordinates or sequence numbers within the data. The element position of a data element indicates its location or sequence number within the corresponding dataset (e.g., data to be transformed, input data blocks, and output data blocks). Therefore, multiple target data elements within an intermediate data block can be stored in parallel using multiple banks.

[0051] Multiple memory banks can operate in parallel, each used to store data written by the data writing circuit 130. The number of data elements in the input data block can be associated with the number of memory banks. For example, the memory array 110 may include 64 memory banks, with the 64 data elements in the input data block corresponding to the 64 memory banks respectively. The 64 data elements can be written to the 64 memory banks respectively. The input data block can be configured to be 64 bytes, and each data element is 1 byte.

[0052] The depth of a memory bank can be designed based on hardware area and throughput requirements. In some examples, a memory bank includes 64 memory cells to improve pipeline throughput. In other examples, the depth of each memory bank can be reduced to 2 or other numbers to reduce area overhead. Memory cells can include registers, latches, static random access memory (SRAM), or other circuitry capable of storing data elements.

[0053] In practical applications, the depth of the memory bank can be configured according to the needs of the neural network processor. If the neural network processor has high throughput requirements, a deeper memory bank can be configured (with more storage cells, such as 64), so that the memory array can store more intermediate data rows; if the neural network processor is a low-power chip that is sensitive to hardware area, a shallower memory bank can be configured (with fewer storage cells, such as 2), thereby reducing the number of registers and wiring resources.

[0054] For example, the number of memory banks in storage array 110 may not be 64. If the number of memory banks changes, the first data arrangement of the data to be converted, the size of the input data block obtained by dividing the data to be converted, the data element bit width, or the bus width can be adjusted accordingly. For example, if storage array 110 includes 32 memory banks, the input data block may include 32 data elements.

[0055] The input rearrangement circuit 120 is configured to acquire an input data block arranged according to a first data arrangement, and select data elements corresponding to multiple storage units from multiple data elements in the input data block based on the configuration parameters of the function operator and the position of the input data block in the data to be converted.

[0056] For example, the input rearrangement circuit 120 is coupled to the memory array and the controller to receive input data blocks from the data to be converted according to control signals from the controller. The output of the input rearrangement circuit 120 is coupled to the input of the data writing circuit 130 to output data elements corresponding to the selected multiple memory banks to the data writing circuit 130. The data to be converted can be data read from memory according to the access address, or data provided by the on-chip cache or DMA controller. The data to be converted is divided into multiple input blocks according to a first data arrangement.

[0057] An input data block can be understood as a data unit read from the data to be transformed and participating in one input rearrangement process. An input data block consists of multiple data elements, each corresponding to a different element position in the data to be transformed.

[0058] The first data arrangement is used to represent the order of multiple dimensions (e.g., H, W, C, etc.) in a data block and the number of data elements in each dimension. For example, the first data arrangement can be represented as 2H4W8C, meaning that a data block includes 2 positions in the H dimension, 4 positions in the W dimension, and 8 positions in the C dimension. This representation is only an example; the first data arrangement can also be represented by other dimensional orders or other dimensions.

[0059] The data arrangement conversion device 100 can perform related operations on various types of function operators. In this embodiment, the specific type of function operator is not limited. Taking the three-dimensional transpose operator as an example, the input data block can be a data block in the data to be converted. The data to be converted is the input data corresponding to the function operator. The following embodiment uses the transpose operator as an example for illustrative explanation.

[0060] Figure 2 This is a schematic diagram illustrating the arrangement of data blocks to be converted, provided in an embodiment of this disclosure. For example... Figure 2 As shown, taking the first data to be converted 21 and the second data to be converted 22 as examples, each input data block has a size of 1H1W64C and a first arrangement of 2H4W8C. The first data to be converted 21, arranged in 2H4W8C, may include the first input data block 211, the second input data block 212, the third input data block 213, the fourth input data block 214, and other data blocks not shown. The second data to be converted 22, arranged in 2H4W8C, may include the fifth input data block 221, the sixth input data block 222, the seventh input data block 223, the eighth input data block 224, and other data blocks not shown. The data elements in each input data block can be represented by H, W, C combination positions, such as H0W0C0, H0W0C1, H1W0C0, etc.

[0061] Figure 2 The data arrangement shown is merely an example; the data to be converted can be a three-dimensional tensor or data containing more dimensions. As long as there is a correspondence between the data element positions determined by the function operator configuration parameters between the input data block and the output data block, the data arrangement conversion device 100 disclosed herein can be used to complete the data arrangement conversion.

[0062] A function operator is a function operator used to perform a rearrangement operation on the data to be transformed. The configuration parameters of the function operator are parameters used to describe the data rearrangement task. Configuration parameters may include the input arrangement required by the function operator, the output arrangement, the size of the data to be transformed, the dimensional information involved in the rearrangement, and / or other parameters used to determine the positional relationship of data elements.

[0063] The position of the input data block within the data to be transformed can be determined by the H, W, and C dimension block numbers to which the input data block belongs. For example, if the size of the data to be transformed is 128H1W64C, and the input data block includes data elements H0W0C0-H0W0C63, then the input data block can be determined as the first data block in the W dimension, the first data block in the C dimension, and the first data block in the H dimension. The position of the input data block within the data to be transformed can be used to determine the dimensional range covered by the current input data block within the data to be transformed, and can also determine whether candidate data elements belong to the target data elements that the current input data block can provide.

[0064] The data elements corresponding to each of the multiple memory banks are selected from the input data block for each memory bank. The data elements corresponding to different memory banks can come from different element positions within the input data block. This allows the input data block to be matched with the memory banks before being written to the storage array.

[0065] The input rearrangement circuit 120 can acquire an input data block arranged according to a first data arrangement method. The input data block can be a data block within the data to be transformed, and the input data block includes multiple data elements. The first data arrangement method characterizes the arrangement rules of the multiple data elements in the input data block. For example, the multiple data elements can be arranged according to one or more dimensions of the data to be transformed.

[0066] The input rearrangement circuit 120 can combine the configuration parameters of the function operator and the position of the input data block in the data to be converted to determine the correspondence between the positions of multiple elements in the input data block and the multiple memory banks in the storage array 110, thereby selecting the data element corresponding to each memory bank.

[0067] For example, the input rearrangement circuit 120 can select data elements corresponding to multiple memory banks from multiple data elements in the input data block according to the correspondence between element positions and memory banks. For multiple memory banks, the input rearrangement circuit 120 can select multiple data elements respectively and provide the selected data elements to the subsequent data writing circuit 130. Thus, the data elements in the input data block have been rearranged on the input side according to the memory bank correspondence required by the current data rearrangement task before being written to the memory array 110.

[0068] Because the input rearrangement circuit 120 considers both the configuration parameters of the function operator and the position of the input data block in the data to be converted when selecting data elements, even if different input data blocks have the same first data arrangement, the input rearrangement circuit 120 can select different data elements corresponding to different memory banks based on the position of the different input data blocks in the data to be converted. This ensures that the data elements subsequently written to the memory array 110 meet the periodic access requirements during the data rearrangement process and provides a basis for the output data blocks to be formed according to the second data arrangement.

[0069] During the data layout transformation process, based on the correspondence between element positions and memory addresses in the input data block, it is possible to determine the data element that should be written to the storage array at a specific element position in the output data block, its memory address and storage cell address, the input data block in which the data element is located, its element position in the input data block, and its element position in the data to be transformed. Therefore, based on the predetermined input-output correspondence, data elements in the output data block are collected from the data to be transformed. This allows us to determine the element position in the data to be transformed of the data element at a specific element position in the output data block obtained based on the data layout transformation operator.

[0070] Based on the position of the data element in the input data block and the position of the input data block in the data to be converted, the position of the data element in the data to be converted can be determined. Based on the position of the data element in the data to be converted and the position of the data element at each element position in the output data block in the data to be converted, the memory bank corresponding to that data element can be determined.

[0071] The data writing circuit 130 is configured to write multiple data elements into the same storage row in the storage array in response to a first cycle type of the write cycle; and to write multiple data elements into multiple storage rows in the storage array in response to a second cycle type of the write cycle, based on a first data arrangement and configuration parameters.

[0072] A write cycle can be defined as the cycle corresponding to one write operation performed by the data write circuit 130. Within one write cycle, the data write circuit can receive multiple data elements from an input data block and write these multiple data elements from the input data block into the corresponding memory cells in the memory array.

[0073] The input rearrangement circuit 120, data writing circuit 130, data reading circuit 140, and output rearrangement circuit 150 can operate in a pipelined manner. In one data arrangement conversion cycle, the input rearrangement circuit 120 can input a new input data block; the data writing circuit 130 can write the first intermediate data block obtained in the previous data arrangement conversion cycle into the storage array 110; the data reading circuit 140 can read the target data element from the already written storage cell and generate an intermediate data block; and the output rearrangement circuit 150 can perform a second data rearrangement on the intermediate data block read from the previous data arrangement conversion cycle.

[0074] It is important to note that the actual operating cycles of the input rearrangement circuit 120, data writing circuit 130, data reading circuit 140, and output rearrangement circuit 150 are not exactly the same as the data arrangement conversion cycle. For example, in the first data arrangement conversion cycle, the input rearrangement circuit 120 reads the first input data block, but the data writing circuit 130, data reading circuit 140, and output rearrangement circuit 150 do not operate during this data arrangement conversion cycle. Therefore, the first data arrangement conversion cycle is the first actual operating cycle of the input rearrangement circuit 120 (i.e., the first data input cycle of the input rearrangement circuit 120). Similarly, the second data arrangement conversion cycle is the second actual operating cycle of the input rearrangement circuit 120 (i.e., the second data input cycle corresponding to the input rearrangement circuit 120), the first actual operating cycle of the data writing circuit 130 (i.e., the first data writing cycle corresponding to the data writing circuit 130), and the first actual operating cycle of the data reading circuit 140 (i.e., the first data reading cycle corresponding to the data reading circuit 140). The third data arrangement conversion cycle is the third actual working cycle of the input rearrangement circuit 120 (i.e., the third data input cycle corresponding to the input rearrangement circuit 120), the second actual working cycle of the data writing circuit 130 (i.e., the second data writing cycle corresponding to the data writing circuit 130), the second actual working cycle of the data reading circuit 140 (i.e., the second data reading cycle corresponding to the data reading circuit 140), and the first actual working cycle of the output rearrangement circuit 150 (i.e., the first data rearrangement cycle corresponding to the output rearrangement circuit 150).

[0075] The data layout conversion circuit 100 can divide the multiple cycles of the data layout conversion to be transformed into at least two different types of cycles. In the different types of cycles, the data writing circuit 130 and the data reading circuit 140 perform different operations. For example, the write cycles can be divided into a first cycle type and a second cycle type based on the sequence number of the write cycle. Taking a storage array comprising 64 memory banks, each comprising 64 memory cells, as an example, cycle 0-cycle 63 can be considered as the first cycle type, and cycle 64-cycle 127 as the second cycle type.

[0076] During a write cycle of the first cycle type, multiple data elements from the input data block are written to the same storage row in different banks of the storage array. The same storage row represents a group of storage cells with the same row address across multiple banks. For example, the data read circuit 140 can read 64B of data from the 0th row of banks Bank0, Bank1, ..., Bank63 based on the 0th row address, or it can read 64B of data from the 1st row of banks Bank0, Bank1, ..., Bank63 based on the 1st row address. If each bank stores 1B of data in one storage cell, the data read circuit 140 can read 64B of data from the same storage row across 64 banks.

[0077] During a write cycle of the second cycle type, multiple data elements from the input data block are written to different storage rows in different memory banks of the storage array. Multiple storage rows consist of multiple groups of memory cells with different row positions in the storage array. When multiple data elements are written to multiple storage rows, different data elements can correspond to different row positions. For example, multiple data elements can be written to memory cells located on the diagonal of the storage array.

[0078] For example, taking a case where the data to be converted includes multiple input data blocks, different input data blocks can be input into the data arrangement conversion device 100 at different write cycles. For one input data block, the data writing circuit 130 can write multiple data elements corresponding to it into the same storage row when the write cycle of the input data block is of the first cycle type. For another input data block, the data writing circuit 130 can write multiple data elements corresponding to it into multiple storage rows when the write cycle of the input data block is of the second cycle type.

[0079] In the write cycle corresponding to the first cycle type, the data write circuit 130 can simultaneously write data elements to storage cells at the same storage row position in multiple storage banks, so as to quickly fill a storage row in the storage array 110. In the write cycle corresponding to the second cycle type, the data write circuit 130 can simultaneously write data elements to storage cells at different row positions in multiple storage banks, thereby forming a cross-storage row distribution in the storage array 110.

[0080] This disclosure avoids writing all input data sequentially into the storage array 110 during the writing phase by having the data writing circuit 130 select different writing methods according to the type of writing cycle. Data elements are allocated to storage locations corresponding to the same or multiple storage rows according to the needs of the current data rearrangement task during writing. The subsequent data reading circuit 140 can then read multiple data elements based on these storage locations to obtain intermediate data blocks for output rearrangement.

[0081] Taking the transpose operator as an example, the input data block is arranged according to a first data arrangement, and the output data block can be arranged according to another arrangement. The data writing circuit 130 performs the same storage row write in the first cycle type and performs multiple storage row writes in the second cycle type, so that the arrangement of data elements inside the storage array 110 gradually approaches the arrangement relationship required for subsequent readings. As a result, the dependence on additional intermediate caches can be reduced, and the storage resource overhead during the data rearrangement process can be reduced.

[0082] The data read circuit 140 is configured to read multiple data elements from multiple storage rows in the storage array to obtain an intermediate data block in response to a second cycle type of read cycle and a first data arrangement; and to read multiple data elements from the same storage row in the storage array to obtain an intermediate data block in response to a first cycle type of read cycle.

[0083] A read cycle can be understood as the period corresponding to one read operation performed by the data read circuit. Within one read cycle, the data read circuit 140 can read multiple data elements from a single storage row in the storage array, or from different storage rows in the storage array. The number of data elements read by the data read circuit 140 can be determined by the configuration parameters of the function operator.

[0084] For example, if the configuration parameters of the function operator indicate that the data arrangement of the output data block is 64H1W1C, then the number of data elements read can be 64. The data reading circuit 140 can read one data element from one storage cell in each memory bank.

[0085] An intermediate data block is a data set formed by multiple data elements read from the storage array by the data reading circuit. The data arrangement of the intermediate data block can be the same as the first data arrangement or the same as the data arrangement of the output data block (i.e., the second data arrangement), and this disclosure does not limit it in this way.

[0086] The data read circuit 140 can be coupled to the storage array 110 and the output rearrangement circuit 150. The storage array 110 stores multiple data elements written by the data write circuit 130. The data read circuit 140 can read multiple data elements from the storage array 110 according to the type of read cycle, and provide the read multiple data elements as intermediate data blocks to the output rearrangement circuit 150.

[0087] In response to the read cycle being of the second cycle type, the data read circuit 140 can read multiple data elements from multiple storage rows in the storage array 110 based on the first data arrangement to obtain an intermediate data block. The data read circuit 140 determines the storage row of each data element in each storage unit based on the first data arrangement, ensuring that the read data elements correspond to the intermediate data arrangement required for the current data rearrangement task. The order of data elements in the intermediate data block may differ from the order of data elements in the input data block or the order of data elements in the output data block. The intermediate data arrangement may be the same as the first data arrangement.

[0088] In the read cycle corresponding to the second cycle type, the data read circuit 140 can read multiple data elements from different storage rows. For example, it can read one data element from a storage row of the first storage bank and another data element from another storage row of the second storage bank. Through this cross-row read method, the data read circuit 140 can read scattered data elements from the storage array 110 and combine these data elements into an intermediate data block.

[0089] In response to a read cycle of type 1, the data read circuit 140 can read multiple data elements from the same storage row in the storage array 110 to obtain an intermediate data block. At this time, the multiple data elements may come from multiple storage banks, but these data elements correspond to the same storage row in their respective storage banks. Through this read method, the data read circuit 140 can obtain a horizontally arranged set of data elements from the storage array 110.

[0090] The first and second cycle types correspond to different reading methods. In the reading cycle corresponding to the first cycle type, a group of data elements that are already in the same row position can be read from the same storage row; in the reading cycle corresponding to the second cycle type, scattered data elements can be read from multiple storage rows. The two reading methods can be combined with the different writing methods corresponding to the aforementioned data writing circuit 130 to ensure that the data elements in the storage array 110 are read sequentially according to the data rearrangement process.

[0091] For example, in the write or read cycle corresponding to the first cycle type, the data write circuit 130 writes data to the same storage row, and the data read circuit 140 reads multiple data elements from the same storage row of the storage array. In the write or read cycle corresponding to the second cycle type, the data write circuit 130 writes data to different storage rows, and the data read circuit 140 reads multiple data elements from different storage rows of the storage array.

[0092] If the input data block is written to the storage array 110 according to the first data arrangement, and different output data blocks need to obtain corresponding data elements from multiple input data blocks, the data reading circuit 140 can read data elements from multiple storage rows in the second cycle type. Thus, data elements originally distributed in different storage rows can be combined in the same reading cycle to form the intermediate data block required for subsequent output rearrangement.

[0093] If a storage row in storage array 110 already contains a set of data elements that can participate in the current output rearrangement, the data read circuit 140 can read multiple data elements from the same storage row in the first cycle type. This method reduces cross-row selection complexity and allows the reading process to be performed along the storage row dimension.

[0094] The data reading circuit 140 does not need to change the value of the data elements. The function of the data reading circuit 140 is to determine the reading position according to the type of reading cycle and read multiple data elements from the storage array 110. After the multiple data elements read form an intermediate data block, the output rearrangement circuit 150 performs subsequent data rearrangement according to the target layout requirements.

[0095] This disclosure enables the storage array 110 to simultaneously support row-by-row reading and cross-row reading by employing different reading methods in different reading cycles through the data reading circuit 140. In transpose-based data rearrangement scenarios, input data elements may be written to the storage array 110 according to different storage row relationships. The data reading circuit 140 reads data elements from the same or multiple storage rows based on the type of reading cycle, thereby converting the already formed internal arrangement in the storage array 110 into intermediate data blocks, providing a basis for the output data blocks to be formed according to a second data arrangement method.

[0096] A storage row in the storage array 110 can store multiple data elements from the first input data block 211, the second input data block 212, and the third input data block 213. For example, the first storage row in the storage array 110 may include the data elements corresponding to element positions H0W3C5 and H0W3C7 in the first input data block 211, the data elements corresponding to element positions H0W3C9, H0W3C11, H0W3C13, and H0W3C15 in the second input data block 212, and the data elements corresponding to H0W3C17 and H0W3C19 in the third input data block 213.

[0097] The output rearrangement circuit 150 is configured to rearrange multiple data elements in the intermediate data block to obtain an output data block arranged according to the second data arrangement method. The output rearrangement circuit 150 can adjust the output order through position mapping between the first and second data arrangement methods. Therefore, while completing the data arrangement conversion, it ensures that the obtained output data block can adapt to the data format requirements of subsequent computing units or storage circuits.

[0098] The first data layout method and the second data layout method are used to represent the data layout method of the data block. The first data layout method can represent the layout corresponding to the input data block when it is read from the storage circuit. The second data layout method can represent the target layout that the output data block needs to satisfy. The first data layout method and the second data layout method can be the same or different, and this disclosure does not limit them. In one example, the first data layout method is 2H4W8C, and the second data layout method can be 8C2H4W.

[0099] The data layout conversion apparatus disclosed herein, in a first cycle type, uses a data writing circuit to write multiple data elements to the same storage row, and a data reading circuit to read multiple data elements from the same storage row. In a second cycle type, multiple data elements are written to multiple storage rows using a data writing circuit, and multiple data elements are read from multiple storage rows using a data reading circuit. This allows the two cycle types to employ different storage row write and read relationships, enabling data elements written to the storage array in the previous cycle type to be read and combined in the subsequent cycle type or a later corresponding cycle. The storage array can simultaneously store data elements corresponding to different cycle types. Therefore, data layout conversion can be achieved using a storage array smaller than the size of the data to be converted, improving storage array utilization, reducing cache overhead, thereby reducing hardware area and cost, and improving data layout conversion efficiency.

[0100] In some embodiments, the data arrangement conversion device 100 further includes a controller. The controller receives configuration information from the compiler or upper-level scheduling logic, and generates a select signal and a write enable signal based on the configuration information to control the input rearrangement circuit 120, data writing circuit 130, data reading circuit 140, and output rearrangement circuit 150 to perform their respective functions. The controller can be connected to… Figure 1 The input rearrangement circuit 120, data writing circuit 130, data reading circuit 140, and output rearrangement circuit 150 are respectively coupled. The controller changes the mapping relationship between the element positions in the data to be converted and the element positions in the output data block by selecting a signal, thereby realizing the operation corresponding to different data arrangement conversion operators without changing the hardware physical connection relationship of the data arrangement conversion device 100.

[0101] Figure 3 This is a structural diagram of a data layout conversion device provided in an embodiment of this disclosure. Figure 3 As shown, the data arrangement conversion device includes a storage array 110, an input rearrangement circuit 120, a data writing circuit 130, a data reading circuit 140, and an output rearrangement circuit 150. The storage array 110 includes multiple storage cells, each storage cell having multiple storage units, and each storage unit storing data elements.

[0102] In some embodiments, the input rearrangement circuit includes a plurality of first multiplexers, each configured to correspond to a plurality of memory banks; the first multiplexers are configured to select a target data element from a plurality of data elements of the input data block based on configuration parameters of a function operator and the position of the input data block in the data to be converted, and output the target data element.

[0103] For example, the number of first multiplexers included in the input rearrangement circuit 120 is the same as the number of memory banks included in the memory array 110, and the data elements output by each first multiplexer can be written into the corresponding memory bank.

[0104] like Figure 3 As shown, taking a storage array comprising 64 memory banks as an example, the input rearrangement circuit 120 (i.e., MUX0) may include 64 first multiplexers, such as first multiplexer 331, first multiplexer 332, and first multiplexer 333, etc. The multiple target data elements output by these 64 first multiplexers can be organized according to the first data arrangement method to generate intermediate data blocks.

[0105] For example, the first multiplexer can be a 64-to-1 multiplexer. Taking an input data block comprising 64 data elements as an example, the first multiplexer can select one data element from the 64 data elements. Multiple first multiplexers can operate in parallel to determine the target data element corresponding to each of the 64 memory banks within a single data input cycle.

[0106] For example, if the data width of the input data block is 64 bytes, then MUX0 can include 64 first multiplexers, each of which is a 64-to-1 selector. Each first multiplexer is used to select a 1-byte data element from the 64-byte input data block for output, and the output 1-byte data element will subsequently be written into the memory corresponding to that first multiplexer. The first multiplexer selects a target data element from multiple data elements in the input data block and outputs the target data element.

[0107] The first multiplexer is further configured to: determine the position of the first element of the target data element in the input data block based on the first selection signal; and output the target data element based on the position of the first element.

[0108] The first selection signal is used to control the first multiplexer in the input rearrangement circuit 120. The controller can determine the position of the target data element corresponding to each memory bank within the input data block based on the configuration parameters of the data arrangement conversion operator, the first data arrangement method, and the addresses of multiple memory banks, and generate the first selection signal accordingly. For example, memory banks Bank0, Bank1, ..., Bank63 correspond to 64 first multiplexers in the input rearrangement circuit 120. For any memory bank, the controller can determine its corresponding element position in the input data block based on its address, and determine, in conjunction with the configuration parameters, which element position in the current input data block the memory bank should retrieve data from. The first selection signal is provided to the corresponding first multiplexer, causing the first multiplexer to select the target data element from the input data block. For example, the first selection signal may include a select signal, which instructs the first multiplexer to select and output the data element from a specific element position in the input data block.

[0109] The first element position can be one of the element positions in the sequence of positions 0 to 63 in the input data block. The first selection signal can be a select signal, which instructs the first multiplexer to select and output the data element from a certain element position in the input data block. For the 64 first multiplexers in the input rearrangement circuit 120, the 64 first multiplexers will receive 64 first selection signals from the controller within the same data read cycle. These 64 first selection signals are used to instruct the corresponding first selection signal to select a first element position in the input data block and output the data element corresponding to that first element position. It should be noted that the first element positions selected by the 64 first selection signals are all different, thereby realizing the conversion of the input data block of the first data arrangement method into the first intermediate data block of the second data arrangement method.

[0110] For example, the input rearrangement circuit 120 can support different data element bit widths. If a data element is 1B, a 64B input data block includes 64 element positions. If a data element is 2B, a 64B input data block includes 32 element positions. The input rearrangement circuit 120 can select according to the 32 element positions, or split a data element into multiple byte paths for synchronous selection. The specific structure of the input rearrangement circuit 120 can be determined according to one or more of the on-chip bus bit width, data type, and subsequent memory organization method.

[0111] The first selection signal can be a signal generated by controller 30. For example... Figure 3 As shown, Figure 3 A data layout conversion device including a controller 30 is shown. The controller 30 can respectively input rearrangement circuit 120, data writing circuit 130, data reading circuit 140, and data rearrangement circuit 150. The controller 30 can generate a first selection signal based on the configuration parameters of the data layout conversion operator, a first data layout mode, and a memory address. Thus, the controller 30 can convert the configuration parameters of the data layout conversion operator on the software side or compiler side into a hardware-executable strobe signal.

[0112] In some embodiments, the data layout conversion apparatus further includes a controller configured to: determine the position of the input data block in the data to be converted, a first data layout method, the size and configuration parameters of the data to be converted; determine the shift number corresponding to multiple data elements based on the position of the input data block in the data to be converted, the first data layout method, the size and configuration parameters of the data to be converted; and control the input rearrangement circuit to select data elements corresponding to multiple memory banks from the multiple data elements in the input data block based on the shift number.

[0113] The controller 30 can determine the input spatial location mapping relationship based on the first data arrangement of the input data block and the data arrangement of the multiple data elements selected by the multiple first multiplexers. The input spatial location mapping relationship can indicate which element position in the input data block the corresponding data element of the storage bank should come from.

[0114] The controller can perform shift operations on multiple data elements in the input data block using a data rearrangement circuit based on a predetermined shift number, to obtain multiple data elements. The controller can determine the shift number corresponding to the multiple data elements based on the position of the input data block in the data to be converted, the first data arrangement method, the size of the data to be converted, and configuration parameters. The shift number represents the number of data elements in the input data block that need to be moved relative to the memory bank. The input rearrangement circuit 120 completes the selection of the target data element based on this shift number.

[0115] The controller 30 first acquires the first data arrangement method, the position of the input data block in the data to be converted, the size of the storage array 110, and the configuration parameters of the function operator. Based on the first data arrangement method and the configuration parameters, the controller 30 determines the dimensional correspondence of multiple data elements in the input data block before and after rearrangement; then, based on the position of the input data block in the data to be converted, it determines the cycle number of the current input data block in a data arrangement conversion process. Based on the size of the storage array 110, the cycle number is mapped to the row address range supported by the storage array 110, thereby obtaining the shift number corresponding to the input data block.

[0116] Taking a storage array 110 comprising N storage banks, each containing N storage cells, as an example, the controller 30 can convert the position of the current input data block within the data to be converted into a period number i, and then perform a modulo operation on the period number i based on N to obtain the shift value corresponding to the current input data block. This modulo operation ensures that the shift value falls within the range of 0 to N-1, preventing the subsequently generated row address from exceeding the valid row address range of the storage array 110.

[0117] The controller 30 generates a first selection signal for each first multiplexer based on the determined shift value, to control the first multiplexer to select and output a data element from the input data block. For example, if it is determined that the third memory bank (memory bank address bank3) corresponds to the element position H0W3C5 in the input data block, the data element corresponding to memory bank 3 can be read from H0W3C5 using the first selection signal.

[0118] The controller is further configured to: determine a first correspondence between the positions of multiple data elements in the input data block and the addresses of multiple memory banks based on the position of the input data block in the data to be converted, the first data arrangement, the size of the data to be converted, and the configuration parameters; and determine the shift bit based on the first correspondence.

[0119] For example, taking an input data block comprising N data elements and N memory banks, the first correspondence can be the correspondence between the positions of the N elements in the input data block and the addresses of the N memory banks. In the i-th input data block, this correspondence can be shifted relative to the 0th input data block. The shift amount can be the shift number corresponding to the first selection signal.

[0120] For example, taking an input data block containing 64 data elements as an example, in the 0th input data block, the first multiplexer 331 can select H0W0C0, the first multiplexer 332 can select H0W0C1, and the first multiplexer 333 can select H0W0C2. In the 1st input data block, the first multiplexer 331 can select H1W0C63, the first multiplexer 332 can select H1W0C0, and the first multiplexer 333 can select H1W0C1.

[0121] The first correspondence can be represented by entries, each of which can include the position of the first element within the input data block and the memory address. When processing an input data block, the controller 30 can look up or calculate the corresponding entry based on the position of the input data block in the data to be converted, and convert the entry into the first selection signal of multiple first multiplexers. This method is suitable for scenarios where there are many configuration parameters for function operators and the relationship between the position of the input data block and the memory address is not easily expressed by simple shifting. The first correspondence can also be directly represented by a shift number. If the positions of multiple elements in the input data block are numbered from 0 to N-1, and the multiple memory addresses are also numbered from 0 to N-1, the controller 30 can determine a shift number based on the current position of the input data block, and then map each memory address to an element position in the input data block. Thus, it is not necessary to save the first correspondence item by item; only the shift number corresponding to each first multiplexer needs to be saved or calculated.

[0122] Configuration parameters can indicate the first data layout and the size of the data to be converted. If the first data layout is 1H1W64C, then adjacent element positions in the input data block can correspond to adjacent data elements in the C direction. If the position of the input data block in the data to be converted increases along the H direction, then the input shift number can change with the block number in the H direction. Configuration parameters can limit the dimensions selected on the input side. For example, configuration parameters can indicate that the current transpose operation needs to interchange the layout relationships in the H and C directions. Controller 30 can then determine how the C-direction element positions in the input data block are mapped to multiple memory banks. If the configuration parameters indicate a layout relationship between another set of dimensions, then controller 30 can correspondingly generate another set of first correspondences.

[0123] The position of the input data block within the data to be converted can be provided by the block count result of the input address generation unit. For example, the input address generation unit can update the block number of the current input data block each time it generates a first access address.

[0124] like Figure 3 As shown, the data writing circuit 130 may include multiple data distributors, each configured to correspond to a plurality of first multiplexers in the input rearrangement circuit 120, and each data distributor is coupled to a plurality of memory cells in the memory bank. A data distributor is configured to, in response to a first cycle type, write multiple data elements output by the first multiplexer corresponding to the data distributor into first memory cells belonging to the same memory row in the plurality of memory banks corresponding to the data distributor; and in response to a second cycle type, write multiple data elements output by the first multiplexer corresponding to the data distributor into second memory cells belonging to multiple memory rows in the plurality of memory banks corresponding to the data distributor.

[0125] For example, the number of data distributors included in the data writing circuit 130 is the same as the number of first multiplexers included in the input rearrangement circuit 120, and also the same as the number of memory banks included in the memory array 110. Each data distributor corresponds to a different memory bank, and each data distributor is used to write data elements into the corresponding memory bank. Figure 3As shown, taking a storage bank comprising 64 storage cells as an example, the data writing circuit 130 includes 64 data distributors (DEMUX), such as data distributors 341, 342, and 343, etc. Each data distributor can correspond to one storage bank. For example, data distributor 341 can correspond to storage bank 111, data distributor 342 can correspond to storage bank 112, data distributor 343 can correspond to storage bank 113, and so on. Each data distributor receives candidate data elements output from the corresponding first multiplexer, and writes the candidate data elements as target data elements into the target storage cell of the corresponding storage bank if the candidate data elements meet preset conditions.

[0126] Data distributors can employ a one-input, multiple-output (ITO) gating structure (e.g., 1to64). The input to a data distributor is a candidate data element, and its output is coupled to multiple memory cells within the corresponding memory bank. The data distributor selects a row address from multiple row addresses within its corresponding memory bank for writing. The row address can be the depth of a memory cell within the memory bank. Thus, each data distributor can write one data element to its corresponding memory bank within a single data write cycle, and different data distributors can write to different memory banks in parallel.

[0127] The data distributor can employ a decoder-plus-write-enable structure. The second selection signal is first decoded through row address to determine multiple row write-enable signals, and then ANDed with the write mask signal to drive the write terminal of the corresponding memory cell. This reduces the number of data lines and facilitates adaptation to memory arrays. If SRAM is used as the memory bank, the second selection signal can include the SRAM row address and the write-enable write mask signal.

[0128] The second selection signal is used to control the data distributor in the data writing circuit 130. The controller can determine the target storage row to be written to the target data element based on the data collection stage corresponding to the target data element, the position of the input data block in the data to be converted, and the storage address corresponding to the target data element, and generate the second selection signal accordingly.

[0129] If the write cycle type is the first cycle type, the data distributor writes the data element output by the first multiplexer to the first storage cell belonging to the same storage row in the corresponding memory bank. In this case, the write row addresses corresponding to multiple memory banks can be the same. For example, memory banks Bank0, Bank1, ..., Bank63 all write to the i-th row. If the write cycle type is the second cycle type, the data distributor writes the data element output by the first multiplexer to the second storage cell belonging to multiple storage rows in the corresponding memory bank. In this case, the write row addresses corresponding to different memory banks can be different. For example, writing to the storage cell in the 0th row of memory bank Bank0, the storage cell in the 1st row of memory bank Bank1, and the storage cell in the 2nd row of memory bank Bank2. The second selection signal can include the row address itself or a decoded write enable signal.

[0130] The controller 30 determines the shift value corresponding to the input data block based on the first data arrangement, the position of the input data block in the data to be converted, and the size and configuration parameters of the storage array 110. This shift value can be used by the input rearrangement circuit 120 to generate a first selection signal or by the data writing circuit 130 to generate a second selection signal. Therefore, the selection strategy of the input rearrangement circuit 120 and the writing strategy of the data writing circuit 130 can be kept consistent.

[0131] If the write cycle type is a first cycle type, the controller 30 determines multiple first row addresses corresponding to the multiple memory banks based on the shift bit and the memory bank addresses corresponding to the multiple memory banks. Multiple first row addresses can have the same value, thus allowing multiple data elements to be written to the same memory bank. Even if the controller 30 generates a separate first row address for each memory bank, as long as these first row addresses point to the same memory bank, they are considered to be written to the same memory bank. If the write cycle type is a second cycle type, the controller 30 determines multiple second row addresses corresponding to the multiple memory banks based on the shift bit and the memory bank addresses corresponding to the multiple memory banks. Multiple second row addresses can change with the memory bank addresses, thus allowing multiple data elements to be written to multiple memory banks.

[0132] The target storage unit is determined by the row address of the corresponding storage bank. The storage bank address can be determined by hardware connection relationships, and the row address corresponding to the target storage unit can be determined by the second selection signal. For example, the data distributor 341 can correspond to storage bank 111, and the second selection signal indicates that the row address is 12, then the target storage unit is the storage unit with a depth of 12 in storage bank 111.

[0133] In some embodiments, the data distributor is further configured to: determine, based on a second selection signal, a first row address of the first storage unit in the storage bank corresponding to the data distributor, or determine a second row address of the second storage unit in the storage bank corresponding to the data distributor; write data elements output by the first multiplexer corresponding to the data distributor into the first storage unit based on the first row address; or write data elements output by the first multiplexer corresponding to the data distributor into the second storage unit based on the second row address.

[0134] The data writing mode executed by the data writing circuit within the period corresponding to the first cycle type is called the first operating mode (i.e., pattern A), and the data writing mode executed within the period corresponding to the second cycle type is called the second operating mode (i.e., pattern B). The data writing circuit 130 can write multiple data elements to the same storage row in the storage array 110 in the first operating mode. The storage array 110 includes N storage banks, and each storage bank includes N storage cells.

[0135] In some embodiments, the type and corresponding operating mode of the current write cycle or read cycle can be determined based on the actual operating cycle number of each circuit. For any of the input rearrangement circuit, data write circuit, data read circuit, and output rearrangement circuit, i represents the actual operating cycle number of the circuit, and N represents the number of memory banks included in the memory array. In some embodiments, the quotient of i and N can be rounded down, and the remainder obtained by dividing the rounded result by 2 can be used to determine the type of the current cycle. When (i / N)%2 = 0, it is determined that the circuit determines the type of the current cycle to be the first cycle type, and the current actual operating cycle executes the first operating mode patternA; when (i / N)%2 = 1, it is determined that the circuit determines the type of the current cycle to be the first cycle type, and the circuit executes the second operating mode patternB in the current actual operating cycle.

[0136] The actual operating cycle number of each circuit is counted independently based on the cycle in which that circuit begins executing the current data rearrangement task. Since pipelines can be configured between the input rearrangement circuit, data write circuit, data read circuit, and output rearrangement circuit, the actual operating cycle numbers of each circuit within the same physical cycle can be different. Therefore, the write cycle type and read cycle type within the same physical cycle can also be different.

[0137] `bank_id` represents the identifier of the current storage bank, and `i` represents the cycle number of the current write cycle during the data layout transition. The controller 30 can generate a second selection signal for multiple data distributors based on the current write cycle number `i`. The write row address indicated by this second selection signal can be represented as: sel_demux_bank_id=i%N (1) Where sel_demux_bank_id is the write row address corresponding to the data distributor, and N is the number of memory banks in the storage array. Within the same write cycle, data distributors corresponding to multiple memory banks can obtain the same write row address. The data write circuit 130 can thus write multiple data elements into memory cells belonging to the same memory row in multiple memory banks.

[0138] Taking N=64 as an example, when i=0, sel_demux_bank_id=0, and the data writing circuit 130 can write the 64 data elements output by the input rearrangement circuit 120 into the 0th row of storage units of Bank0 to Bank63 respectively. When i=1, sel_demux_bank_id=1, and the data writing circuit 130 can write the 64 data elements corresponding to the next input data block into the 1st row of storage units of storage banks Bank0, Bank1, ..., Bank63 respectively. Similarly, when i=63, the data writing circuit 130 can write the corresponding 64 data elements into the 63rd row of storage units of storage banks Bank0, Bank1, ..., Bank63 respectively.

[0139] Table 1

[0140] Table 1 shows the data arrangement in the storage array under the first operating mode provided in this disclosure. In the first operating mode, a shift operation can ensure that the data elements in the storage cells located on the diagonal of the storage array are the data elements H0W0C0, H1W0C0, H2W0C0, H3W0C0…, H63W0C0, as desired by the transpose operator, while maintaining that all data elements in the input data block are located in the same storage row. That is, the order of the data elements on the diagonal is the transposed element data.

[0141] In the first operating mode, the data writing process can be horizontal. During a single write cycle, multiple data elements enter different memory banks, but these elements share the same row address within their respective banks. An input data block, after being processed by the input rearrangement circuit 120, can be written as a group of data to the same memory row. After N consecutive write cycles, the N memory rows in the memory array 110 can be filled sequentially.

[0142] The write method in the first operating mode can be used to establish the data foundation required for subsequent cross-line readings. Since the input rearrangement circuit 120 has adjusted the correspondence between multiple data elements and the memory bank according to the position of the input data block in the data to be converted, even if the data writing circuit 130 writes multiple data elements to the same memory row, different memory rows can have different input-side shift relationships. The subsequent data reading circuit 140 can read data elements from multiple memory rows separately to form intermediate data blocks for output rearrangement.

[0143] The data writing circuit 130 can write multiple data elements to multiple storage rows in the storage array 110 in the second operating mode. The controller 30 can generate a second selection signal for each of the multiple data distributors based on the current write cycle number i and the storage bank address bank_id. The write row address indicated by this second selection signal can be represented as: sel_demux_bank_id=(bank_id+i)%N (2) It can be seen that the write row address in equation (2) is determined by both the bank address (bank_id) and the current write cycle number (i). Since different banks have different bank_ids, the write row addresses obtained by multiple data distributors can be different within the same write cycle. Thus, the data write circuit 130 can write multiple data elements into multiple storage rows respectively.

[0144] Taking N=64 as an example, when i=0, the write line address corresponding to memory bank Bank0 is 0, the write line address corresponding to memory bank Bank1 is 1, the write line address corresponding to memory bank Bank2 is 2, and so on, with the write line address corresponding to memory bank Bank63 being 63. In this case, the 64 data elements in the same input data block can be written distributed along multiple memory lines. When i=1, the write line address corresponding to memory bank Bank0 is 1, the write line address corresponding to memory bank Bank1 is 2, the write line address corresponding to memory bank Bank2 is 3, and the write line address corresponding to memory bank Bank63 is 0. Therefore, the write line address shifts cyclically as the write cycle progresses.

[0145] Table 2

[0146] In the second operating mode, the data writing and reading methods from the storage array are shown in Table 2. The dark gray areas in Table 2 represent the read and write positions for cycle 64, and the light gray areas represent the write and read positions for cycle 65. As shown in Table 2, in the second operating mode, data elements H0W0C0, H1W0C0, H2W0C0, ..., H62W0C0 and H63W0C0 in the data to be converted are read from the storage array (the element positions are indicated by strikethrough in the dark gray areas of Table 2). Data elements H0W0C0, H0W0C1, H0W0C2, ..., H0W0C62 and H0W0C63 in the data to be converted are written to different storage banks in the storage array. The data writing process in the second operating mode can be diagonal writing. Within a write cycle, multiple data elements are written to different storage banks, corresponding to different storage rows in their respective storage banks. Since the write row address changes according to both the storage bank address and the cycle number, multiple data elements form a cross-row distribution in storage array 110.

[0147] The write method in the second operating mode can be coordinated with the lateral read on the read side. When the data read circuit 140 reads multiple data elements from the same storage row in the same cycle or corresponding pipeline cycle, the data write circuit 130 can write the newly input data elements to multiple storage rows in a distributed manner. Thus, the storage array 110 can gradually write the next set of data to be converted while outputting the already formed data blocks, reducing the waiting cycle.

[0148] In some embodiments, the controller 30 can perform a modulo operation on the sum of the bank address and the period number (bank_id+i) to ensure that the write row address always falls within the range of 0 to N-1. For the scenario where N=64, the modulo operation can be implemented by retaining the lower 6 bits of the binary index of the bank address, thereby reducing the hardware computational complexity. This implementation is suitable for a storage array 110 consisting of 64 banks and 64 storage cells per bank.

[0149] The data writing circuit 130 can be configured to write a temporary register, which is used to receive the target data element output by the first multiplexer and write it to the target memory cell after the row address is stabilized. This temporary register structure helps improve timing and does not change the function of the data distributor in determining the write position based on the second selection signal.

[0150] In some embodiments, the controller in the data layout conversion device is configured to: in response to a first cycle type, control the data writing circuit to write multiple data elements into the same storage row of multiple storage banks based on a first data layout method, the position of the input data block in the data to be converted, the size of the storage array, and configuration parameters; and in response to a second cycle type, control the data writing circuit to write multiple data elements into multiple storage rows in the storage array based on the first data layout method, the position of the input data block in the data to be converted, the size of the storage array, and configuration parameters.

[0151] In some embodiments, the controller 30 in the data layout conversion device 100 may be coupled to the data writing circuit 130 to control the writing mode of the data writing circuit 130 according to the type of the writing cycle. The type of writing cycle may include a first cycle type and a second cycle type. The first cycle type corresponds to writing multiple data elements into the same storage row of multiple memory banks, and the second cycle type corresponds to writing multiple data elements into multiple storage rows in the storage array.

[0152] The controller 30 can acquire the first data arrangement, the position of the input data block in the data to be transformed, the size of the storage array 110, and the configuration parameters of the function operator. The size of the storage array 110 may include the number of storage blocks and the number of storage cells in each storage block. The configuration parameters may indicate the rearrangement direction required by the function operator, the data block size, or the dimension involved in the rearrangement.

[0153] The controller 30 can determine the initial correspondence between multiple data elements in the input data block and multiple memory banks based on the first data arrangement and configuration parameters. Based on the position of the input data block in the data to be converted, the initial correspondence is offset. According to the size of the storage array 110, the offset correspondence is restricted to the range of memory banks and rows supported by the storage array 110, thereby obtaining the write position of multiple data elements in the current write cycle.

[0154] In response to a write cycle type of the first cycle type, the controller 30 can generate a selection signal for controlling the data write circuit 130 based on the aforementioned write position. This selection signal can include write row addresses corresponding to multiple memory banks. For the first cycle type, the controller 30 can direct the write row addresses corresponding to multiple memory banks to the same memory row. Based on this selection signal, the data write circuit 130 writes multiple data elements to memory cells belonging to the same memory row within the multiple memory banks.

[0155] In the first cycle type, the controller 30 first determines the storage row address corresponding to the current write cycle based on the position of the input data block in the data to be converted; then, it constrains the range of the storage row address according to the size of the storage array 110, ensuring that the storage row address falls within the range of row addresses supported by the storage array 110. The storage row address is then used as the write row address shared by multiple storage banks. Thus, multiple data elements are written to different storage banks, and these data elements correspond to the same storage row in multiple storage banks.

[0156] In response to the write cycle being of type two, controller 30 can generate write row addresses corresponding to multiple memory banks based on the first data arrangement, the position of the input data block in the data to be converted, and the size and configuration parameters of the storage array 110. Unlike the first cycle type, the multiple write row addresses under the second cycle type can be different from each other. Controller 30 can determine the base row address of the current write cycle based on the position of the input data block in the data to be converted, and then offset this base row address by combining it with the memory bank addresses of the multiple memory banks to obtain the write row addresses corresponding to the multiple memory banks.

[0157] In the second cycle type, the controller 30 first determines the arrangement direction of multiple data elements in the input data block according to the first data arrangement method and configuration parameters; then, it determines the offset of the current input data block relative to the rearrangement window according to the position of the input data block in the data to be converted; then, it combines this offset with the memory bank addresses corresponding to the multiple memory banks to obtain multiple candidate row addresses; finally, it performs modulo or truncation processing on the multiple candidate row addresses according to the size of the memory array 110 to obtain the write row addresses corresponding to the multiple memory banks. Based on these write row addresses, the data writing circuit 130 writes multiple data elements into multiple memory rows in the memory array.

[0158] Taking a storage array 110 comprising N storage banks, each storage bank comprising N storage cells as an example, the controller 30 can convert the position of the input data block in the data to be converted into the cycle number i within the rearrangement window of the current write cycle. For the first cycle type, the controller 30 can use the result of taking i modulo N as the write row address shared by multiple storage banks. For the second cycle type, the controller 30 can add the storage bank address of each storage bank to i and take the modulo N to obtain the write row address corresponding to each storage bank. Thus, writing to the same storage row and writing to multiple storage rows can be implemented respectively.

[0159] The modulo or truncation processing described above is used to restrict the write row address to the range of valid row addresses supported by the storage array 110. For example, when the storage bank includes 64 storage cells, the row address of a storage cell can be represented by 6 bits. The controller 30 can obtain a row address in the range of 0 to 63 by changing the position of the data element in the 6-bit row address.

[0160] The controller 30 first determines the correspondence between data elements and memory banks, then generates write row addresses corresponding to the same or multiple memory rows based on the type of write cycle, and finally causes the data write circuit 130 to perform the write according to the obtained write row addresses. This ensures that the write control process has a clear generation path and can support the formation of intermediate data blocks in the subsequent read process.

[0161] In some embodiments, the controller is further configured to: determine the shift number corresponding to the input data block based on a first data arrangement, the position of the input data block in the data to be converted, the size of the storage array, and configuration parameters; in response to a write cycle of a first cycle type, determine multiple first row addresses corresponding to the multiple storage banks based on the shift number and the storage bank addresses corresponding to the multiple storage banks respectively; based on the multiple first row addresses, control the data writing circuit to write multiple data elements into the same storage row of the multiple storage banks; in response to a write cycle of a second cycle type, determine multiple second row addresses corresponding to the multiple storage banks based on the shift number and the storage bank addresses corresponding to the multiple storage banks respectively; based on the multiple second row addresses, control the data writing circuit to write multiple data elements into multiple storage rows in the storage array.

[0162] The shift value represents the offset of a data element in the current input data block relative to multiple memory banks or rows. The shift value varies with the position of the input data block within the data to be transformed, and is used to determine the row address relationship that should be used when writing the current input data block to the memory array.

[0163] The first row address can be a row address determined for multiple memory banks in the write cycle corresponding to the first cycle type. The first row address can be generated for multiple memory banks, and multiple first row addresses point to the same memory row.

[0164] The second row address can be a row address determined separately for multiple memory banks in the write cycle corresponding to the second cycle type. Multiple second row addresses can be different from each other, allowing multiple data elements to be written to multiple memory rows respectively.

[0165] The memory bank address can be the address of the memory bank in the memory array (e.g., 0X00011) or the memory bank identifier (e.g., the serial number bank55 in the memory array). For example, when the memory array includes N memory banks, each memory bank can have a memory bank identifier from 0 to N-1.

[0166] In some embodiments, the controller 30 in the data layout conversion device 100 may be coupled to the data writing circuit 130. The controller 30 is used to determine the shift number corresponding to the input data block and generate the row address required by the data writing circuit 130 according to the type of writing cycle, so as to control multiple data elements to be written to the same storage row or multiple storage rows.

[0167] In response to the write cycle type being a first cycle type, the controller 30 can determine multiple first row addresses corresponding to the multiple memory banks based on the shift bit and the memory bank addresses corresponding to the multiple memory banks respectively. The first cycle type is used to write multiple data elements to the same memory row of multiple memory banks. Therefore, the controller 30 can make multiple first row addresses all point to the same row position determined by the shift bit.

[0168] In the write cycle corresponding to the first cycle type, the controller 30 can use the shift bit as the reference row address and configure this reference row address as the first row address corresponding to multiple memory banks. For example, if the memory bank addresses of the multiple memory banks are 0 to N-1, the controller 30 can generate a first row address for each memory bank address, and all the first row addresses are equal to the reference row address. After receiving the multiple first row addresses, the data write circuit 130 writes the multiple data elements into the memory cells belonging to the same memory row in the multiple memory banks.

[0169] In response to a write cycle of type two, controller 30 can determine multiple second row addresses corresponding to the multiple memory banks based on the shift bit and the memory bank addresses corresponding to the multiple memory banks respectively. In the write cycle corresponding to the second cycle type, multiple data elements can be written to multiple memory rows in the storage array, causing the second row address to change with the memory bank address.

[0170] In the write cycle corresponding to the second cycle type, the controller 30 can use the shift bit as a reference offset and combine the reference offset with multiple memory bank addresses to obtain multiple candidate row addresses. Then, according to the size of the memory array 110, the multiple candidate row addresses are moduloed or truncated to obtain multiple second row addresses. Through this process, the second row addresses corresponding to different memory banks can be different, and all of them are within the range of valid row addresses supported by the memory array 110.

[0171] Taking N memory banks as an example, for the k-th memory bank, the controller 30 can add the shift bit to the memory bank address k, and perform modulo operation on the N sums to obtain the second row address corresponding to the k-th memory bank. Thus, the second row address corresponding to the memory bank will cyclically change as the memory bank address increases, thereby writing multiple data elements into multiple memory rows.

[0172] The data writing circuit 130 may include multiple write paths. Each write path corresponds to a memory bank. After the controller 30 generates multiple first row addresses or multiple second row addresses, it can provide each row address to the corresponding write path. Based on the received row address, each write path selects a target memory cell in the corresponding memory bank and writes a data element to the target memory cell. Thus, the same memory array 110 can form different internal data arrangements in different write cycles, providing a basis for subsequent reading of intermediate data blocks.

[0173] In some embodiments, the data read circuit includes a plurality of second multiplexers; the plurality of second multiplexers are respectively configured to correspond to a plurality of memory banks, and the second multiplexers are respectively coupled to a plurality of memory cells in the memory banks; the second multiplexers are configured to read and output a target data element from a first memory cell located in a first memory row in the plurality of memory banks corresponding to the second multiplexer in response to a read cycle type of a first cycle type; and to read and output a target data element from a second memory cell located in a plurality of second memory rows in the plurality of memory banks corresponding to the second multiplexer in response to a read cycle type of a second cycle type.

[0174] The data read circuit 140 may include a plurality of second multiplexers. Each of the second multiplexers is configured to correspond to a plurality of memory banks in the memory array 110, and each second multiplexer is coupled to a plurality of memory cells within its corresponding memory bank. Thus, a second multiplexer can select one memory cell from the plurality of memory cells in its corresponding memory bank and read the data element stored in that memory cell within one read cycle.

[0175] The memory bank includes multiple memory cells, which can be located in different memory rows. A second multiplexer selects one of the memory cells, allowing the data element in that cell to enter the output path of the data read circuit 140. Multiple second multiplexers select data elements from their respective memory cells and output them, forming an intermediate data block based on the data elements output by the multiple second multiplexers.

[0176] In response to a first-cycle read cycle, multiple second multiplexers can read and output target data elements from the first storage cell located in the first storage row of their respective storage banks. The first storage row can be a row containing a group of storage cells with the same or corresponding row addresses in multiple storage banks. That is, under the first-cycle type, multiple second multiplexers can select storage cells on the same storage row in multiple storage banks, thereby reading multiple target data elements located in the same storage row.

[0177] In response to a second-cycle type read cycle, multiple second multiplexers can read and output target data elements from second storage cells located in multiple second storage rows within their respective memory banks. These multiple second storage rows can be non-identical storage rows in multiple memory banks. Under the second-cycle type, different second multiplexers can select storage cells on different storage rows, thereby reading multiple target data elements distributed across multiple storage rows.

[0178] The second storage cell refers to the storage cell selected by the second multiplexer under the second cycle type. For different second multiplexers, their corresponding second storage cells can be located in different second storage rows. For example, one second multiplexer can read the target data element from row 0 of the corresponding storage bank, while another second multiplexer can read the target data element from row 1 of the corresponding storage bank. In this way, the data read circuit 140 can read data elements from multiple storage rows within one read cycle.

[0179] The first and second cycle types correspond to different read organization methods. In the read cycle corresponding to the first cycle type, the read objects are concentrated in the same storage row, and the data read circuit 140 can retrieve a group of data elements from the same row position; in the read cycle corresponding to the second cycle type, the read objects are distributed across multiple storage rows, and the data read circuit 140 reads a group of data elements across rows from the storage array 110.

[0180] By configuring multiple second multiplexers corresponding to multiple memory banks, the data read circuit 140 can read multiple target data elements in parallel within a single read cycle. Each second multiplexer only needs to perform the selection within its corresponding memory bank, without needing to read data across memory banks. This reduces the connection complexity of the read path and enables multiple memory banks to output multiple data elements in parallel.

[0181] In some embodiments, the second multiplexer is further configured to: determine a first row address of the first storage cell in the storage bank corresponding to the second multiplexer based on a third selection signal; select a storage cell located in the first storage row in the storage bank corresponding to the second multiplexer based on the first row address; and read a target data element from the target storage cell located in the first row address in the storage bank corresponding to the second multiplexer; or, determine a second row address of the second storage cell in the storage bank corresponding to the second multiplexer based on the third selection signal; select a storage cell located in the second storage row in the storage bank corresponding to the second multiplexer based on either the first row address or the second row address; and read a target data element from the target storage cell located in the second row address in the storage bank corresponding to the second multiplexer.

[0182] The second multiplexer can determine the row address of the memory cell to be read based on the third selection signal. The third selection signal can be provided by the control logic in the data layout conversion device 100, and is used to instruct the second multiplexer to select the corresponding memory cell in the corresponding memory bank. The third selection signal can directly carry the row address, or it can carry a selection field used to generate the row address.

[0183] In response to the read cycle type being a first cycle type, the second multiplexer can determine the first row address of the first memory cell in the corresponding memory bank based on the third selection signal. Specifically, the second multiplexer can receive the third selection signal and parse the first row address field from it; alternatively, the second multiplexer can determine that the first row address should be used based on the cycle type field and the address field in the third selection signal. The first row address is used to indicate the storage row position of the first memory cell in the corresponding memory bank.

[0184] After determining the first row address, the second multiplexer can select the memory cell located in the first row of the corresponding memory bank based on the first row address. For example, if the first row address is 1, the second multiplexer can select the memory cell in the first row of its corresponding memory bank. The selected memory cell can be used as the target memory cell, and the data element stored in the target memory cell is the data element that needs to be output in the current read cycle.

[0185] The generation process of the first row address may include signal parsing and address decoding. The third selection signal is first parsed into a row address by the second multiplexer or its preceding decoding logic; the row address is decoded into a strobe signal for the corresponding memory row; the strobe signal enables the target memory cell located in the first memory row in the corresponding memory bank to access the read output terminal. Through this process, the third selection signal is converted into an actual memory cell selection action.

[0186] In response to the read cycle being of type two, the second multiplexer can determine the second row address of the second memory cell in the corresponding memory bank based on the third selection signal. The second row address may be different from the first row address. For multiple second multiplexers, the third selection signals received by each second multiplexer may be different, or the address fields in the third selection signals corresponding to each second multiplexer may be different, thereby allowing multiple second multiplexers to determine multiple second row addresses.

[0187] After determining the second row address, the second multiplexer can select the memory cell located in the second row of the corresponding memory bank based on the second row address. For example, if the second row address corresponding to one second multiplexer is r1 and the second row address corresponding to another second multiplexer is r2, and r1 and r2 are different, then the two second multiplexers can read target data elements from different memory rows respectively. Thus, the data read circuit 140 can read multiple target data elements from multiple second memory rows in the read cycle corresponding to the second cycle type.

[0188] The third selection signal can include cycle type information and row address information. The second multiplexer can first determine whether the current read cycle corresponds to the first cycle type or the second cycle type based on the cycle type information. In the read cycle corresponding to the first cycle type, the second multiplexer uses the first row address information in the third selection signal; in the read cycle corresponding to the second cycle type, the second multiplexer uses the second row address information in the third selection signal. Through this signal organization method, the same second multiplexer can reuse the same read path to support two read modes.

[0189] The third selection signal can also bypass the explicit distinction between the first and second row address fields, directly providing the target row address required for the current read cycle to the second multiplexer. In the first cycle type, multiple target row addresses received by multiple second multiplexers can point to the same storage row; in the second cycle type, target row addresses received by multiple second multiplexers can each point to a different second storage row. This reduces the internal decision-making logic of the second multiplexer, improving data read efficiency.

[0190] After the second multiplexer reads the target data element from the target memory cell located at the first or second row address, it can output the target data element to the output terminal of the data read circuit 140. After multiple second multiplexers output target data elements respectively, the target data elements can be combined according to the output order of the multiple second multiplexers to form an intermediate data block.

[0191] The data reading mode executed by the data reading circuit within the period corresponding to the first cycle type is called the first working mode (i.e., pattern A), and the data reading mode executed within the period corresponding to the second cycle type is called the second working mode (i.e., pattern B).

[0192] In the first operating mode, the data read circuit 140 can read multiple data elements from multiple memory rows in the memory array 110. The controller 30 can generate third selection signals for multiple second multiplexers based on the current read cycle number i and the memory bank address bank_id. The read row address indicated by this third selection signal can be represented as: sel_mux1_bank_id=(bank_id+i)%N (3) Where sel_mux1_bank_id is the read row address, N is the number of memory banks in the storage array 110, and the read row address is determined by the memory bank address bank_id and the current read cycle number i. Since the memory bank addresses bank_id are different for different memory banks, multiple second multiplexers can select memory cells in different memory rows within the same read cycle. The data read circuit 140 can thus read multiple data elements from multiple memory rows to obtain an intermediate data block.

[0193] Taking a storage array with 64 storage banks as an example, when i=0, the read row address of storage bank Bank0 is 0, the read row address of storage bank Bank1 is 1, the read row address of storage bank Bank2 is 2, and the read row address of storage bank Bank63 is 63. The data read circuit 140 retrieves data elements from multiple storage banks respectively. When i=1, the read row address of storage bank Bank0 is 1, the read row address of storage bank Bank1 is 2, the read row address of storage bank Bank2 is 3, and the read row address of storage bank Bank63 is 0. Thus, the read row address changes cyclically as the read cycle progresses.

[0194] The data reading process in the first operating mode can be a diagonal read. Since multiple second multiplexers select different memory rows in the same read cycle, the multiple data elements read can come from data written to the memory array in previous write cycles. Thus, the data read circuit 140 can combine data elements distributed in multiple memory rows into an intermediate data block.

[0195] The read method in the first operating mode can be coordinated with the lateral write operation on the write side. In the first operating mode, the data write circuit 130 writes multiple data elements to the same storage row according to sel_demux_bank_id=i%N; the data read circuit 140 reads multiple data elements from multiple storage rows according to sel_mux1_bank_id=(bank_id+i)%N. Thus, a data distribution can be formed in the storage array 110 by writing data row by row, and then the read side reads the data elements related to the transpose arrangement across rows.

[0196] The intermediate data block obtained by the data reading circuit 140 in the first operating mode can be further processed by the output rearrangement circuit 150. Since the data elements in the intermediate data block have been combined from multiple storage rows, the order of the data elements in the intermediate data block may differ from the target order of the final output data block. The output rearrangement circuit 150 can reselect the intermediate data block based on the fourth selection signal to obtain an output data block arranged according to the second data arrangement.

[0197] For example, the data read circuit 140 can read multiple data elements from the same storage row in the storage array 110 in a second operating mode. The controller 30 can generate a third selection signal for multiple second multiplexers based on the current read cycle number i. The read row address indicated by this third selection signal can be represented as: sel_mux1_bank_id=i%N (4) Where sel_mux1_bank_id is the read row address, N is the number of memory banks in the storage array 110, and i is the current read cycle number. As can be seen from formula (4), the read row address is determined by the current read cycle number i, and is independent of the memory bank address bank_id. Therefore, within the same read cycle, the second multiplexers corresponding to multiple memory banks can select the same read row address. Thus, the data read circuit 140 can read multiple data elements from the same memory row in the storage array 110 to obtain an intermediate data block.

[0198] Taking a storage array with 64 storage banks as an example, when i=0, the data reading circuit 140 can read one data element from the 0th row of storage cells in storage banks Bank0, Bank1, ..., Bank63 respectively; when i=1, the data reading circuit 140 can read one data element from the 1st row of storage cells in storage banks Bank0, Bank1, ..., Bank63 respectively. Similarly, when i=63, the data reading circuit 140 can read one data element from the 63rd row of storage cells in storage banks Bank0, Bank1, ..., Bank63 respectively.

[0199] For example, the data reading process in the second operating mode can be a horizontal read. In one read cycle, multiple data elements come from different memory banks, but these data elements are located in the same memory row. This read method is suitable for reading out data elements that have already formed a horizontal arrangement in the memory array 110 at once and providing them to the output rearrangement circuit 150.

[0200] The read method in the second operating mode can be coordinated with the oblique write operation on the write side. In the second operating mode, the data write circuit 130 writes multiple data elements to multiple storage rows according to sel_demux_bank_id=(bank_id+i)%N; the data read circuit 140 reads multiple data elements from the same storage row according to sel_mux1_bank_id=i%N. Thus, the storage array 110 can form a cross-row distribution when writing new data, while the read side retrieves a set of data elements from the already formed data rows.

[0201] The intermediate data block read in the second operating mode may include multiple data elements from the same storage line. The order of elements in this intermediate data block can be determined by the output order of multiple second multiplexers. The output rearrangement circuit 150 can further rearrange the multiple data elements in the intermediate data block based on the current cycle number and the second data arrangement method to obtain the output data block.

[0202] The first and second operating modes can be executed alternately. In the first operating mode, the data writing circuit 130 writes to the same storage row, while the data reading circuit 140 reads from multiple storage rows. In the second operating mode, the data writing circuit 130 writes to multiple storage rows, while the data reading circuit 140 reads from the same storage row. Through this alternation, the storage array 110 can alternately form and release internal data arrangements suitable for transpose in different cycles, thereby reducing the reliance on additional intermediate caches.

[0203] In some embodiments, the controller in the data layout conversion apparatus is configured to: in response to a second cycle type, control the data reading circuit to read multiple data elements from multiple storage rows of multiple memory banks in the storage array based on a first data layout method, the position of the input data block in the data to be converted, the size of the storage array, and configuration parameters; and in response to a first cycle type, control the data reading circuit to read multiple data elements from the same storage row in the storage array based on a first data layout method, the position of the input data block in the data to be converted, the size of the storage array, and configuration parameters.

[0204] The data layout conversion device 100 may include a controller 30. The controller 30 may be coupled to the data reading circuit 140 and is used to control the data reading circuit 140 to read multiple data elements from the storage array 110 according to the type of reading cycle. The type of reading cycle may include a first cycle type and a second cycle type, and different reading cycle types correspond to different storage row reading methods.

[0205] The controller 30 can determine the dimensional correspondence between the element positions of multiple data elements in the input data block and their positions in the read data block in the current data rearrangement task, based on the first data arrangement method and configuration parameters. Based on the position of the input data block in the data to be converted, the cycle number corresponding to the current read cycle is determined. For example, if the input data block is the second data block in the data to be converted, then the cycle number corresponding to the current read cycle is determined to be 2. Combining this with the size of the storage array 110, the rearrangement window position is converted into read control information that the storage array 110 can support. This read control information can be used to instruct the data read circuit 140 to read from the same storage row or from multiple storage rows in the current read cycle.

[0206] In response to the second cycle type of the read cycle, the controller 30 can control the data read circuit 140 to read multiple data elements from multiple storage rows of multiple memory banks in the storage array 110 based on the first data arrangement, the position of the input data block in the data to be converted, the size and configuration parameters of the storage array 110. Thus, the read positions corresponding to different memory banks can be located in different storage rows, enabling the data read circuit 140 to read multiple data elements from cross-row distributed data within one read cycle.

[0207] In the read cycle corresponding to the second cycle type, the controller 30 can first determine the dimensional distribution of the data elements to be read before rearrangement based on the first data arrangement method and configuration parameters. Based on the position of the input data block in the data to be transformed, the controller determines the offset relationship of these data elements within the current rearrangement cycle. According to the size of the storage array 110, this offset relationship is converted into read positions corresponding to multiple storage banks. Based on these read positions, the data read circuit 140 reads multiple data elements from multiple storage rows of multiple storage banks.

[0208] In response to the read cycle being of the first cycle type, the controller 30 can control the data read circuit 140 to read multiple data elements from the same storage row in the storage array 110 based on the first data arrangement, the position of the input data block in the data to be converted, the size and configuration parameters of the storage array 110. The multiple data elements can come from multiple storage banks, and these data elements correspond to the same storage row in each storage bank.

[0209] In the first cycle type, the controller 30 can first determine the target row position corresponding to the current read cycle based on the position of the current input data block in the data to be converted. Based on the size of the storage array 110, the target row position is restricted to the range of valid storage rows. The controller 30 generates read control information to indicate the same storage row. Based on this read control information, the data read circuit 140 reads multiple data elements from storage cells located in the same storage row across multiple storage banks.

[0210] In some embodiments, the controller is further configured to: determine the shift number corresponding to the input data block based on a first data arrangement, the position of the input data block in the data to be converted, the size of the storage array, and configuration parameters; in response to the read cycle type being a second cycle type, determine multiple first row addresses corresponding to multiple storage banks based on the shift number and the storage bank addresses corresponding to the multiple storage banks respectively; control the data read circuit to read multiple data elements from the multiple first storage rows in the storage array based on the multiple first row addresses; in response to the read cycle type being a first cycle type, determine the second row addresses corresponding to the multiple storage banks based on the shift number and the storage bank addresses corresponding to the multiple storage banks respectively; and control the data read circuit to read multiple data elements from the second storage rows in the storage array based on the second row addresses.

[0211] The controller 30 can determine, based on the first data arrangement and configuration parameters, which dimension along which the currently read data element in the data to be converted undergoes position transformation. Based on the position of the input data block in the data to be converted, it determines the block number or periodicity of the current input data block in that dimension. Based on the size of the storage array 110, it applies a range constraint to the block number or periodicity to obtain the shift value corresponding to the input data block. For example, if the storage array 110 includes N memory banks and each memory bank includes N storage rows, the controller 30 can map the periodicity to the range of 0 to N-1 to obtain the shift value.

[0212] In response to the read cycle type being a second cycle type, the controller 30 can determine multiple first row addresses corresponding to multiple memory banks based on the shift bit and the memory bank addresses corresponding to the multiple memory banks respectively. The second cycle type corresponds to reading multiple data elements from multiple first memory rows; therefore, the multiple first row addresses can change with the memory bank addresses.

[0213] In the read cycle corresponding to the second cycle type, the controller 30 can use the shift bit as a reference offset and combine this reference offset with multiple memory bank addresses to obtain multiple candidate row addresses. Based on the size of the memory array 110, the multiple candidate row addresses are modulo- or truncated to obtain multiple first row addresses. Through this generation process, the first row addresses corresponding to different memory banks can be different, and all are within the valid row address range supported by the memory array 110.

[0214] Taking a storage array 110 comprising N memory banks as an example, if the memory bank address of the k-th memory bank is k, the controller 30 can add the shifted bit to k, and perform modulo operation on the N pairs of addition results to obtain the first row address corresponding to the k-th memory bank. Since multiple memory bank addresses are different, multiple first row addresses can point to multiple first storage rows. Based on the multiple first row addresses, the controller 30 controls the data reading circuit 140 to read multiple data elements from the multiple first storage rows.

[0215] In response to the read cycle type being a first cycle type, the controller 30 can determine the second row address corresponding to the multiple memory banks based on the shift bit and the memory bank addresses corresponding to the multiple memory banks respectively. The first cycle type corresponds to reading multiple data elements from the second storage row; therefore, the controller 30 can make the second row addresses corresponding to the multiple memory banks point to the same storage row.

[0216] In the read cycle corresponding to the first cycle type, the controller 30 can use the shift bit as the base row address and determine the base row address as the second row address common to multiple memory banks. Since the multiple memory banks have different memory bank addresses, the controller 30 can, in the first cycle type, prevent the read row address from changing with the memory bank address, and instead make all multiple memory banks point to the same second memory row determined by the shift bit.

[0217] If the storage array 110 includes N storage banks and each storage bank includes N storage rows, the controller 30 can use the result of shifting the bit modulo N as the address of the second row. Based on this second row address, the data read circuit 140 reads multiple data elements from storage cells located in the same second storage row across the multiple storage banks. Thus, multiple data elements from the same storage row can be obtained within one read cycle.

[0218] In the above manner, the controller 30 first generates a shift number based on the first data arrangement, the position of the input data block in the data to be converted, the size of the storage array 110, and the configuration parameters. Then, according to the type of read cycle, it combines the shift number with the storage address to generate multiple first row addresses or second row addresses. Subsequently, the controller 30 uses these read row addresses to control the data read circuit 140 to read data elements from multiple first storage rows or the same second storage row, thereby providing a data source for forming intermediate data blocks.

[0219] The output rearrangement circuit 150 includes multiple third multiplexers, each configured to correspond to an element position of multiple data elements in the output data block. Each third multiplexer is configured to select a target data element from the multiple data elements in the intermediate data block and output the target data element to its corresponding target position. Each third multiplexer receives multiple target data elements from the intermediate data block and selects one of them for output according to a fourth selection signal. If the output data block includes 64 data element positions, the output rearrangement circuit 150 may include 64 third multiplexers. Each third multiplexer corresponds to a target element position in the output data block. Thus, the output rearrangement circuit 150 can rearrange multiple target data elements read from the target storage line into an output data block according to the second data arrangement method.

[0220] The fourth selection signal is used to control the third multiplexer in the output rearrangement circuit 150. The controller 30 can determine the spatial position mapping relationship between the data element positions in the intermediate data block, the element positions in the output data block, and the second data arrangement, and generate the fourth selection signal based on the spatial position mapping relationship.

[0221] For example, after the data reading circuit 140 reads multiple target data elements from the same target storage line, the arrangement order of these target data elements in the intermediate data block may differ from the required arrangement order of the output data block. The controller can determine, based on the second data arrangement method, which position in the intermediate data block each element in the output data block should be retrieved from. A fourth selection signal is provided to the corresponding third multiplexer, causing the third multiplexer to select the corresponding target data element from the intermediate data block and output it to the target position in the output data block. The fourth selection signal is used to complete the data rearrangement between the intermediate data block and the output data block.

[0222] In one example, with input data blocks arranged in a 2H4W8C configuration, the output rearrangement circuit 150 needs to convert the input data blocks into output data blocks arranged in an 8C2H4W configuration. Each third multiplexer can have its own position number (or bankid). If the position number is 6 bits, the selection value can be determined by rearranging the bit order of these 6 bits. Bit order rearrangement refers to adjusting the order of data in the position number. For example, if the position number is 010011, swapping the 3rd and 6th bits will result in a new position number of 011010. For instance, when converting the input data block configuration from 2H4W8C to 8C2H4W, after conversion, bit 0 corresponds to the original bit 3, bit 1 corresponds to the original bit 4, bit 2 corresponds to the original bit 5, bit 3 corresponds to the original bit 0, bit 4 corresponds to the original bit 1, and bit 5 corresponds to the original bit 2. For the first multiplexer with position number 15, if its storage address bank_id is binary 001111, after the bit order is rearranged as described above, it can be obtained as binary 111001, which corresponds to the 57th element in the input data block.

[0223] In some embodiments, the third multiplexer is further configured to: determine the second element position of the target data element in the intermediate data block based on the fourth selection signal; and output the target data element based on the second element position.

[0224] The controller 30 can determine the shift number corresponding to multiple data elements in the intermediate data block based on configuration parameters, the position of the input data block in the data to be converted, the position of multiple data elements in the intermediate data block, and the second data arrangement method; based on the shift number, it controls the output rearrangement circuit to rearrange the multiple data elements in the intermediate data block. The second spatial position mapping relationship can be used to represent the correspondence between the positions of data elements in the intermediate data block and the positions of data elements in the output data block.

[0225] The controller 30 generates or configures a fourth selection signal based on the second spatial location mapping relationship, controls multiple third multiplexers in the output rearrangement circuit 150, and enables multiple third multiplexers to select corresponding data from multiple target data elements read out and output them to the corresponding positions in the output data block, thereby realizing data rearrangement.

[0226] The data read circuit 140 can read multiple target data elements from multiple memory cells located in the same target memory row in the memory array 110 and output an intermediate data block. The multiple target data elements in the intermediate data block can be arranged according to the arrangement order of multiple memory banks, for example, in the order of memory bank Bank0, memory bank Bank1, ..., memory bank Bank63. This arrangement order can be different from the second data arrangement required for the output data block.

[0227] The controller 30 can determine a second spatial position mapping relationship based on the positions of multiple target data elements in the intermediate data block and the positions of multiple data elements in the output data block. The second spatial position mapping relationship represents the correspondence between the positions of elements in the intermediate data block and the positions of elements in the output data block. The controller 30 can generate a fourth selection signal based on the second spatial position mapping relationship and provide the fourth selection signal to the corresponding third multiplexer.

[0228] For example, for a target element position in the output data block, the controller 30 can determine the position of the target data element required for that target position in the intermediate data block based on the second spatial position mapping relationship. The third multiplexer corresponding to that target element position selects the target data element corresponding to that position from multiple target data elements in the intermediate data block based on the fourth selection signal, and outputs it to the target element position in the output data block. Other third multiplexers can also perform selection operations according to their respective corresponding fourth selection signals.

[0229] If the intermediate data blocks read by the data reading circuit 140 are arranged in the order of the memory bank, while the output data blocks need to be arranged according to the second data arrangement method, the controller 30 can map the element positions under the memory bank order to the element positions under the second data arrangement method. Therefore, the output rearrangement circuit 150 can rearrange the multiple target data elements read by memory row into an output data block that conforms to the second data arrangement method.

[0230] Therefore, the output rearrangement circuit can adjust the position of the target data elements that have been read without re-accessing the data to be converted, so that the output data block meets the requirements of the subsequent storage or subsequent calculation for the data arrangement.

[0231] In some embodiments, the controller 30 can determine a second correspondence between the positions of multiple data elements in the intermediate data block and their positions in the output data block based on configuration parameters and a second data arrangement method; and determine the shift number corresponding to the multiple data elements in the intermediate data block based on the second correspondence and the position of the input data block in the data to be converted. For example, when the arrangement order of the intermediate data block read by the data reading circuit 140 is inconsistent with the required arrangement order of the output data block, the controller 30 can generate a fourth selection signal based on the second correspondence, causing the output rearrangement circuit 150 to output the target data element to the target position in the output data block.

[0232] The controller 30 can rearrange the data elements in the intermediate data block based on the second spatial location mapping relationship between the first and second data arrangement methods. The second spatial location mapping relationship is used to represent the correspondence between the element positions in the intermediate data block 32 and the element positions in the output data block. For example, if the intermediate data block 32 is arranged according to 8C2H4W, and the output data block needs to be arranged according to 2H4W8C, the controller can convert the H, W, and C indices corresponding to each target position in the output data block into the source position indices in the intermediate data block 32, and generate a fourth selection signal to control each third multiplexer accordingly. Thus, the output rearrangement circuit 150 can rearrange the target data elements that have been read according to the target storage row into the data arrangement required by the subsequent storage circuit or subsequent operator.

[0233] The second correspondence can be represented as element position pairs. For example, the i-th element position in the first intermediate data block 32 corresponds to the j-th element position in the output data block. The controller then converts multiple element position pairs into fourth selection signals corresponding to each third multiplexer. In one example, a target position in the output data block corresponds to H0W1C2. The controller determines the output number of the target position according to the second data arrangement, and then determines the element position of H0W1C2 in the intermediate data block 32 according to the first data arrangement. This element position is the second element position that the corresponding third multiplexer needs to select.

[0234] Table 3

[0235] Table 3 shows the layout of the output data after the transpose operation. As shown in Table 3, the data layout of the data to be transformed after the transpose operator is converted to 64H1W1C.

[0236] In some embodiments, the data layout conversion apparatus further includes a controller, which includes an input address generation unit and an output address generation unit. The input address generation unit is configured to generate a first access address for reading an input data block from memory based on the size of the data to be converted, a first data layout method, a first dimension step, a first access start address, and a first access range. The output address generation unit is configured to generate a second access address for writing an output data block to memory based on a second data layout method, a second dimension step, a second access start address, and a second access range. The input address generation unit can generate the first access address for reading an input data block from memory based on the size of the data to be converted, the first data layout method, the first dimension step, the first access start address, and the first access range. The output address generation unit can generate the second access address for writing an output data block to memory based on the second data layout method, the second dimension step, the second access start address, and the second access range. Thus, the data layout conversion apparatus 100 can establish an address correspondence between reading an input data block, forming an output data block, and writing back an output data block.

[0237] The input address generation unit can generate a first access address for reading the input data block based on the first access start address, the first dimension step size, and the H, W, and C ranges covered by the first current input data block. For example, in the case of a first data arrangement of 2H4W8C, an input data block covers the data element positions corresponding to 2 H, 4 W, and 8 C. The input address generation unit can determine the H, W, and C index ranges covered by the current data block number, and then calculate the read address of the input data block in memory based on the first dimension step size.

[0238] The output address generation unit can generate a second access address based on the output data block number, the second data arrangement method, and the second access start address, enabling the output data blocks obtained by the output rearrangement circuit 150 to be written back to the memory in a predetermined block order. When the output data block corresponds to a consecutive position in the rearrangement result, the output address generation unit can update the second access address based on the number of data blocks that have already been output; in the case of boundary data blocks, the output address generation unit can determine whether the current output data block falls within the valid write-back range by combining the second access range, and generate the corresponding write-back address.

[0239] The following is combined with Figure 3The data block processing procedure is described below. During the data arrangement and transformation process, the data rearrangement cycles 0 to 63 are of the first cycle type. In these cycles, the data writing circuit 130 and the data reading circuit 140 execute the data arrangement and transformation task according to the first operating mode. The data rearrangement cycles 64 to 127 are of the second cycle type. In these cycles, the data arrangement and transformation circuit 100 executes the data arrangement and transformation task according to the second operating mode. The data rearrangement cycles 128 to 191 are of the first cycle type. In these cycles, the data arrangement and transformation circuit 100 executes the data arrangement and transformation task according to the first operating mode.

[0240] The following example illustrates the data arrangement conversion process across multiple consecutive data rearrangement cycles, using a data size of 128H×1W×64C, a first data arrangement of 1H1W64C, a second data arrangement of 64H1W1C, and a storage array 110 comprising 64 memory banks, each containing 64 memory cells. The data rearrangement cycles described below are logical cycles used for ease of describing the data relationships between different circuits. In actual circuits, pipeline registers can be configured between input rearrangement, data writing, data reading, and output rearrangement, and the actual data rearrangement cycles performed by different circuits may have corresponding offsets.

[0241] In cycle 0, controller 30 determines that the current data rearrangement cycle is of type 1 cycle. The input address generation unit generates the first access address of the first input data block and reads the first input data block, including H0W0C0 to H0W0C63, from the memory. The current cycle number is 0, and the input rearrangement circuit 120 does not generate a position offset for the first input data block. First multiplexer 321 selects H0W0C0, first multiplexer 322 selects H0W0C1, first multiplexer 323 selects H0W0C2, and the other first multiplexers sequentially select the corresponding data elements according to the memory bank identifier.

[0242] In cycle 0, the data writing circuit 130 performs writing according to the first operating mode. The controller 30 converts cycle number 0 into write row address 0 and provides this write row address to each data distributor. Data distributor 341 writes H0W0C0 to the 0th storage row of memory bank 111, data distributor 342 writes H0W0C1 to the 0th storage row of memory bank 112, and data distributor 343 writes H0W0C2 to the 0th storage row of memory bank 113. The remaining data distributors complete the writing using the same row address, so that the 64 data elements of the first input data block are written to the 0th storage rows of multiple memory banks. Since the memory array 110 has not yet completed its initial filling, the data reading circuit 140 does not output a valid intermediate data block in this data rearrangement cycle, and the output rearrangement circuit 150 does not form a valid output data block.

[0243] In cycle 1, the input rearrangement circuit 120 reads the second input data block, including H1W0C0 to H1W0C63. The current cycle number is 1, and the input rearrangement circuit 120 shifts the second input data block one element position to the right relative to the memory bank direction. The first multiplexer 321 selects H1W0C63, the first multiplexer 322 selects H1W0C0, and the first multiplexer 323 selects H1W0C1. The controller 30 converts cycle number 1 to write row address 1, and the data writing circuit 130 writes the aforementioned data elements to the first storage row of the multiple memory banks respectively. At this time, the first storage row of memory bank 111 stores H1W0C63, the first storage row of memory bank 112 stores H1W0C0, and the first storage row of memory bank 113 stores H1W0C1.

[0244] In cycle 2, the input rearrangement circuit 120 receives a third input data block including H2W0C0 to H2W0C63 and shifts this input data block two element positions to the right according to cycle number 2. First multiplexer 321 selects H2W0C62, first multiplexer 322 selects H2W0C63, and first multiplexer 323 selects H2W0C0. The data writing circuit 130 uses write row address 2 to write the data elements output by the multiple first multiplexers into the second storage row of multiple memory banks.

[0245] In cycles 3 through 62, the input address generation unit continues to read subsequent input data blocks cycle by cycle of data rearrangement. The input rearrangement circuit 120 determines the shift number of the input data block based on the current cycle number, shifting the i-th input data block i element positions to the right. The data writing circuit 130 writes the shifted data elements into the i-th storage row of the multiple memory banks. After each data rearrangement cycle, the storage array 110 adds a row of data elements arranged according to the corresponding shift relationship.

[0246] In cycle 63, the input rearrangement circuit 120 receives an input data block including H63W0C0 to H63W0C63 and shifts the input data block 63 element positions to the right. First multiplexer 321 selects H63W0C1, first multiplexer 322 selects H63W0C2, and first multiplexer 323 selects H63W0C3. The data writing circuit 130 writes these data elements to the 63rd storage row of the multiple memory banks. After this data rearrangement cycle is completed, data has been written to storage rows 0 through 63, forming a complete data rearrangement window in the storage array 110 for subsequent reading.

[0247] In cycle 64, controller 30 switches to the second operating mode, and the cycle number within the current 64 data rearrangement cycles is recalculated from 0. Input rearrangement circuit 120 receives a new input data block and selects data elements corresponding to multiple memory banks from the input data block according to cycle number 0. Data writing circuit 130 performs writing according to the second operating mode, and each data distributor generates a different write row address based on the memory bank identifier and cycle number 0. For example, data distributor 341 selects the 0th memory bank, data distributor 342 selects the 1st memory bank, data distributor 343 selects the 2nd memory bank, and other data distributors sequentially select the corresponding memory banks, thereby writing the new input data block to multiple memory banks.

[0248] Within the same cycle 64, the data read circuit 140 performs a read operation according to the first cycle type. Multiple second multiplexers read data elements previously written to the memory array in cycles 0 to 63 from the same memory row across multiple memory banks, resulting in the first valid intermediate data block 32. The output rearrangement circuit 150 generates a fourth selection signal based on the current cycle number 0, selects the positions of multiple data elements in the intermediate data block 32, and forms the first valid output data block arranged according to the second data arrangement. The output address generation unit generates a second access address for this output data block, enabling the output data block to be written to the corresponding location in the memory.

[0249] In cycle 65, the input rearrangement circuit 120 receives the next input data block and shifts it one element position to the right. The data writing circuit 130 adds the bank identifier to the cycle number 1 and takes the modulo of the number of rows in the memory array to obtain the write row address for each bank. For example, data distributor 341 selects the first storage row, data distributor 342 selects the second storage row, data distributor 343 selects the third storage row, and the last data distributor selects the zeroth storage row. A new input data block is thus written to multiple storage rows.

[0250] In the same cycle 65, the data read circuit 140 updates the read row address to the first storage row, and multiple second multiplexers read data elements from the first storage row of their respective memory banks. The output rearrangement circuit 150 adjusts the output side of the intermediate data block 32 by one element position according to cycle number 1, sending each data element to the corresponding target position in the output data block to form a second valid output data block. Therefore, starting from cycle 64, input rearrangement, writing to multiple storage rows, reading from the same storage row, and output rearrangement can be performed in parallel within consecutive data rearrangement cycles.

[0251] In cycle 66, the input rearrangement circuit 120 shifts the current input data block two element positions to the right. The data writing circuit 130 assigns memory banks 111, 112, and 113 to the 2nd, 3rd, and 4th memory rows, respectively, with the write row addresses of other memory banks changing sequentially according to the same relationship. The data reading circuit 140 reads multiple data elements from the 2nd memory row of multiple memory banks, and the output rearrangement circuit 150 adjusts the position of the intermediate data block 32 according to the cycle number 2 to obtain the next output data block.

[0252] In cycles 67 to 126, the input rearrangement circuit 120 increases the input-side shift bit every data rearrangement cycle; the data writing circuit 130 changes the write row address corresponding to each memory bank every data rearrangement cycle; the data reading circuit 140 reads memory rows 3 to 62 sequentially; and the output rearrangement circuit 150 changes the position of the element selected by each third multiplexer according to the corresponding cycle number. Each data rearrangement cycle can read out a previously collected data block and simultaneously write a new input data block.

[0253] In cycle 127, the cycle number within the current 64 data rearrangement cycles is 63. The input rearrangement circuit 120 shifts the current input data block 63 element positions to the right. The data writing circuit 130 determines multiple write row addresses based on the memory bank identifier and cycle number 63. For example, data distributor 341 selects the 63rd memory row, data distributor 342 selects the 0th memory row, and data distributor 343 selects the 1st memory row. The data reading circuit 140 reads multiple data elements from the 63rd memory row of multiple memory banks, and the output rearrangement circuit 150 adjusts the corresponding output position according to the cycle number 63. After completing this data rearrangement cycle, the data written to the memory array has been read out sequentially, and the new data received in the data rearrangement cycle corresponding to the second cycle type has been stored in the memory array 110 according to the multiple memory row writing method.

[0254] In cycle 128, controller 30 switches back to the first operating mode. Input rearrangement circuit 120 receives the first input data block from the next set of input data blocks. The cycle number in the current window is 0, so input rearrangement circuit 120 does not generate a position offset. Data writing circuit 130 writes multiple data elements to the 0th storage row of multiple memory banks according to the first cycle type.

[0255] Within the same cycle 128, the data read circuit 140 performs reads according to the second cycle type. The controller 30 combines the current cycle number 0 with the memory bank identifiers of multiple memory banks to obtain the read row address corresponding to each memory bank. For example, the second multiplexer 351 reads a data element from the 0th memory bank of memory bank 111, the second multiplexer 352 reads a data element from the 1st memory bank of memory bank 112, and the second multiplexer 353 reads a data element from the 2nd memory bank of memory bank 113. Multiple second multiplexers thus read data elements from multiple memory banks respectively, resulting in an intermediate data block 32. The output rearrangement circuit 150 selects the output of the intermediate data block 32 according to the cycle number 0, forming a new output data block.

[0256] In cycle 129, the input rearrangement circuit 120 shifts the current input data block one element position to the right, and the data writing circuit 130 writes the shifted data elements into the first storage row of multiple storage banks. The data reading circuit 140 adds the cycle number 1 to the identifier of each storage bank and takes the modulo, causing the second multiplexer 351 to read the first storage row, the second multiplexer 352 to read the second storage row, the second multiplexer 353 to read the third storage row, and the last second multiplexer to read the 0th storage row. The output rearrangement circuit 150 adjusts the element order in the intermediate data block 32 according to the cycle number 1 to form the next output data block.

[0257] In cycles 130 to 190, the data writing circuit 130 continues to update the storage array 110 row by row according to the same storage row writing method, and the data reading circuit 140 continues to obtain the intermediate data block 32 according to the multiple storage row reading method. The output rearrangement circuit 150 adjusts the output side position of the intermediate data block 32 according to the current cycle number. Unlike the initial filling stage from cycle 0 to cycle 63, the storage array 110 has already stored the data written in the previous stage. Therefore, the data reading circuit 140 and the output rearrangement circuit 150 in this stage can continuously generate valid output data blocks.

[0258] In cycle 191, the cycle number within the current window is 63. The data writing circuit 130 writes the current input data block to the 63rd storage row of multiple memory banks. The data reading circuit 140 reads data elements from the corresponding storage rows of the multiple memory banks, and the output rearrangement circuit 150 adjusts the output position of the last intermediate data block 32 in this window according to cycle number 63. After completing this data rearrangement cycle, the controller 30 can switch back to the second operating mode, allowing subsequent data rearrangement cycles to re-execute multiple storage row writing and same storage row reading.

[0259] Therefore, the first and second operating modes alternate in 64 data rearrangement cycles. During the data arrangement transformation, the input rearrangement circuit, data writing circuit, data reading circuit, and output rearrangement circuit can process different input data blocks in a pipelined manner in each data rearrangement cycle. Data elements are read from a subset of storage units in the storage array and written to the same storage units within the same data rearrangement cycle, eliminating the need for separate read and write operations via a ping-pong buffer. Utilizing the same storage array to continuously complete the data arrangement transformation from the first to the second data arrangement mode reduces caching costs and improves data arrangement transformation efficiency.

[0260] Exemplary methods Figure 4 This is a schematic flowchart of a data arrangement conversion method provided in an exemplary embodiment of this disclosure. This embodiment can be applied to electronic devices, such as... Figure 4 As shown, it includes the following steps: Step 410: Obtain the input data block arranged according to the first data arrangement method. Based on the configuration parameters of the function operator and the position of the input data block in the data to be converted, select the data elements corresponding to multiple storage volumes from the multiple data elements in the input data block.

[0261] Step 420: In response to the write cycle type being the first cycle type, multiple data elements are written to the same storage row in the storage array; in response to the write cycle type being the second cycle type, multiple data elements are written to multiple storage rows in the storage array based on the first data arrangement method and configuration parameters.

[0262] Step 430: In response to the type of the read cycle being the second cycle type, multiple data elements are read from multiple storage rows in the storage array based on the first data arrangement to obtain an intermediate data block; in response to the type of the read cycle being the first cycle type, multiple data elements are read from the same storage row in the storage array to obtain an intermediate data block.

[0263] Step 440: Rearrange multiple data elements in the intermediate data block to obtain an output data block arranged according to the second data arrangement method.

[0264] Figure 5 This is a flowchart illustrating a data input rearrangement method provided in an exemplary embodiment of this disclosure, as shown below. Figure 5 As shown, step 410 above, which involves selecting data elements corresponding to multiple storage banks from multiple data elements in the input data block, includes: Step 510: Based on the configuration parameters of the function operator and the position of the input data block in the data to be transformed, select the target data element from multiple data elements of the input data block and output the target data element.

[0265] Figure 6 This is a flowchart illustrating a target data element output method provided in an exemplary embodiment of this disclosure, such as... Figure 6 As shown, step 510 above, based on the configuration parameters of the function operator and the position of the input data block in the data to be transformed, selects the target data element from multiple data elements of the input data block and outputs the target data element, including: Step 610: Based on the first selection signal, determine the position of the first element of the target data element in the input data block; Step 620: Output the target data element based on the position of the first element.

[0266] Figure 7 This is a flowchart illustrating a data element selection method provided in an exemplary embodiment of this disclosure, such as... Figure 7 As shown, step 410 above, which involves selecting data elements corresponding to multiple storage banks from multiple data elements in the input data block, includes: Step 710: Determine the position of the input data block in the data to be converted, the first data layout method, the size of the data to be converted, and the configuration parameters; Step 720: Determine the shift number corresponding to multiple data elements based on the position of the input data block in the data to be converted, the first data arrangement method, the size of the data to be converted, and the configuration parameters. Step 730: Select data elements corresponding to multiple storage banks from multiple data elements in the input data block according to the shift number.

[0267] Figure 8 This is a flowchart illustrating a method for determining the shift value provided in an exemplary embodiment of this disclosure, as shown below. Figure 8 As shown, step 720 above, determining the shift values ​​corresponding to multiple data elements based on the position of the input data block in the data to be converted, the first data arrangement method, the size of the data to be converted, and the configuration parameters, includes: Step 810: Based on the position of the input data block in the data to be converted, the first data arrangement method, the size and configuration parameters of the data to be converted, determine the first correspondence between the position of multiple data elements in the input data block and the addresses of multiple storage entities; Step 820: Determine the shift number based on the first correspondence.

[0268] Figure 9 This is a flowchart illustrating a data element writing method provided in an exemplary embodiment of this disclosure, as shown below. Figure 9 As shown, step 420 above, which involves writing multiple data elements into multiple storage rows in the storage array based on the first data arrangement method and configuration parameters, includes: Step 910: In response to the type of the write cycle being the first cycle type, multiple data elements output by the first multiplexer corresponding to the data distributor are written into the first storage cell belonging to the same storage row in the multiple storage banks corresponding to the data distributor. Step 920: In response to the write cycle type being the second cycle type, multiple data elements output by the first multiplexer corresponding to the data distributor are written into the second storage unit belonging to multiple storage rows in the multiple storage banks corresponding to the data distributor.

[0269] Figure 10 This is a flowchart illustrating a method for writing data elements into the same storage row according to an exemplary embodiment of this disclosure, as shown below. Figure 10 As shown, step 910 above, which involves writing multiple data elements output by the first multiplexer corresponding to the data distributor into the first storage cell belonging to the same storage row in multiple storage banks corresponding to the data distributor, includes: Step 1010: Based on the second selection signal, determine the first row address of the first storage unit in the storage bank corresponding to the data distributor; Step 1020: Based on the first row address, write the data element output by the first multiplexer corresponding to the data distributor into the first storage unit.

[0270] Figure 11 This is a flowchart illustrating a method for writing data elements into multiple storage rows according to an exemplary embodiment of this disclosure, as shown below. Figure 11 As shown, step 920 above, which involves writing multiple data elements output by the first multiplexer corresponding to the data distributor into the second storage unit belonging to multiple storage rows in the multiple storage banks corresponding to the data distributor, includes: Step 1110: Based on the second selection signal, determine the second row address of the second storage cell in the storage bank corresponding to the data distributor; Step 1120: Based on the second row address, write the data element output by the first multiplexer corresponding to the data distributor into the second storage unit.

[0271] Figure 12 This is a flowchart illustrating another data element writing method provided by an exemplary embodiment of this disclosure, such as... Figure 12 As shown, step 420 above, writing multiple data elements into multiple storage rows in the storage array, includes: Step 1210: In response to the type of the write cycle being the first cycle type, based on the first data arrangement, the position of the input data block in the data to be converted, the size of the storage array, and the configuration parameters, multiple data elements are written to the same storage row of multiple storage banks. Step 1220: In response to the write cycle type being the second cycle type, multiple data elements are written to multiple storage rows of the storage array based on the first data arrangement, the position of the input data block in the data to be converted, the size of the storage array, and the configuration parameters.

[0272] Figure 13 This is a flowchart illustrating a method for determining the same storage row address provided in an exemplary embodiment of this disclosure, as shown below. Figure 13 As shown, writing multiple data elements into the same storage row of multiple storage banks in step 1210 above includes: Step 1310: Based on the first data arrangement, the position of the input data block in the data to be converted, the size and configuration parameters of the storage array, determine the number of shift bits corresponding to the input data block; Step 1320: In response to the write cycle type being the first cycle type, determine the multiple first row addresses corresponding to the multiple memory banks based on the shift bit and the memory bank addresses corresponding to the multiple memory banks respectively; Step 1330: Based on multiple first row addresses, write multiple data elements into the same storage row of multiple storage banks.

[0273] Figure 14 This is a flowchart illustrating a method for determining multiple storage row addresses provided in an exemplary embodiment of this disclosure, as shown below. Figure 14 As shown, writing multiple data elements into multiple storage rows of the storage array in step 1220 above includes: Step 1410: Based on the first data arrangement, the position of the input data block in the data to be converted, the size and configuration parameters of the storage array, determine the number of shift bits corresponding to the input data block; Step 1420: In response to the type of the write cycle being the second cycle type, determine the multiple second row addresses corresponding to the multiple memory banks based on the shift bit and the memory bank addresses corresponding to the multiple memory banks respectively; Step 1430: Based on multiple second row addresses, write multiple data elements to multiple storage rows of the storage array.

[0274] Figure 15This is a flowchart illustrating a data element output method provided in an exemplary embodiment of this disclosure, such as... Figure 15 As shown, step 1430 above, which involves reading multiple data elements from multiple storage rows in the storage array, includes: Step 1510: In response to the type of the read cycle being the first cycle type, the target data element is read from the first storage cell located in the first storage row from the multiple storage banks corresponding to the second multiplexer and output. Step 1520: In response to the read cycle type being the second cycle type, the target data element is read from the second storage cell located in the multiple second storage rows of the multiple storage banks corresponding to the second multiplexer and output.

[0275] Figure 16 This is a flowchart illustrating a data element reading method provided in an exemplary embodiment of this disclosure, as shown below. Figure 16 As shown, step 1510 above, which involves reading the target data element from the first storage cell located in the first storage row of the multiple storage banks corresponding to the second multiplexer and outputting it, includes: Step 1610: Based on the third selection signal, determine the first row address of the first storage cell in the storage bank corresponding to the second multiplexer; Step 1620: Based on the address of the first row, select the memory bank corresponding to the second multiplexer that is located in the first memory row; Step 1630: Read the target data element from the target storage cell located at the first row address in the storage bank corresponding to the second multiplexer.

[0276] Figure 17 This is a flowchart illustrating another data element reading method provided by an exemplary embodiment of this disclosure, such as... Figure 17 As shown, step 1520 above, which involves reading the target data element from the second storage cell located in the second storage row of the multiple storage banks corresponding to the second multiplexer and outputting it, includes: Step 1710: Based on the third selection signal, determine the second row address of the second storage cell in the memory bank corresponding to the second multiplexer; Step 1720: Based on the first row address or the second row address, select the memory cell located in the second memory row in the memory bank corresponding to the second multiplexer; Step 1730: Read the target data element from the target memory cell located at the second row address in the memory bank corresponding to the second multiplexer.

[0277] Figure 18 This is a flowchart illustrating another data reading method provided in an exemplary embodiment of this disclosure, such as... Figure 18 As shown, reading multiple data elements from the same storage row in the storage array in step 430 above includes: Step 1810: In response to the read cycle type being the second cycle type, based on the first data arrangement, the position of the input data block in the data to be converted, the size and configuration parameters of the storage array, the data read circuit is controlled to read multiple data elements from multiple storage rows of multiple storage banks in the storage array; Step 1820: In response to the type of the read cycle being the first cycle type, multiple data elements are read from the same storage row in the storage array based on the first data arrangement, the position of the input data block in the data to be converted, the size of the storage array, and the configuration parameters.

[0278] Figure 19 This is a flowchart illustrating multiple row address determination methods provided in an exemplary embodiment of this disclosure, such as... Figure 19 As shown, step 430 above, reading multiple data elements from multiple storage rows in the storage array, includes: Step 1910: Based on the first data arrangement, the position of the input data block in the data to be converted, the size and configuration parameters of the storage array, determine the number of shift bits corresponding to the input data block; Step 1920: In response to the read cycle type being the second cycle type, determine multiple first row addresses corresponding to multiple memory banks based on the shift bit and the memory bank addresses corresponding to the multiple memory banks respectively; Step 1930: Based on multiple first row addresses, read multiple data elements from multiple storage rows in the storage array respectively.

[0279] Figure 20 This is a flowchart illustrating a method for determining the same storage row address provided in an exemplary embodiment of this disclosure, as shown below. Figure 20 As shown, reading multiple data elements from the same storage row in the storage array in step 430 above includes: Step 2010: Based on the first data arrangement, the position of the input data block in the data to be converted, the size and configuration parameters of the storage array, determine the number of shift bits corresponding to the input data block; Step 2020: In response to the read cycle type being the first cycle type, determine the second row address corresponding to the multiple memory banks based on the shift bit and the memory bank addresses corresponding to the multiple memory banks respectively; Step 2030: Based on the second row address, control the data reading circuit to read multiple data elements from the second storage row in the storage array.

[0280] Figure 21 This is a flowchart illustrating a data element output rearrangement method provided in an exemplary embodiment of this disclosure, as shown below. Figure 21As shown, step 440 above involves rearranging multiple data elements in the intermediate data block to obtain an output data block arranged according to the second data arrangement method, including: Step 2110: Select the target data element from the multiple data elements in the intermediate data block and output the target data element to the target position corresponding to the third multiplexer.

[0281] Figure 22 This is a flowchart illustrating a data element output method provided in an exemplary embodiment of this disclosure, such as... Figure 22 As shown, step 2110 above, which involves selecting the target data element from multiple data elements in the intermediate data block and outputting the target data element to the target position corresponding to the third multiplexer, includes: Step 2210: Based on the fourth selection signal, determine the position of the second element of the target data element in the intermediate data block; Step 2220: Output the target data element based on the position of the second element.

[0282] Figure 23 This is a flowchart illustrating a data rearrangement method provided in an exemplary embodiment of this disclosure, as shown below. Figure 23 As shown, step 440 above involves rearranging multiple data elements in the intermediate data block to obtain an output data block arranged according to the second data arrangement method, including: Step 2310: Determine the shift number corresponding to the multiple data elements in the intermediate data block based on the configuration parameters, the position of the input data block in the data to be converted, the position of multiple data elements in the intermediate data block, and the second data arrangement method. Step 2320: Based on the shift value, control the output rearrangement circuit to rearrange multiple data elements in the intermediate data block.

[0283] Figure 24 This is a flowchart illustrating a method for determining the shift value provided in an exemplary embodiment of this disclosure, as shown below. Figure 24 As shown, step 2310 above, determining the shift value corresponding to multiple data elements in the intermediate data block based on configuration parameters, the position of the input data block in the data to be converted, the position of multiple data elements in the intermediate data block, and the second data arrangement method, includes: Step 2410: Based on the configuration parameters and the second data arrangement method, determine the second correspondence between the positions of multiple data elements in the intermediate data block and their positions in the output data block; Step 2420: Based on the second correspondence and the position of the input data block in the data to be converted, determine the shift number corresponding to multiple data elements in the intermediate data block.

[0284] Figure 25This is a flowchart illustrating an exemplary embodiment of the access address generation method provided in this disclosure, as shown below. Figure 25 As shown, the method also includes: Step 2510: Based on the size of the data to be converted, the first data layout, dimension step, access start address and access range, generate a first access address for reading the input data block from the memory; Step 2520: Based on the second data arrangement method, dimension step size, access start address and access range, generate a second access address for writing the output data block into the memory.

[0285] The beneficial technical effects corresponding to the exemplary embodiments of this device can be found in the corresponding beneficial technical effects of the exemplary method section above, and will not be repeated here.

[0286] Exemplary electronic devices Figure 26 A structural diagram of an electronic device provided in an embodiment of this disclosure includes at least one processor 2601 and a memory 2602.

[0287] The processor 2601 may be a central processing unit (CPU) or other form of processing unit with data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device 2600 to perform desired functions.

[0288] The memory 2602 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 2601 may execute one or more computer program instructions to implement the data arrangement conversion methods and / or other desired functions of the various embodiments of this disclosure described above.

[0289] In one example, the electronic device 2600 may also include an input device 2603 and an output device 2604, which are interconnected via a bus system and / or other forms of connection mechanism (not shown).

[0290] The input device 2603 may also include, for example, a keyboard, a mouse, etc.

[0291] The output device 2604 can output various information to the outside, including, for example, a display, a speaker, a printer, and a communication network and its connected remote output devices, etc.

[0292] Of course, for the sake of simplicity, Figure 26 Only some of the components of the electronic device 2600 relevant to this disclosure are shown, omitting components such as buses, input / output interfaces, etc. In addition, the electronic device 2600 may include any other suitable components depending on the specific application.

[0293] Exemplary neural network processor Figure 27 This is a schematic diagram of the structure of a neural network processor provided in an embodiment of the present disclosure, such as... Figure 27 As shown, the neural network processor 2700 includes a data layout conversion device 2701 and a memory 2702.

[0294] The data layout conversion device 2701 can perform layout conversion on the obtained data to be converted, thereby converting the dimensions of the data elements in the data to be converted. The specific implementation of the data layout conversion device 2701 in performing the layout conversion on the data to be converted can be found in the corresponding content of the foregoing embodiments. This data layout conversion device 2701 can be the same as the data layout conversion device 100 in the foregoing embodiments.

[0295] The memory 2702 is used to store data during the data layout conversion process performed by the data layout conversion device 2701. For example, the memory 2702 is used to store data such as data to be converted, input data blocks, intermediate data blocks, output data blocks, and output data blocks obtained from the layout conversion.

[0296] Neural Network Processor 2700 After obtaining the data to be converted, it can be done through... Neural Network Processor 2700 The data layout conversion device 2701 performs layout conversion processing on the data to be converted to obtain layout conversion data. The obtained layout conversion data can be stored in the memory 2702 for subsequent retrieval or further processing.

[0297] Exemplary computer program products and computer-readable storage media In addition to the methods and apparatus described above, embodiments of this disclosure may also provide a computer program product, including computer program instructions, which, when executed by a processor, cause the processor to perform the steps in the data arrangement conversion methods of the various embodiments of this disclosure described in the "Exemplary Methods" section above.

[0298] Computer program products can be written in any combination of one or more programming languages ​​to perform the operations of embodiments of this disclosure. The programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on a user's computing device, partially on a user's computing device, as a standalone software package, partially on a user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0299] Furthermore, embodiments of this disclosure may also be computer-readable storage media storing computer program instructions thereon, which, when executed by a processor, cause the processor to perform the steps in the data arrangement conversion methods of the various embodiments of this disclosure described in the "Exemplary Methods" section above.

[0300] Computer-readable storage media may take the form of any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may include, but is not limited to, systems, apparatuses, or devices that are electrical, magnetic, optical, electromagnetic, infrared, or semiconductor, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0301] The basic principles of this disclosure have been described above with reference to specific embodiments. However, the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.

[0302] Various modifications and variations can be made to this disclosure without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include such modifications and variations.

Claims

1. A data layout conversion device, comprising: A storage array, comprising multiple storage units, wherein each storage unit comprises multiple storage cells; The input rearrangement circuit is configured to acquire an input data block arranged according to a first data arrangement, and select multiple data elements corresponding to the storage bank from multiple data elements in the input data block based on the configuration parameters of the function operator and the position of the input data block in the data to be converted. The data writing circuit is configured to write multiple data elements into the same storage row in the storage array in response to a first cycle type of the write cycle; and to write multiple data elements into multiple storage rows in the storage array based on the first data arrangement and the configuration parameters in response to a second cycle type of the write cycle. The data reading circuit is configured to, in response to a reading cycle of the second cycle type, read multiple data elements from multiple storage rows in the storage array based on the first data arrangement to obtain an intermediate data block; and in response to a reading cycle of the first cycle type, read multiple data elements from the same storage row in the storage array to obtain the intermediate data block. The output rearrangement circuit is configured to rearrange multiple data elements in the intermediate data block to obtain an output data block arranged according to a second data arrangement.

2. The data layout conversion device according to claim 1, wherein, The input rearrangement circuit includes a plurality of first multiplexers, and the plurality of first multiplexers are respectively configured to correspond to a plurality of memory banks; The first multiplexer is configured to select a target data element from a plurality of data elements in the input data block based on configuration parameters of the function operator and the position of the input data block in the data to be transformed, and output the target data element.

3. The data layout conversion device according to claim 2, wherein, The first multiplexer is further configured as follows: Based on the first selection signal, the first element position of the target data element in the input data block is determined; Based on the position of the first element, the target data element is output.

4. The data layout conversion device according to claim 2, wherein the data layout conversion device further comprises a controller, the controller being configured to: Determine the position of the input data block in the data to be converted, the first data arrangement method, the size of the data to be converted, and the configuration parameters; Based on the position of the input data block in the data to be converted, the first data arrangement method, the size of the data to be converted, and the configuration parameters, determine the shift number corresponding to multiple data elements; Based on the shift value, the input rearrangement circuit is controlled to select multiple data elements corresponding to the memory bank from multiple data elements in the input data block.

5. The data layout conversion device according to claim 4, wherein, The controller is further configured to: Based on the position of the input data block in the data to be converted, the first data arrangement method, the size of the data to be converted, and the configuration parameters, a first correspondence between the positions of multiple data elements in the input data block and the addresses of multiple storage bodies is determined. Based on the first correspondence, the shift number is determined.

6. The data layout conversion device according to any one of claims 1-5, wherein, The data writing circuit includes multiple data distributors, each of which is configured to correspond to a plurality of first multiplexers in the input rearrangement circuit; each data distributor is coupled to a plurality of memory cells in the memory bank. The data distributor is configured to, in response to the type of the write cycle being the first cycle type, write a plurality of data elements output by the first multiplexer corresponding to the data distributor into a first storage cell belonging to the same storage row in a plurality of storage banks corresponding to the data distributor; and in response to the type of the write cycle being the second cycle type, write a plurality of data elements output by the first multiplexer corresponding to the data distributor into a second storage cell belonging to a plurality of storage rows in a plurality of storage banks corresponding to the data distributor.

7. The data layout conversion device according to claim 6, wherein, The data distributor is further configured to: Based on the second selection signal, determine the first row address of the first storage unit in the storage bank corresponding to the data distributor, or determine the second row address of the second storage unit in the storage bank corresponding to the data distributor; Based on the first row address, the data element output by the first multiplexer corresponding to the data distributor is written into the first storage unit; or, based on the second row address, the data element output by the first multiplexer corresponding to the data distributor is written into the second storage unit.

8. The data layout conversion device according to claim 1, wherein, The data layout conversion device further includes a controller, which is configured to: In response to the type of the write cycle being the first cycle type, based on the first data arrangement, the position of the input data block in the data to be converted, the size of the storage array, and the configuration parameters, the data write circuit is controlled to write multiple data elements into the same storage row of multiple storage banks; In response to the type of the write cycle being the second cycle type, based on the first data arrangement, the position of the input data block in the data to be converted, the size of the storage array, and the configuration parameters, the data write circuit is controlled to write multiple data elements into multiple storage rows of multiple storage bodies.

9. The data layout conversion device according to claim 8, wherein, The controller is further configured to: Based on the first data arrangement method, the position of the input data block in the data to be converted, the size of the storage array, and the configuration parameters, the shift number corresponding to the input data block is determined; In response to the type of the write cycle being the first cycle type, multiple first row addresses corresponding to the multiple memory banks are determined based on the shift bit and the memory bank addresses corresponding to the multiple memory banks respectively; Based on multiple first row addresses, the data writing circuit is controlled to write multiple data elements into the same storage row of multiple storage banks; In response to the type of the write cycle being the second cycle type, based on the shift bit and the memory addresses corresponding to the multiple memory banks respectively, multiple second row addresses corresponding to the multiple memory banks are determined; based on the multiple second row addresses, the data write circuit is controlled to write the multiple data elements into the multiple memory banks' multiple storage rows.

10. The data layout conversion apparatus according to any one of claims 1-9, wherein, The data reading circuit includes a plurality of second multiplexers; the plurality of second multiplexers are respectively configured corresponding to a plurality of the memory banks, and the second multiplexers are respectively coupled to a plurality of memory cells in the memory banks; The second multiplexer is configured to, in response to the type of the read cycle being the first cycle type, read and output a target data element from a first storage cell located in a first storage row among the plurality of storage banks corresponding to the second multiplexer; and in response to the type of the read cycle being the second cycle type, read and output a target data element from a second storage cell located in a plurality of second storage rows among the plurality of storage banks corresponding to the second multiplexer.

11. The data layout conversion device according to claim 10, wherein, The second multiplexer is further configured as follows: Based on the third selection signal, the first row address of the first storage cell in the storage bank corresponding to the second multiplexer is determined; Based on the first row address, the storage cell located in the first storage row in the storage bank corresponding to the second multiplexer is selected; Read the target data element from the target storage cell located at the first row address in the storage bank corresponding to the second multiplexer; or, Based on the third selection signal, the second row address of the second storage cell in the memory bank corresponding to the second multiplexer is determined; Based on the first row address or the second row address, select the storage cell located in the second storage row in the storage bank corresponding to the second multiplexer; The target data element is read from the target storage cell located at the second row address in the storage bank corresponding to the second multiplexer.

12. The data layout conversion apparatus according to any one of claims 1-11, wherein the data layout conversion apparatus further comprises a controller, the controller being configured to: In response to the read cycle being of the second cycle type, based on the first data arrangement, the position of the input data block in the data to be converted, the size of the storage array, and the configuration parameters, the data read circuit is controlled to read multiple data elements from multiple storage rows of multiple storage cells in the storage array. In response to the read cycle being of the first cycle type, the data read circuit is controlled to read multiple data elements from the same storage row in the storage array based on the first data arrangement, the position of the input data block in the data to be converted, the size of the storage array, and the configuration parameters.

13. The data layout conversion device according to claim 12, wherein, The controller is further configured to: Based on the first data arrangement method, the position of the input data block in the data to be converted, the size of the storage array, and the configuration parameters, the shift number corresponding to the input data block is determined; In response to the read cycle being of the second cycle type, multiple first row addresses corresponding to the multiple memory banks are determined based on the shift bit and the memory bank addresses corresponding to the multiple memory banks respectively. Based on multiple first row addresses, the data reading circuit is controlled to read multiple data elements from multiple first storage rows in the storage array; In response to the read cycle being of the first cycle type, the second row address corresponding to the plurality of memory banks is determined based on the shift bit and the memory bank addresses corresponding to the plurality of memory banks respectively; Based on the second row address, the data reading circuit is controlled to read multiple data elements from the second storage row in the storage array.

14. The data arrangement conversion device according to any one of claims 1-13, wherein the output rearrangement circuit includes a plurality of third multiplexers, and the plurality of third multiplexers are respectively configured to correspond to the element positions of a plurality of data elements in the output data block; The third multiplexer is configured to select a target data element from a plurality of data elements in the intermediate data block and output the target data element to the target position corresponding to the third multiplexer.

15. The data layout conversion device according to claim 14, wherein, The third multiplexer is further configured to: Based on the fourth selection signal, the position of the target data element as the second element in the intermediate data block is determined; Based on the position of the second element, the target data element is output.

16. The data layout conversion device according to claim 1, wherein the data layout conversion device further comprises a controller, the controller being configured to: Based on the configuration parameters, the position of the input data block in the data to be converted, the positions of multiple data elements in the intermediate data block, and the second data arrangement, determine the shift number corresponding to the multiple data elements in the intermediate data block; Based on the shift number, the output rearrangement circuit is controlled to rearrange the data elements in the intermediate data block.

17. The data layout conversion device according to claim 16, wherein, The controller is further configured to: Based on the configuration parameters and the second data arrangement method, a second correspondence between the positions of multiple data elements in the intermediate data block and their positions in the output data block is determined. Based on the second correspondence and the position of the input data block in the data to be converted, the shift number corresponding to the multiple data elements in the intermediate data block is determined.

18. The data layout conversion device according to claim 1, wherein the data layout conversion device further includes a controller, the controller including an input address generation unit and an output address generation unit; The input address generation unit is configured to generate a first access address for reading the input data block from the memory based on the size of the data to be converted, the first data arrangement method, the first dimension step size, the first access start address, and the first access range. The output address generation unit is configured to generate a second access address for writing the output data block into the memory based on the second data arrangement method, the second dimension step size, the second access start address, and the second access range.

19. A data layout transformation method, comprising: Obtain the input data block arranged according to the first data arrangement method, and select data elements corresponding to multiple storage volumes from multiple data elements in the input data block based on the configuration parameters of the function operator and the position of the input data block in the data to be converted; In response to a write cycle of type 1, multiple data elements are written to the same storage row in the storage array; in response to a write cycle of type 2, multiple data elements are written to multiple storage rows in the storage array based on the first data arrangement and the configuration parameters. In response to the read cycle type being the second cycle type, based on the first data arrangement, multiple data elements are read from multiple storage rows in the storage array to obtain an intermediate data block; in response to the read cycle type being the first cycle type, multiple data elements are read from the same storage row in the storage array to obtain the intermediate data block. The data elements in the intermediate data block are rearranged to obtain an output data block arranged according to the second data arrangement method.

20. A neural network processor, comprising a data layout conversion device and a memory; wherein, The data layout conversion device includes the data layout conversion device as described in any one of claims 1-18.

21. A computer-readable storage medium storing a computer program for executing the data arrangement conversion method of claim 19.

22. An electronic device, the electronic device comprising: processor; Memory used to store the processor's executable instructions; The processor is configured to read the executable instructions from the memory and execute the instructions to implement the data arrangement conversion method of claim 19.

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