Parameter configuration method and apparatus

Abstract

Embodiments of the present application disclose a parameter configuration method and device; the method comprises: obtaining a configuration instruction, obtaining a plurality of configuration sub-instructions from a storage unit according to address information in the configuration instruction; splitting each configuration sub-instruction into a corresponding source sub-instruction and a destination sub-instruction; wherein the source sub-instruction carries configuration parameter source information of the corresponding configuration sub-instruction, and the destination sub-instruction carries destination address information of the corresponding configuration sub-instruction; controlling each parallel configuration unit to perform the following operation: reading the source sub-instruction and the destination sub-instruction corresponding to all configuration sub-instructions, obtaining the configuration parameters of the corresponding configuration sub-instruction according to the configuration parameter source information in each source sub-instruction; determining the target operation core corresponding to each configuration sub-instruction according to the reference address information of the parallel configuration unit and the destination address information of each destination sub-instruction; and sending the configuration parameters of each configuration sub-instruction to the corresponding target operation core.

Description

Technical Field

[0001] This application relates to the field of artificial intelligence, specifically to a parameter configuration method and apparatus. Background Technology

[0002] With the increasing demand for computing power in artificial intelligence (AI), AI chips typically integrate large-scale arrays of computing cores to achieve high parallel computing output. In scenarios such as AI chip power-on initialization, operating mode switching, and dynamic parameter updates, configuration parameters need to be sent to a large number of computing cores. The configuration efficiency directly affects the startup speed and overall performance of the AI ​​chip.

[0003] Current core computing parameter configuration schemes cannot meet the high-efficiency configuration requirements of large-scale multi-core arrays. Summary of the Invention

[0004] This application provides a parameter configuration method and apparatus to solve the problem that the core parameter configuration schemes in related technologies cannot meet the high-efficiency configuration requirements of large-scale multi-core arrays.

[0005] In a first aspect, embodiments of this application provide a parameter configuration method, the method comprising: Obtain configuration instructions, and retrieve multiple configuration sub-instructions from the storage unit based on the address information in the configuration instructions; Each configuration sub-instruction is broken down into a one-to-one source sub-instruction and a destination sub-instruction; wherein, the source sub-instruction carries the source information of the configuration parameters of the corresponding configuration sub-instruction, and the destination sub-instruction carries the destination address information of the corresponding configuration sub-instruction; Each parallel configuration unit is controlled to perform the following operations: read the source and destination sub-instructions corresponding to all configuration sub-instructions, obtain the configuration parameters of the corresponding configuration sub-instruction based on the configuration parameter source information in each source sub-instruction; determine the target computing core corresponding to each configuration sub-instruction based on the base address information of the parallel configuration unit and the destination address information of each destination sub-instruction; and send the configuration parameters of each configuration sub-instruction to the corresponding target computing core.

[0006] In one embodiment, the configuration parameter source information includes the number of parameters to be configured, and one of an immediate value parameter or a read address; The configuration parameters of the corresponding configuration sub-instruction are obtained based on the configuration parameter source information in each source sub-instruction, including: Determine the relationship between the number of parameters to be configured in the source sub-instruction and the preset number threshold; If the number of parameters to be configured is less than or equal to the preset number threshold, then the immediate value parameter is extracted from the source sub-instruction and used as the configuration parameter of the corresponding configuration sub-instruction. If the number of parameters to be configured exceeds a preset threshold, a read request is generated based on the read address in the source sub-instruction to read the configuration parameters of the corresponding configuration sub-instruction from the storage unit.

[0007] In one embodiment, after generating a read request based on the read address in the source sub-instruction, the method provided by the first aspect further includes: Summarize all read requests generated by all parallel configuration units based on the read addresses in each source sub-instruction; Multiple read requests pointing to the same read address are merged into a single read request. The storage unit is accessed through the merged read request and the read request that is not merged, and the configuration parameters returned by the storage unit are broadcast to all parallel configuration units.

[0008] In one embodiment, determining the target computing core corresponding to each configuration sub-instruction based on the base address information of the parallel configuration unit and the destination address information of each destination sub-instruction includes: For each configuration sub-instruction, the base address information of the parallel configuration unit is calculated with the address offset in the destination address information of the corresponding destination sub-instruction to obtain the access address of the target computing core corresponding to each configuration sub-instruction.

[0009] In one embodiment, before sending the configuration parameters of each configuration sub-instruction to the corresponding target computing core, the method provided in the first aspect further includes: Based on the initial values ​​of the parallel configuration unit and the preset maximum values ​​of each dimension in the three-dimensional coordinate space, the three-dimensional coordinate information of each target computing core in the parallel configuration unit is generated. Send the configuration parameters of each configuration sub-instruction to the corresponding target computing core, including: Send the configuration parameters corresponding to each configuration sub-instruction, as well as the three-dimensional coordinate information of the corresponding target computing core, to the corresponding target computing core; The initial value of the parallel configuration unit is determined as follows: Obtain the initial value of the first parallel configuration unit; the initial values ​​of the remaining parallel configuration units are equal to the sum of the initial value of the previous parallel configuration unit and the total number of target computing cores to be configured in the previous parallel configuration unit.

[0010] In one embodiment, based on the initial value of the parallel configuration unit and the preset maximum value of each dimension in the three-dimensional coordinate space, the three-dimensional coordinate information of each target computing core in the parallel configuration unit is generated, including: The initial value of the parallel configuration unit is compared with the maximum value of the first dimension in the three-dimensional coordinate space. The first remainder obtained from the first comparison is determined as the first dimension coordinate value of the first target computing core of the parallel configuration unit, and the first quotient obtained from the first comparison is determined as the intermediate computing value. The intermediate calculated value is compared with the preset maximum value of the second dimension in the three-dimensional coordinate space. The second remainder obtained from the second comparison is determined as the second dimension coordinate value of the first target computing core of the parallel configuration unit. The second quotient obtained from the second comparison is determined as the third dimension coordinate value of the first target computing core of the parallel configuration unit. Based on the first, second, and third dimension coordinates of the first target computing core of the parallel configuration unit, the three-dimensional coordinate information of each target computing core corresponding to the parallel configuration unit is determined.

[0011] Secondly, embodiments of this application provide a parameter configuration device applied to a chip system integrating multiple computing cores. The parameter configuration device includes an instruction fetch engine and multiple parallel configuration units. The instruction fetching engine is used to obtain configuration instructions and retrieve multiple configuration sub-instructions from the storage unit based on the address information in the configuration instructions. Each configuration sub-instruction is then split into a one-to-one source sub-instruction and a destination sub-instruction. The source sub-instruction carries the source information of the configuration parameters of the corresponding configuration sub-instruction, and the destination sub-instruction carries the destination address information of the corresponding configuration sub-instruction. The parallel configuration unit is used to read the source and destination sub-instructions corresponding to all configuration sub-instructions, obtain the configuration parameters of the corresponding configuration sub-instruction based on the configuration parameter source information in each source sub-instruction, determine the target computing core corresponding to each configuration sub-instruction based on the reference address information of the parallel configuration unit and the destination address information of each destination sub-instruction, and send the configuration parameters of each configuration sub-instruction to the corresponding target computing core.

[0012] In one embodiment, the apparatus provided by the second aspect further includes a source sub-instruction cache and a destination sub-instruction cache; The source sub-instruction cache is used to cache the source sub-instructions split from each configuration sub-instruction; The destination sub-instruction cache is used to cache the destination sub-instructions split from each configuration sub-instruction.

[0013] In one embodiment, the parallel configuration unit includes a source data engine, a destination address engine, and a parameter cache to be configured; the apparatus provided in the second aspect further includes a data retrieval engine. The source data engine is used to read all source sub-instructions in the source sub-instruction cache; determine the relationship between the number of parameters to be configured corresponding to each source sub-instruction and the preset number threshold; if the number of parameters to be configured is less than or equal to the preset number threshold, then extract the immediate value parameter from the source sub-instruction as the configuration parameter of the corresponding configuration sub-instruction and write it into the parameter to be configured cache; if the number of parameters to be configured is greater than the preset number threshold, then generate a read request based on the read address in the source sub-instruction. The data retrieval engine is used to aggregate read requests generated by all parallel configuration units, merge multiple read requests pointing to the same read address into a single read request; access the storage unit through the merged read request and the read requests that were not merged, and broadcast the configuration parameters returned by the storage unit to all parallel configuration units; The destination address engine is used to read all destination sub-instructions in the destination sub-instruction cache, calculate the base address information of the parallel configuration unit to which it belongs and the address offset in the destination address information of each destination sub-instruction to obtain the access address of the target computing core corresponding to each configuration sub-instruction, and write the access address into the parameter cache to be configured. The configuration parameter cache is used to cache the configuration parameters broadcast by the data retrieval engine and the access address of the target computing core corresponding to the parallel configuration unit, and to send the configuration parameters to the corresponding target computing core according to the access address.

[0014] In one embodiment, the parallel configuration unit further includes a coordinate calculator; The coordinate calculator is used to determine the three-dimensional coordinate information of each target computing core corresponding to the parallel configuration unit based on the initial value of the parallel configuration unit and the preset maximum value of each dimension in the three-dimensional coordinate space.

[0015] The parameter configuration method provided in this application decouples the source and target address information of configuration parameters by splitting each configuration sub-instruction into a one-to-one source sub-instruction and a destination sub-instruction, thereby improving the addressing flexibility and scenario adaptability of parameter configuration. A single parallel configuration unit can process multiple configuration sub-instructions and complete the parameter configuration of multiple target computing cores, effectively improving the configuration coverage and execution efficiency of a single configuration unit. At the same time, after controlling multiple parallel configuration units to read all configuration sub-instructions, they independently determine the target computing cores based on their own base address information and execute the configuration parameter distribution in parallel. There is no need to set up a complex scheduling module. While simplifying the hardware architecture and reducing costs, it fully improves the overall concurrency of configuration operations and can efficiently adapt to the batch configuration requirements of large-scale computing core arrays.

[0016] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are merely embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort, and this application can be applied to other similar scenarios based on the provided drawings.

[0018] Figure 1 A flowchart illustrating a parameter configuration method provided in an embodiment of this application; Figure 2 This is a schematic diagram of the structure of the configuration sub-instructions provided in the embodiments of this application; Figure 3 A flowchart illustrating the method for obtaining configuration parameters provided in an embodiment of this application; Figure 4 A schematic diagram of the parameter configuration provided in the embodiments of this application. Detailed Implementation

[0019] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. The described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0020] It should be noted that the terms "system," "device," "unit," and / or "module" used in this application are methods of distinguishing different components, elements, parts, sections, or assemblies at different levels. However, if other terms can achieve the same purpose, they can be replaced by other expressions.

[0021] Hereinafter, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature.

[0022] With the increasing demand for computing power in artificial intelligence (AI), AI chips typically integrate large-scale arrays of computing cores to achieve high parallel computing output. In scenarios such as AI chip power-on initialization, operating mode switching, and dynamic parameter updates, configuration parameters need to be sent to a large number of AI computing cores. The configuration efficiency directly affects the startup speed and overall performance of the AI ​​chip.

[0023] There are two main types of parameter configuration schemes for the computing core: First, the serial configuration scheme: only a single configuration path is set up, and configuration parameters are sent to each computing core sequentially. This scheme has simple hardware logic, but the configuration process of all computing cores is executed serially. The larger the scale of the computing core array, the longer the overall configuration time and the lower the efficiency.

[0024] Second, the multi-channel parallel configuration scheme: Although the multi-channel parallel configuration scheme improves the parameter configuration efficiency to a certain extent, firstly, the parallelism is low, and each channel can only configure parameters for one computing core; secondly, the configuration parameters are the same for all computing cores, and it is impossible to configure different configuration parameters according to the different computing cores.

[0025] To address at least one of the aforementioned technical problems, embodiments of this application provide a parameter configuration method and apparatus.

[0026] Figure 1 This is a flowchart illustrating a parameter configuration method provided in an embodiment of this application.

[0027] like Figure 1 As shown, the parameter configuration method provided in this application embodiment can be applied to a chip system integrating multiple computing cores and multiple parallel configuration units. The parameter configuration method includes the following steps: Step 101: Obtain configuration instructions; retrieve multiple configuration sub-instructions from the storage unit based on the address information in the configuration instructions. In one embodiment, the configuration instruction may be issued by the instruction decoding and dispatching unit of the chip system. The configuration instruction indicates the storage location of the configuration sub-instructions in the memory unit; for example, the configuration instruction may include a start address field, the value of which indicates the storage address of the configuration sub-instructions in the memory unit. The memory unit may be the shared memory of the chip system to be configured, or it may be shared memory shared by multiple chip systems. After obtaining the configuration instruction, multiple configuration sub-instructions can be retrieved from the shared memory based on the value of the start address field in the configuration instruction.

[0028] In one embodiment, the configuration sub-instruction includes a type field, a quantity field, a reserved field, an address offset field, and a configuration data field. The Type field is used to indicate the business type of the configuration sub-directive, such as a configuration sub-directive for parameter configuration; The quantity field (Cnt) is used to indicate the number of parameters to be configured in the configuration sub-instruction; The reserved field (rsvd) is used to reserve unused bits to provide redundant space for the chip system to add configuration functions and expand instruction formats in the future. In this embodiment, it does not participate in configuration logic operations. The address offset field (addr_offset) is used to indicate the relative offset address of the target computing core to be configured by the configuration sub-instruction. The parallel configuration unit can calculate the actual hardware access address of the computing core to be configured by combining its own stored base address with this address offset. The configuration data field (TDDW) is used to carry the main content of the parameters to be configured. When the number of parameters to be configured is less than or equal to the preset number threshold, it stores the embedded immediate parameters (i.e. the parameters to be configured). When the number of parameters to be configured is greater than the preset number threshold, it stores the parameter read address of the storage unit (i.e. the storage address of the parameters to be configured).

[0029] Step 102: Divide each configuration sub-instruction into a one-to-one source sub-instruction and a destination sub-instruction; The source sub-instruction carries the source information of the configuration parameters of the corresponding configuration sub-instruction (quantity field (Cnt) and configuration data field (TDDW)), and the destination sub-instruction carries the destination address information of the corresponding configuration sub-instruction (addr_offset field).

[0030] Specifically, Figure 2 This is a schematic diagram illustrating the structure of the configuration sub-instructions provided in an embodiment of this application. For example... Figure 2 As shown, the source sub-instruction includes a type field (Type), a quantity field (Cnt), and a configuration data field (TDDW), while the destination sub-instruction includes a type field (Type), a quantity field (Cnt), and an address offset field (addr_offset).

[0031] After splitting the configuration sub-instructions into corresponding source and destination sub-instructions, the source and destination sub-instructions can be stored in the chip system's source and destination sub-instruction caches, respectively. Specifically, in the source and destination sub-instruction caches, starting from the entry with index 0, assuming there are n configuration sub-instructions, the indices corresponding to the entries are 0, 1, 2, ..., n-1. Each entry also has a valid bit: the valid bit is 1 for entries that store source or destination sub-instructions, and 0 for entries that do not store source or destination sub-instructions.

[0032] Step 103: Control each parallel configuration unit to perform the following operations: read the source sub-instructions and destination sub-instructions corresponding to all configuration sub-instructions, obtain the configuration parameters of the corresponding configuration sub-instruction according to the configuration parameter source information in each source sub-instruction; determine the target computing core corresponding to each configuration sub-instruction according to the reference address information of the parallel configuration unit and the destination address information of each destination sub-instruction; and send the configuration parameters of each configuration sub-instruction to the corresponding target computing core.

[0033] In one embodiment, if a source sub-instruction cache and a destination sub-instruction cache are configured, the configuration unit reads all source sub-instructions corresponding to configuration sub-instructions from the source sub-instruction cache. Specifically, the reading process involves traversing and reading all entries in the source sub-instruction cache until the valid bit of the currently read entry is 0. During the reading process, the configuration parameters of the corresponding configuration sub-instruction are obtained directly or indirectly from the configuration data field (TDDW) of the read source sub-instruction. Direct acquisition means that if the number of parameters to be configured (the quantity field (Cnt)) is less than or equal to a preset quantity threshold, an immediate parameter is extracted from the configuration data field (TDDW) as the configuration parameter of the corresponding configuration sub-instruction. Indirect acquisition means that if the number of parameters to be configured is greater than the preset quantity threshold, a read request is generated based on the read address of the configuration data field (TDDW) of the source sub-instruction to read the configuration parameters of the corresponding configuration sub-instruction from the storage unit.

[0034] The destination address engine is used to read all destination sub-instructions corresponding to all configuration sub-instructions. Specifically, the configuration unit reads all destination sub-instructions corresponding to all configuration sub-instructions from the destination sub-instruction cache. The reading process is the same as reading data from the source sub-instruction cache, and will not be elaborated here. During the reading process, the address offset of the corresponding configuration sub-instruction is obtained from the address offset field (addr_offset) of the read destination sub-instruction. Based on the base address information of the parallel configuration unit and the destination address information of each destination sub-instruction, the target computation core corresponding to each configuration sub-instruction is determined. Then, the configuration parameters of all configuration sub-instructions and their corresponding target computing cores are stored in the cache, and the configuration parameters of each configuration sub-instruction are sent to the corresponding target computing core.

[0035] The parameter configuration method provided in this application decouples the source and target address information of configuration parameters by splitting each configuration sub-instruction into a one-to-one source sub-instruction and a destination sub-instruction, thereby improving the addressing flexibility and scenario adaptability of parameter configuration. A single parallel configuration unit can process multiple configuration sub-instructions and complete the parameter configuration of multiple target computing cores, effectively improving the configuration coverage and execution efficiency of a single configuration unit. At the same time, after controlling multiple parallel configuration units to read all configuration sub-instructions, they independently determine the target computing cores based on their own base address information and execute the configuration parameter distribution in parallel. There is no need to set up a complex scheduling module. While simplifying the hardware architecture and reducing costs, it fully improves the overall concurrency of configuration operations and can efficiently adapt to the batch configuration requirements of large-scale computing core arrays.

[0036] In one embodiment, as described in step 103 above, the configuration parameter source information includes the number of parameters to be configured, and one of an immediate value parameter or a read address; The configuration parameters of the corresponding configuration sub-instruction are obtained based on the configuration parameter source information in each source sub-instruction, including: Determine the relationship between the number of parameters to be configured in the source sub-instruction and the preset number threshold; If the number of parameters to be configured is less than or equal to the preset number threshold, then the immediate value parameter is extracted from the source sub-instruction and used as the configuration parameter of the corresponding configuration sub-instruction. If the number of parameters to be configured exceeds a preset threshold, a read request is generated based on the read address in the source sub-instruction to read the configuration parameters of the corresponding configuration sub-instruction from the storage unit.

[0037] In one embodiment, the preset quantity threshold is usually set to 1. Since the number of parameters that a configuration sub-instruction can carry is limited, when there is only one configuration parameter, the configuration data field (TDDW) of the corresponding configuration sub-instruction can be directly embedded in the form of an immediate parameter. If there are multiple configuration parameters, the configuration data field (TDDW) of the configuration sub-instruction only stores the storage address of the configuration parameter in the storage unit.

[0038] Figure 3 This is a flowchart illustrating the method for obtaining configuration parameters provided in an embodiment of this application.

[0039] like Figure 3 As shown, in one embodiment, after generating a read request based on the read address in the source sub-instruction in step 103, the parameter configuration method provided in this application embodiment further includes the following steps: Step 301: Summarize all read requests generated by all parallel configuration units based on the read addresses in each source sub-instruction; In one embodiment, the read request generated by the parallel configuration unit based on the read address in each source sub-instruction contains a read address identifier, which is used to uniquely indicate the corresponding read address. Therefore, read requests with the same read address identifier obtain the same configuration parameters from the storage unit.

[0040] Step 302: Merge multiple read requests that point to the same read address into a single read request; In one embodiment, based on the description of step 301, read requests pointing to the same read address have the same read address identifier. Therefore, read requests with the same read address identifier can be merged into the same read request to reduce the number of interactions with the storage unit and further improve parameter configuration efficiency.

[0041] Step 303: Access the storage unit through the merged read request and the read request that did not participate in the merge, and broadcast the configuration parameters returned by the storage unit to all parallel configuration units.

[0042] In one embodiment, the configuration parameters returned by the storage unit are broadcast to all parallel configuration units, and each parallel configuration unit can obtain its own configuration parameters as needed and store them in a cache.

[0043] It is understandable that if the cache of the parallel configuration unit is insufficient to store all the configuration parameters, then it is possible to choose to store only some of the configuration parameters.

[0044] Based on this, after the parallel configuration unit generates a read request according to the read address in the source sub-instruction, it can obtain the corresponding configuration parameters from the storage unit.

[0045] In one embodiment, according to the description of step 103, determining the target computing core corresponding to each configuration sub-instruction based on the base address information of the parallel configuration unit and the destination address information of each destination sub-instruction in step 103 includes: For each configuration sub-instruction, the base address information of the parallel configuration unit is calculated with the address offset in the destination address information of the corresponding destination sub-instruction to obtain the access address of the target computing core corresponding to each configuration sub-instruction.

[0046] In one embodiment, the address offset can be configured as needed. For example, the configuration offset of different destination sub-instructions can be a continuous value, such as 1, 2, 3, ..., or a discrete value, such as 1, 3, 6, ..., to achieve continuous or discrete configuration of multiple computing cores corresponding to the parallel configuration unit.

[0047] In one embodiment, the above configuration process is based on the same configuration sub-instruction, that is, the configuration parameters of the computing cores configured by different parallel configuration units are the same.

[0048] To achieve differentiated configurations for different computing cores, before sending the configuration parameters of each configuration sub-instruction to the corresponding target computing core in step 103, the parameter configuration method provided in this application embodiment further includes the following steps: Based on the initial values ​​of the parallel configuration unit and the preset maximum values ​​of each dimension in the three-dimensional coordinate space, the three-dimensional coordinate information of each target computing core in the parallel configuration unit is generated. Send the configuration parameters of each configuration sub-instruction to the corresponding target computing core, including: The configuration parameters corresponding to each configuration sub-instruction, as well as the three-dimensional coordinate information of the corresponding target computing core, are sent to the corresponding target computing core.

[0049] The initial value of the parallel configuration unit is determined as follows: Obtain the initial value of the first parallel configuration unit; the initial values ​​of the remaining parallel configuration units are equal to the sum of the initial value of the previous parallel configuration unit and the total number of target computing cores to be configured in the previous parallel configuration unit.

[0050] In one embodiment, the three-dimensional coordinate space refers to any three-dimensional coordinate space, such as the three-dimensional coordinate space formed by the arrangement of computing cores in a chip; in the three-dimensional coordinate space, the preset maximum value of each dimension is the number of computing cores in that dimension.

[0051] In one embodiment, the initial value of the first parallel configuration unit can be any preset value, such as 0 or 1, which is not limited in this application.

[0052] In one embodiment, taking the initial value of the first parallel configuration unit as 0 and the number of computing cores to be configured in the first parallel configuration unit as 5, the initial value of the second parallel configuration unit is equal to 5+0, that is, the initial value of the second parallel configuration unit is 5.

[0053] In one embodiment, based on the initial value of the parallel configuration unit and the preset maximum value of each dimension in the three-dimensional coordinate space, the three-dimensional coordinate information of each target computing core in the parallel configuration unit is generated, including: The initial value of the parallel configuration unit is compared with the maximum value of the first dimension in the three-dimensional coordinate space. The first remainder obtained from the first comparison is determined as the first dimension coordinate value of the first target computing core of the parallel configuration unit, and the first quotient obtained from the first comparison is determined as the intermediate computing value. The intermediate calculated value is compared with the preset maximum value of the second dimension in the three-dimensional coordinate space. The second remainder obtained from the second comparison is determined as the second dimension coordinate value of the first target computing core of the parallel configuration unit. The second quotient obtained from the second comparison is determined as the third dimension coordinate value of the first target computing core of the parallel configuration unit. Based on the first, second, and third dimension coordinates of the first target computing core of the parallel configuration unit, the three-dimensional coordinate information of each target computing core corresponding to the parallel configuration unit is determined.

[0054] In one embodiment, after determining the first-dimensional coordinate value, the second-dimensional coordinate value, and the third-dimensional coordinate value of the first target computing core of the parallel configuration unit, the three-dimensional coordinates of the first target computing core of the parallel configuration unit can be represented as (first-dimensional coordinate value, second-dimensional coordinate value, third-dimensional coordinate value). The three-dimensional coordinates of the other target computing cores of the parallel configuration unit can be generated by incrementally increasing the three-dimensional coordinates of the first target computing core in each dimension. For example, the three-dimensional coordinates of the second target computing core can be represented as (first-dimensional coordinate value + 1, second-dimensional coordinate value + 1, third-dimensional coordinate value + 1).

[0055] In one embodiment, after determining the three-dimensional coordinates of each target computing core corresponding to the parallel configuration unit, the configuration parameters corresponding to each configuration sub-instruction and the three-dimensional coordinate information of the corresponding target computing core can be sent to the corresponding target computing core.

[0056] Corresponding to the parameter configuration method provided in the above embodiments of this application, the embodiments of this application also provide a parameter configuration device for implementing the above parameter configuration method.

[0057] Figure 4 A schematic diagram of the parameter configuration provided in the embodiments of this application.

[0058] like Figure 4 As shown, the parameter configuration provided in this application embodiment is applied to a chip system integrating multiple computing cores. The parameter configuration device includes an instruction fetch engine 401 and multiple parallel configuration units 402 (such as...). Figure 4 In the first parallel configuration unit 402, ..., the nth parallel configuration unit 402); the instruction fetching engine 401 is used to fetch configuration instructions and retrieve multiple configuration sub-instructions from the storage unit 403 according to the address information in the configuration instructions; each configuration sub-instruction is split into a one-to-one corresponding source sub-instruction and destination sub-instruction; wherein, the source sub-instruction carries the configuration parameter source information of the corresponding configuration sub-instruction, and the destination sub-instruction carries the destination address information of the corresponding configuration sub-instruction; The parallel configuration unit 402 is used to read the source sub-instructions and destination sub-instructions corresponding to all configuration sub-instructions, obtain the configuration parameters of the corresponding configuration sub-instruction according to the configuration parameter source information in each source sub-instruction, determine the target computing core corresponding to each configuration sub-instruction according to the reference address information of the parallel configuration unit 402 and the destination address information of each destination sub-instruction, and send the configuration parameters of each configuration sub-instruction to the corresponding target computing core.

[0059] In one embodiment, the parameter configuration device provided in this application further includes a source sub-instruction cache 4011 and a destination sub-instruction cache 4012; Source sub-instruction cache 4011 is used to cache the source sub-instructions split from each configuration sub-instruction; Destination sub-instruction cache 4012 is used to cache the destination sub-instructions split from each configuration sub-instruction.

[0060] In one embodiment, the parallel configuration unit 402 includes a source data engine 4021, a destination address engine 4022, and a parameter cache to be configured 4023, and the device further includes a data retrieval engine 404. The source data engine 4021 is used to read all source sub-instructions in the source sub-instruction cache 4011; determine the relationship between the number of parameters to be configured corresponding to each source sub-instruction and the preset number threshold; if the number of parameters to be configured is less than or equal to the preset number threshold, then the immediate value parameter is extracted from the source sub-instruction as the configuration parameter of the corresponding configuration sub-instruction and written to the parameter to be configured cache 4023; if the number of parameters to be configured is greater than the preset number threshold, then a read request is generated according to the read address in the source sub-instruction. The data retrieval engine 404 is used to aggregate all read requests generated by the parallel configuration units 402, merge multiple read requests pointing to the same read address into a single read request; access the storage unit 403 through the merged read request and the read requests that did not participate in the merging, and broadcast the configuration parameters returned by the storage unit 403 to all parallel configuration units 402. The destination address engine 4022 is used to read all destination sub-instructions in the destination sub-instruction cache 4012, calculate the base address information of the parallel configuration unit 402 to which it belongs and the address offset in the destination address information of each destination sub-instruction, obtain the access address of the target computing core corresponding to each configuration sub-instruction, and write the access address into the parameter cache to be configured 4023. The configuration parameter cache 4023 is used to cache the configuration parameters broadcast by the data retrieval engine 404 and the access address of the target computing core corresponding to the parallel configuration unit 402, and to send the configuration parameters to the corresponding target computing core according to the access address.

[0061] In one embodiment, the parallel configuration unit 402 further includes a coordinate calculator 4024; The coordinate calculator 4024 is used to determine the three-dimensional coordinate information of each target computing core corresponding to the parallel configuration unit 402 based on the initial value of the parallel configuration unit 402 and the preset maximum value of each dimension in the three-dimensional coordinate space.

[0062] Understandably, after the coordinate calculator 4024 determines the three-dimensional coordinate information of each target computing core corresponding to the parallel configuration unit 402, it can send the three-dimensional coordinate information of the target computing core to the parameter cache 4023 to be configured. The parameter cache 4023 then sends the configuration parameters corresponding to each configuration sub-instruction and the three-dimensional coordinate information of the corresponding target computing core to the corresponding target computing core.

[0063] In the parameter configuration device provided in the above-described embodiments of this application, the implementation process of each step can be referred to the embodiments of the parameter configuration method described above, and will not be repeated here.

[0064] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A parameter configuration method, characterized in that, The method, applied to a chip system integrating multiple computing cores and multiple parallel configuration units, includes: Obtain configuration instructions, and retrieve multiple configuration sub-instructions from the storage unit based on the address information in the configuration instructions; Each configuration sub-instruction is divided into a one-to-one source sub-instruction and a destination sub-instruction; wherein, the source sub-instruction carries the source information of the configuration parameters of the corresponding configuration sub-instruction, and the destination sub-instruction carries the destination address information of the corresponding configuration sub-instruction; Each of the parallel configuration units is controlled to perform the following operations: read the source sub-instruction and the destination sub-instruction corresponding to all the configuration sub-instructions; obtain the configuration parameters of the corresponding configuration sub-instruction according to the configuration parameter source information in each source sub-instruction; determine the target computing core corresponding to each configuration sub-instruction according to the base address information of the parallel configuration unit and the destination address information of each destination sub-instruction; and send the configuration parameters of each configuration sub-instruction to the corresponding target computing core. Wherein, obtaining the configuration parameters of the corresponding configuration sub-instruction based on the configuration parameter source information in each of the source sub-instructions includes: Determine the relationship between the number of parameters to be configured in the source sub-instruction and the preset number threshold; If the number of parameters to be configured is less than or equal to a preset number threshold, then an immediate parameter is extracted from the source sub-instruction and used as the configuration parameter of the corresponding configuration sub-instruction. If the number of parameters to be configured is greater than the preset number threshold, a read request is generated based on the read address in the source sub-instruction to read the configuration parameters of the corresponding configuration sub-instruction from the storage unit.

2. The method according to claim 1, characterized in that, After generating a read request based on the read address in the source sub-instruction, the method further includes: Summarize all read requests generated by all the parallel configuration units based on the read addresses in each source sub-instruction; Multiple read requests pointing to the same read address are merged into a single read request. The storage unit is accessed through the merged read request and the read request that is not merged, and the configuration parameters returned by the storage unit are broadcast to all parallel configuration units.

3. The method according to claim 1, characterized in that, The step of determining the target computing core corresponding to each configuration sub-instruction based on the base address information of the parallel configuration unit and the destination address information of each destination sub-instruction includes: For each configuration sub-instruction, the base address information of the parallel configuration unit is calculated with the address offset in the destination address information of the corresponding destination sub-instruction to obtain the access address of the target computing core corresponding to each configuration sub-instruction.

4. The method according to claim 1, characterized in that, Before sending the configuration parameters of each configuration sub-instruction to the corresponding target computing core, the method further includes: Based on the initial value of the parallel configuration unit and the preset maximum value of each dimension in the three-dimensional coordinate space, the three-dimensional coordinate information of each target computing core in the parallel configuration unit is generated. Sending the configuration parameters of each configuration sub-instruction to the corresponding target computing core includes: The configuration parameters corresponding to each configuration sub-instruction, and the three-dimensional coordinate information of the corresponding target computing core are sent to the corresponding target computing core; The initial value of the parallel configuration unit is determined as follows: Obtain the initial value of the first parallel configuration unit; the initial values ​​of the remaining parallel configuration units are equal to the sum of the initial value of the previous parallel configuration unit and the total number of target computing cores to be configured in the previous parallel configuration unit.

5. The method according to claim 4, characterized in that, The step of generating the three-dimensional coordinate information of each target computing core in the parallel configuration unit based on the initial value of the parallel configuration unit and the preset maximum value of each dimension in the three-dimensional coordinate space includes: The initial value of the parallel configuration unit is compared with the preset maximum value of the first dimension in the three-dimensional coordinate space. The first remainder obtained from the first comparison is determined as the first dimension coordinate value of the first target computing core of the parallel configuration unit, and the first quotient obtained from the first comparison is determined as the intermediate computing value. The intermediate calculated value is compared with the preset maximum value of the second dimension in the three-dimensional coordinate space. The second remainder obtained from the second comparison is determined as the second dimension coordinate value of the first target computing core of the parallel configuration unit. The second quotient obtained from the second comparison is determined as the third dimension coordinate value of the first target computing core of the parallel configuration unit. Based on the first-dimensional coordinate value, the second-dimensional coordinate value, and the third-dimensional coordinate value of the first target computing core of the parallel configuration unit, the three-dimensional coordinate information of each target computing core corresponding to the parallel configuration unit is determined.

6. A parameter configuration device, characterized in that, Applied to chip systems integrating multiple computing cores, the device includes an instruction fetch engine and multiple parallel configuration units; The instruction fetching engine is used to obtain configuration instructions, retrieve multiple configuration sub-instructions from the storage unit according to the address information in the configuration instructions, and split each configuration sub-instruction into a one-to-one corresponding source sub-instruction and destination sub-instruction; wherein, the source sub-instruction carries the configuration parameter source information of the corresponding configuration sub-instruction, and the destination sub-instruction carries the destination address information of the corresponding configuration sub-instruction; The parallel configuration unit is used to read all the source sub-instructions and destination sub-instructions corresponding to the configuration sub-instructions, obtain the configuration parameters of the corresponding configuration sub-instruction according to the configuration parameter source information in each source sub-instruction, determine the target computing core corresponding to each configuration sub-instruction according to the reference address information of the parallel configuration unit and the destination address information of each destination sub-instruction, and send the configuration parameters of each configuration sub-instruction to the corresponding target computing core. The parallel configuration unit includes: The source data engine is used to read all source sub-instructions in the source sub-instruction cache; determine the relationship between the number of parameters to be configured corresponding to each source sub-instruction and a preset number threshold; if the number of parameters to be configured is less than or equal to the preset number threshold, then an immediate parameter is extracted from the source sub-instruction as the configuration parameter of the corresponding configuration sub-instruction and written into the parameter to be configured cache; if the number of parameters to be configured is greater than the preset number threshold, then a read request is generated according to the read address in the source sub-instruction.

7. The apparatus according to claim 6, characterized in that, The device further includes a source sub-instruction cache and a destination sub-instruction cache; The source sub-instruction cache is used to cache the source sub-instructions split from each of the configuration sub-instructions; The destination sub-instruction cache is used to cache the destination sub-instructions split from each of the configuration sub-instructions.

8. The apparatus according to claim 7, characterized in that, The parallel configuration unit includes a destination address engine and a parameter cache to be configured, and the device also includes a data retrieval engine. The data retrieval engine is used to aggregate all the read requests generated by the parallel configuration units and merge multiple read requests pointing to the same read address into a single read request. The storage unit is accessed through the merged read request and the read request that is not merged, and the configuration parameters returned by the storage unit are broadcast to all parallel configuration units; The destination address engine is used to read all the destination sub-instructions in the destination sub-instruction cache, calculate the base address information of the parallel configuration unit to which it belongs and the address offset in the destination address information of each destination sub-instruction to obtain the access address of the target computing core corresponding to each configuration sub-instruction, and write the access address into the parameter cache to be configured. The configuration parameter cache is used to cache the configuration parameters broadcast by the data retrieval engine and the access address of the target computing core corresponding to the parallel configuration unit, and to send the configuration parameters to the corresponding target computing core according to the access address.

9. The apparatus according to claim 6, characterized in that, The parallel configuration unit also includes a coordinate calculator; The coordinate calculator is used to determine the three-dimensional coordinate information of each target computing core corresponding to the parallel configuration unit based on the initial value of the parallel configuration unit and the preset maximum value of each dimension in the three-dimensional coordinate space.

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