Netlist logic hierarchy restructuring method, system, and apparatus for logic eco

Abstract

The application provides a netlist logic level reconstruction method, system and device for logic ECO, relates to the technical field of integrated circuit computer-aided design, and the method comprises the following steps: obtaining a comprehensive netlist S with complete logic levels and an ECO benchmark netlist P optimized through a back end; identifying a target logic level M related to engineering changes in S, determining a first boundary point set {Si} composed of boundary ports, and searching for nodes with logic equivalence in P to form a second boundary point set {Pi}; obtaining an ECO target netlist E, determining a third boundary point set {Ei} composed of boundary ports corresponding to logic modules in E, and inputting the pairing relationship between {Pi} and {Ei} as a constraint condition into an ECO generation tool; and the ECO generation tool performs difference comparison in a local range defined by the constraint condition, thereby generating an ECO script. The application greatly reduces the search space, significantly improves the ECO generation efficiency and success rate, effectively reduces the iteration risk in the design later stage, and is easy to integrate without changing the core algorithm of the existing ECO tool.

Description

Technical Field

[0001] This invention relates to the field of computer-aided design technology for integrated circuits, and more specifically, to a method, system, and device for reconstructing the netlist logic hierarchy for logic ECO. Background Technology

[0002] In the digital integrated circuit design flow, engineering change orders (ECOs) are often required in the later stages of the design process to fix design errors or update chip functionality. Automated ECO generation tools typically compare the design netlist before the change (usually the netlist after place-and-route and back-end optimization, denoted as P) with the target netlist after the change (the netlist obtained by synthesis from the modified register-transfer level description, denoted as E), and automatically output corrective scripts to implement the changed logic functions. This is an indispensable and crucial step before chip tape-out.

[0003] Currently, the core prerequisite for the efficient operation of existing commercial ECO tools (such as Cadence Conformal ECO and Synopsys Formality) is that netlist P and netlist E maintain a high degree of logical structural similarity, especially the existence of a clear and mappable logical hierarchical correspondence. When this condition is met, the tool can decompose the complex global netlist alignment problem into local alignments within multiple corresponding logical modules, thereby efficiently generating concise ECO scripts.

[0004] However, in actual back-end physical design processes, to achieve physical optimization goals such as timing, area, and power consumption, logic synthesis and physical implementation tools typically perform deep structural optimization on the netlist. This includes employing a "flattening" strategy, which intentionally removes or merges intermediate logic layers, transforming the hierarchical circuit structure into a flattened gate-level netlist. This results in the netlist P used as a benchmark often being a netlist with a simplified or even completely flattened hierarchical structure. When this flattened netlist P is compared with a target netlist E that has a complete and clear hierarchical structure, the original module hierarchy correspondence between the two is severely disrupted.

[0005] In situations where the netlist structures differ significantly, existing ECO tools can no longer confine the comparison scope to specific logic modules, forcing them to degenerate into global graph matching and difference searching across the entire gate-level netlist (i.e., the gate-level circuit diagram of the entire chip). This global comparison mode has significant technical drawbacks: on the one hand, its computational complexity increases exponentially, resulting in extremely long runtimes, and in large-scale or structurally significantly different circuits, the matching accuracy and success rate drop sharply; on the other hand, even if an ECO script can be generated, its output will inevitably be lengthy and complex, containing a large number of global, unnecessary modification instructions. This not only significantly increases the burden of subsequent functional verification but may also introduce uncontrollable disturbances to the already converged timing, power consumption, and physical layout in the design, severely impacting the efficiency of design iterations and the final tape-out success rate.

[0006] Therefore, how to reconstruct the logical hierarchy boundary in the flattened netlist P to effectively constrain the comparison space of the ECO tool, thereby generating a simplified ECO script efficiently and reliably, has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0007] To address the shortcomings of existing technologies, this invention provides a method, system, and device for reconstructing the netlist logical hierarchy for logical ECO.

[0008] According to the present invention, a method, system, and device for reconstructing the netlist logical hierarchy for a logical ECO are provided, the solution of which is as follows: Firstly, a method for reconstructing the netlist logical hierarchy for logical ECO is provided, the method comprising: Obtain the comprehensive netlist S with complete logical hierarchy, the ECO target netlist E, and the backend-optimized ECO baseline netlist P; Identify the target logical level M related to engineering changes in the comprehensive netlist S, thereby determining that the boundary ports of the target logical level M in the netlist S constitute the first boundary point set {Si}. In the ECO baseline netlist P, find the nodes that are logically equivalent to the first boundary point set {Si} to form the second boundary point set {Pi}. The boundary ports of the logic modules corresponding to the target logic level M in the ECO target netlist E constitute the third boundary point set {Ei}. The pairing relationship between the second boundary point set {Pi} and the third boundary point set {Ei} is used as a constraint condition input into the ECO generation tool; The ECO generation tool performs a difference comparison within a local range defined by the constraints, thereby generating an ECO script.

[0009] Preferably, the boundary ports of the target logic level M in the netlist S include all input ports and all output ports of the target logic level M; the boundary ports of the logic module corresponding to the target logic level M in the ECO target netlist E include all input ports and all output ports of the logic module.

[0010] Preferably, finding a node in the ECO baseline netlist P that is logically equivalent to the first boundary point set {Si} includes: By checking the logical equivalence of nodes or matching node names, a node logically equivalent to the first boundary point set {Si} is found in the ECO baseline netlist P, so as to establish a one-to-one mapping relationship between the first boundary point set {Si} and the second boundary point set {Pi}.

[0011] Preferably, the target logical level M includes a top-level module and one or more sub-levels; The mapping relationship not only maps the boundaries {Si_M} to {Pi_M} of the top-level module M, but also further maps the boundaries {Si_Sub} to {Pi_Sub} of the key sub-modules inside M through the comparison of the integrated netlist S and the ECO benchmark netlist P. The mapping relationship between the top-level module and the sub-module is used as a multi-level mapping relationship, and all of them are provided as constraints to the ECO generation tool. This enables the ECO generation tool to reconstruct a virtual hierarchical subnet list in the ECO baseline netlist P and perform local comparisons at multiple levels.

[0012] Preferably, the second set of boundary points {Pi} includes: The internal nodes and / or logic unit output pins in the ECO reference netlist P; the internal nodes are intermediate signal lines in the ECO reference netlist P that are equivalent to the corresponding port logic functions in the first boundary point set {Si}, and the output pins of the logic units are the output terminals of the logic units in the ECO reference netlist P that are equivalent to the corresponding output port logic functions in the first boundary point set {Si}; the second boundary point set {Pi} defines the logic boundaries of the sub-circuit regions in the ECO reference netlist P that correspond to the functions carried by the target logic level M but have no explicit hierarchical boundaries.

[0013] Preferably, the ECO baseline netlist P is a flattened and optimized netlist, and the intermediate logical levels of the ECO baseline netlist P are deleted or merged so that there is no explicit module correspondence between the ECO baseline netlist P and the comprehensive netlist S. The synthesized netlist S is the netlist after logic synthesis and before back-end optimization, retaining complete logical hierarchy information; the ECO target netlist E is the netlist resynthesized according to the modified register transfer level description, and has a complete logical hierarchy.

[0014] Preferably, the pairing relationship between the second boundary point set {Pi} and the third boundary point set {Ei} includes: The constraint command is input to the ECO generation tool, and the constraint conditions are provided before the ECO generation tool performs a global comparison, so that the ECO generation tool directly focuses on the local range when performing difference analysis.

[0015] Preferably, the ECO script generation includes one or more of the following instructions: A unit replacement instruction is used to replace the logic units within the local area with logic units of different types. The logic gate addition instruction is used to add a new logic gate within the local scope. And a logic gate deletion instruction, used to delete redundant logic gates within the local area.

[0016] Secondly, a netlist logical hierarchy reconstruction system for logical ECO is provided, the system comprising: The boundary mapping module is used to obtain a comprehensive netlist S with a complete logical hierarchy and an ECO baseline netlist P optimized by the backend, identify the target logical level M related to engineering changes in the comprehensive netlist S, determine the boundary ports of the target logical level M in the netlist S to form a first boundary point set {Si}, and find the nodes in the ECO baseline netlist P that are logically equivalent to the first boundary point set {Si} to form a second boundary point set {Pi}. The constraint comparison module is used to obtain the ECO target netlist E, determine that the boundary ports of the logic modules corresponding to the target logic level M in the ECO target netlist E constitute the third boundary point set {Ei}, and input the pairing relationship between the second boundary point set {Pi} and the third boundary point set {Ei} as the constraint condition into the ECO generation tool. The script generation module is used by the ECO generation tool to perform difference comparisons and generate ECO scripts within a local range defined by the constraints.

[0017] Thirdly, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the netlist logical hierarchy reconstruction method for logical ECO as described above.

[0018] Compared with the prior art, the advantages of the present invention are as follows: 1. Order-of-magnitude improvement in ECO generation efficiency and success rate: By narrowing the comparison space from the entire design (potentially containing millions of instances) to the internal logic functional modules, this invention completely avoids the globally time-limited and highly complex graph matching operations performed by ECO tools on flattened netlists. Experiments show that the generation speed of ECO scripts is increased by tens to hundreds of times, while the success rate of ECO generation due to matching failures is increased from the low level of traditional methods to nearly 100%. 2. ECO scripts are reduced by hundreds of times: Because the comparison and modification are strictly constrained to the local area corresponding to the target function, the generated ECO script only contains necessary logic gate addition, subtraction, or replacement instructions, completely eliminating the massive redundant operations generated by global search. Experiments show that compared with traditional methods, the ECO script generated by applying this invention can reduce the number of instruction lines by hundreds of times. For example, a complex ECO that originally required thousands of commands can be simplified to dozens of core instructions, greatly reducing the cost and risk of script verification, timing updates, and physical iteration; 3. Significantly reduces the risk of late-stage design iterations: The extremely streamlined script means that the disturbance to the original, unchanged parts of the chip design is minimized. This maintains the convergence state of the original design in terms of timing, power consumption, and physical layout to the greatest extent, avoiding new design violations caused by the introduction of large-scale, unpredictable ECO modifications, and comprehensively improving the reliability of the design process and the final tape-out success rate; 4. No need to change the core algorithm of existing ECO tools: This invention is a preprocessing and constraint method, rather than a replacement for the comparison algorithm of existing ECO generation tools. By providing accurate boundary constraint information, it creates applicable conditions for existing efficient but structurally similar algorithms, protects the company's existing tool investment, and is easy to integrate into the existing design process.

[0019] Other beneficial effects of the present invention will be explained in detail through the introduction of specific technical features and technical solutions in specific embodiments. Those skilled in the art should be able to understand the beneficial technical effects brought about by these technical features and technical solutions through the introduction of these technical features and technical solutions. Attached Figure Description

[0020] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 A flowchart illustrating the overall process of netlist logical hierarchy reconstruction and ECO generation method provided in this embodiment of the invention; Figure 2 This is a schematic diagram illustrating the logical hierarchy boundary mapping between the integrated netlist S and the ECO baseline netlist P in step S1 of an embodiment of the present invention. Figure 3 This is a schematic diagram illustrating the local comparison between the ECO reference netlist P and the ECO target netlist E using logical boundary constraints in step S2 of this embodiment of the invention. Detailed Implementation

[0021] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the scope of protection of the present invention.

[0022] This invention provides a method for reconstructing the logical hierarchy of a netlist for logical ECO. By introducing an early synthesized netlist S as a reference, the "virtual boundary" of the target logical hierarchy is reconstructed in the flattened netlist P, thereby transforming the global search problem of the ECO tool into a local comparison problem, bringing significant technical advantages.

[0023] Example 1: This embodiment uses the generation of an ECO (Engineering Cost Equivalent) for an ALU (Arithmetic Logic Unit) that has undergone backend optimization as an example for detailed explanation. (Refer to...) Figure 1 As shown, the method includes the following steps: Step S1, Logical Hierarchy Boundary Mapping: Obtain the original integrated netlist S with complete logical hierarchy, and the backend optimized netlist P as the ECO baseline; identify one or more target logical levels M related to engineering changes in the integrated netlist S, and determine all input ports and output ports of the target logical level M in the netlist S, forming the first logical boundary point set {Si}; subsequently, in the ECO baseline netlist P, find all internal nodes or ports that are completely equivalent to the logical functions of each port in the first logical boundary point set {Si}, forming the second logical boundary point set {Pi}; the second logical boundary point set {Pi} defines the logical boundaries of the sub-circuit regions in the ECO baseline netlist P that are completely corresponding to the functions carried by the target logical level M, but without explicit hierarchical boundaries.

[0024] Reference Figure 2As shown, the triangle represents the bottom standard unit, and the wireframe M represents the module whose logic has changed. Specifically, firstly, the netlist S (i.e., the synthesized netlist S) of the design before logic synthesis and optimization is obtained, which contains the module_alu module with a complete hierarchy. Simultaneously, the netlist P, after place-and-route and optimization, serving as the starting point for ECO, is obtained. Here, the ECO baseline netlist P is preferably a flattened and optimized netlist, whose internal intermediate logic levels are deleted or merged, resulting in no explicit module correspondence between netlist P and the synthesized netlist S.

[0025] Identify the target logical level M (module_alu in this example) related to the engineering change in the comprehensive netlist S, and determine the boundary ports of the target logical level M in netlist S. The boundary ports include all input ports and all output ports of M. Assuming the input ports are a, b, cin, and the output ports are sum, cout, the first boundary point set {Si} = {a,b, cin, sum, cout} is thus formed.

[0026] Subsequently, the tool searches the netlist P for nodes logically equivalent to the first boundary point set {Si}. This search process establishes a one-to-one correspondence between {Si} and {Pi} through node logical equivalence checks or node name matching. Assume the results are: internal node net_123 is equivalent to a, net_456 is equivalent to b, net_789 is equivalent to cin, the output pin Y of unit U1 is equivalent to sum, and the output pin Y of unit U2 is equivalent to cout. Thus, the second boundary point set {Pi} = {net_123, net_456, net_789, U1 / Y, U2 / Y} is obtained. Here, internal nodes such as net_123 are intermediate signal lines in netlist P that are logically equivalent to the corresponding input ports in {Si}, and the output pins of logic units such as U1 / Y are the output terminals of logic units in netlist P that are logically equivalent to the corresponding output ports in {Si}. The {Pi} set defines the logic boundaries of sub-circuit regions in netlist P that correspond to the functions carried by the original target logic level M but have no explicit hierarchy boundaries.

[0027] Step S2, Constrained ECO Comparison and Generation: Obtain the target ECO netlist E, and determine all input and output ports of the logic modules corresponding to the target logic level M, forming the third logic boundary point set {Ei}; when using the ECO generation tool to perform difference comparison between the ECO reference netlist P and the target ECO netlist E, the pairing relationship between the second logic boundary point set {Pi} and the third logic boundary point set {Ei} is used as a constraint condition, input and applied to the ECO generation tool; based on the pairing relationship, the ECO generation tool strictly limits the scope of its difference search and logic comparison operations to the sub-circuit region defined by {Pi} and the logic module defined by {Ei}.

[0028] Reference Figure 3 As shown, triangles represent the underlying standard cells, wireframes M represent modules with logical changes, and ellipses within M represent logical changes in E relative to S and P. Specifically, based on the new RTL design, the ECO target netlist E containing the modified ALU module (e.g., module_alu_new) is resynthesized. The boundary ports of module_alu_new are determined as {a_new, b_new, cin_new, sum_new, cout_new}, thus forming the third boundary point set {Ei}.

[0029] Launch the commercial ECO generation tool and import netlists P and E. Before the ECO generation tool performs a global comparison, input the pairing relationship between the second boundary point set {Pi} and the third boundary point set {Ei} using the tool's constraint command. Input the pairing relationship: net_123 -> a_new, net_456 -> b_new, net_789 -> cin_new, U1 / Y -> sum_new, U2 / Y -> cout_new into the ECO tool as a constraint condition. The purpose of this constraint condition is to strictly limit the difference search and logic comparison range of the ECO generation tool to the sub-circuit region defined by {Pi} (i.e., the combinational logic cones in netlist P driven by net_123, net_456, and net_789, and converging in U1 / Y and U2 / Y) and the internal logic module defined by {Ei} (i.e., the module_alu_new module in netlist E).

[0030] Step S3, Local ECO Script Output: Within the local scope defined in step S2, the ECO generation tool performs logic difference analysis to identify gate-level netlist differences between sub-circuit regions and logic modules, and generates a simplified ECO script that only contains modifications to the sub-circuit regions defined by {Pi}.

[0031] Based on local difference analysis, the ECO tool generates a simplified ECO script containing only modifications to the sub-circuit regions. The generated ECO script includes, but is not limited to, one or more of the following instructions: cell replacement instructions (e.g., replacing the two-input AND gate AND2 in the P logic cone with a NOR gate NOR2), logic gate addition instructions (e.g., inserting an inverter INV on the path to U1 / Y), or logic gate deletion instructions. The final script is extremely concise, containing only two instructions: change_cell -instance alu / U_35 -new_type NOR2 insert_instance -instance alu / ECO_INST -new_type INV -net net_U1 After applying this script, the function corresponding to the ALU in netlist P can be precisely modified to match that in netlist E without affecting any other logic. In contrast, traditional global matching methods involve hundreds of logic gates and are complex and time-consuming.

[0032] Example 2: ECO generation for multi-level flattening modules In more complex scenarios, the target logical level M may contain a top-level module and one or more sub-levels. The method of this invention is also applicable, and the specific operations are as follows: In step S1, not only is the boundary {Si_M} -> {Pi_M} of the top-level module M mapped, but also the boundaries {Si_Sub} -> {Pi_Sub} of the key sub-modules within M are further mapped by comparing the comprehensive netlist S with the ECO baseline netlist P. That is, the mapping relationship includes the mapping relationship of the top-level module and the mapping relationship of the sub-modules, forming a multi-level mapping relationship.

[0033] In step S2, the mapping relationships of the top-level module and the sub-modules are provided as constraints (i.e., multi-level mapping relationships) to the ECO generation tool. In this way, the ECO generation tool can reconstruct a "virtual" hierarchical subnet list in the ECO baseline netlist P, and perform accurate local comparisons at multiple levels, further improving its ability to handle complex ECOs and script generation efficiency.

[0034] The effect data generated by the methods of Example 1 and Example 2 described above are shown in the following table:

[0035] Example 3: Based on the same inventive concept, this invention also provides a netlist logical hierarchy reconstruction system for logical ECO, the functions of which can be implemented by computer programs or hardware logic. The system includes: Boundary mapping module: used to obtain the comprehensive netlist S with complete logical hierarchy and the backend optimized ECO baseline netlist P, identify the target logical level M related to engineering changes in the comprehensive netlist S, determine the boundary ports of the target logical level M in the netlist S to form the first boundary point set {Si}, and find the nodes in the ECO baseline netlist P that are logically equivalent to the first boundary point set {Si} to form the second boundary point set {Pi}. Constraint Comparison Module: Used to obtain the ECO target netlist E, determine the boundary ports of the logic modules corresponding to the target logic level M in the ECO target netlist E to form the third boundary point set {Ei}, and input the pairing relationship between the second boundary point set {Pi} and the third boundary point set {Ei} as the constraint conditions into the ECO generation tool. Script generation module: Used by the ECO generation tool to perform difference comparisons within a localized range limited by constraints and generate ECO scripts.

[0036] This specific implementation provides a method, system, and device for reconstructing the logical hierarchy of a netlist for logical ECO. By introducing a comprehensive netlist S, the "virtual boundary" of the target logical hierarchy is reconstructed in the flattened netlist P. This successfully transforms the global search problem of ECO tools into a local comparison problem, fundamentally solving the shortcomings of existing technologies, such as huge search space, lengthy scripts, and low success rate due to low netlist structure similarity. Compared to traditional methods, efficiency and success rate are improved by orders of magnitude. By narrowing the comparison space from the entire chip to specific sub-circuits, the ECO generation speed is increased by tens or even hundreds of times, with a matching success rate approaching 100% after experiments. The script is extremely streamlined, reducing the number of ECO script instructions by hundreds of times, completely eliminating the massive redundant operations generated by global searches. The risk of later iterations is greatly reduced, as the streamlined script maintains the convergence state of the original design in terms of timing, power consumption, and physical layout to the greatest extent, avoiding the introduction of uncontrollable disturbances. In addition, as a preprocessing method, this invention does not require changes to the core algorithm of existing ECO tools, making it easy to integrate into existing design flows, comprehensively improving the reliability of the design flow and the final tape-out success rate.

[0037] Those skilled in the art will understand that, besides implementing the system and its various devices, modules, and units provided by this invention in the form of purely computer-readable program code, the same functions can be achieved entirely through logical programming of the method steps, enabling the system and its various devices, modules, and units provided in this specific embodiment to be implemented in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers. Therefore, the system and its various devices, modules, and units provided in this specific embodiment can be considered as a hardware component, and the devices, modules, and units included therein for implementing various functions can also be considered as structures within the hardware component; alternatively, the devices, modules, and units for implementing various functions can be considered as both software modules implementing the method and structures within the hardware component.

[0038] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

Claims

1. A method for reconstructing the netlist logical hierarchy for a logical ECO, characterized in that, include: Obtain the comprehensive netlist S with complete logical hierarchy, the ECO target netlist E, and the backend-optimized ECO baseline netlist P; Identify the target logical level M related to engineering changes in the comprehensive netlist S, thereby determining that the boundary ports of the target logical level M in the netlist S constitute the first boundary point set {Si}. In the ECO baseline netlist P, find the nodes that are logically equivalent to the first boundary point set {Si} to form the second boundary point set {Pi}. The boundary ports of the logic modules corresponding to the target logic level M in the ECO target netlist E constitute the third boundary point set {Ei}. The pairing relationship between the second boundary point set {Pi} and the third boundary point set {Ei} is used as a constraint condition input into the ECO generation tool; The ECO generation tool performs a difference comparison within a local range defined by the constraints, thereby generating an ECO script.

2. The netlist logic hierarchy reconstruction method for logic ECO according to claim 1, characterized in that, The boundary ports of the target logic level M in the netlist S include all input ports and all output ports of the target logic level M; the boundary ports of the logic module corresponding to the target logic level M in the ECO target netlist E include all input ports and all output ports of the logic module.

3. The netlist logic hierarchy reconstruction method for logic ECO according to claim 1, characterized in that, The process of finding nodes in the ECO baseline netlist P that are logically equivalent to the first boundary point set {Si} includes: By checking the logical equivalence of nodes or matching node names, a node logically equivalent to the first boundary point set {Si} is found in the ECO baseline netlist P, so as to establish a one-to-one mapping relationship between the first boundary point set {Si} and the second boundary point set {Pi}.

4. The netlist logic hierarchy reconstruction method for logic ECO according to claim 3, characterized in that, The target logical level M includes a top-level module and one or more sub-levels; The mapping relationship not only maps the boundaries {Si_M} to {Pi_M} of the top-level module M, but also further maps the boundaries {Si_Sub} to {Pi_Sub} of the key sub-modules inside M through the comparison of the integrated netlist S and the ECO benchmark netlist P. The mapping relationship between the top-level module and the sub-module is used as a multi-level mapping relationship, and all of them are provided as constraints to the ECO generation tool. This enables the ECO generation tool to reconstruct a virtual hierarchical subnet list in the ECO baseline netlist P and perform local comparisons at multiple levels.

5. The netlist logic hierarchy reconstruction method for logic ECO according to claim 1, characterized in that, The second set of boundary points {Pi} includes: The internal nodes and / or logic unit output pins in the ECO reference netlist P; the internal nodes are intermediate signal lines in the ECO reference netlist P that are equivalent to the corresponding port logic functions in the first boundary point set {Si}, and the output pins of the logic units are the output terminals of the logic units in the ECO reference netlist P that are equivalent to the corresponding output port logic functions in the first boundary point set {Si}; the second boundary point set {Pi} defines the logic boundaries of the sub-circuit regions in the ECO reference netlist P that correspond to the functions carried by the target logic level M but have no explicit hierarchical boundaries.

6. The netlist logic hierarchy reconstruction method for logic ECO according to claim 1, characterized in that, The ECO baseline netlist P is a netlist that has been flattened and optimized. The intermediate logical levels of the ECO baseline netlist P are deleted or merged so that there is no explicit module correspondence between the ECO baseline netlist P and the comprehensive netlist S. The synthesized netlist S is the netlist after logic synthesis and before back-end optimization, retaining complete logical hierarchy information; the ECO target netlist E is the netlist resynthesized according to the modified register transfer level description, and has a complete logical hierarchy.

7. The netlist logic hierarchy reconstruction method for logic ECO according to claim 1, characterized in that, The pairing relationship between the second boundary point set {Pi} and the third boundary point set {Ei} includes: The constraint command is input to the ECO generation tool, and the constraint conditions are provided before the ECO generation tool performs a global comparison, so that the ECO generation tool directly focuses on the local range when performing difference analysis.

8. The netlist logic hierarchy reconstruction method for logic ECO according to claim 1, characterized in that, The ECO script generation includes one or more of the following instructions: A unit replacement instruction is used to replace the logic units within the local area with logic units of different types. The logic gate addition instruction is used to add a new logic gate within the local scope. And a logic gate deletion instruction, used to delete redundant logic gates within the local area.

9. A netlist logical hierarchy reconfiguration system for logical ECO, the system comprising: The boundary mapping module is used to obtain a comprehensive netlist S with a complete logical hierarchy and an ECO baseline netlist P optimized by the backend, identify the target logical level M related to engineering changes in the comprehensive netlist S, determine the boundary ports of the target logical level M in the netlist S to form a first boundary point set {Si}, and find the nodes in the ECO baseline netlist P that are logically equivalent to the first boundary point set {Si} to form a second boundary point set {Pi}. The constraint comparison module is used to obtain the ECO target netlist E, determine that the boundary ports of the logic modules corresponding to the target logic level M in the ECO target netlist E constitute the third boundary point set {Ei}, and input the pairing relationship between the second boundary point set {Pi} and the third boundary point set {Ei} as the constraint condition into the ECO generation tool. The script generation module is used by the ECO generation tool to perform difference comparisons and generate ECO scripts within a local range defined by the constraints.

10. A computer terminal, comprising: At least one processor; And a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the netlist logical hierarchy reconstruction method for logical ECO according to any one of claims 1 to 8.

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