Hardware design code multi-granularity semantic extraction system for large language model

Abstract

The application relates to the technical field of electronic design automation, in particular to a hardware design code multi-granularity semantic extraction system for a large language model, which realizes multi-granularity semantic extraction and on-demand delivery of hardware design code through construction of a three-layer architecture of a client, a protocol service layer and a compilation engine, and the model can request semantic information of different granularities according to the actual needs of a current reasoning task. Thus, the model is provided with semantic information verified by a compiler, and the model is forced to generate code under strict structured constraints, so that the situation of logical illusion when the model generates code is avoided, the multi-granularity mechanism breaks through the context window limit of traditional pure text input, instruction data is composed of linear intermediate representation data and target control flow graphs, the model is provided with more concise and easy-to-understand design logic representation, so that the model is provided with more accurate and rich semantic information, and the accuracy and efficiency of the model in a hardware design auxiliary task are improved.

Description

Technical Field

[0001] This invention relates to the field of electronic design automation technology, and in particular to a multi-granular semantic extraction system for hardware design code oriented towards large language models. Background Technology

[0002] In scenarios where large language models (LLMs) are used for integrated circuit (IC) computer-aided design, a semantic gap exists in the understanding of hardware description languages ​​(HDLs) by the LLMs. Existing techniques typically rely on inputting source code as plain text into the LLMs. However, since hardware designs (such as SystemVerilog) are based on concurrent timing and topological connections, large models struggle to construct accurate causal chains across clock domains and modules by simply reading one-dimensional text code. This can lead to logical illusions during computer-aided design, such as fabricated signal drives or incorrect handshake timings.

[0003] Moreover, industrial-grade chip designs contain a massive amount of non-functional information, such as macro nesting, comments, and non-standard encoding. Directly inputting unstructured text will consume the context window of a large language model and introduce noise, leading to a decrease in the accuracy of model inference.

[0004] In addition, the compiler data (AST / CFG) of existing EDA toolchains are usually closed in a black box. Large language models lack a standardized interface for reading the hardware "ground truth" and can only understand the code intent by guessing, which leads to further deviations in semantic understanding.

[0005] Therefore, how to provide more accurate and richer semantic information for large language models has become an urgent problem to be solved. Summary of the Invention

[0006] To address the aforementioned technical problems, the technical solution adopted by this invention is as follows: A hardware design code multi-granularity semantic extraction system for large language models, the system includes a client, a protocol service layer and a compilation engine, wherein the client includes a large language model, the protocol service layer includes an interaction protocol adapter and a scaling controller, and the compilation engine includes a compiler front-end, a multi-granularity data warehouse and a semantic abstraction layer; The compiler front-end is used to parse hardware design code and generate macroscopic topology data; The semantic abstraction layer is used to extract static hardware connection diagrams and dynamic verification object diagrams based on the macro-topology data, and store the static hardware connection diagrams and dynamic verification object diagrams as overview data in the multi-granularity data warehouse. The compilation engine is used to generate linear intermediate representation data and the target control flow graph corresponding to the linear intermediate representation data based on the macro topology data, and store the linear intermediate representation data and the target control flow graph as instruction data in the multi-granularity data warehouse. The large language model is used to send protocol requests to the interaction protocol adapter, wherein the protocol request corresponds to semantic granularity, and the semantic granularity includes overview granularity, instruction granularity, and focus granularity; The interaction protocol adapter is used to receive the protocol request and send the semantic granularity corresponding to the protocol request to the scaling controller. The multi-granularity data warehouse is used to generate dependency slice data based on the objects of interest contained in the protocol request, the linear intermediate representation data, and the target control flow graph corresponding to the linear intermediate representation data when the semantic granularity corresponding to the received protocol request is the focus granularity, and to store the dependency slice data as focus data. The scaling controller is used to receive the semantic granularity corresponding to the protocol request, and to schedule the target data corresponding to the semantic granularity from the multi-granularity data warehouse and return it to the interaction protocol adapter according to the semantic granularity. The target data is the overview data, the instruction data, or the focus data. The interaction protocol adapter is also used to perform format conversion on the target data and return the format conversion result to the large language model through a standard protocol.

[0007] Compared with the prior art, the present invention has significant advantages. Through the above technical solution, the hardware design code multi-granularity semantic extraction system for large language models provided by the present invention achieves considerable technical progress and practicality, and has broad industrial application value. It has at least the following advantages: This invention achieves multi-granularity semantic extraction and on-demand delivery of hardware design code by constructing a three-layer architecture consisting of a client, a protocol service layer, and a compilation engine. The model can request semantic information of different granularities according to the actual needs of the current inference task. This provides the model with compiler-verified semantic information, forcing the model to generate code under strict structured constraints and avoiding logical illusions during code generation. The multi-granularity mechanism breaks through the context window limitations of traditional plain text input. The instruction data consists of linear intermediate representation data and a target control flow graph, providing the model with a more concise and easily understood design logic representation. This results in more accurate and richer semantic information for the model, improving its accuracy and efficiency in hardware design assistance tasks. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 This is a schematic diagram of the structure of a hardware design code multi-granularity semantic extraction system for large language models, provided as an embodiment of the present invention. Detailed Implementation

[0010] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0011] This embodiment provides a hardware design code multi-granularity semantic extraction system for large language models. The system includes a client, a protocol service layer, and a compilation engine. The client includes a large language model, the protocol service layer includes an interaction protocol adapter and a scaling controller, and the compilation engine includes a compiler front-end, a multi-granularity data warehouse, and a semantic abstraction layer. The compiler front-end is used to parse hardware design code and generate macroscopic topology data; The semantic abstraction layer is used to extract static hardware connection diagrams and dynamic verification object diagrams based on the macro-topology data, and store the static hardware connection diagrams and dynamic verification object diagrams as overview data in the multi-granularity data warehouse. The compilation engine is used to generate linear intermediate representation data and the target control flow graph corresponding to the linear intermediate representation data based on the macro topology data, and store the linear intermediate representation data and the target control flow graph as instruction data in the multi-granularity data warehouse. The large language model is used to send protocol requests to the interaction protocol adapter, wherein the protocol request corresponds to semantic granularity, and the semantic granularity includes overview granularity, instruction granularity, and focus granularity; The interaction protocol adapter is used to receive the protocol request and send the semantic granularity corresponding to the protocol request to the scaling controller. The multi-granularity data warehouse is used to generate dependency slice data based on the objects of interest contained in the protocol request, the linear intermediate representation data, and the target control flow graph corresponding to the linear intermediate representation data when the semantic granularity corresponding to the received protocol request is the focus granularity, and to store the dependency slice data as focus data. The scaling controller is used to receive the semantic granularity corresponding to the protocol request, and to schedule the target data corresponding to the semantic granularity from the multi-granularity data warehouse and return it to the interaction protocol adapter according to the semantic granularity. The target data is the overview data, the instruction data, or the focus data. The interaction protocol adapter is also used to perform format conversion on the target data and return the format conversion result to the large language model through a standard protocol.

[0012] The client contains a large language model for assisting integrated circuit design. As a consumer of semantic data, the client sends protocol requests to the compilation engine through the protocol service layer and receives the returned format conversion results.

[0013] The protocol service layer is an intermediate layer located between the client and the compilation engine. It is responsible for protocol parsing, granular scheduling, and data format conversion.

[0014] The compilation engine is responsible for parsing the hardware design code and generating multi-granular semantic data.

[0015] The interaction protocol adapter is the entry component of the protocol service layer. It is used to receive protocol requests from the large language model, parse the protocol requests, route the obtained semantic granularity to the scaling controller, and convert the target data returned by the scheduling into a format that can be read by the large language model.

[0016] The compiler front end is the entry point component of the compiler engine, responsible for lexical and syntactic analysis, and parsing hardware design code into macroscopic topology data.

[0017] A multi-granularity data warehouse refers to a storage unit that stores semantic data of different granularities, including overview data, focused data, and instruction data, and supports on-demand querying and dynamic generation of focused data.

[0018] The semantic abstraction layer is used to perform semantic processing on macro-topology data, constructing static hardware connectivity graphs and dynamic verification object graphs. Static hardware connection diagrams are structured data used to describe the topological connections between hardware modules, while dynamic verification object diagrams are structured data used to describe the relationships between components (such as UVM components) in the verification platform.

[0019] Linear intermediate representation data refers to a flattened intermediate representation between the abstract syntax tree and the underlying netlist, which retains high-level semantics while possessing a target control flow graph.

[0020] A protocol request refers to a query request sent by a large language model through a standard protocol, which includes the expected semantic granularity and the objects of interest under the focus granularity. For example, the standard protocol is the MCP (Model Context Protocol) protocol or a custom RPC (Remote Procedure Call) protocol.

[0021] See Figure 1 This is a schematic diagram of a hardware design code multi-granularity semantic extraction system for large language models provided by an embodiment of the present invention. In this system, linear IR refers to linear intermediate representation data, and CFG refers to the target control flow graph corresponding to the linear intermediate representation data.

[0022] Specifically, the large language model sends a protocol request to the interaction protocol adapter via a standard protocol, specifying the required semantic granularity. The interaction protocol adapter passes the semantic granularity to the scaling controller, which schedules the corresponding data from the multi-granularity data warehouse based on the semantic granularity. When the semantic granularity is a focused granularity, the multi-granularity data warehouse dynamically generates dependency slice data as the target data to be returned, based on the object of interest, linear intermediate representation data, and the target control flow graph. The scaling controller returns the scheduled data to the interaction protocol adapter, which performs format conversion and then returns it to the large language model via the standard protocol. It can be seen that the compilation engine can pre-convert macro-topology data into overview data and instruction data and store them in the multi-granularity data warehouse. When it receives a protocol request with a focused semantic granularity, it then generates focused data, thus forming a mechanism that combines offline preparation, online generation, and online scheduling.

[0023] In one specific implementation, the step of parsing the hardware design code and generating macroscopic topology data includes: Parse the hardware design code to obtain the abstract syntax tree corresponding to the hardware design code; Based on the abstract syntax tree corresponding to the hardware design code, the module hierarchy, port definitions, and parameter list are extracted, and the macroscopic topology data is formed by the module hierarchy, the port definitions, and the parameter list.

[0024] The Abstract Syntax Tree (AST) is a tree-like structure generated by the compiler front-end after performing syntactic analysis on the source code. Each node represents a syntactic structure in the source code, including module declarations, port lists, always blocks, etc.

[0025] Module hierarchy refers to the instantiation relationship between modules, including top-level modules, sub-modules and their nesting relationships, which are used to describe the hierarchical structure in the design.

[0026] A port definition is a description of the interface through which a module interacts with the outside world, including the port name, direction, and bit width.

[0027] The parameter list refers to the parameterized configuration of a module, which is used to control configurable attributes such as the module's bit width and depth.

[0028] In one specific implementation, the semantic abstraction layer includes a hardware topology serializer and a verification object serializer; The hardware topology serializer is used to extract module information, port information, and specific block information from the abstract syntax tree corresponding to the macro topology data, and to construct the static hardware connection diagram based on the module information, the port information, the specific block information, and the detailed information corresponding to the abstract syntax tree. The verification object sequencer is used to extract type information, inheritance information, and connection information of transaction-level modeling ports from the abstract syntax tree corresponding to the macro-topology data, and to construct the dynamic verification object graph based on the type information, inheritance information, and connection information of the transaction-level modeling ports.

[0029] Among them, the hardware topology serializer is responsible for extracting the static hardware structure from the abstract syntax tree corresponding to the macro topology data and serializing it into a graph structure, while the verification object serializer is responsible for extracting the dynamic structure of the verification platform from the abstract syntax tree corresponding to the macro topology data and serializing it into a graph structure.

[0030] Module information can include the module's name, instantiation path, parameter configuration, etc.; port information can include the port's name, direction, bit width, connection target, etc.; specific block information can include behavioral description structures such as always blocks, initial blocks, and assign statements.

[0031] Elaboration information corresponding to an abstract syntax tree refers to the complete hardware structure information obtained by the compilation engine after instantiating, parsing, expanding, and inferring the abstract syntax tree.

[0032] Type information includes type declarations such as class definitions, struct definitions, and enumeration definitions; inheritance information includes the inheritance relationship between validation components; and transaction-level modeling port (TLM Port) connection information refers to the connection relationship established between validation components through the transaction-level modeling port.

[0033] Specifically, the static hardware connection diagram reflects the physical connections of the design under test, while the dynamic verification object diagram reflects the logical connections of the test platform. Together, they constitute the overview data.

[0034] In one specific implementation, the compilation engine further includes a compilation normalization engine; The step of generating linear intermediate representation data and the target control flow graph corresponding to the linear intermediate representation data based on the macroscopic topology data includes: Based on the macroscopic topology data, generate linear intermediate representation data and the corresponding initial control flow graph; The compilation normalization engine maps the loop structures in the initial control flow graph to jump instructions, thereby obtaining the target control flow graph corresponding to the linear intermediate representation data.

[0035] The initial control flow graph refers to the control flow graph generated directly from the linear intermediate representation data. The initial control flow graph may contain various loop structures. Loop structures refer to the syntax structures used for iterative execution in hardware description languages, such as the forever, repeat, while, and for structures.

[0036] Specifically, the compilation normalization engine downgrades the loop structures in the initial control flow graph to a combination of basic blocks and jump instructions to obtain the target control flow graph. Through lossy transformation, it eliminates the syntactic noise of diverse loop structures in hardware description languages, providing a purer execution logic for large language models. This, in turn, improves the accuracy of large language models in understanding loop semantics and their ability to analyze timing paths.

[0037] In one specific implementation, generating dependency slice data based on the objects of interest included in the protocol request, the linear intermediate representation data, and the target control flow graph corresponding to the linear intermediate representation data includes: Based on the objects of interest included in the protocol request, and using the linear intermediate representation data and the target control flow graph corresponding to the linear intermediate representation data, a reverse tracing algorithm is executed to obtain the dependency slice data.

[0038] Among them, the reverse tracing algorithm refers to an algorithm that starts from the object of interest, traverses the target control flow graph and linear intermediate representation data in reverse along the signal driving direction, and collects all logical nodes that affect the object.

[0039] For example, when focusing on the fifo_full signal, the driving logic chain and data dependency graph are extracted as dependency slice data through the reverse tracing algorithm, thereby eliminating irrelevant logic and achieving semantic noise reduction. The driving logic chain refers to the signal assignment path that affects the object of interest, including combinational logic drive and temporal logic drive, forming a transmission chain from the source signal to the object of interest. The data dependency graph is a directed graph that describes the data flow between the object of interest and other signals, with signals as nodes and assignment relationships as edges.

[0040] In one specific implementation, the step of scheduling the target data corresponding to the semantic granularity from the multi-granularity data warehouse and returning it to the interaction protocol adapter according to the semantic granularity includes: When the semantic granularity is an overview granularity, the overview data is scheduled from the multi-granularity data warehouse and returned to the interaction protocol adapter as the target data. When the semantic granularity is the instruction granularity, the instruction data is scheduled from the multi-granularity data warehouse and returned to the interaction protocol adapter; When the semantic granularity is a focused granularity, the focused data is scheduled from the multi-granularity data warehouse and returned to the interaction protocol adapter as the target data.

[0041] The scaling controller receives the semantic granularity of the protocol request, performs conditional routing, and if it is at the overview granularity, it obtains overview data from the multi-granularity data warehouse; if it is at the instruction granularity, it obtains instruction data; if it is at the focus granularity, it obtains focus data. After routing is completed, it returns the target data to the interaction protocol adapter.

[0042] In one specific implementation, when the semantic granularity is an overview granularity, the interaction protocol adapter is further configured to establish an association between the static hardware connection graph and the dynamic verification object graph in the target data through a cross-domain mapping graph to obtain the association information corresponding to the target data; Accordingly, the step of returning the format conversion result to the large language model via a standard protocol includes: When the semantic granularity is at the overview granularity, the format conversion result and the associated information corresponding to the target data are returned to the large language model through a standard protocol.

[0043] Among them, the cross-domain mapping graph refers to the data structure used to associate the hardware topology domain and the verification object domain, and is used to record the correspondence between signals / ports in the static hardware connection graph and transaction-level modeling ports / transaction objects in the dynamic verification object graph.

[0044] Association information refers to the set of mapping relationships generated after the cross-domain mapping graph is established. It is used to supplement the overview data and enable the large language model to understand the interaction between the verification component and the hardware module.

[0045] In one specific implementation, the format conversion result is in JSON format.

[0046] JSON is a lightweight text-based data exchange format that uses key-value pairs and array structures, making it easy for large language models to understand.

[0047] In one implementation, the implementer may require the format conversion result to be in a format readable by other large language models, such as Protocol Buffers and MessagePack.

[0048] In this embodiment, a three-layer architecture consisting of a client, a protocol service layer, and a compilation engine is constructed to achieve multi-granularity semantic extraction and on-demand delivery of hardware design code. The model can request semantic information of different granularities according to the actual needs of the current inference task. This provides the model with compiler-verified semantic information, forcing the model to generate code under strict structured constraints and avoiding logical illusions during code generation. The multi-granularity mechanism breaks through the context window limitations of traditional plain text input. The instruction data consists of linear intermediate representation data and a target control flow graph, providing the model with a more concise and easily understood design logic representation. This provides the model with more accurate and richer semantic information, improving the accuracy and efficiency of the model in hardware design assistance tasks.

[0049] While specific embodiments of the invention have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the invention. The scope of this invention is defined by the appended claims.

Claims

1. A multi-granularity semantic extraction system for hardware design code oriented towards large language models, characterized in that, The system includes a client, a protocol service layer, and a compilation engine. The client includes a large language model, the protocol service layer includes an interaction protocol adapter and a scaling controller, and the compilation engine includes a compiler front-end, a multi-granularity data warehouse, and a semantic abstraction layer. The compiler front-end is used to parse hardware design code and generate macroscopic topology data; The semantic abstraction layer is used to extract static hardware connection diagrams and dynamic verification object diagrams based on the macro-topology data, and store the static hardware connection diagrams and dynamic verification object diagrams as overview data in the multi-granularity data warehouse. The compilation engine is used to generate linear intermediate representation data and the target control flow graph corresponding to the linear intermediate representation data based on the macro topology data, and store the linear intermediate representation data and the target control flow graph as instruction data in the multi-granularity data warehouse. The large language model is used to send protocol requests to the interaction protocol adapter, wherein the protocol request corresponds to semantic granularity, and the semantic granularity includes overview granularity, instruction granularity, and focus granularity; The interaction protocol adapter is used to receive the protocol request and send the semantic granularity corresponding to the protocol request to the scaling controller. The multi-granularity data warehouse is used to generate dependency slice data based on the objects of interest contained in the protocol request, the linear intermediate representation data, and the target control flow graph corresponding to the linear intermediate representation data when the semantic granularity corresponding to the received protocol request is the focus granularity, and to store the dependency slice data as focus data. The scaling controller is used to receive the semantic granularity corresponding to the protocol request, and to schedule the target data corresponding to the semantic granularity from the multi-granularity data warehouse and return it to the interaction protocol adapter according to the semantic granularity. The target data is the overview data, the instruction data, or the focus data. The interaction protocol adapter is also used to perform format conversion on the target data and return the format conversion result to the large language model through a standard protocol.

2. The hardware design code multi-granularity semantic extraction system for large language models according to claim 1, characterized in that, The process of analyzing hardware design code and generating macroscopic topology data includes: Parse the hardware design code to obtain the abstract syntax tree corresponding to the hardware design code; Based on the abstract syntax tree corresponding to the hardware design code, the module hierarchy, port definitions, and parameter list are extracted, and the macroscopic topology data is formed by the module hierarchy, the port definitions, and the parameter list.

3. The hardware design code multi-granularity semantic extraction system for large language models according to claim 2, characterized in that, The semantic abstraction layer includes a hardware topology serializer and a verification object serializer; The hardware topology serializer is used to extract module information, port information, and specific block information from the abstract syntax tree corresponding to the macro topology data, and to construct the static hardware connection diagram based on the module information, the port information, the specific block information, and the detailed information corresponding to the abstract syntax tree. The verification object sequencer is used to extract type information, inheritance information, and connection information of transaction-level modeling ports from the abstract syntax tree corresponding to the macro-topology data, and to construct the dynamic verification object graph based on the type information, inheritance information, and connection information of the transaction-level modeling ports.

4. The hardware design code multi-granularity semantic extraction system for large language models according to claim 1, characterized in that, The compilation engine also includes a compilation normalization engine; The step of generating linear intermediate representation data and the target control flow graph corresponding to the linear intermediate representation data based on the macroscopic topology data includes: Based on the macroscopic topology data, generate linear intermediate representation data and the corresponding initial control flow graph; The compilation normalization engine maps the loop structures in the initial control flow graph to jump instructions, thereby obtaining the target control flow graph corresponding to the linear intermediate representation data.

5. The hardware design code multi-granularity semantic extraction system for large language models according to claim 1, characterized in that, The step of generating dependency slice data based on the objects of interest included in the protocol request, the linear intermediate representation data, and the target control flow graph corresponding to the linear intermediate representation data includes: Based on the objects of interest included in the protocol request, and using the linear intermediate representation data and the target control flow graph corresponding to the linear intermediate representation data, a reverse tracing algorithm is executed to obtain the dependency slice data.

6. The hardware design code multi-granularity semantic extraction system for large language models according to claim 1, characterized in that, The step of scheduling the target data corresponding to the semantic granularity from the multi-granularity data warehouse and returning it to the interaction protocol adapter according to the semantic granularity includes: When the semantic granularity is an overview granularity, the overview data is scheduled from the multi-granularity data warehouse and returned to the interaction protocol adapter as the target data. When the semantic granularity is the instruction granularity, the instruction data is scheduled from the multi-granularity data warehouse and returned to the interaction protocol adapter; When the semantic granularity is a focused granularity, the focused data is scheduled from the multi-granularity data warehouse and returned to the interaction protocol adapter as the target data.

7. The hardware design code multi-granularity semantic extraction system for large language models according to claim 1, characterized in that, When the semantic granularity is an overview granularity, the interaction protocol adapter is also used to establish an association between the static hardware connection diagram and the dynamic verification object diagram in the target data through a cross-domain mapping graph to obtain the association information corresponding to the target data; Accordingly, the step of returning the format conversion result to the large language model via a standard protocol includes: When the semantic granularity is at the overview granularity, the format conversion result and the associated information corresponding to the target data are returned to the large language model through a standard protocol.

8. The hardware design code multi-granularity semantic extraction system for large language models according to claim 1, characterized in that, The format conversion result is in JSON format.

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