Differential signal wiring method, apparatus, storage medium, and electronic device

Abstract

The application discloses a differential signal wiring method, device, storage medium and electronic equipment. The differential signal wiring method comprises the following steps: taking two pins of a differential pair as the starting points of bidirectional expansion, without presetting fixed endpoints, performing opposite wiring expansion by using an advanced A-star algorithm, and generating a plurality of candidate convergence points; evaluating the plurality of candidate convergence points based on a multi-dimensional cost function, and determining a target convergence point; taking the target convergence point as a junction node, physically converging two wiring lines extending to the junction node, merging into a single coupled main line, and planning middle section wiring by using the single coupled main line; setting a split node at the end of the single coupled main line, synchronously leading out two independent signal lines from the split node, and restoring into a standard differential double-wire structure; generating a shielded metal wiring line grounded on both sides of the standard differential double-wire structure, arranging a ground via along the shielded metal wiring line, and connecting the shielded metal wiring line with a bottom ground plane to form a local closed shielding structure.

Description

Technical Field

[0001] This application relates to the field of physical routing technology in semiconductor advanced packaging EDA (Electronic Design Automation), specifically to a differential signal routing method, apparatus, storage medium, and electronic device for interposers and multilayer metal structures of 2.5D / 3D multi-chip stacked chips. Background Technology

[0002] With the rapid development of emerging technologies such as artificial intelligence, high-performance computing, and 5G communication, chip integration and system data transmission rates continue to rise, making traditional two-dimensional packaging unable to meet the ever-increasing demands for bandwidth and energy efficiency. Advanced packaging technologies based on 2.5D / 3D stacking architectures are gradually becoming an important path to continue Moore's Law. 2.5D packaging achieves high-density signal interconnection between multiple dies through an interposer, while 3D packaging stacks chips vertically through through-silicon vias (TSVs) to significantly shorten interconnection distances and reduce signal delay and loss. In such high-density packaging scenarios, differential signal transmission has become the mainstream signal form for high-speed data transmission interfaces (such as UCIe and SerDes) due to its excellent common-mode noise immunity and low electromagnetic interference characteristics.

[0003] However, current differential signal routing schemes can only split the differential pair into two independent single-ended routing steps, which not only doubles the computational load but also makes it difficult to match the routing of the two independent routing steps, resulting in large deviations in the length of the pair and unstable coupling distance. Summary of the Invention

[0004] This application provides a differential signal routing method, apparatus, storage medium, and electronic device, which can reduce the computational complexity of differential signal routing.

[0005] In a first aspect, embodiments of this application provide a differential signal routing method, including: Using the two pins of the differential pair as bidirectional expansion start points and without a preset fixed end point, an advanced A-star algorithm is used to expand the traces in opposite directions to generate several candidate convergence points. The candidate convergence points are evaluated based on a multi-dimensional cost function to determine the target convergence point; Using the target convergence point as the junction node, the two traces extending from the two pins to the junction node are physically merged into a single coupled main line, and the middle section of the trace is planned using the single coupled main line. A splitting node is set at the end of the single coupled main line, and two independent signal lines are synchronously led out from the splitting node to restore the standard differential dual-line structure. Grounded shielded metal traces are generated on both sides of the standard differential dual-line structure, and grounding vias are laid along the shielded metal traces to connect the shielded metal traces to the bottom ground plane, forming a partially closed shielded structure.

[0006] In the differential signal routing method provided in this application embodiment, the step of using an advanced A* algorithm to extend the opposite routing to generate several candidate convergence points includes: During the initial trace expansion, the two pins are initially expanded along four preset directions to form 16 initial trace combinations; Calculate the current cost function value for each initial routing combination, and then expand subsequent routings in ascending order of the current cost function value. During the subsequent trace expansion process, when the expanded traces of the two pins meet the preset intersection conditions, a candidate convergence point is generated, thereby obtaining several candidate convergence points.

[0007] In the differential signal routing method provided in this application embodiment, the subsequent trace extension process further includes: After each step of trace expansion is completed, invalid extended traces in the subsequent traces to be expanded are trimmed according to the current trace direction of each of the two pins. The invalid extended trace is a trace in the subsequent traces to be extended whose direction is opposite to the current trace direction.

[0008] In the differential signal routing method provided in this application embodiment, the subsequent trace extension process further includes: Each time the trace is extended, a bend process constraint is applied to the next trace direction of the pin. The cornering process constraint prohibits right-angle turns. The angle between the current routing direction and the previous routing direction must meet 135°. Only the neighboring grid points that meet the cornering process constraint are retained as the next routing direction.

[0009] In the differential signal routing method provided in this application embodiment, the step of evaluating several candidate convergence points based on a multi-dimensional cost function to determine the target convergence point includes: Calculate the multidimensional cost function value for each of the candidate convergence points; For each candidate convergence point, a triple constraint check is performed sequentially. The candidate convergence points that pass the triple constraint check are sorted in ascending order of the multi-dimensional cost function value, and the one with the smallest cost function value is selected as the target convergence point.

[0010] In the differential signal routing method provided in this application embodiment, the triple constraint verification includes: Verify whether the spacing between the two lines at each of the candidate convergence points is equal to or close to the preset differential coupling distance; if so, pass. Verify whether the routing direction after the intersection of each candidate convergence point conflicts with the overall direction of the subsequent single coupling main line, and whether it meets the cornering process constraint. If there is no conflict and the cornering process constraint is met, then it passes. Verify whether the multi-dimensional cost function value of the current extended trace is less than the preset threshold; if so, pass.

[0011] In the differential signal routing method provided in this application embodiment, the step of setting a splitting node at the end of the single coupled main line and synchronously leading out two independent signal lines from the splitting node to restore a standard differential two-wire structure includes: A split node is set at the end of the single coupled main line; Starting from the split node, two independent signal lines are simultaneously led out to the differential signal receiving end; During the extraction process, a mirror symmetry expansion strategy is adopted, taking the perpendicular bisector of the line connecting the split node and the differential signal receiver as the axis of symmetry, and simultaneously expanding the candidate grid points of the two independent signal lines in pairs, thereby forming a standard differential dual-line structure.

[0012] Secondly, embodiments of this application provide a differential signal wiring apparatus, comprising: The trace expansion unit is used to expand the traces in opposite directions using the two pins of the differential pair as bidirectional expansion start points and without a preset fixed end point, and to generate several candidate convergence points by using an advanced A-star algorithm. The target determination unit is used to evaluate several candidate convergence points based on a multi-dimensional cost function in order to determine the target convergence point; The mid-section planning unit is used to physically merge the two traces extending from the two pins to the intersection node, taking the target convergence point as the intersection node, and merge them into a single coupled main line, and use the single coupled main line to plan the mid-section routing. The standard restoration unit is used to set a splitting node at the end of the single coupled main line, and synchronously lead out two independent signal lines from the splitting node to restore the standard differential dual-line structure. A shielding forming unit is used to generate grounded shielding metal traces on both sides of the standard differential double-wire structure, and to lay grounding vias along the shielding metal traces to connect the shielding metal traces with the underlying ground plane to form a partially closed shielding structure.

[0013] Thirdly, this application provides a storage medium storing a plurality of instructions that are adapted for loading by a processor to execute the differential signal routing method described in any of the preceding claims.

[0014] Fourthly, this application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the differential signal wiring method described in any of the preceding claims.

[0015] In summary, the differential signal routing method provided in this application includes using two pins of the differential pair as bidirectional expansion start points, without pre-setting a fixed end point, and employing an advanced A* algorithm to perform opposite routing expansion to generate several candidate convergence points; evaluating the several candidate convergence points based on a multi-dimensional cost function to determine the target convergence point; using the target convergence point as the junction node, physically merging the two traces extending from the two pins to the junction node into a single coupled main line, and using the single coupled main line for mid-section routing planning; setting a splitting node at the end of the single coupled main line, and synchronously leading out two independent signal lines from the splitting node to restore the standard differential dual-line structure; generating grounded shielded metal traces on both sides of the standard differential dual-line structure, and routing grounding vias along the shielded metal traces to connect the shielded metal traces to the underlying ground plane, forming a partially closed shielded structure. In this embodiment, the two pins of the differential pair are used as bidirectional expansion starting points, and no fixed endpoint is preset. An advanced A-Star algorithm is used for opposite routing expansion to generate several candidate convergence points. Then, the target convergence point is determined based on a multi-dimensional cost function. This transforms the traditional single-endpoint A-Star algorithm's "point-to-point" directional expansion into a differential dual-pin "opposite search, dynamic convergence" expansion mode. During the expansion process, the number of branches increases linearly with the number of steps rather than exponentially. Moreover, it can adaptively converge to the optimal convergence position without presetting the endpoint, which significantly reduces the size of the expansion space and the number of algorithm iterations, thereby reducing the computational complexity of differential signal routing. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram illustrating an application scenario of the differential signal wiring method provided in the embodiments of this application.

[0018] Figure 2This is a flowchart illustrating the differential signal routing method provided in the embodiments of this application.

[0019] Figure 3 This is a schematic diagram of the differential signal wiring device provided in the embodiments of this application.

[0020] Figure 4 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application. Detailed Implementation

[0021] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0022] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same names in different embodiments of this application may have the same meaning or different meanings, the specific meaning of which must be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment.

[0023] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0024] In the following description, the use of suffixes such as "module," "part," or "unit" to denote elements is solely for the purpose of illustrative purposes and has no specific meaning in itself. Therefore, "module," "part," or "unit" may be used interchangeably.

[0025] In the description of this application, it should be noted that the terms "upper," "lower," "left," "right," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. In addition, terms such as "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0026] Current differential signal routing schemes can only split differential pairs into two independent single-ended routing steps, which not only doubles the computational load but also makes it difficult to match the routing of the two independent routing steps, resulting in large deviations in the length of the pairs and unstable coupling distances.

[0027] Based on this, embodiments of this application provide a differential signal wiring method, apparatus, storage medium, and electronic device. Specifically, the differential signal wiring apparatus can be integrated into an electronic device, which can be a server or a terminal, etc. The terminal can include mobile phones, wearable smart devices, tablet computers, laptops, and personal computers (PCs), etc., as well as other computers and auxiliary devices. The server can be a single server or a server cluster composed of multiple servers, and can be a physical server or a virtual server.

[0028] For example, such as Figure 1 As shown, the electronic device can use the two pins of the differential pair as bidirectional expansion start points, without a preset fixed end point, and use an advanced A* algorithm to expand the traces in opposite directions to generate several candidate convergence points. The candidate convergence points are evaluated based on a multi-dimensional cost function to determine the target convergence point. Using the target convergence point as the intersection node, the two traces extending from the two pins to the intersection node are physically merged into a single coupled main line. The mid-section trace planning is carried out using the single coupled main line. A split node is set at the end of the single coupled main line, and two independent signal lines are synchronously led out from the split node to restore the standard differential double-line structure. Grounded shielded metal traces are generated on both sides of the standard differential double-line structure, and grounding vias are laid along the shielded metal traces to connect the shielded metal traces to the underlying ground plane to form a partially closed shielded structure.

[0029] The technical solutions shown in this application will be described in detail below through specific embodiments. It should be noted that the order of description of the following embodiments is not intended to limit the priority of the embodiments.

[0030] Please see Figure 2 , Figure 2This is a flowchart illustrating the differential signal routing method provided in an embodiment of this application. The specific flow of the differential signal routing method is as follows: 101. Using the two pins of the differential pair as bidirectional expansion start points and without a preset fixed end point, the advanced A-star algorithm is used to expand the traces in opposite directions to generate several candidate convergence points.

[0031] In this embodiment, the differential signal consists of a pair of complementary signals, transmitted through a first pin (hereinafter referred to as Pin1) and a second pin (hereinafter referred to as Pin2). Pin1 and Pin2 correspond to the positive and negative signals in the differential pair, respectively. They need to start from their respective physical pin locations, be routed through a 2.5D interposer or multi-layer metal wiring layer, converge at an intermediate node, and then be transmitted together to the target receiving area. Traditional AlphaGo algorithms only support a single-start, single-endpoint directional expansion mode, which cannot directly adapt to the routing requirements of differential dual-pin convergence. If the dual pins are planned separately and then manually spliced, not only does the computational load increase exponentially, but the matching degree of the two routes is also poor. To address these issues, this application sets both pins (Pin1 and Pin2) as bidirectional expansion start points simultaneously, without pre-setting a fixed end point. The two routes expand synchronously towards each other until they intersect to generate a candidate convergence point. This dual-start, non-endpoint, opposing expansion method directly adapts to the physical requirements of differential signal dual-line convergence, overcoming the inherent limitation of the traditional A-star algorithm which only supports single-start, single-endpoint mode.

[0032] In this embodiment of the application, the step "using an advanced A* algorithm to expand the opposing traces to generate several candidate convergence points" can be specifically described as follows: During the initial trace expansion, the two pins are initially expanded along four preset trace directions to form 16 initial trace combinations.

[0033] In this embodiment, the four preset routing directions are up, down, left, and right, which are orthogonal grid structures based on the wiring grid of the 2.5D / 3D stacked chip interposer layer. These four directions cover all possible forward directions starting from the current node in the grid topology.

[0034] Specifically, Pin1 and Pin2 each independently open four routing directions (up, down, left, and right) during the initial routing expansion. Combining the four routing directions of Pin1 with the four routing directions of Pin2 generates 4 × 4 = 16 initial routing combinations: (up, up), (up, down), (up, left), (up, right), (down, up), (down, down), (down, left), (down, right), (left, up), (left, down), (left, left), (left, right), (right, up), (right, down), (right, left), (right, right). The first element of each combination represents the routing direction of Pin1, and the second element represents the routing direction of Pin2. These 16 initial routing combinations constitute the initial input of the advanced A* algorithm's priority queue, ensuring that all relative motion trends are exhausted at the initial stage, avoiding local optima in subsequent expansion due to improper initial routing direction selection.

[0035] Then, the current cost function value of each initial routing combination can be calculated separately, and subsequent routing expansions can be performed in ascending order of the current cost function value.

[0036] The current cost function value is the Manhattan distance between the current positions of Pin1 and Pin2, which is the sum of the absolute values ​​of the differences in their x-coordinates and y-coordinates in the grid coordinate system. This Manhattan distance directly reflects the spatial proximity between the expansion fronts of the two paths. The smaller the distance, the closer the two paths are to intersecting, and they should be expanded first. After the current cost function values ​​of all 16 initial path combinations are calculated, each combination, along with its current cost function value, is pushed into a priority queue, which is dynamically sorted in ascending order of current cost function values.

[0037] The Priority Queue is a data structure used in the A* algorithm to manage nodes to be expanded. Its characteristic is that each element popped from the queue is the one with the highest priority. Therefore, each time a trace is expanded, the Priority Queue automatically pops the combination with the smallest current cost function value for the next trace expansion, thus ensuring that the expansion process always proceeds along the trace direction where the two pins are close to each other.

[0038] During the subsequent trace expansion process, when the expanded traces of two pins meet the preset intersection conditions, a candidate convergence point is generated, thus obtaining several candidate convergence points.

[0039] As the expansion continues, the expansion fronts of Pin1 and Pin2 gradually converge. When they coincide at a certain grid point coordinate, or when the Manhattan distance between them shrinks to within a preset differential coupling distance range, the preset convergence condition is met, and this coordinate location is recorded as a candidate convergence point. Multiple locations meeting the convergence condition may occur during the entire expansion process, resulting in several candidate convergence points for subsequent selection. Through this method, this application achieves autonomous, opposite-direction convergence of differential dual pins without a preset fixed endpoint, avoiding the computational redundancy and poor trace matching issues caused by two independent expansion traces in traditional schemes.

[0040] In the embodiments of this application, the subsequent trace expansion process may further include: after each trace expansion step is completed, according to the current trace direction of each of the two pins, cutting off the invalid extended traces in their respective subsequent traces to be expanded.

[0041] Invalid extended routes are those subsequent routes whose direction is opposite to the current route. For example, if the current route of Pin1 is to the right, then all subsequent routes to be extended that include routes to the left are considered invalid extended routes and are directly discarded; similarly, if the current route of Pin2 is to the left, then all subsequent routes to be extended that include routes to the right are considered invalid extended routes and are discarded.

[0042] Understandably, effective transmission of differential signals requires that the two traces, starting from their respective pins, should be close to each other rather than far apart. Reverse routing inevitably increases the spatial distance between the two pins, contradicting the fundamental goal of convergence. Therefore, removing such traces from all subsequent traces to be expanded will not miss any effective optimal solutions. Through immediate reverse pruning after each trace expansion, this application can effectively compress the expansion tree size from exponential growth to near linear growth, significantly reducing unnecessary expansion traces and significantly accelerating the convergence speed of the algorithm.

[0043] In some embodiments, the subsequent trace expansion process may further include: applying a bend process constraint to the next trace direction of the pin each time the trace is expanded.

[0044] The cornering process constraint prohibits right-angle turns, and the angle between the current routing direction and the previous routing direction must meet 135°. Only the neighboring grid points that meet the cornering process constraint are retained as the next routing direction.

[0045] Specifically, in a grid routing model, when a trace extends from the current grid point to the next, it forms a corner formed by the previous trace direction and the current trace direction. If this corner is 90°, it forms a right-angle bend. In advanced packaging manufacturing processes, 90° right-angle bends can easily cause electric field concentration effects in metal conductors at the corners, increasing the risk of electromigration. Furthermore, the etching accuracy at right-angle bends is difficult to guarantee, potentially causing the actual conductor width to deviate from the design value, affecting the continuity of differential impedance. Therefore, in each trace expansion, this embodiment filters out all trace directions that would form a 90° corner from the eight neighboring grid points of the current grid point, retaining only the neighboring grid points with an angle of 135° to the previous trace direction as the next trace direction. It should be noted that in the initial trace expansion, since there is no previous trace direction, the first trace expansion is not limited by the cornering process, and all four preset trace directions can be selected. Starting from the second trace expansion, each step of the expansion must be verified against the corner bending process constraint to ensure that the final trace fully complies with the 135° corner bending manufacturing specification, avoiding iterative corrections of violations during subsequent design rule checks. This 135° corner bending process constraint is embedded before the trace expansion process, ensuring that the expanded trace naturally meets manufacturing specifications, avoiding the repeated iterations of corner bending corrections after routing is completed in traditional processes.

[0046] It should be noted that the aforementioned reverse trimming operation and the corner process constraint application operation are executed synchronously during each trace expansion. That is, each trace expansion first applies corner process constraints to filter the direction of the trace to be routed, and then reverse trimming is performed on the remaining direction of the trace to be routed after filtering. The two work together to compress the expansion space. In some embodiments, reverse trimming can be performed first and then corner process constraint filtering can be performed. This application does not limit the execution order of the two.

[0047] 102. Evaluate several candidate convergence points based on a multi-dimensional cost function to determine the target convergence point.

[0048] It is understandable that although several candidate convergence points may all meet the intersection conditions, the local cabling environment, the spacing between the two lines, and the smoothness of their connection with subsequent mid-section cabling may vary significantly. If only a single distance indicator is used as the selection criterion, the selected intersection point may have the shortest distance, but its location may happen to be in an area with dense obstacles or cause subsequent cabling to require a large-angle turnback, which would increase the overall cabling difficulty. Therefore, this application's embodiment introduces a multi-dimensional cost function to comprehensively and quantitatively evaluate all candidate convergence points in order to select the globally optimal one as the target convergence point.

[0049] Specifically, step 102 may include the following steps: 1021. Calculate the multidimensional cost function value for each candidate convergence point.

[0050] In some embodiments, the expression for the multidimensional cost function F can be: F = α·L + β·D + γ·θ.

[0051] Where L represents the trace length between the leading edges of Pin1 and Pin2 at the current candidate convergence point. In actual calculations, it can be the sum of the actual trace lengths extending from their respective starting points to the candidate convergence point, or the Manhattan distance between the two leading edges can be used as an equivalent metric. The physical meaning of L is to reflect the trace length traversed by the differential signal from the transmitting end to the convergence point. The smaller L is, the smaller the signal transmission delay and the less wiring resources are required.

[0052] D represents the deviation between the actual pair spacing and the preset differential coupling distance at the current candidate convergence point. The differential coupling distance is a process parameter preset by the process library, representing the optimal spacing between the two signal lines of the differential pair. At this spacing, the differential signal can achieve the best electromagnetic field coupling effect, thereby effectively canceling common-mode noise. For each candidate convergence point, the absolute value of the difference between its actual pair spacing and the preset differential coupling distance is calculated, which is D. The smaller D is, the closer the pair coupling at the convergence point is to the ideal state, and the stronger the anti-interference capability of the differential signal.

[0053] θ represents the offset angle of the merged main line's routing direction after convergence. Specifically, it's the angle between the actual routing direction of the coupled main line and the pre-planned ideal routing direction after merging two traces into a single coupled main line at the candidate convergence point. This ideal routing direction is typically determined by the chip's global routing plan, reflecting the optimal macroscopic transmission direction from the differential transmitter region to the receiver region. A smaller θ indicates a more consistent routing direction after convergence with the global ideal routing direction, reducing the need for significant bends and adjustments in subsequent intermediate routing, resulting in smoother routing and less overhead routing resources.

[0054] α, β, and γ are the weighting coefficients for the three dimensions mentioned above, and their specific values ​​can be flexibly adjusted according to the actual application scenario. For example, in high-speed interface cabling scenarios with high signal integrity requirements, β can be set to a higher value to strengthen the penalty for coupling spacing deviation; in high-density interposer layer scenarios where cabling area is more sensitive, α can be set to a higher value to prioritize the convergence point with the shortest trace length. The adjustment of the weighting coefficients is automatically completed by EDA tools according to the current design constraints or manually configured by the cabling engineer; this application does not impose any restrictions on this.

[0055] 1022. For each candidate convergence point, perform triple constraint verification in sequence. Sort the candidate convergence points that pass the triple constraint verification in ascending order of multi-dimensional cost function value, and select the one with the smallest cost function value as the target convergence point.

[0056] The specific details of the triple constraint verification are as follows: The first verification step checks whether the spacing between the two lines at each candidate convergence point is equal to or close to the preset differential coupling distance. The preset differential coupling distance is provided by the Technology LEF File (TechLEF), and its value is typically a target value plus an allowable tolerance range. If the actual spacing between the two lines at the candidate convergence point falls within this tolerance range (for example, if the preset coupling distance is 2μm and the tolerance is ±0.1μm, then an actual spacing between 1.9μm and 2.1μm is considered acceptable), the first verification step is passed; if the actual spacing deviates from the preset value and exceeds the tolerance range, the candidate convergence point is discarded. This verification ensures that the differential lines have a good coupling foundation at the intersection point, avoiding coupling mismatch at the beginning of the trace.

[0057] The second verification step involves checking whether the routing direction after the convergence of each candidate convergence point conflicts with the overall direction of the subsequent single coupled main line, and whether it meets the cornering constraint. Specifically, when extending along the merging main line from the candidate convergence point, the routing direction of the first segment cannot deviate from or significantly revert to the routing direction at the convergence point (i.e., the routing direction cannot be opposite to the global ideal direction or the angle cannot be close to 180°). Simultaneously, this angle must meet the aforementioned 135° cornering constraint. If the routing direction after convergence does not conflict with the overall direction of the main line and the angle meets the cornering constraint, the second verification is passed; if there is a routing direction conflict or the cornering constraint is not met, the candidate convergence point is discarded. This verification ensures that the convergence point is not only the point where two routing lines meet, but also the natural starting point for the extension of subsequent intermediate routing lines, avoiding forced sharp turns or detours in subsequent routing lines due to improper selection of the convergence point location.

[0058] The third verification step checks whether the multi-dimensional cost function value of the current extended routing is less than a preset threshold. The preset threshold is set by multiplying the Manhattan distance between Pin1 and Pin2 in the initial state by a preset coefficient (e.g., 2). If the multi-dimensional cost function value corresponding to the candidate convergence point is less than the preset threshold, the third verification is passed. If the cost function value is greater than or equal to the preset threshold, it indicates that even if the routing reaches the intersection, its accumulated routing length, spacing deviation, or routing direction offset is too large, and the intersection point is not practical for actual cabling and is discarded. This re-verification acts as a global pruning mechanism, eliminating candidate solutions that are too far-fetched or too costly from the source, ensuring that subsequent evaluations are only conducted on candidate convergence points that are practically feasible for the project.

[0059] It should be noted that the execution order of the above-mentioned triple verification is not strictly limited in this application. In some embodiments, the first, second, and third verifications can be performed in order of increasing computational complexity to discard unqualified candidate convergence points as early as possible and reduce unnecessary computation.

[0060] Finally, all candidate convergence points that have passed the triple constraint verification are sorted in ascending order according to the multi-dimensional cost function values ​​F calculated above. The one ranked first, i.e., the one with the smallest F value, represents the candidate convergence point with the best overall performance in the three dimensions of trace length, coupling spacing maintenance, and trace direction consistency, and is selected as the target convergence point.

[0061] In this embodiment, through comprehensive quantitative evaluation of multi-dimensional cost functions and hard screening of triple constraint verification, the final selected target convergence point not only performs well in a single indicator, but also achieves a global optimal balance in multiple dimensions such as trace length, coupling quality, and trace smoothness, which significantly reduces the design rule violations that may occur in the subsequent routing process.

[0062] 103. Using the target convergence point as the junction node, physically merge the two traces extending from the two pins to the junction node into a single coupled main line, and use the single coupled main line for mid-section routing planning.

[0063] Understandably, after selecting the target convergence point, the traces of Pin1 and Pin2 have already extended from their respective physical pin locations to that target convergence point. At this point, the two traces physically intersect at the target convergence point. This step uses this intersection node as a boundary node, locking the trace segments of the two traces from their respective physical pins to the intersection node, and using this intersection node as a new starting point to merge the two independent traces into a single coupled main line for mid-section routing planning.

[0064] The single coupled main line refers to merging the centerlines of two traces into a single abstract trace entity in terms of topology. Physically, this trace still contains two parallel metal wires maintaining a coupling distance, but at the algorithmic level, it is treated as a single entity for routing planning. When performing obstacle avoidance calculations, the EDA tool only needs to perform obstacle detection and routing optimization on this single abstract trace entity, rather than simultaneously maintaining the obstacle avoidance constraints of two independent traces and their relative spacing constraints. Because high-density 2.5D interposers typically contain a large number of TSVs (Through Silicon Vias), power / ground networks, and adjacent signal channels, obstacle avoidance calculation is the most time-consuming part of the routing algorithm. Merging the two lines into a single line halves the number of objects requiring obstacle avoidance detection and significantly reduces the number of related calculation iterations.

[0065] Specifically, when performing mid-section routing planning after merging into a single coupled main line, the routing expansion algorithm only needs to ensure that the distance between the single coupled main line and surrounding obstacles meets the design rules. The geometric width of the single coupled main line is treated as the equivalent total width of two routing lines plus the coupling distance in actual calculations. After the mid-section routing planning is completed, the routing of the coupled main line is restored to two parallel routing lines with a fixed distance for subsequent processing. Through the above "merge first, then separate" routing planning strategy, this application can significantly reduce the computational pressure required for parallel planning of dual lines in high-density packaging scenarios, effectively shortening the physical design cycle. This step merges the dual lines into a single coupled main line at the target convergence point for mid-section planning, reducing the dual-line parallel obstacle avoidance problem to a single-line obstacle avoidance problem, significantly reducing the number of constraints that the routing algorithm needs to maintain synchronously in high-density packaging scenarios, and significantly reducing the number of computation iterations.

[0066] 104. Set a split node at the end of the single coupled main line, and synchronously lead out two independent signal lines from the split node to restore the standard differential dual-line structure.

[0067] It should be noted that the essential characteristic of differential signals is that the two complementary signal lines are always transmitted in parallel with tight coupling. Therefore, after the merging transition in the middle section, the final output to the receiving end must still be restored to a standard differential dual-line structure to ensure that the positive and negative components of the differential signal can be correctly compared and sampled at the receiving end. This step involves splitting the merging trace back into two independent signal lines at the end of the single coupled main line.

[0068] Specifically, a split node can be set at the end of a single coupled main line.

[0069] It is understandable that after a single coupled main line undergoes mid-section routing planning, its end point becomes the endpoint of the mid-section routing. Choosing this endpoint as the splitting node allows the entire routing to naturally transition from a merged state to a split state without the need for additional transition segments or detours, avoiding unnecessary increases in routing length or the introduction of additional impedance discontinuities due to improper selection of the transition location. In some embodiments, if the density of obstacles around this endpoint is high, hindering the simultaneous routing of two independent signal lines, the splitting node can be traced back along the coupled main line to a location with a more relaxed routing environment; this application does not impose limitations on this.

[0070] Next, starting from the split node, two independent signal lines are simultaneously led to the differential signal receiver.

[0071] Specifically, starting from the split node simultaneously, two independent signal lines can be led out to the differential signal receiving end (i.e., the receiving pins or receiving areas corresponding to Pin1 and Pin2, respectively). "Synchronous lead-out" means that the lead-out actions of the two independent signal lines belong to the same atomic operation in the algorithmic logic. Each step of the expansion of the two leads is decided and executed simultaneously, rather than sequentially. Compared to sequential execution, synchronous lead-out ensures that the two lines share a completely consistent decision-making benchmark during processing, avoiding asymmetry in the routing direction of the two lines due to environmental changes caused by sequential decisions (such as the timing difference of when a previous trace is occupied by another trace).

[0072] During the extraction process, a mirror-symmetric expansion strategy is adopted, using the perpendicular bisector of the line connecting the split node and the differential signal receiver as the axis of symmetry. Simultaneously, candidate grid points for the two independent signal lines are expanded in pairs to form a standard differential dual-line structure. To ensure complete electrical balance between the two independent signal lines after splitting, this application enforces a mirror-symmetric expansion strategy during the extraction process of the split segment.

[0073] Specifically, using the perpendicular bisector of the line connecting the split node and the differential signal receiver as the axis of symmetry, the two target pins of the differential signal receiver are symmetrically positioned on either side. During trace expansion, whenever a candidate grid point is selected for the left independent signal line, the system automatically selects a corresponding candidate grid point for the right independent signal line at the mirror position of that grid point about the axis of symmetry; and vice versa. Through this paired expansion method, the total length, line width, adjacent bend positions, and number of bends of the two independent signal lines remain completely consistent in real time during the expansion process. Simultaneously, a 135° bend process constraint is continuously applied during the expansion of the split segment to ensure that all the split traces meet the interposer manufacturing specifications.

[0074] The standard differential dual-line structure refers to a parallel transmission structure in which two independent signal lines maintain geometric symmetry and electrical characteristics of equal length, equal spacing, and equal impedance. This standard differential dual-line structure is a prerequisite for achieving optimal common-mode noise suppression for differential signals. The electromagnetic fields generated by the two complementary independent signal lines cancel each other out during transmission, and the coupling effect of external interference on the two independent signal lines remains consistent, thus being eliminated by the differential amplifier at the receiving end. Through the above-mentioned mirror-symmetric extension strategy, the embodiments of this application can eliminate the possibility of differential length mismatch and coupling spacing mismatch at the source, avoiding the cumbersome process of passive equal-length adjustment through serpentine winding after wiring in traditional solutions. This mechanism enables differential signals to achieve optimal common-mode noise suppression.

[0075] 105. Grounded shielded metal traces are generated on both sides of the standard differential double-wire structure, and grounding vias are laid along the shielded metal traces to connect the shielded metal traces with the bottom ground plane to form a partially closed shielded structure.

[0076] Understandably, in high-density 2.5D / 3D stacked chips, the spacing between traces in the interposer or metal wiring layer is extremely tight. Adjacent clock signal lines, power networks, high-speed data buses, etc., can all cause crosstalk interference to the standard differential two-wire structure through spatial electromagnetic coupling. Although the standard differential two-wire structure itself has a certain common-mode rejection capability, when the interference frequency or interference intensity is high, differential coupling alone may not be sufficient to control the crosstalk within the allowable range. Therefore, this application further implements automated grounding shielding after completing the complete routing of the standard differential two-wire structure.

[0077] Specifically, you can first identify the overall outline and trace of the standard difference dual-line structure to determine the area where shielding needs to be applied.

[0078] This range typically covers the entire trace segment of a standard differential two-wire structure, from the starting pin area of ​​the first and second pins to the receiving end area.

[0079] Subsequently, grounded shielded metal traces are generated on both sides of the standard differential dual-wire structure. These shielded metal traces are continuous, long strip-shaped metal conductors, and their routing direction is consistent with that of the standard differential dual-wire structure. During the generation process, the linewidth of the shielded traces and the spacing between the shielded traces and the standard differential dual-wire structure are strictly set according to the design rules specified in the process library file to ensure that manufacturing constraints such as minimum spacing and minimum linewidth are not violated.

[0080] After the shielding metal traces are generated, an array of grounding vias can be laid out along the trace direction at fixed intervals. Each grounding via is a conductive channel that vertically penetrates the insulating dielectric layer and connects different metal layers. One end of each grounding via is connected to the shielding metal trace, and the other end is connected to the bottom complete ground plane of the chip. Through this via array, the shielding metal traces form a low-impedance electrical connection with the bottom ground plane throughout the entire trace, ensuring good grounding performance of the shielding structure across the entire frequency band.

[0081] After the shielded metal traces are connected to the underlying ground plane, two grounded "isolation walls" can be formed on both sides of the standard differential two-wire structure. Together with the underlying ground plane and the upper reference metal layer (if any), they form a locally enclosed shielded isolation zone. This shielded isolation zone physically separates the standard differential two-wire structure from the surrounding wiring area, blocking the electric and magnetic field coupling paths generated by adjacent signal lines. At the same time, since the shielded lines provide an adjacent low-impedance return path, the return loop area of ​​the standard differential two-wire structure is significantly reduced, further reducing loop radiation and external interference. Through the above-mentioned automated grounding shielding process, that is, generating grounded shielded metal traces on both sides of the standard differential two-wire structure and laying grounding vias along the shielded metal traces to connect the shielded metal traces to the underlying ground plane, thereby forming a locally enclosed shielding structure, the embodiments of this application can significantly improve the anti-interference capability of the standard differential two-wire structure in complex stacked chip environments without the need for manual drawing of shielded ground lines. This fully automated grounding shielding process effectively reduces the signal return loop area and blocks electromagnetic coupling interference from surrounding power networks and digital signal lines.

[0082] In some embodiments, after the partial enclosed shielding structure is constructed, a design rule check can be performed to verify whether the trace width of the shielding metal trace, the spacing between the shielding metal trace and the standard differential dual-line structure, the diameter of the grounding via, and the center distance between adjacent vias all meet the design rules in the process library file. If any violations are found, automatic fine-tuning is performed until all design rule checks are passed. After the design rule check is passed, the standard differential dual-line structure, along with the shielding metal traces on both sides and the grounding via array, are merged and output as complete routing data. This complete routing data may include the routing information of the standard differential dual-line structure, the routing information of the shielding metal trace, and the position information of the grounding via array. All data are organized according to the layout data format for subsequent physical verification and tape-out process calls.

[0083] In summary, the differential signal routing method provided in this application includes using the two pins of the differential pair as bidirectional expansion start points, without pre-setting a fixed end point, and using an advanced A* algorithm to expand the routing towards each other to generate several candidate convergence points; evaluating the several candidate convergence points based on a multi-dimensional cost function to determine the target convergence point; using the target convergence point as the intersection node, physically merging the two traces extending from the two pins to the intersection node into a single coupled main line, and using the single coupled main line for mid-section routing planning; setting a splitting node at the end of the single coupled main line, and synchronously leading out two independent signal lines from the splitting node to restore the standard differential dual-line structure; generating grounded shielded metal traces on both sides of the standard differential dual-line structure, and routing grounding vias along the shielded metal traces to connect the shielded metal traces to the underlying ground plane to form a partially closed shielded structure. In this embodiment, the two pins of the differential pair are used as bidirectional expansion starting points, and no fixed endpoint is preset. An advanced A-Star algorithm is used for opposite routing expansion to generate several candidate convergence points. Then, the target convergence point is determined based on a multi-dimensional cost function. This transforms the traditional single-endpoint A-Star algorithm's "point-to-point" directional expansion into a differential dual-pin "opposite search, dynamic convergence" expansion mode. During the expansion process, the number of branches increases linearly with the number of steps rather than exponentially. Moreover, it can adaptively converge to the optimal convergence position without presetting the endpoint, which significantly reduces the size of the expansion space and the number of algorithm iterations, thereby reducing the computational complexity of differential signal routing.

[0084] To facilitate better implementation of the differential signal routing method provided in this application, this application also provides a differential signal routing apparatus. The meanings of the terms used are the same as in the differential signal routing method described above, and specific implementation details can be found in the descriptions within the method embodiments.

[0085] Please see Figure 3 , Figure 3 This is a schematic diagram of the differential signal routing device provided in an embodiment of this application. The differential signal routing device may include a routing extension unit 201, a target determination unit 202, a mid-section planning unit 203, a standard restoration unit 204, and a shielding formation unit 205. The trace expansion unit 201 is used to expand the traces in opposite directions using the two pins of the differential pair as bidirectional expansion start points and without a preset fixed end point, and to generate several candidate convergence points by using an advanced A-star algorithm. The target determination unit 202 is used to evaluate several candidate convergence points based on a multi-dimensional cost function in order to determine the target convergence point; The mid-section planning unit 203 is used to physically merge two traces extending from two pins to the intersection node with the target convergence point as the intersection node, and merge them into a single coupled main line, and use the single coupled main line for mid-section routing planning. Standard restoration unit 204 is used to set a split node at the end of a single coupled main line, and synchronously lead out two independent signal lines from the split node to restore it to a standard differential dual-line structure. The shielding forming unit 205 is used to generate grounded shielding metal traces on both sides of the standard differential double-wire structure, and to lay grounding vias along the shielding metal traces to connect the shielding metal traces with the bottom ground plane to form a partially enclosed shielding structure.

[0086] For specific implementation methods of each of the above units, please refer to the embodiments of the differential signal routing method described above, which will not be repeated here.

[0087] In summary, the differential signal routing device provided in this application embodiment can use the routing expansion unit 201 to expand the routing in opposite directions with the two pins of the differential pair as bidirectional expansion start points and without a preset fixed end point, using an advanced A* algorithm to generate several candidate convergence points; the target determination unit 202 evaluates the several candidate convergence points based on a multi-dimensional cost function to determine the target convergence point; the mid-section planning unit 203 uses the target convergence point as the intersection node to physically merge the two routing lines extending from the two pins to the intersection node, merging them into a single coupled main line, and uses the single coupled main line for mid-section routing planning; the standard restoration unit 204 sets a split node at the end of the single coupled main line, and synchronously leads out two independent signal lines from the split node to restore the standard differential double-line structure; the shielding formation unit 205 generates grounded shielded metal routing lines on both sides of the standard differential double-line structure, and lays grounding vias along the shielded metal routing lines to connect the shielded metal routing lines with the bottom ground plane, forming a partially closed shielding structure. In this embodiment, the two pins of the differential pair are used as bidirectional expansion starting points, and no fixed endpoint is preset. An advanced A-Star algorithm is used for opposite routing expansion to generate several candidate convergence points. Then, the target convergence point is determined based on a multi-dimensional cost function. This transforms the traditional single-endpoint A-Star algorithm's "point-to-point" directional expansion into a differential dual-pin "opposite search, dynamic convergence" expansion mode. During the expansion process, the number of branches increases linearly with the number of steps rather than exponentially. Moreover, it can adaptively converge to the optimal convergence position without presetting the endpoint, which significantly reduces the size of the expansion space and the number of algorithm iterations, thereby reducing the computational complexity of differential signal routing.

[0088] This application also provides an electronic device that may integrate the differential signal wiring device of this application embodiment, such as... Figure 4 As shown, it illustrates a structural schematic diagram of the electronic device involved in the embodiments of this application, specifically: The electronic device may include components such as a processor 301 with one or more processing cores and a memory 302 with one or more computer-readable storage media. Those skilled in the art will understand that... Figure 4 The electronic device structure shown does not constitute a limitation on the electronic device and may include more or fewer components than shown, or combine certain components, or have different component arrangements. Wherein: The processor 301 is the control center of the electronic device. It connects various parts of the electronic device via various interfaces and lines. By running or executing software programs stored in the memory 302 and / or the methods provided in this application, and by calling data stored in the memory 302, it performs various functions and processes data, thereby providing overall monitoring of the electronic device. Optionally, the processor 301 may include one or more processing cores; preferably, the processor 301 may integrate an application processor and a modem processor, wherein the application processor mainly handles the operation of the storage medium, user interface, and application programs, while the modem processor mainly handles wireless communication. It is understood that the modem processor may not be integrated into the processor 301.

[0089] The memory 302 can be used to store software programs and the methods provided in this application. The processor 301 executes various functional applications and data processing by running the software programs stored in the memory 302 and the methods provided in this application. The memory 302 may mainly include a program storage area and a data storage area. The program storage area may store applications required for operating the storage medium and at least one function; the data storage area may store data created based on the use of the electronic device. In addition, the memory 302 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other volatile solid-state storage device. Accordingly, the memory 302 may also include a memory controller to provide the processor 301 with access to the memory 302.

[0090] Although not shown, the electronic device may also include a display unit, an input unit, and a power supply, etc., which will not be described in detail here. Specifically, in this embodiment, the processor 301 in the electronic device loads the executable files corresponding to the processes of one or more application programs into the memory 302 according to the following instructions, and the processor 301 runs the application programs stored in the memory 302 to realize various functions, as follows: Using the two pins of the differential pair as bidirectional expansion start points and without a preset fixed end point, an advanced A-star algorithm is used to expand the traces in opposite directions to generate several candidate convergence points. Several candidate convergence points are evaluated based on a multi-dimensional cost function to determine the target convergence point; Using the target convergence point as the junction node, the two traces extending from the two pins to the junction node are physically merged into a single coupled main line, and the middle section of the trace is planned based on the single coupled main line. A splitting node is set at the end of the single coupled main line, and two independent signal lines are synchronously drawn out from the splitting node to restore the standard differential dual-line structure. Grounded shielded metal traces are generated on both sides of the standard differential dual-wire structure, and grounding vias are laid along the shielded metal traces to connect the shielded metal traces to the bottom ground plane, forming a partially enclosed shielded structure.

[0091] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be performed by instructions, or by instructions controlling related hardware. These instructions can be stored in a computer-readable storage medium and loaded and executed by a processor.

[0092] Therefore, embodiments of this application provide a storage medium storing a plurality of instructions that can be loaded by a processor to execute steps in any of the methods provided in embodiments of this application. For example, the instructions can execute the following steps: Using the two pins of the differential pair as bidirectional expansion start points and without a preset fixed end point, an advanced A-star algorithm is used to expand the traces in opposite directions to generate several candidate convergence points. Several candidate convergence points are evaluated based on a multi-dimensional cost function to determine the target convergence point; Using the target convergence point as the junction node, the two traces extending from the two pins to the junction node are physically merged into a single coupled main line, and the mid-section routing is planned using the single coupled main line. A splitting node is set at the end of the single coupled main line, and two independent signal lines are synchronously drawn out from the splitting node to restore the standard differential dual-line structure. Grounded shielded metal traces are generated on both sides of the standard differential dual-wire structure, and grounding vias are laid along the shielded metal traces to connect the shielded metal traces to the bottom ground plane, forming a partially enclosed shielded structure.

[0093] For details on the implementation of each of the above operations, please refer to the previous examples, which will not be repeated here.

[0094] The storage medium may include: read-only memory (ROM), random access memory (RAM), disk or optical disk, etc.

[0095] Since the instructions stored in the storage medium can execute the steps of any method provided in the embodiments of this application, the beneficial effects that any method provided in the embodiments of this application can achieve can be realized. For details, please refer to the previous embodiments, which will not be repeated here.

[0096] The differential signal wiring method, apparatus, storage medium, and electronic device provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A differential signal routing method, characterized in that, include: With the two pins of the differential pair as the starting points for bidirectional expansion and without a preset fixed end point, during the initial trace expansion, the two pins are initially expanded along four preset directions to form 16 initial trace combinations. Calculate the current cost function value for each initial routing combination, and then expand subsequent routings in ascending order of the current cost function value. In the subsequent trace expansion process, when the expanded traces of two pins meet the preset intersection conditions, a candidate convergence point is generated, thereby obtaining several candidate convergence points; The candidate convergence points are evaluated based on a multi-dimensional cost function to determine the target convergence point; Using the target convergence point as the junction node, the two traces extending from the two pins to the junction node are physically merged into a single coupled main line, and the middle section of the trace is planned using the single coupled main line. A splitting node is set at the end of the single coupled main line, and two independent signal lines are synchronously led out from the splitting node to restore the standard differential dual-line structure. Grounded shielded metal traces are generated on both sides of the standard differential dual-line structure, and grounding vias are laid along the shielded metal traces to connect the shielded metal traces to the bottom ground plane, forming a partially closed shielded structure.

2. The differential signal routing method as described in claim 1, characterized in that, The subsequent trace extension process also includes: After each step of trace expansion is completed, invalid extended traces in the subsequent traces to be expanded are trimmed according to the current trace direction of each of the two pins. The invalid extended trace is a trace in the subsequent traces to be extended whose direction is opposite to the current trace direction.

3. The differential signal routing method as described in claim 1, characterized in that, The subsequent trace extension process also includes: Each time the trace is extended, a bend process constraint is applied to the next trace direction of the pin. The cornering process constraint prohibits right-angle turns. The angle between the current routing direction and the previous routing direction must meet 135°. Only the neighboring grid points that meet the cornering process constraint are retained as the next routing direction.

4. The differential signal routing method as described in claim 1, characterized in that, The evaluation of several candidate convergence points based on a multi-dimensional cost function to determine the target convergence point includes: Calculate the multidimensional cost function value for each of the candidate convergence points; For each candidate convergence point, a triple constraint check is performed sequentially. The candidate convergence points that pass the triple constraint check are sorted in ascending order of the multi-dimensional cost function value, and the one with the smallest cost function value is selected as the target convergence point.

5. The differential signal routing method as described in claim 4, characterized in that, The triple constraint verification includes: Verify whether the spacing between the two lines at each candidate convergence point is equal to the preset differential coupling distance; if so, pass. Verify whether the routing direction after the intersection of each candidate convergence point conflicts with the overall direction of the subsequent single coupling main line, and whether it meets the cornering process constraint. If there is no conflict and the cornering process constraint is met, then it passes. Verify whether the multi-dimensional cost function value of the current extended trace is less than the preset threshold; if so, pass.

6. The differential signal routing method as described in claim 1, characterized in that, The step involves setting a splitting node at the end of the single coupled main line, from which two independent signal lines are synchronously led out to restore the standard differential dual-line structure, including: A split node is set at the end of the single coupled main line; Starting from the split node, two independent signal lines are simultaneously led out to the differential signal receiving end; During the extraction process, a mirror symmetry expansion strategy is adopted, taking the perpendicular bisector of the line connecting the split node and the differential signal receiver as the axis of symmetry, and simultaneously expanding the candidate grid points of the two independent signal lines in pairs, thereby forming a standard differential dual-line structure.

7. A differential signal wiring device, characterized in that, include: The trace expansion unit is used to expand bidirectionally from the two pins of the differential pair as the starting point, without a preset fixed end point. During the first trace expansion, the two pins are initially expanded along four preset directions to form 16 initial trace combinations. The current cost function value of each initial trace combination is calculated, and subsequent trace expansion is performed in order of increasing current cost function value. During the subsequent trace expansion process, when the expanded traces of the two pins meet the preset intersection conditions, a candidate convergence point is generated, thereby obtaining several candidate convergence points. The target determination unit is used to evaluate several candidate convergence points based on a multi-dimensional cost function in order to determine the target convergence point; The mid-section planning unit is used to physically merge the two traces extending from the two pins to the intersection node, taking the target convergence point as the intersection node, and merge them into a single coupled main line, and use the single coupled main line to plan the mid-section routing. The standard restoration unit is used to set a splitting node at the end of the single coupled main line, and synchronously lead out two independent signal lines from the splitting node to restore the standard differential dual-line structure. A shielding forming unit is used to generate grounded shielding metal traces on both sides of the standard differential double-wire structure, and to lay grounding vias along the shielding metal traces to connect the shielding metal traces with the underlying ground plane to form a partially closed shielding structure.

8. A storage medium, characterized in that, The storage medium stores multiple instructions, which are applicable to a processor for loading to execute the differential signal routing method according to any one of claims 1-6.

9. An electronic device, characterized in that, It includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements the differential signal routing method as described in any one of claims 1-6.

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