Verification system and method for multi-category quantum measurement and control chip

Abstract

The application provides a multi-class quantum measurement and control chip verification system and method, and relates to the technical field of electronic circuit testing. The method comprises the following steps: an upper computer is configured to generate at least one verification instruction with unified frame structure according to at least one test case in response to receiving the at least one test case, and determine the test result of at least one quantum measurement and control chip according to at least one test response data respectively; a programmable processor is configured to route and distribute at least one verification instruction to at least one target hardware port in at least one first hardware interface according to the type identification field of the at least one verification instruction, and forward at least one test response data received via at least one target hardware port to the upper computer respectively; and at least one verification card, a second hardware interface is detachably connected to a corresponding target hardware port, and a third hardware interface is used for connecting to a corresponding quantum measurement and control chip.

Description

Technical Field

[0001] This invention relates to the field of testing and verification technology for application-specific integrated circuits (ASICs), and more specifically, to a verification system and method for multiple types of quantum measurement and control chips. Background Technology

[0002] Quantum measurement and control chips are application-specific integrated circuits used in quantum computing systems, providing waveform modulation, bias control, and microwave readout functions. As the scale of qubits increases, traditional measurement and control systems become bulky, and the large number of cables introduced at extremely low temperatures introduces thermal loads and noise interference, prompting the development of measurement and control chips towards miniaturization, integration, and near-quantum processor integration.

[0003] In the post-chip tape-out verification stage, a common approach is to use customized evaluation boards for each chip type in conjunction with general-purpose instruments. This results in a high degree of dependency between the test hardware and software and the individual chip, lacking a unified verification framework compatible with different functional types of chips. When multiple chip types iterate rapidly, the underlying hardware and the communication interface with the host computer need to be repeatedly reconstructed, leading to lengthy test development cycles and making it difficult to meet the requirements for unified and integrated testing. Summary of the Invention

[0004] In view of this, the present invention provides a verification system and method for multiple types of quantum measurement and control chips.

[0005] One aspect of the present invention provides a verification system for multiple types of quantum measurement and control chips, comprising: a host computer configured to, in response to receiving at least one test case, generate at least one verification instruction with a unified frame structure according to the at least one test case, and determine the test results of at least one corresponding quantum measurement and control chip according to at least one received test response data; wherein the verification instruction includes a type identification field for the quantum measurement and control chip; a programmable processor connected to the host computer and including at least one first hardware interface; the programmable processor is configured to, according to the type identification field of the at least one verification instruction, route the at least one verification instruction to at least one target hardware port of the at least one first hardware interface, and forward at least one test response data received via the at least one target hardware port to the host computer; at least one verification card, each verification card including a second hardware interface and a third hardware interface, the second hardware interface being detachably connected to the corresponding target hardware port, and the third hardware interface being used to connect to the corresponding quantum measurement and control chip, wherein the quantum measurement and control chip is configured to generate corresponding test response data according to the verification instruction from the verification card.

[0006] According to an embodiment of the present invention, the host computer is further configured to: in response to receiving a port configuration instruction, create at least one Transmission Control Protocol (TCP) service port, and start listening for a specified TCP port among the at least one TCP service port to wait for the programmable processor to initiate a TCP connection request; send network configuration information, including the address of the specified TCP port, to the TCP offload engine of the programmable processor via a User Datagram Protocol (UDP) channel to trigger the TCP offload engine to create a TCP client port, and send a TCP connection request to the specified TCP port through the TCP client port; and in response to receiving the TCP connection request, establish a TCP link with the programmable processor, the TCP link being used to transmit the verification instruction and receive the test response data.

[0007] According to an embodiment of the present invention, the verification instruction further includes a read / write identifier field and a read / write length field; wherein, when the read / write identifier field is a read identifier field, the data length represented by the read / write length field is used as the expected data length of the test response data expected to be received from the quantum measurement and control chip when a read operation is performed on the quantum measurement and control chip; when the read / write identifier field is a write identifier field, the data length represented by the read / write length field is used as the data length of the test data carried by the verification instruction for writing to the quantum measurement and control chip.

[0008] According to an embodiment of the present invention, the host computer is further configured to, for any verification command: receive the test response data corresponding to the verification command via the transmission control protocol link, wherein the test response data includes multiple first data segments belonging to the same batch; store the multiple first data segments respectively into an accumulation pool corresponding to the verification command, and accumulate and record the total length of the first data segments stored in the accumulation pool; if the total length of the stored first data segments is equal to the expected data length, splice the first data segments stored in the accumulation pool to obtain a complete test response data frame; and generate the test result based on the complete test response data frame.

[0009] According to an embodiment of the present invention, the host computer is further configured to: maintain the storage state of the plurality of first data segments during a first time period when the total length of the stored first data segments is less than the expected data length, so that the next batch of second data segments can be stored in the accumulation pool during the first time period; and splice the first data segments and second data segments stored in the accumulation pool together when the total length of the first data segments and second data segments stored in the accumulation pool is equal to the expected data length, to obtain the complete test response data frame.

[0010] According to an embodiment of the present invention, the host computer is further configured to: during a second time period following the first time period, if the total length of the data segments stored in the accumulation pool is less than the expected data length, clear the accumulation pool.

[0011] According to an embodiment of the present invention, the host computer is further configured to: determine the expected number of read instructions to be returned from the test cases based on the read / write identifier field; obtain the actual number of read instructions to be returned based on the number of returned complete test response data frames; and obtain the return data integrity verification result based on the comparison result between the actual number of read instructions to be returned and the expected number of read instructions to be returned.

[0012] According to an embodiment of the present invention, the host computer is further configured to: determine at least one target waveform analysis template from a plurality of preset waveform analysis templates based on the at least one quantum measurement and control chip, wherein the plurality of preset waveform analysis templates correspond to different waveform data types; use the at least one target waveform analysis template to analyze the data payload in the complete test response data frame corresponding to the at least one quantum measurement and control chip to obtain the analysis result data of the at least one quantum measurement and control chip; and display data charts corresponding to the analysis result data in the display area of ​​the graphical user interface, wherein the data charts include at least one of time-domain waveform diagram, IQ scatter plot, state statistics diagram, and frequency-domain spectrum diagram.

[0013] According to an embodiment of the present invention, the test case further includes a data payload field, which represents the data length of the test data in the test case; the host computer is further configured to: compare the data length represented by the data payload field with the data length represented by the read / write length field to obtain a comparison result; if the comparison result indicates that the data lengths represented by the data payload field and the read / write length field are the same, load the verification instruction into the pending-send buffer queue so as to send it to the programmable processor in sequence.

[0014] Another aspect of the present invention provides a verification method for multiple types of quantum measurement and control chips, applied to a verification system for any of the aforementioned multiple types of quantum measurement and control chips. The method includes: a host computer, in response to receiving at least one test case, generating at least one verification instruction with a unified frame structure based on the at least one test case; wherein the verification instruction includes a type identification field for the quantum measurement and control chip; a programmable processor, based on the type identification field of the at least one verification instruction, routes and distributes the at least one verification instruction to at least one target hardware port among the at least one first hardware interface, so as to send at least one verification instruction to at least one quantum measurement and control chip via at least one verification card connected to the at least one target hardware port; wherein the quantum measurement and control chip is configured to generate corresponding test response data based on the verification instruction from the verification card; the programmable processor forwards the at least one test response data received via the at least one target hardware port to the host computer; and the host computer determines the test result of the corresponding at least one quantum measurement and control chip based on the received at least one test response data.

[0015] According to an embodiment of the present invention, a unified frame structure verification instruction including a type identifier field is generated by a host computer, and the verification instruction is routed and distributed to the corresponding target hardware port by a programmable processor according to the type identifier field. The instruction is then delivered to the chip under test via a detachable verification card. This decoupled architecture ensures that when verifying multiple types of chips, the core instruction generation, routing and distribution, and data return logic do not require any hardware reconstruction or code modification. Only a low-cost verification card needs to be replaced, which greatly shortens the test development cycle and reduces the system iteration cost. Attached Figure Description

[0016] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings.

[0017] Figure 1 A schematic diagram of a verification system for multi-category quantum measurement and control chips according to an embodiment of the present invention is shown.

[0018] Figure 2 A schematic diagram of a data frame structure according to a specific embodiment of the present invention is shown.

[0019] Figure 3 A flowchart of a dynamic data reconstruction process according to a specific embodiment of the present invention is shown.

[0020] Figure 4 A schematic diagram of an envelope data storage structure according to a specific embodiment of the present invention is shown.

[0021] Figure 5A schematic diagram of interpolation waveform analysis templates at different multiples according to a specific embodiment of the present invention is shown.

[0022] Figure 6 The following diagram shows the time-frequency domain waveform of the carrier signal of the target quantum measurement and control chip according to a specific embodiment of the present invention, wherein (a) is the time-domain waveform of the carrier signal of the target quantum measurement and control chip, and (b) is the frequency domain spectrum of the carrier signal of the target quantum measurement and control chip.

[0023] Figure 7 A scatter plot of the multi-bit characteristic readout IQ of the target quantum measurement and control chip according to a specific embodiment of the present invention is shown.

[0024] Figure 8 The IQ amplitude diagram of the readout signal time series of the target quantum measurement and control chip according to a specific embodiment of the present invention is shown.

[0025] Figure 9 A state statistics diagram of a target quantum measurement and control chip according to a specific embodiment of the present invention is shown.

[0026] Figure 10 A schematic diagram of the hardware and software co-architecture of a verification system according to a specific embodiment of the present invention is shown.

[0027] Figure 11 A schematic diagram of a communication module in a hardware-software co-engineering architecture according to a specific embodiment of the present invention is shown.

[0028] Figure 12A A schematic diagram of the register interface single read / write area and the test case loading interface batch read / write area of ​​the basic test page according to a specific embodiment of the present invention is shown.

[0029] Figure 12B A schematic diagram of the automated testing area of ​​the multi-test-case continuous testing interface of the basic test page according to a specific embodiment of the present invention is shown.

[0030] Figure 12C A schematic diagram of the test result display area of ​​the basic test page according to a specific embodiment of the present invention is shown.

[0031] Figure 12D A schematic diagram of the network configuration area and communication and debugging window of the basic test page according to a specific embodiment of the present invention is shown.

[0032] Figure 13A The diagram illustrates a single read / write area of ​​the register interface for reading a test page and a batch read / write area of ​​the test case loading interface according to a specific embodiment of the present invention.

[0033] Figure 13B This diagram illustrates the execution and readback area of ​​a large batch of test cases for reading out test pages according to a specific embodiment of the present invention.

[0034] Figure 13C A schematic diagram of the test result display area of ​​the readout test page according to a specific embodiment of the present invention is shown.

[0035] Figure 14 A flowchart illustrating a verification method for multi-category quantum measurement and control chips according to an embodiment of the present invention is shown. Detailed Implementation

[0036] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the invention. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the invention for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concept of the invention.

[0037] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. The terms “comprising,” “including,” etc., as used herein indicate the presence of features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0038] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0039] When using expressions such as "at least one of A, B and C", they should generally be interpreted in accordance with the meaning that is commonly understood by those skilled in the art (e.g., "a system having at least one of A, B and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B and C, etc.).

[0040] Quantum measurement and control chips are application-specific integrated circuits (ASICs) used in quantum computing systems to provide measurement and control functions such as waveform modulation, bias control, and microwave readout to the quantum processor. As quantum computing technology evolves towards scales of hundreds or even thousands of qubits, traditional superconducting quantum measurement and control systems, limited by their large hardware size, require the introduction of numerous coaxial cables in extremely low-temperature environments. The resulting thermal load and noise interference have become physical bottlenecks restricting system expansion. To overcome this limitation, highly integrated application-specific quantum measurement and control chips are being vigorously developed to miniaturize the measurement and control system and deploy it as close as possible to the quantum processor.

[0041] In the verification stage after the quantum measurement and control chip is fabricated, a loose verification mode is typically adopted, which combines a single-category customized evaluation board with general-purpose instruments and offline analysis software. In this mode, the evaluation board is highly bound to a specific type of chip under test, and the test software and hardware are all customized around a single chip, i.e., a "one chip, one system" test system.

[0042] The aforementioned verification methods have significant shortcomings in testing scenarios involving multiple types of chips. Due to the strong coupling between the testing platform and the chip type, there is a lack of a backward-compatible unified verification framework between quantum measurement and control chips of different functional types. When facing rapid iterative testing of multiple types of chips, it is necessary to frequently reconstruct the underlying hardware logic and the upper-level computer communication interface, resulting in a lengthy test development cycle and high costs, making it difficult to meet the unified integration testing requirements of multiple types of quantum measurement and control chips.

[0043] In view of this, embodiments of the present invention generate a unified frame structure verification instruction including a type identifier field through a host computer, and the programmable processor routes and distributes the verification instruction to the corresponding target hardware port according to the type identifier field, and then delivers it to the chip under test via a detachable verification card. This decoupled architecture allows the core instruction generation, routing and distribution and data return logic to be reconfigured without any hardware reconstruction or code modification when verifying multiple types of chips. Only a low-cost verification card needs to be replaced, which greatly shortens the test development cycle and reduces the system iteration cost.

[0044] Specifically, embodiments of the present invention provide a verification system for multiple types of quantum measurement and control chips, comprising: a host computer configured to, in response to receiving at least one test case, generate at least one verification instruction with a unified frame structure based on the at least one test case, and determine the test results of at least one corresponding quantum measurement and control chip based on at least one received test response data; wherein the verification instruction includes a type identification field for the quantum measurement and control chip; a programmable processor connected to the host computer and including at least one first hardware interface; the programmable processor is configured to, based on the type identification field of the at least one verification instruction, route and distribute at least one verification instruction to at least one target hardware port in at least one of the at least one first hardware interface, and forward at least one test response data received via at least one target hardware port to the host computer; at least one verification card, each verification card including a second hardware interface and a third hardware interface, the second hardware interface being detachably connected to the corresponding target hardware port, and the third hardware interface being used to connect to the corresponding quantum measurement and control chip, wherein the quantum measurement and control chip is configured to generate corresponding test response data based on the verification instruction from the verification card.

[0045] It should be noted that the multi-category quantum measurement and control chip verification system and method provided in this embodiment of the invention can be applied to the field of electronic circuit testing technology, such as for the verification and testing of quantum computing measurement and control chips. The verification system and method provided in this embodiment of the invention can also be used in other related technical fields such as digital circuit functional testing and communication protocol error control; therefore, the application field of the verification system and method provided in this embodiment of the invention is not limited.

[0046] Figure 1 A schematic diagram of a verification system for multi-category quantum measurement and control chips according to an embodiment of the present invention is shown.

[0047] like Figure 1 As shown, the verification system includes a host computer 110, a programmable processor 120, and at least one verification card 130.

[0048] The host computer 110 can be the software platform and user interface of the verification system. The host computer 110 includes any electronic device with computing power, network communication capabilities, and graphics display capabilities, such as a personal computer, workstation, or embedded industrial control computer.

[0049] In this embodiment, a main control program runs on the host computer 110. This main control program can adopt a modular design, for example, including a basic test page and multiple expandable function pages. In some specific implementations, users can load test cases through the graphical user interface of the host computer 110.

[0050] Test cases can be a set of test tasks pre-written by the user to verify specific functions of the quantum measurement and control chip 140. They can be in the form of a text configuration file, which may include at least one read and write instruction arranged in sequence.

[0051] In some specific implementations, test cases can be pre-generated by external scripting tools, such as Python-based code projects, according to the characteristics of the chip under test and the testing requirements. The output can be a text configuration file containing multiple verification instructions. In this embodiment, the main control software of the host computer 110 is responsible for loading the text configuration file and executing the subsequent parsing, distribution, and result determination processes.

[0052] In this embodiment, after receiving the test case, the host computer 110 does not directly send the original text. Instead, it parses each instruction in the test case and encapsulates it into verification instructions with a unified frame structure. The unified frame structure means that regardless of the type of chip under test, all verification instructions issued by the host computer 110 follow the same predefined data frame format. This data frame format can serve as a common language for communication between the host computer 110 and the programmable processor 120.

[0053] The verification instruction includes a type identifier field. This type identifier field can be a data area within the verification instruction frame structure, used to carry the value of the type identifier (Chip Identifier, CID).

[0054] In some implementations, the system can assign a unique type identifier to each quantum measurement and control chip 140 under test to uniquely identify that individual chip. In some implementations, the quantum measurement and control chip 140 includes, but is not limited to, an XY waveform modulation chip, a Z-bias control chip, or a microwave readout chip. In one example, the system can assign a type identifier of 1 to any XY waveform modulation chip and a type identifier of 2 to any microwave readout chip.

[0055] In this embodiment, the host computer 110 can explicitly specify the target execution object of this verification instruction through the type identification field, without needing to care about the physical connection location or functional type of the quantum measurement and control chip 140.

[0056] In addition, the host computer 110 is also responsible for receiving the test response data returned from the programmable processor 120, and determining the test results based on this data to complete the test loop.

[0057] The programmable processor 120 can serve as the general-purpose main control hardware for this verification system. In practical engineering implementation, the programmable processor 120 may include a field-programmable gate array (FPGA), and its internal firmware may integrate various functional modules.

[0058] In this embodiment, the programmable processor 120 can be connected to the host computer 110 via a high-speed communication link such as gigabit fiber optic Ethernet to receive verification commands issued by the host computer 110.

[0059] In this embodiment, the programmable processor 120 is provided with at least one first hardware interface. This first hardware interface may be a standardized interface for physical connection and electrical communication between the programmable processor 120 and at least one external verification card 130. In some specific embodiments, the first hardware interface may be a standardized board-to-board interface of an FPGA Mezzanine Card (FMC) to provide abundant I / O pins and high-speed transceiver channels.

[0060] In this embodiment, the programmable processor 120 may integrate routing and distribution logic. When the programmable processor 120 receives a verification command from the host computer 110, it parses the verification command data frame and extracts the type identifier field. Based on the value of the type identifier indicated by the extracted type identifier field, it determines which specific first hardware interface should be sent to this command; this interface is the target hardware port. This method allows the distribution of verification commands to be automatically completed by the hardware according to the command content, without the host computer intervening in the underlying physical details, thus achieving hardware-level decoupling.

[0061] In this embodiment, the programmable processor 120 is also responsible for receiving test response data returned from each target hardware port, encapsulating it, and forwarding it back to the host computer 110.

[0062] The verification card 130 can be a customized printed circuit board (PCB) on which a second hardware interface and a third hardware interface can be set.

[0063] The second hardware interface is physically and electrically compatible with the first hardware interface of the programmable processor 120, for example, a mating connector that is also an FMC interface, and the two can be detached and pluggable connected.

[0064] The third hardware interface can be used to connect the quantum measurement and control chip 140 under test. In some specific embodiments, the quantum measurement and control chip 140 can be fixed to the circuit board of the verification card 130 by means of soldering, forming a permanent or semi-permanent electrical connection with the third hardware interface. The physical form, pin definitions, level standards, and communication protocols of this third hardware interface can be completely customized for a specific type of quantum measurement and control chip 140. For example, for a verification card used to verify an XY waveform modulation chip, its third hardware interface will provide the specific voltage power supply, differential clock signal, and Serial Peripheral Interface (SPI) communication pins required by the XY waveform modulation chip. For a verification card used to verify a microwave readout chip, its third hardware interface may provide different power rails and RF signal interfaces.

[0065] In this embodiment, the quantum measurement and control chip 140 can be used to receive verification instructions transmitted from the third hardware interface of the verification card 130, perform internal logic operations, such as register reading and writing, waveform generation, data acquisition operations, etc., and generate corresponding test response data. The test response data is returned to the programmable processor 120 through the original path, such as sequentially through the third hardware interface, verification card 130, second hardware interface, and target hardware port.

[0066] It should be noted that, since the host computer 110, programmable processor 120 and verification card 130 adopt a unified frame structure verification instruction and a type identifier-based routing distribution mechanism, when it is necessary to switch to verify different types of quantum measurement and control chips 140, the user only needs to turn off the system power, unplug the verification card 130 currently connected to the first hardware interface, insert the new verification card corresponding to the new chip into the same or another first hardware interface, and update the CID configuration of the chip under test in the host computer 110 software.

[0067] Based on this, embodiments of the present invention generate a unified frame structure verification instruction including a type identifier field through a host computer, and the programmable processor routes and distributes the verification instruction to the corresponding target hardware port according to the type identifier field, and then delivers it to the chip under test via a detachable verification card. This decoupled architecture means that when verifying multiple types of chips, the core instruction generation, routing and distribution, and data return logic do not require any hardware reconstruction or code modification. Only a low-cost verification card needs to be replaced, which greatly shortens the test development cycle and reduces the system iteration cost.

[0068] According to an embodiment of the present invention, the first hardware interface includes a plurality of candidate hardware ports, and the programmable processor is further configured to: determine the candidate hardware port corresponding to the type identifier field as the target hardware port based on the mapping relationship between the type identifier field and the plurality of candidate hardware ports, and output the verification instruction corresponding to the type identifier field through the target hardware port.

[0069] In this embodiment, the mapping relationship between the type identifier field and each candidate hardware port can be used to represent a one-to-one correspondence between the type identifier field and each candidate hardware port. In some specific implementations, this mapping relationship can be a lookup table hard-coded in the programmable processor firmware or a simple logical judgment statement. For example, when CID=1, it can be mapped to candidate hardware port 1, CID=2 can be mapped to candidate hardware port 2, and so on. It should be noted that the first hardware interface can be a standardized physical connection interface (such as an FMC interface) between the programmable processor and the verification card. This first hardware interface provides multiple physical pins, which can be divided into multiple logical candidate hardware ports, each candidate hardware port corresponding to a chip under test on the verification card.

[0070] In this embodiment, the programmable processor also integrates a data combiner. This data combiner can be used to find the mapping relationship between the received type identifier field and multiple candidate hardware ports based on the type identifier field, to determine the target hardware port corresponding to the type identifier field, and to route and distribute the verification command to the target hardware port.

[0071] In this embodiment, after the programmable processor receives a complete verification instruction frame from the host computer, its frame parsing module extracts the type identifier field from the instruction. This CID value is then sent to the data combiner. The data combiner uses this CID value as an index to look up the mapping table between the internal type identifier field and the first hardware interface, thereby uniquely determining a candidate hardware port. This selected candidate hardware port is the target hardware port for this instruction.

[0072] In this embodiment, after the target hardware port is determined, the protocol conversion module (e.g., SPI master controller) inside the programmable processor is activated. This protocol conversion module can generate a standard SPI bus communication timing sequence based on the physical pins corresponding to the target hardware port. Specifically, the level of the chip select signal (CS) corresponding to the target hardware port can be pulled low to select the chip under test (DUT) connected to the verification card at the target hardware port. Subsequently, information such as the read / write identifier, register address, and data payload in the verification instruction is output bit by bit to the DUT through the data lines of the target hardware port according to the SPI protocol timing sequence.

[0073] Based on this, embodiments of the present invention, by defining direct mapping routing logic from the type identifier field to candidate hardware ports, completely embed the core control function of instruction distribution into the hardware circuitry of the programmable processor. This method has low latency and completely deterministic behavior, requiring no software protocol stack to run.

[0074] According to an embodiment of the present invention, the host computer is further configured to: in response to receiving a port configuration instruction, create at least one Transmission Control Protocol (TCP) service port, and start listening for a specified TCP port among the at least one TCP service port to wait for the programmable processor to initiate a TCP connection request; send network configuration information, including the address of the specified TCP port, to the TCP offload engine of the programmable processor via a User Datagram Protocol (UDP) channel to trigger the TCP offload engine to create a TCP client port, and send a TCP connection request to the specified TCP port via the TCP client port; and in response to receiving the TCP connection request, establish a TCP link with the programmable processor, the TCP link being used to transmit verification instructions and receive test response data.

[0075] According to an embodiment of the present invention, the host computer is also configured to implement a dual-channel communication link establishment process with the programmable processor.

[0076] The Transmission Control Protocol (TCP) channel is a reliable data transmission channel in the verification system used to carry the issuance of verification commands and the uploading of test response data. It is implemented through a TCP link and is a connection-oriented communication channel that provides reliable byte stream transmission services.

[0077] The Transmission Control Protocol (TCP) service port can be a network port created by the host computer as a TCP server to listen for network connection requests from the programmable processor side. It can be identified by both the Internet Protocol Address (IP) and the port number.

[0078] The User Datagram Protocol (UDP) channel is a connectionless, lightweight communication channel between a host computer and a programmable processor. It is used only for transmitting configuration commands and does not carry test service data.

[0079] Port configuration commands are operation commands triggered by the user through the host computer's graphical user interface after completing network parameter configuration, used to initiate the communication link establishment process. For example, after configuring the local UDP IP address and port number, TCP local IP address and port number on the host computer, and the UDP destination IP address and port number on the programmable processor side in the host computer's communication function area, the user clicks a connection button (such as the "Open" button) on the interface, and the host computer receives the port configuration command. In response to this port configuration command, the host computer begins to execute subsequent communication link establishment operations such as TCP service port creation, listening startup, and TCP offload engine (TOE) configuration distribution.

[0080] In this embodiment, after receiving the port configuration command, the host computer first creates at least one TCP service port and starts listening on the user-specified Transmission Control Protocol (TCP) port used to carry business data. At this time, the host computer acts as the server, waiting for the programmable processor to initiate a connection. It should be noted that the creation and listening of the TCP service port are operations in the communication link establishment phase, which occurs before the test cases are loaded and distributed. The test cases are business data transmitted through the TCP link after it is established.

[0081] Since programmable processors typically lack the ability to run a complete operating system and TCP / IP protocol stack, they integrate a Transmission Control Protocol Offload Engine (TOE). This TOE can be a hardware protocol stack module integrated within the programmable processor, capable of encapsulating and parsing the TCP / IP protocol at the hardware level. This eliminates the need for the processor to run a software protocol stack, significantly reducing protocol processing latency and improving data throughput.

[0082] In this embodiment, after configuration, the host computer can encapsulate the address of the specified Transmission Control Protocol (TCP) port previously set by the user in a UDP packet and send it to the programmable processor via the User Datagram Protocol (UDP) channel. The programmable processor receives the UDP packet, parses out the TCP server address information, and writes it into the configuration register inside the TOE.

[0083] In this embodiment, after the TOE's configuration register is written to the target server address, the TOE is immediately triggered, and its internal state machine begins to operate. First, it creates a Transmission Control Protocol (TCP) client port and, acting as a TCP client, actively sends a standard TCP connection request, such as a Synchronize Message (SYN message), to the specified TCP port that the host computer is listening on. Upon receiving this connection request, the host computer's TCP server socket, through a standard three-way handshake, establishes a bidirectional, reliable TCP link with the programmable processor. All subsequent verification instructions and test response data are transmitted through this TCP link.

[0084] From this point on, the verification system formed two logical channels: the UDP channel serves as the control plane, used to dynamically configure and manage the TOE register during the communication establishment phase and subsequent operation; the TCP channel serves as the data plane, specifically used to carry out the issuance of large numbers of verification commands and the uploading of test response data, ensuring the reliability and order of data transmission.

[0085] Based on this, embodiments of the present invention utilize the lightweight nature of the UDP protocol to achieve flexible remote configuration of the hardware TOE engine and trigger the programmable processor to actively initiate a TCP connection return, so that the programmable processor acts as a TCP client and the host computer always acts as a server. This architecture simplifies the network management logic of the host computer and offloads the protocol processing burden of the host computer's central processing unit (CPU) by utilizing the programmable processor's TOE, providing a stable link foundation for high-throughput, low-latency waveform data transmission of subsequent large amounts of verification data.

[0086] According to an embodiment of the present invention, the verification instruction further includes a read / write identifier field and a read / write length field; wherein, when the read / write identifier field is a read identifier field, the data length represented by the read / write length field is used as the expected data length of the test response data expected to be received from the quantum measurement and control chip when a read operation is performed on the quantum measurement and control chip; when the read / write identifier field is a write identifier field, the data length represented by the read / write length field is used as the data length of the test data carried by the verification instruction for writing to the quantum measurement and control chip.

[0087] In this embodiment, the verification command can be generated by the host computer according to a predefined transaction data frame structure. This data frame structure is an application layer protocol data unit that can serve as the smallest complete unit for data exchange between the host computer and the programmable processor. The data frame structure includes at least the following key fields: a read / write identifier field, a type identifier field, and a read / write length field.

[0088] Figure 2 A schematic diagram of a data frame structure according to a specific embodiment of the present invention is shown.

[0089] like Figure 2 As shown, the top layer of this data frame structure is a batch transmission Transaction instruction sequence, which is composed of multiple independent Transaction frames such as Transaction[1], Transaction[2]...Transaction[n], which correspond to the multi-test case instruction stream continuously issued by the host computer in the batch testing scenario, or the multi-response data stream continuously returned by the chip. It supports the continuous transmission of multiple frames in a single batch and adapts to the concurrent issuance requirements of instructions for batch automated testing of the system.

[0090] The middle layer of this data frame structure is the complete format of a single transaction data frame structure. It can adopt a structure with a fixed command header and a variable data payload, and is divided into two parts: the command field (CMD Field) and the data field (DATA Field).

[0091] The command field is a fixed 64-bit (8-byte) instruction header, from the most significant bit (bit 63) to the least significant bit (bit 0), carrying all control fields. This fixed-length command header design allows the programmable processor's hardware parsing module to quickly extract each control field from a defined offset address, eliminating the need for complex variable-length parsing logic and ensuring the efficiency and determinism of instruction routing and distribution.

[0092] The data field is a variable-length data payload segment, consisting of n 32-bit (4-byte) data units, from the most significant bit (bit 31) to the least significant bit (bit 0), with a total length of n × 4 bytes, satisfying the 4-byte alignment requirement. This variable-length payload design allows the same frame structure to adapt to the differentiated data volume requirements of different types of quantum measurement and control chips. For example, from 4 bytes of data configured in a single register to thousands of bytes of data in a complete waveform memory, all can be carried by a unified frame format.

[0093] The bottom layer of this data frame structure is the 64-bit instruction header CMD[63:0] field bit allocation rule, which divides the data into 6 fixed fields with distinct functions from the highest bit 63 to the lowest bit 0: read / write identifier field, active readback flag field, type identifier field, address field, extended address field, and read / write length field. The data field is a variable-length data payload field.

[0094] The read / write flag field (W / R) is a fixed-length flag bit in the instruction header. The field length of the read / write flag field is 1 bit, and the corresponding bit order is the highest bit of the command field

[63] . It is used to identify the operation type of the current instruction. For example, if the field value is "1", it indicates that the current instruction is a read operation (R), and the host computer requests to read data from a certain address of the chip under test; if the field value is "0", it indicates that the current instruction is a write operation (W), and the host computer requests to write data to a certain address of the chip under test.

[0095] The active readback flag field (ARD FLAG) is a flag bit for the active readback request of the measurement and control chip. The field length of the active readback flag field is 1 bit, and the corresponding bit order is

[62] , so as to support the measurement and control chip to actively initiate a data upload request to the host computer in a specific test scenario (such as asynchronous event triggering).

[0096] The Type Identifier (CID) field is a unique type ID assigned to each quantum measurement and control chip. The field length of the Type Identifier field is 5 bits, and the corresponding bit order is [61:57], which is used to distinguish different types of quantum measurement and control chips.

[0097] The address field (ADDR) is the register offset address field in the instruction header. The field length of this address field is 25 bits, and the corresponding bit order is [56:32]. It is used to carry the register offset address inside the quantum measurement and control chip and to specify the starting address of the register or memory corresponding to this read and write operation.

[0098] The extended address field (EXADDR) is a single chip number identifier within the same type of chipset. The field length of the extended address field is 12 bits, and the corresponding bit order is [31:20]. It is used to distinguish multiple independent chips that are tested in parallel within the same product category, and can be used together with the address field to form a complete instruction addressing space.

[0099] The read / write length field (LENGTH) is a data length indicator field in the instruction header. The field length of this read / write length field is 20 bits, with a corresponding bit order of [19:0] and a unit of bytes. It is used to represent the data length corresponding to this read / write operation, and its semantics are dynamically bound to the status of the read / write identifier field.

[0100] Specifically, when the read / write identifier field is set to read (e.g., a value of 1), the corresponding verification instruction is a register or memory read operation of the quantum measurement and control chip. When encapsulating this instruction, the host computer writes the total number of bytes of test response data expected to be read from the quantum measurement and control chip to be measured into the read / write length field. At this point, the data length represented by this read / write length field is the expected data length.

[0101] When the read / write flag field is a write flag (e.g., a value of 0), the corresponding verification instruction is a write operation to the register or memory of the quantum measurement and control chip. When encapsulating this instruction, the host computer writes the number of bytes of test data to be written to the quantum measurement and control chip, actually carried in the data field, into the read / write length field. At this point, the data length represented by this read / write length field is the actual length of the test data to be written to the quantum measurement and control chip in the verification instruction data payload. It can be used to inform the programmable processor and the chip under test how many bytes of the data payload following the command field need to be sequentially written to the target address.

[0102] The embodiments of this invention, through the dynamic definition of field semantics, allow the same read / write length field in the same Transaction data frame structure to carry different functions under different instruction types: describing "how much data is being sent" in a write instruction, and specifying "how much data will be received" in a read instruction. This design provides essential information for closed-loop data integrity checks in automated verification processes without increasing the complexity of the data frame structure.

[0103] The data payload field (DATA) is the valid data payload field for the verification instructions. This data payload field is of variable length, with each data unit being 32 bits (4 bytes), for a total of n units and a total length of n×4 bytes, satisfying the 4-byte alignment requirement, with a corresponding bit order of [31:0]. During a write operation, this data payload field carries the configuration data to be written to the chip; during a read response, it carries the test waveform or register data returned by the chip. This variable-length payload design allows the same frame structure to adapt to the varying data volume requirements of different types of quantum measurement and control chips, from 4 bytes of data configured in a single register to thousands of bytes of data in a complete waveform memory, all carried by a unified frame format.

[0104] Based on this, embodiments of the present invention employ a unified Transaction data frame structure. A fixed-format command header ensures the universality of hardware routing and parsing. Regardless of the type of chip under test or the type of data it generates, the programmable processor's frame parsing and routing logic can reuse the same hardware circuitry, eliminating the need to redesign communication protocols for different chips. Variable-length data payloads adapt to the varying data volume requirements of different chips, from single-register read / write to large-capacity waveform memory return, all carried by the same frame format. This three-level nested hierarchical design balances the efficiency of batch transmission with the reliability of single-frame parsing, completely decoupling the interaction between the host computer and the programmable processor from specific chip functions. This provides a standardized information carrier for subsequent automatic data integrity verification and seamless switching verification between multiple chip types.

[0105] According to an embodiment of the present invention, the test case further includes a data payload field, which represents the data length of the test data in the test case; the host computer is further configured to: compare the data length represented by the data payload field with the data length represented by the read / write length field to obtain a comparison result; if the comparison result indicates that the data lengths represented by the data payload field and the read / write length field are the same, the verification instruction is loaded into the pending-send buffer queue so as to be sent to the programmable processor in sequence.

[0106] In this embodiment, the host computer can also pre-validate the test case configuration file input by the user. This pre-validation process is executed after the verification instruction has been generated but before it is issued. It is used to check the format and logic compliance of the generated verification instruction to prevent abnormal testing due to errors in test case writing.

[0107] In addition to information such as instruction type, type identifier, and address, user-written test cases also include the test data to be written to the chip when it is a write instruction. In the test case configuration file, the instruction frame structure consists of multiple fields, including a data payload field and a read / write length field. The data payload field stores the actual test data to be written to the chip; its actual byte length is the true length of the test data. The read / write length field specifies the user-declared data length.

[0108] Since test cases are typically manually written or generated text files using scripts, human error is inevitable. For example, the actual length of the data written may not match the declared length of the LENGTH field. Executing this incorrect test case directly could result in writing data of incorrect length or content to the chip.

[0109] Therefore, after the host computer loads and parses the test cases and generates the corresponding verification instructions, it can first execute the pre-verification process. After loading the test cases, the host computer first extracts the actual data length of the data payload field and compares it with the value represented by the read / write length field in the test cases to obtain the consistency comparison result.

[0110] If the comparison results show that the two length values ​​are completely identical, it indicates that the test case is correctly formatted, the data is consistent, and the instruction intent is clear. At this point, the host computer determines that the test instruction is valid and loads the generated verification instruction into the pending-send buffer queue, proceeding to the subsequent delivery process. The pending-send buffer queue can be a data structure in the host computer's memory, used to store pre-verified verification instructions sequentially according to the order of the test cases, which are then retrieved and delivered to the programmable processor by the sending thread in order.

[0111] If the comparison results show that the two length values ​​are inconsistent, it indicates that there is an error in the test case. In this case, the host computer will directly report an error, for example, by explicitly printing the line number of the erroneous instruction and the specific inconsistent value in the log, and refuse to execute the test case with the error, prompting the user to modify the configuration file.

[0112] In this embodiment, during the pre-verification process, the host computer can also automatically remove invalid characters such as extra spaces, newlines, and special symbols from the configuration file, and perform logical checks on the register address range, channel number validity, and other contents to comprehensively filter invalid test cases from the input end.

[0113] In some specific implementations, after successful verification, the host computer can batch cache the verification instructions in the pending buffer queue and automatically execute and send them out in sequence. During execution, the progress can be displayed in real time, and the test results are automatically archived and stored as a text file (TXT).

[0114] Based on this, the embodiments of the present invention use a pre-verification mechanism of length consistency and multi-dimensional pre-verification to filter out test cases with incorrect format and invalid logic from the test input end, thereby avoiding test anomalies and resource waste caused by invalid command issuance. At the same time, combined with batch test case loading and automatic archiving functions, the reliability and execution efficiency of automated testing can be greatly improved.

[0115] According to an embodiment of the present invention, the host computer is further configured to, for any verification command: receive test response data corresponding to the verification command via a transmission control protocol link, the test response data including multiple first data segments belonging to the same batch; store the multiple first data segments respectively into an accumulation pool corresponding to the verification command, and accumulate and record the total length of the first data segments stored in the accumulation pool; if the total length of the stored first data segments is equal to the expected data length, splice the first data segments stored in the accumulation pool to obtain a complete test response data frame; and generate a test result based on the complete test response data frame.

[0116] In this embodiment, due to the varying complexity and time required for the programmable processor to process and execute different test instructions, when the test response data volume is large, the programmable processor employs a segmented transmission mechanism to divide the complete response data frame into multiple data fragments for batch transmission. The time interval between each data fragment returning to the host computer is uncertain due to the asynchronous nature of hardware processing, making it difficult to directly determine the ownership of each data fragment based on its arrival time.

[0117] In this embodiment, after the host computer sends a read-type verification command, it allocates an independent accumulation pool in memory for this verification command based on the expected data length recorded in the read / write length field of the verification command. This accumulation pool serves as a dedicated buffer area for each pending read command, used to temporarily store received data fragments. The accumulation pools for different verification commands are isolated from each other to avoid data crosstalk.

[0118] In this embodiment, the host computer continuously listens to the TCP port and receives data from the programmable processor. Upon receiving a first data segment, such as a TCP data packet, the host computer first routes it to the corresponding accumulation pool based on its source or internal association information. The first data segment is a segmented data packet belonging to the same response batch.

[0119] Specifically, the host computer can append the first data segment to the end of the buffer of the accumulation pool and update a counter associated with the accumulation pool. This counter can be used to accumulate the total length of the first data segment stored in the accumulation pool.

[0120] After each data storage and accumulation operation is completed, the host computer performs a comparison operation. In some specific implementations, the comparison operation includes: comparing the total length of the first data segment currently stored in the accumulation pool with the expected data length previously extracted and stored from the instruction. If the comparison result shows that the data lengths are equal, it indicates that the accumulation pool has received all the bytes of data that exactly constitute a complete response data frame.

[0121] At this point, the host computer can trigger a splicing and reassembly operation. In some specific implementations, this splicing and reassembly operation includes: concatenating multiple first data segments stored sequentially in the accumulation pool buffer according to the receiving order into a continuous and complete byte sequence, which can then serve as a complete test response data frame. The host computer can then generate the corresponding chip's test results based on the content of this complete data frame.

[0122] Based on this, embodiments of the present invention achieve dynamic splicing of TCP streaming data fragments by allocating an independent accumulation pool for each verification instruction and using the expected data length as a reference for integrity judgment. This mechanism does not rely on specific end markers within the data; by establishing an independent accumulation pool for each verification instruction and making deterministic judgments based on the expected data length, it solves the problem of difficulty in determining the ownership of data fragments caused by the segmentation and splitting transmission mechanism of programmable processors. This mechanism can guarantee the integrity of data frames without modifying the underlying hardware communication protocol, thus adapting to high-throughput transmission scenarios with large amounts of waveform data and improving the reliability of data reception.

[0123] According to an embodiment of the present invention, the host computer is further configured to: maintain the storage state of multiple first data segments during a first time period when the total length of the stored first data segments is less than the expected data length, so that the next batch of second data segments can be stored in the accumulation pool during the first time period, and when the total length of the first data segments and second data segments stored in the accumulation pool is equal to the expected data length, splice the first data segments and second data segments stored in the accumulation pool to obtain a complete test response data frame.

[0124] In this embodiment, if the comparison result indicates that the total length of the currently stored first data segment is less than the expected data length, the host computer will determine that the test response data of the current verification command has not yet been completely received. At this time, the host computer will not immediately report an error or discard the received data, but will instead enter a waiting state.

[0125] The first time period can be a preset data reception waiting window duration. In one example, the first time period can be the longest fragment waiting time for a single instruction response pre-configured by the system, for example, configured as 500 milliseconds.

[0126] In this embodiment, during the first time period, the host computer maintains the storage state of multiple first data segments, without closing, clearing, or releasing the accumulation pool associated with the instruction and its stored data, but instead continues to keep the accumulation pool in an active receiving state. Since the TCP protocol can ensure the orderly arrival of data streams, the next batch of second data segments belonging to the same response will continue to be appended to the end of the same accumulation pool.

[0127] The host computer continuously performs the same comparison operation as described above for each subsequent second data segment. When, after any accumulation, it is determined that the total length of the first and second data segments stored in the accumulation pool is finally equal to the expected data length, the host computer immediately ends the waiting state and performs a splicing and reassembly operation on all the fragments stored in the accumulation pool (including the first and second data segments) to obtain a complete test response data frame.

[0128] In some specific implementations, the duration of the first time period can be preset by the user according to actual testing needs. For example, if a fast hardware response or a good network environment is expected, the first time period can be configured to a shorter duration (e.g., 200 milliseconds). In this case, if data is not returned in time due to hardware processing delays or network fluctuations, the system will trigger a timeout error, allowing the user to judge the hardware processing performance or network fluctuations. If a large amount of data is expected or the network environment is complex, the first time period can be configured to a longer duration (e.g., 500 milliseconds) to provide a more ample data reception window and avoid misjudgments caused by normal fluctuations. This configurable timeout mechanism provides testers with flexible debugging and diagnostic tools.

[0129] Based on this, embodiments of the present invention introduce a time-limited waiting state and a continuous accumulation mechanism, enabling the verification system to adapt to the differences in data segment return intervals caused by the uncertain time consumption of the programmable processor when processing different test instructions. This avoids test misjudgments and process interruptions caused by the asynchronous nature of hardware response, and the verification process can automatically recover and complete data reception, thereby improving the system's adaptability to complex network environments and overall testing efficiency.

[0130] According to an embodiment of the present invention, the host computer is further configured to: during a second time period following the first time period, if the total length of the data segments stored in the accumulation pool is less than the expected data length, clear the accumulation pool.

[0131] To prevent the automated verification process from being suspended indefinitely due to severe network failures, abnormal hardware responses, or significant data loss during transmission, embodiments of the present invention are also equipped with timeout determination logic.

[0132] The second time period is the period after the waiting threshold of the first time period is exceeded, and it can be used as a timeout trigger node.

[0133] In this embodiment, when the waiting time in the accumulation pool exceeds the first time period and the second time period begins, if the total length of the data segments stored in the accumulation pool is still less than the expected data length, the host computer determines that the current verification instruction execution has timed out, the test response data reception of the instruction has failed, and an exception handling operation is performed. In some specific implementations, the exception handling operation includes recording the timeout error information, such as the current test case number, instruction content, expected length, and actual received length, and then clearing the accumulation pool.

[0134] In some implementations, the clearing operation includes releasing the memory buffer occupied by the accumulation pool and resetting the associated counter so that the memory resource can be reused by subsequent test cases.

[0135] At the same time, the host computer automatically terminates the execution of the current test case and marks it as "failed" or "timed out", and then automatically triggers the test engine to load and execute the next test case in the queue.

[0136] Based on this, the embodiments of the present invention avoid the problem of the cumulative pool occupying memory for a long time and the test process being stuck in the scenario of hardware unresponsiveness or network abnormality by setting a timeout clearing mechanism. This ensures that even in extreme abnormal situations, the failure of a single test case will not be propagated to the entire batch test task. The system can autonomously diagnose faults, release resources and automatically resume the execution of subsequent tasks, ensuring the continuous and stable operation of batch automated testing and improving the system's fault tolerance and automation level.

[0137] Figure 3 A flowchart of a dynamic data reconstruction process according to a specific embodiment of the present invention is shown.

[0138] like Figure 3 As shown, the dynamic data reorganization process includes operations S301 to S312.

[0139] In operation S301, load and select the test case configuration file.

[0140] In operation S302, the configuration file is pre-verified.

[0141] Specifically, the host computer performs format and logic pre-validation on the verification instructions in the configuration file. If an error occurs during the validation, it loops back to operation S301 to prompt the user to reconfigure.

[0142] When operating S303, the test cases are configured by splitting and parsing instructions.

[0143] Specifically, the host computer parses the read / write flag, chip ID, and register address of each verification instruction, and calculates and stores the expected data length corresponding to this verification instruction based on the read / write length field of the instruction. Simultaneously, it can obtain the ideal value for this test from the benchmark library for subsequent comparison.

[0144] In operation S304, verification instructions for the test cases are issued sequentially.

[0145] Specifically, the host computer can sequentially send verification instructions, encapsulated in a unified Transaction data frame structure, to the programmable processor via the TCP link. After the instructions are sent, the host computer immediately starts the timeout timer for the first period and enters the waiting state.

[0146] In operation S305, determine whether the total length of the data segments currently stored in the accumulation pool is equal to the expected data length. If yes, proceed to operation S306. If no, proceed to operation S307.

[0147] Specifically, the host computer continuously listens to the TCP port, receives multiple data segments belonging to the current verification instruction transmitted back by the hardware through the TCP link, appends and stores them into an independent accumulation pool that uniquely corresponds to the current verification instruction, updates the counter associated with the accumulation pool to accumulate and record the total length of the stored segments, and performs a comparison operation to determine whether the total length stored in the current accumulation pool is equal to the expected data length.

[0148] In operation S306, data segments in the cumulative pool are spliced ​​and reassembled.

[0149] Specifically, if the total length currently stored in the accumulation pool equals the expected data length, the host computer immediately triggers a splicing and reassembly operation, connecting multiple data segments stored sequentially in the accumulation pool into a continuous byte sequence to obtain a complete test response data frame. After splicing is completed, operation S310 is executed.

[0150] In operation S307, determine whether the current waiting time has exceeded the first time period and entered the second time period. If not, execute operation S308; if yes, execute operation S309.

[0151] During operation S308, continue to receive and accumulate data segments.

[0152] Specifically, if no timeout occurs, the host computer keeps the accumulator pool in an active receiving state, waits for the second data segment belonging to the same response to arrive later, and re-executes operation S305.

[0153] In operation S309, clear the current accumulation pool. Then execute operation S310.

[0154] Specifically, if a timeout has occurred, the host computer determines that the current instruction execution has failed, clears the current accumulation pool and resets the counter, and records the timeout error information. After completing the exception handling, operation S310 is executed.

[0155] During operation of S310, results are compared and archived.

[0156] Specifically, the host computer automatically compares the spliced ​​complete test response data frame with the acquired ideal value, and automatically archives the comparison result, execution time, and original waveform data into a text file. After archiving is complete, operation S311 is executed.

[0157] In operation S311, determine whether all test cases have been executed. If yes, proceed to operation S312; otherwise, return to operation S303 and issue the next test case in sequence according to its number.

[0158] S312 is used to summarize the test results.

[0159] Specifically, after all test cases have been executed, the host computer summarizes the execution status, pass rate, error logs and time consumption of all test cases in this automated test, and generates a structured test result summary report, thus completing the entire automated dynamic data reorganization and verification process.

[0160] According to an embodiment of the present invention, the host computer is further configured to: determine the expected number of read instructions to be returned from the test cases based on the read / write identifier field; obtain the actual number of read instructions to be returned based on the number of returned data frames of the complete test response; and obtain the return data integrity verification result based on the comparison result between the actual number of read instructions to be returned and the expected number of read instructions to be returned.

[0161] In this embodiment, in addition to verifying the integrity of the data length of a single verification instruction, the system can also verify the execution integrity of the entire test case from the perspective of the number of instructions, forming a two-layer complementary verification system.

[0162] The first layer of verification is the aforementioned cumulative pool concatenation and reassembly mechanism based on the expected data length, used to ensure that the response data frame returned by each read instruction is complete and error-free in terms of data length. The second layer of verification is the instruction count verification mechanism described in this embodiment, used to ensure that all read instructions that should be returned in the test case have actually been returned.

[0163] Specifically, when the host computer loads and parses the test case configuration file, it can iterate through all the verification instructions in the configuration file. Based on the read / write identifier field in the data frame structure of each verification instruction, it identifies all read instructions and counts the total number of read instructions, recording this total number as the expected number of read instructions to be returned. For example, if a test case contains two write instructions and two read instructions, the host computer determines that the expected number of read instructions to be returned is 2.

[0164] During the test response data reception phase, the host computer successfully receives and splices a complete test response data frame each time, and counts the actual returned read commands to obtain the actual number of returned read commands.

[0165] After all response data for this test case has been processed, the host computer compares the actual number of read commands returned with the expected number of returned commands. If the actual number of returned commands matches the expected number, the command execution for this test case is considered complete, and the return data integrity check passes. If the actual number of returned commands is less than the expected number, an anomaly is considered to exist, indicating that a command was missed or a response was lost. The return data integrity check fails, and the test result is marked as a failure.

[0166] It's important to note that passing the data integrity check does not equate to a successful final test result. Beyond the integrity check, the host computer must further parse the data payload within the complete test response data frame, comparing the parsed actual data with pre-set reference data item by item. Only when the item-by-item comparison results match is the test result for this test case considered successful. If the integrity check fails, or the item-by-item comparison results are inconsistent, the test result is marked as failed.

[0167] Based on this, the embodiments of this disclosure, through overall comparison at the instruction count level, can form a two-layer complementary verification system with single data length comparison. Single data length comparison ensures the correctness of the data content returned by each instruction, while instruction count comparison ensures that all instructions have been executed and returned. On the basis of passing both layers of integrity verification, a step-by-step comparison of data content with preset reference data is then combined to decouple integrity verification from data content verification. This allows users to accurately pinpoint whether the root cause of test failure is incomplete data transmission or a chip functional error. Both together ensure the accuracy and reliability of automated test results.

[0168] According to an embodiment of the present invention, the host computer is further configured to: determine at least one target waveform analysis template from a plurality of preset waveform analysis templates based on at least one quantum measurement and control chip, wherein the plurality of preset waveform analysis templates correspond to different waveform data types; use the at least one target waveform analysis template to analyze the data payload in the complete test response data frame corresponding to at least one quantum measurement and control chip to obtain the analysis result data of at least one quantum measurement and control chip; and display data charts corresponding to the analysis result data in the display area of ​​the graphical user interface, wherein the data charts include at least one of time-domain waveform diagram, in-phase and quadrature (IQ) scatter plot, state statistics diagram, and frequency-domain spectrum diagram.

[0169] After obtaining the complete test response data frame, the system needs to parse the binary raw data carried within into a waveform chart that can be intuitively understood. Since different types of quantum measurement and control chips (such as XY chips and readout chips) and different test items on the same chip, such as envelope data, numerically controlled oscillator (NCO) data, IQ data, and state statistics data, have different data arrangements in memory, sample precision, and interpolation factors, different parsing methods are required.

[0170] In this embodiment, the host computer may have a pre-installed waveform analysis template library, which includes multiple preset waveform analysis templates. Each preset waveform analysis template may correspond to a waveform data type, and the preset waveform analysis template may include, but is not limited to, envelope data templates, NCO modulation data templates, multi-rate interpolation data templates, IQ dual-channel data templates, and state statistics data templates.

[0171] Each preset waveform parsing template can represent a set of data parsing rules, used to define the storage structure of specific binary data in memory (e.g., whether IQ components are stored alternately or in segments), the data bit width of the corresponding waveform, sample arrangement rules, number of channels, byte order, and other parsing parameters. For state statistics templates, the parsing rule set also includes a classification and statistical algorithm for the raw measurement data, used to statistically analyze the raw data from multiple measurements into the frequency distribution of each quantum state. In some specific implementations, additional templates can be added based on the chip type.

[0172] In this embodiment, the host computer can determine at least one target waveform analysis template from the waveform analysis template library based on the type of quantum measurement and control chip corresponding to the current test task. In some specific implementations, the user can first select the chip type (such as XY chip) on the host computer interface, and then select the specific waveform data type (such as envelope data), and the system will match a unique template accordingly.

[0173] For time-domain waveform data, the host computer calls the parsing engine to apply the determined target waveform parsing template to the data payload in the complete test response data frame. Following the template rules, multiple digital samples are extracted from the continuous binary byte stream to obtain the time-domain waveform sampling points. The host computer then calls its integrated plotting module to draw the time-domain waveform diagram, composed of these sampling points, in a Cartesian coordinate system (e.g., the horizontal axis for time and the vertical axis for amplitude) within the display area of ​​the graphical user interface.

[0174] Figure 4 A schematic diagram of an envelope data storage structure according to a specific embodiment of the present invention is shown.

[0175] like Figure 4 As shown, in one specific embodiment, a 32-bit wide memory address unit has its high 16 bits [31:16] used to store the in-phase component as envelope I, and its low 16 bits [15:0] used to store the quadrature component as envelope Q. The system can read continuously from address 0x0 to 0xFFC according to this structure, and a total of 1024 samples can be resolved.

[0176] In addition, for chips with waveform interpolation sampling function, the system also has pre-set templates for interpolation data of different multiples.

[0177] Figure 5 A schematic diagram of interpolation waveform analysis templates at different multiples according to a specific embodiment of the present invention is shown.

[0178] like Figure 5 As shown, in one specific implementation, when the chip is configured for 16x interpolation, the system uses a continuous storage and parsing mode, which can extract 2048 valid samples. The corresponding sampling rate is 16×750MHz, or 12GHz. When configured for 8x interpolation, the data in memory uses an alternating storage format of 8 valid data points followed by 8 invalid data points. The system, through the stepping rules set by the template, extracts only 1024 valid samples from the total 2048 sample points, resulting in a sampling rate of 6GHz.

[0179] For data requiring frequency domain analysis, the host computer's analysis engine extracts time-domain waveform sampling points and automatically passes this set of sampling point data to the embedded numerical calculation module. This module calls a preset Fast Fourier Transform (FFT) algorithm to calculate the time-domain sampling points, converting the discrete-time signal into frequency-domain components to obtain frequency-domain spectrum data, where each data point represents the intensity of a specific frequency component. The host computer's plotting module simultaneously creates a new coordinate system (e.g., the horizontal axis for frequency and the vertical axis for amplitude) within the graphical user interface display area and renders the frequency-domain spectrum diagram corresponding to the frequency-domain spectrum data.

[0180] Figure 6 The following diagram shows the time-frequency domain waveform of the carrier signal of the target quantum measurement and control chip according to a specific embodiment of the present invention, wherein (a) is the time-domain waveform of the carrier signal of the target quantum measurement and control chip, and (b) is the frequency domain spectrum of the carrier signal of the target quantum measurement and control chip.

[0181] like Figure 6 As shown, Figure 6 Figure (a) shows the time-domain waveform of the carrier signal of the target quantum measurement and control chip. The horizontal axis represents the sampling point number, indicating the position of the Nth sample in the output sequence of the digital-to-analog converter (DAC), reflecting the temporal order of the output samples. The vertical axis represents the amplitude, specifically the digital code value, measured in least significant bits. The figure illustrates a fixed-frequency, fixed-amplitude microwave carrier digital signal output by an arbitrary waveform generator (AWG). For example, this DAC has an 8-bit resolution, therefore the maximum digital code value is 127, and the minimum is -127.

[0182] Figure 6 Figure (b) shows the frequency domain spectrum of the carrier signal of the target quantum measurement and control chip. It was generated by the Fast Fourier Transform (FFT) algorithm embedded in the host computer after calculating the sampling points in the time domain above. The horizontal axis represents the normalized frequency, which is the ratio of the frequency to the sampling frequency; the vertical axis represents the amplitude, in decibels (dB). This figure intuitively reflects the spectral purity of the output microwave signal, helping operators to identify signal spurious signals and phase noise.

[0183] For the IQ mixing data of the microwave readout chip, the corresponding IQ data template demodulates the I and Q components to obtain scatter plot data on the IQ complex plane. The analytical result data is the coordinate distribution of each qubit on the IQ plane. The host computer then generates an IQ scatter plot based on this.

[0184] Figure 7A scatter plot of the multi-bit characteristic readout IQ of the target quantum measurement and control chip according to a specific embodiment of the present invention is shown.

[0185] like Figure 7 As shown in the figure, the horizontal axis represents the in-phase component (I component), and the vertical axis represents the quadrature component (Q component). Both axes can be represented by digital code values ​​after analog-to-digital conversion, characterizing the precise projection position of each sampling point on the IQ complex plane. The figure distributes multiple measurement results of 16 superconducting qubits (Qubit1~Qubit16) on the IQ complex plane as rays of different colors. The divergence length of each ray intuitively represents the distinguishing distance between the 0 and 1 states on the IQ plane (i.e., state distinguishability). The longer the ray, the stronger the state distinguishability of that qubit, and theoretically, the higher the readout fidelity. This figure provides crucial foundational data for subsequently setting the optimal readout axis and calculating readout fidelity.

[0186] In addition, to meet the timing analysis requirements of the readout signal, the host computer can further combine the IQ amplitude template to perform time series analysis on the IQ mixed signal of multiple qubits, extract the IQ composite amplitude value of each bit at different time points, and generate an IQ amplitude diagram (reflecting the change of amplitude over time) to evaluate the stability and signal-to-noise ratio of the readout signal, and provide auxiliary basis for the optimization of timing parameters.

[0187] Figure 8 The IQ amplitude diagram of the readout signal time series of the target quantum measurement and control chip according to a specific embodiment of the present invention is shown.

[0188] like Figure 8 As shown in the figure, the horizontal axis represents the sampling point order, indicating the position of each sample point acquired along the time sequence after the dispersive readout pulse is applied, which can map and reflect the order of evolution of the readout signal over time. The vertical axis represents the IQ magnitude, in dB, used to characterize the power / amplitude level of the resonant cavity response signal. The figure shows the variation trend of the amplitude of the resonant cavity response signal of each of the 16 qubits (Qubit1~Qubit16) with the sampling point number after the dispersive readout pulse is applied. The horizontal baseline at approximately -75dB in the figure is the noise floor of the system, reflecting the static background energy of the measurement link. Above this baseline, the colored spikes appearing at different time points (different colors represent different qubits) correspond to the transient response signal of each qubit's resonant cavity to the readout pulse. The peak amplitude and the time position of their appearance can be used to accurately analyze the readout timing window, signal rise / fall characteristics, and signal strength consistency of each qubit, providing an important basis for optimizing the readout pulse length and sampling delay.

[0189] For the large amount of raw data obtained from the multiple measurements, the host computer can also call the state statistics template to classify and accumulate the measurement results returned for each qubit, calculating the frequency distribution of each qubit in the ground state, first excited state, second excited state, and abnormal state (leaked or unclassified state) during repeated measurements. The parsed results are presented as the statistical frequency of each quantum state, and the host computer generates a state statistics graph based on this to help users intuitively judge the readout fidelity and energy leakage of each bit.

[0190] Figure 9 A state statistics diagram of a target quantum measurement and control chip according to a specific embodiment of the present invention is shown.

[0191] like Figure 9 As shown, the horizontal axis of the graph represents the qubit number, listing each superconducting qubit under test in sequence (e.g., Qubit1~Qubit16); the vertical axis represents the statistical frequency, in units of times, indicating the cumulative number of times each quantum state is observed under a set number of repeated measurements. The bar chart in the graph uses a stacked segmented design, with different colored blocks representing the statistical frequency and proportion of different quantum states: blue (S0) indicates the qubit is in the ground state, orange (S1) indicates it is in the first excited state, yellow (S2) indicates it is mistakenly excited to the second excited state (an unexpected erroneous excited state), and purple (S3) represents other abnormal states (such as leaky states or unclassified states). This graph intuitively presents the overall state distribution of each qubit in multiple measurement cycles, helping operators to quickly compare the performance of each qubit horizontally, and promptly identify problems such as a low proportion of ground states for a specific qubit, abnormal correlation between adjacent qubit states, or an excessively high frequency of highly excited states. This provides intuitive data support for optimizing readout pulse parameters and calibrating multi-qubit systems.

[0192] In this embodiment, the aforementioned data charts can be displayed in different display areas of the graphical user interface. These display areas can be arranged side-by-side or vertically within the same interface, enabling synchronous rendering and display of multi-dimensional data, or they can be switched and viewed individually. The system can further execute an intelligent peak annotation algorithm on the spectrum graph, automatically identifying and marking the spectral peak with the highest amplitude and its frequency value. This plotting module also supports interactive operations such as waveform dragging and zooming, and supports multiple display modes including single-channel waveforms, dual-channel waveforms (simultaneously displaying I and Q components), and interpolated waveforms.

[0193] Based on this, embodiments of the present invention achieve unified analysis and visualization of various waveform data from different types of quantum measurement and control chips through a multi-template adapted waveform analysis architecture. The waveform analysis template library covers multiple functions such as waveform extraction, data demodulation, and statistical analysis. It can convert raw binary data into various data charts such as time-domain waveforms, frequency-domain spectrograms, IQ scatter plots, and state statistics plots with one click. There is no need to develop separate analysis tools for each chip, nor is it necessary to export raw data to third-party offline software for analysis. This greatly improves the universality and analysis efficiency of waveform testing for multiple types of chips, and provides complete analytical capabilities to support automated closed-loop verification.

[0194] Figure 10 A schematic diagram of the hardware and software co-architecture of a verification system according to a specific embodiment of the present invention is shown.

[0195] like Figure 10 As shown, the verification system can be physically and logically divided into a host computer 110, a programmable processor 120, and its peripheral circuits. The host computer 110 carries the main control program, and its internal logic is divided into a network data transceiver module, a memory management module, a chip selection module, and corresponding application layer functional interfaces (such as register read / write, waveform display, batch testing, etc.). The programmable processor 120 is located at the system's bottom layer, and its firmware integrates multiple functional modules, including a physical layer chip (PHY), a UDP control block, a TCP protocol offload engine (TOE), a double data rate 4 static random access memory (DDR4 SRAM) data cache, and a data combiner. The programmable processor 120 also has multiple first hardware interfaces (such as the FMC interface) for connecting to verification cards 130 corresponding to different types of quantum measurement and control chips 140. Each first hardware interface includes multiple candidate hardware ports, and each candidate hardware port corresponds to a chip under test on the verification card.

[0196] based on Figure 10 The architecture shown, combined with the following embodiments, implements the data interaction and verification process as follows.

[0197] During the communication connection establishment phase, the host computer 110 configures communication parameters through its network transceiver module. The host computer 110 first uses the User Datagram Protocol (UDP) channel to send network configuration information to the UDP control block of the programmable processor 120, dynamically configuring the registers of the underlying TOE. After receiving the configuration, the TOE actively initiates a connection request to the host computer 110 as a TCP client, thereby establishing a stable Transmission Control Protocol (TCP) link between the host computer 110 and the programmable processor 120. This link is specifically used to carry the subsequent large-scale issuance of verification instructions and the uploading of test response data.

[0198] During the test command issuance and execution phase, the host computer 110 encapsulates the user-configured test cases into verification commands with a unified frame structure. The frame structure contains a type identifier (CID) field to distinguish different chip types. This verification command is sent to the PHY chip of the programmable processor 120 via the aforementioned TCP link. After being parsed by TOE, it is temporarily stored in DDR4 SRAM and then processed by a data combiner. The data combiner, based on the extracted CID value, searches for the mapping relationship between the internally preset type identifier field and candidate hardware ports, accurately routing and distributing the command to the corresponding target hardware port. The underlying circuit bridges the Advanced eXtensible Interface (AXI) protocol to the Serial Peripheral Interface (SPI) protocol via an interface conversion chip, ultimately driving the quantum measurement and control chip 140 (such as the XY chip, Z chip, or readout chip) on the corresponding verification card 130 to perform register read / write or waveform generation operations.

[0199] During the test data feedback and closed-loop processing phase, the large amount of response data or waveform data generated by the quantum control chip 140 under test is sequentially transmitted via the SPI bus, interface conversion chip, data combiner, and DDR4 SRAM cache, and then packaged by TOE and transmitted back to the host computer 110 via a TCP link. Due to the varying complexity and time consumption of different test instructions processed and executed by the programmable processor, when the test response data volume is large, the programmable processor employs a segmented transmission mechanism to split the complete response data frame into multiple data segments for batch transmission. For each read operation verification instruction, the host computer 110 allocates an independent accumulation pool in memory and sequentially stores the multiple data segments (first data segment or second data segment) that arrive in segments into this accumulation pool. The host computer 110 compares the total length of the data segments stored in the accumulation pool with the expected data length carried by the verification instruction. If the data lengths are equal, it triggers splicing and reassembly to obtain the complete test response data frame. If the data is not collected within the first time period, the accumulation pool is cleared after timeout and the process moves to the next test case, ensuring that the automated test does not freeze.

[0200] During the result analysis and chip switching phase, after acquiring the complete data frame, the host computer 110 automatically matches the corresponding preset waveform analysis template based on the category CID of the quantum measurement and control chip 140 under test. This template is then used to analyze the data payload in the complete test response data frame, obtaining the analysis result data. The corresponding data charts, including time-domain waveforms, IQ scatter plots, state statistics plots, or frequency-domain spectrograms, are displayed in the graphical user interface's display area, completing multi-dimensional feature extraction and automatic archiving of verification results. When switching the category of the chip under test is required, simply remove the original category verification card, insert the verification card adapted to the new chip, and update the matching CID and waveform analysis template in the host computer 110 to achieve seamless switching, demonstrating the versatility of the hardware-software decoupling and collaborative expansion architecture.

[0201] Figure 11 A schematic diagram of a communication module in a hardware-software co-engineering architecture according to a specific embodiment of the present invention is shown.

[0202] like Figure 11 As shown above, in the above Figure 10 In the hardware-software co-engineering architecture shown, the communication module serves as the core hub for low-level interaction between the host computer and the programmable processor. This communication module can be specifically divided into a network configuration module, a software TCP module, a software UDP module, a hardware TOE configuration module, and a network debugging window.

[0203] On the software side, the network configuration module works in conjunction with the software server to read and write configuration parameters with the upper-layer application through shared memory; the software TCP module is responsible for the reliable transmission of business data, while the software UDP module combines local and target UDP configurations to handle the lightweight distribution and transmission of configuration information and status data via UDP.

[0204] On the hardware side, the hardware TOE configuration module not only writes off registers to the lower-layer TCP / IP protocol stack and network interface, but also handles the sending and receiving of underlying data packets, interacts with the 10 Gigabit fiber optic physical link, and provides real-time feedback of link status information to the upper layer. Furthermore, the network debugging window, as an independent channel, can bypass the standard communication protocol stack, providing flexible low-level debugging and data injection capabilities.

[0205] Specifically, in combination Figure 10 and Figure 11 The interaction implementation process of this communication module is explained as follows.

[0206] The host computer initiates the network configuration module. In this module, the user selects a valid local network card and configures the host computer's TCP service port and UDP port, as well as the programmable processor's target UDP address. After the user clicks the connect button in the communication function area, the host computer receives the port configuration command. Through the software UDP module, it encapsulates the network configuration information, including the host computer's TCP service port address, into a UDP data packet and sends it to the programmable processor via fiber optic cable. This data packet is received by the underlying hardware TOE configuration module, which updates the TOE's configuration register in real time, triggering the programmable processor to act as a TCP client and actively initiate a TCP connection request to the host computer. The host computer's software TCP module listens for this request, completes a three-way handshake, and formally establishes a dedicated TCP data link. Simultaneously, after the connection is established, this UDP channel continues to serve as the control plane, used for dynamic management of the hardware TOE registers and low-level status queries during subsequent operation, forming a dual-channel fiber optic communication architecture of UDP and TCP.

[0207] During subsequent test command issuance and data feedback, the system-generated unified Transaction data frame structure verification commands are issued in an orderly manner through the established software TCP module. The massive waveform data returned by the hardware after executing the commands is also returned through this TCP link. If specific non-standard debugging requirements arise during the verification process, such as needing to bypass the unified frame structure to communicate with the hardware using raw string streams, the host computer will enable the network debugging window. This network debugging window supports user input with specific prefixes (such as "#UDPDATA#" or "#TCPDATA#"), and the system will automatically identify and select the corresponding protocol channel for flexible transmission. It also supports the hardware simultaneously returning UDP and TCP character streams to the debugging window. If a test case fails to collect TCP data within the set time due to uncertain processing time of the programmable processor or network anomalies, the communication module will directly trigger a judgment mechanism, marking the current test case as a timeout failure and automatically transferring it to the next test case. Simultaneously, error information will be printed through the network debugging window or the log module. Because the UDP control channel and the TCP data transmission channel are logically isolated in the architecture, the underlying TOE status monitoring and the main link's business transmission do not interfere with each other.

[0208] Based on this, through Figure 11 The combination of the network configuration module, TOE configuration module, TCP / UDP software module and network debugging window shown, combined with the mechanism of triggering TCP active reconnection by UDP configuration and the logic of dual-channel isolation design, not only ensures high-speed and high-reliability transmission of large batches of waveform data from multiple types of chips, but also provides R&D personnel with flexible debugging methods that can directly reach the underlying layer, further ensuring the integrity and availability of the verification system in complex network environments and various test scenarios.

[0209] As based on Figure 10 Architecture and Figure 11 The data interaction platform established by the communication module is as follows: Figures 12A to 12D as well as Figures 13A to 13C The following are modular schematic diagrams of the test page of the host computer software in actual operation according to embodiments of the present invention.

[0210] In some specific implementations, the host computer's test page adopts a modular layout, with a page switching sidebar on the left and the main operation area on the right. The sidebar lists tabs such as "Basic Tests," "Extended Tests," "Read Tests," and "System-Level Encapsulation Tests," allowing users to flexibly switch between different test modules.

[0211] The following combination Figures 12A to 12D This section explains the various sections of the host computer's basic test page.

[0212] Figure 12A A schematic diagram of the register interface single read / write area and the test case loading interface batch read / write area of ​​the basic test page according to a specific embodiment of the present invention is shown.

[0213] like Figure 12A As shown, the basic test page includes a register interface single read / write area, allowing users to quickly check the register read / write path and network configuration during initial setup or debugging. It includes a write parameter configuration column with four input fields: CID (Hex), extended address (Hex), address (Hex), and data (Hex). Hex represents the hexadecimal value, and users can enter the target register number, extended offset, register address, and the hexadecimal value to be written. It also includes a read data feedback column, displaying four read-only fields: Return-CID (Hex), Return-Extended Address (Hex), Return-Address (Hex), and Return-Data (Hex), showcasing the real-time read-back register contents. This area also includes configuration clock, read, and write buttons, used to set the operating clock source, read data from the current register, and write preset data to the target register, respectively.

[0214] like Figure 12A As shown, the basic test page also includes a batch read / write area for loading test cases, configured with a "configuration file" path display box to specify the batch test case files to be executed; it also includes an "execute configuration" button and a "batch results" display box to start the batch read / write sequence defined in the configuration file and to display the overall execution status and key return information of this batch operation.

[0215] Figure 12BA schematic diagram of the automated testing area of ​​the multi-test-case continuous testing interface of the basic test page according to a specific embodiment of the present invention is shown.

[0216] like Figure 12B As shown, the multi-test-case continuous testing interface automated testing area is used to manage regression test cases and execute continuous automated testing processes. Both the "Test Case" and "Test Results" tables contain a list of Case 1 to Case 16, used to present the execution status (pass / fail) of each test sub-item in real time. Two statistical display areas, "AWG Instruction Count" and "DAQ Instruction Count," are also included. "AWG Instruction Count" represents the number of arbitrary waveform generator instructions, used to quantify the cumulative number of instructions issued to the arbitrary waveform generator during testing; "DAQ Instruction Count" represents the number of data acquisition card instructions, used to quantify the cumulative number of instructions issued to the data acquisition card during testing. This area also includes a "Start Test" button, a progress percentage indicator, a completion status prompt, and a timer display area. Users can use these controls to start the test sequence and monitor the overall execution progress, completion status, and cumulative time in real time.

[0217] Figure 12C A schematic diagram of the test result display area of ​​the basic test page according to a specific embodiment of the present invention is shown.

[0218] like Figure 12C As shown, the test results display area is used to centrally display the data analysis results returned after the test is completed. The first waveform graph has amplitude on the vertical axis and sample on the horizontal axis. The legend marks the Q-channel coordinate points (496.46, 24736.11) and the I-channel coordinate points (496.46, -18965.33), which is used to show the amplitude sampling distribution of the I / Q signals in the time domain. The second waveform graph has amplitude in dB on the vertical axis and frequency in MHz on the horizontal axis. The legend marks the I-channel coordinate points (74.93, 90.17) and the Q-channel coordinate points (74.93, 90.16), which is used to show the amplitude spectrum distribution of the I / Q signals in the frequency domain. This area also features a "Waveform Data" file path display bar, "XY Chip" and "Dual Waveform" mode options, and a "Load Waveform" button for switching data sources or reloading waveform files for offline analysis.

[0219] Figure 12D A schematic diagram of the network configuration area and communication and debugging window of the basic test page according to a specific embodiment of the present invention is shown.

[0220] like Figure 12DAs shown, the network configuration area and communication and debugging window include areas for network parameter configuration, TOE register read / write, and low-level communication log monitoring. The network parameter configuration area is used to set the local network card, UDP / TCP IP address, and port parameters. The TOE register operation area provides TOE ID, address, and data input fields; combined with the "Read" and "Write" buttons, it allows for single register access to the hardware offload engine. The communication log window displays the UDP / TCP connection status and raw hexadecimal data transmission and reception records in real-time, providing transparent feedback for low-level debugging.

[0221] In some specific implementations, clicking the "Readout Test" option in the sidebar will switch to the readout test page. The network configuration area and communication and debugging window of the readout test page are consistent with the basic test page, but the test results display area provides richer graphical analysis tools to address the multi-bit characteristics of microwave readout chips.

[0222] The following combination Figures 13A to 13C This section explains the multiple partitions of the test page read from the host computer.

[0223] Figure 13A The diagram illustrates a single read / write area of ​​the register interface for reading a test page and a batch read / write area of ​​the test case loading interface according to a specific embodiment of the present invention.

[0224] Figure 13B This diagram illustrates the execution and readback area of ​​a large batch of test cases for reading out test pages according to a specific embodiment of the present invention.

[0225] Figure 13C A schematic diagram of the test result display area of ​​the readout test page according to a specific embodiment of the present invention is shown.

[0226] like Figure 13A As shown in the image, the readout test page requires more precise debugging and data acquisition due to the multi-bit characteristics of the microwave readout chip. Therefore, in... Figure 12A The basic test page shown has been expanded with the addition of "Reset" and "Trigger" buttons. The "Reset" button restores the register state to a known initial value to ensure that the starting point of each test is consistent. The "Trigger" button is used to achieve precise synchronization with the chip's operating timing.

[0227] like Figure 13BAs shown, the Batch Test Case Execution and Replay Area supports the import, execution, and result playback of large batches of test cases. It centers around a task queue table, with columns including "Sequence Number," "File Name," "File Path," "Result," and "Result Path," used to centrally manage multiple test cases to be executed and record the execution status and output report location of each case. This area also includes a "Case File" input field, a "Select" button, a "Batch Load" button, and a "Start Execution" button, used to specify the test case files to be added, import them into the task queue, and trigger batch execution. This area also includes a "Result File" field, an "Auto Trigger" checkbox, and a "View Results" button, used to quickly locate and view the playback data after testing.

[0228] like Figure 13C As shown, the test results display area adopts a multi-waveform partition layout to present the time-domain waveforms, IQ amplitude characteristics, and frequency variation curves in microwave readout chip testing. This area includes a time-domain waveform partition, where the vertical axis of the waveform canvas represents amplitude, and the horizontal axis represents the sampling points. This partition has a "Waveform Data" file path bar, a "Time-Domain Waveform" tab, and a "Load Waveform" button for loading and plotting time-domain sampled data. This area also includes an IQ amplitude-times graph partition, where the vertical axis represents the IQ magnitude (IQ_Amplitude), and the horizontal axis represents the sampling point order (Times), used to display the distribution trend of the I / Q signal amplitudes with the number of tests. This area has a "Waveform Data" file path bar, a "Bit Count" setting, an "IQ Amplitude-Times Graph" tab, and a "Load Waveform" button. This area also includes a frequency curve partition, with the vertical axis representing frequency and the horizontal axis representing the qubit number. Each superconducting qubit under test is listed sequentially (e.g., Qubit1~Qubit16), and the graph is marked with coordinate points (X:0.00, Y:0.00) to show the frequency variation of the signal over time, supporting the observation and analysis of frequency-swept or frequency-hopping signals. This area includes a "Waveform Data" file path bar, a "State Data Graph" tab, a "Load Waveform" button, "Number of Acquisitions," and "Sampling Frequency," among other features.

[0229] In this embodiment, Figures 12A to 12D as well as Figures 13A to 13C The software interface shown combines Figure 10 The underlying hardware architecture and Figure 11 The communication protocol stack in the system together form a complete closed loop for a multi-category quantum measurement and control chip verification system, from port configuration and communication establishment, software interaction, protocol parsing to hardware execution and result visualization. Figures 12A to 12D as well as Figures 13A to 13CThis system embodies a modular design architecture that combines a shared basic interface with customized extended interfaces. Different extended interfaces correspond to different types of quantum measurement and control chips and their dedicated waveform analysis templates. When it is necessary to switch to verify different types of chips, operators only need to switch to the corresponding test interface in the sidebar to reuse the underlying hardware and software architecture, demonstrating the system's high scalability and versatility.

[0230] To verify the actual technical effect of the multi-category quantum measurement and control chip verification system and method provided in the embodiments of the present invention, multiple performance index tests were conducted on the verification system, and all measured data were significantly better than expected.

[0231] In terms of speed performance, the expected command transmission and reception speed is no less than 50,000 messages / second, and the actual measured transmission rate reached 8.09 million messages / second, while the receiving and processing rate reached 530,000 messages / second. The expected command data processing speed is no less than 100,000 messages / second, and the actual measured speed reached 793,000 messages / second. The expected latency for a single command transmission and reception is no more than 5 milliseconds, and the actual measured latency was reduced to ≤1 microsecond. In terms of batch testing, the expected time for batch data reading and writing of 16 test cases is no more than 5 minutes, and the actual measured time is only 2 minutes to complete the automatic execution of all test cases, achieving an order-of-magnitude improvement in efficiency compared to the traditional single-step mode.

[0232] In terms of stability, the network packet loss rate is expected to be no higher than 0.5%, and the actual test result is 0%. This is thanks to the cumulative pool verification mechanism, instruction count verification mechanism, and timeout handling mechanism designed in this system, which effectively solves the problems of difficulty in determining the ownership of data segments and missing instruction execution caused by the segmented and split transmission of programmable processors. The single data read and write is expected to support more than 10,000 bytes, and the actual test result shows that it can stably read and write 238 million bytes without any crashes throughout the entire process.

[0233] Regarding resource consumption, the system is expected to run more than 3 parallel threads, with a peak of over 25 threads in actual testing; the system is expected to run ≤500MB of memory, with an average of ≤100MB in actual testing; and the system is expected to utilize ≤40% of the processor, with an average of only 12% in actual testing. This system achieves high-performance automated verification while consuming very few hardware resources and can be widely adapted to various general-purpose computing devices.

[0234] In summary, the verification system and method presented herein significantly outperformed expectations in all core performance indicators, fully demonstrating the effectiveness and superiority of the technical solution of this invention.

[0235] According to an embodiment of the present invention, a verification method for multi-category quantum measurement and control chips is also proposed, which is applied to a verification system for multi-category quantum measurement and control chips.

[0236] Figure 14 A flowchart illustrating a verification method for multi-category quantum measurement and control chips according to an embodiment of the present invention is shown.

[0237] like Figure 14 As shown, the method includes operations S1410~S1440.

[0238] In operation S1410, the host computer responds to receiving at least one test case and generates at least one verification instruction with a unified frame structure based on the at least one test case.

[0239] In operation S1420, the programmable processor routes at least one verification instruction to at least one target hardware port in at least one first hardware interface according to the type identifier field of at least one verification instruction, so as to send at least one verification instruction to at least one quantum measurement and control chip via at least one verification card connected to at least one target hardware port, wherein the quantum measurement and control chip is configured to generate corresponding test response data according to the verification instruction from the verification card.

[0240] In operation S1430, the programmable processor forwards at least one test response data received via at least one target hardware port to the host computer.

[0241] During operation S1440, the host computer determines the test results of at least one quantum measurement and control chip based on the received test response data.

[0242] In this embodiment, the user loads a batch of test case files on the graphical interface. The main control module of the host computer program captures this operation event and initiates the test process. The host computer calls its instruction generation module, traverses each instruction in the test cases, and packages them into a unified frame structure verification instruction according to a preset data structure that is consistent with hardware communication. During this process, the logical test intent written by the user is converted into a binary data stream that can be parsed by the hardware and includes type identifier fields, etc.

[0243] These verification commands are sent from the host computer to the programmable processor (PSP) via the established high-speed TCP data channel. Upon receiving the command frame, the PSP's internal data combiner immediately parses the command and extracts the type identifier field. Based on the mapping between this field and candidate hardware ports, the PSP performs a routing operation, accurately directing the command frame to at least one target hardware port. The command is then physically applied to the input pin of the quantum measurement and control chip via the verification card connected to that port.

[0244] The digital logic circuits inside the quantum measurement and control chip are triggered by external commands to execute corresponding operations and output internal state or memory data as test response data through its communication interface. This response data returns to the programmable processor along the original path, for example via a verification card or the target hardware port.

[0245] The programmable processor is responsible for collecting test response data from different ports, which may return asynchronously. It encapsulates the received response data at the necessary transaction layer and then centrally forwards it to the host computer via its TOE network module and TCP link. The host computer receives the data, performs integrity checks and dynamic reassembly, and obtains a complete response frame. Finally, the host computer calls the result determination logic to compare the parsed actual response data with the expected value or according to rules, determines the test result, and displays and archives the result to the user.

[0246] Based on this, the embodiments of the present invention break through the traditional "one chip, one set" strong coupling test limitation by using a three-layer decoupled verification method of unified frame structure instructions, hardware routing distribution, and detachable verification card adaptation. It can be compatible with the verification requirements of multiple types of quantum measurement and control chips, greatly shorten the test and development cycle of multiple types of chips, and at the same time provide a methodological basis for fully automated verification.

[0247] It should be noted that the verification system part of the multi-category quantum measurement and control chip in the embodiments of the present invention corresponds to the verification method part of the multi-category quantum measurement and control chip in the embodiments of the present invention. For the specific configuration and functional description of the host computer, programmable processor, and verification card in the verification system part, please refer to the corresponding step descriptions in the aforementioned verification method embodiments; for the specific implementation of steps such as the generation of unified frame structure verification instructions, routing distribution based on the type identifier field, dynamic reassembly of the accumulation pool to prevent truncation, and integrated time-frequency domain analysis in the verification method part, please refer to the hardware structure description of the corresponding modules in the aforementioned verification system embodiments. Therefore, the technical content that is repeated or corresponding between the system embodiments and the method embodiments will not be repeated here.

[0248] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions. Those skilled in the art will understand that the features described in the various embodiments of the present invention can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in the present invention. In particular, the features described in the various embodiments of the present invention can be combined and / or combined in various ways without departing from the spirit and teachings of the present invention. All such combinations and / or pairings fall within the scope of this invention.

[0249] The embodiments of the present invention have been described above. However, these embodiments are merely illustrative and not intended to limit the scope of the invention. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the invention, and all such substitutions and modifications should fall within the scope of the invention.

Claims

1. A verification system for multiple types of quantum measurement and control chips, characterized in that, The verification system for the multi-category quantum measurement and control chips includes: The host computer is configured to, in response to receiving at least one test case, generate at least one verification instruction with a unified frame structure based on the at least one test case, and determine the test results of at least one quantum measurement and control chip based on the at least one received test response data; wherein, the verification instruction includes a type identification field for the quantum measurement and control chip; A programmable processor, connected to the host computer and including at least one first hardware interface; the programmable processor is configured to route at least one verification instruction to at least one target hardware port of the at least one first hardware interface according to the type identifier field of the at least one verification instruction, and to forward at least one test response data received via the at least one target hardware port to the host computer. At least one verification card, each verification card including a second hardware interface and a third hardware interface, the second hardware interface being detachably connected to a corresponding target hardware port, the third hardware interface being used to connect to a corresponding quantum measurement and control chip, wherein the quantum measurement and control chip is configured to generate corresponding test response data according to verification instructions from the verification card.

2. The verification system for multi-category quantum measurement and control chips according to claim 1, characterized in that, The host computer is also configured to: In response to receiving a port configuration instruction, at least one Transmission Control Protocol (TCP) service port is created, and listening is started for a specified TCP port among the at least one TCP service port to wait for the programmable processor to initiate a TCP connection request. Network configuration information, including the address of the specified Transmission Control Protocol (TCP) port, is sent to the Transmission Control Protocol (TCP) offload engine of the programmable processor via the User Datagram Protocol (UDP) channel to trigger the TCP offload engine to create a TCP client port and send a TCP connection request to the specified TCP port through the TCP client port. In response to receiving the Transmission Control Protocol (TCP) connection request, a TCP link is established with the programmable processor, the TCP link being used to transmit the verification command and receive the test response data.

3. The verification system for multi-category quantum measurement and control chips according to claim 2, characterized in that, The verification instruction also includes a read / write identifier field and a read / write length field; Wherein, when the read / write identifier field is a read identifier field, the data length represented by the read / write length field is used as the expected data length of the test response data to be received from the quantum measurement and control chip when a read operation is performed on the quantum measurement and control chip; When the read / write identifier field is a write identifier field, the data length represented by the read / write length field is used as the data length of the test data carried by the verification instruction for writing into the quantum measurement and control chip.

4. The verification system for multi-category quantum measurement and control chips according to claim 3, characterized in that, The host computer is also configured to respond to any verification command: The test response data corresponding to the verification command is received via the transmission control protocol link. The test response data includes multiple first data segments belonging to the same batch. The plurality of first data segments are stored in the cumulative pool corresponding to the verification instruction, and the total length of the first data segments stored in the cumulative pool is accumulated and recorded. If the total length of the stored first data segment is equal to the expected data length, the first data segments stored in the cumulative pool are spliced ​​together to obtain a complete test response data frame. The test results are generated based on the complete test response data frame.

5. The verification system for multi-category quantum measurement and control chips according to claim 4, characterized in that, The host computer is also configured to: If the total length of the stored first data segments is less than the expected data length, the storage status of the plurality of first data segments is maintained during the first time period so that the second data segments in the next batch are stored in the accumulation pool during the first time period. If the total length of the first data segments and the second data segments stored in the accumulation pool is equal to the expected data length, the first data segments and the second data segments stored in the accumulation pool are spliced ​​together to obtain the complete test response data frame.

6. The verification system for multi-category quantum measurement and control chips according to claim 5, characterized in that, The host computer is also configured to: In the second period following the first period, if the total length of the data segments stored in the cumulative pool is less than the expected data length, the cumulative pool is cleared.

7. The verification system for multi-category quantum measurement and control chips according to claim 4, characterized in that, The host computer is also configured to: Based on the read / write identifier field, determine the expected number of read commands to be returned from the test cases; The actual number of read commands returned is obtained based on the number of returned data frames in the complete test response frame. The data integrity verification result is obtained by comparing the actual number of data returned by the read instruction with the expected number of data returned by the read instruction.

8. The verification system for multi-category quantum measurement and control chips according to any one of claims 4 to 7, characterized in that, The host computer is also configured to: Based on the at least one quantum measurement and control chip, at least one target waveform analysis template is determined from a plurality of preset waveform analysis templates, wherein the plurality of preset waveform analysis templates correspond to different waveform data types; Using the at least one target waveform analysis template, the data payload in the complete test response data frame corresponding to at least one quantum measurement and control chip is analyzed to obtain the analysis result data of at least one quantum measurement and control chip; Within the display area of ​​the graphical user interface, data charts corresponding to the parsed result data are displayed, wherein the data charts include at least one of time-domain waveform graphs, IQ scatter plots, state statistics graphs, and frequency-domain spectrum graphs.

9. The verification system for multi-category quantum measurement and control chips according to any one of claims 3 to 7, characterized in that, The test case also includes a data payload field, which represents the data length of the test data in the test case; The host computer is also configured to: The data length represented by the data payload field is compared with the data length represented by the read / write length field to obtain the comparison result; If the comparison result indicates that the data length represented by the data payload field and the read / write length field are the same, the verification instruction is loaded into the send-to-be-sent cache queue so that it can be sent to the programmable processor in sequence.

10. A verification method for multi-category quantum measurement and control chips, characterized in that, The method, applied to a verification system for multi-category quantum measurement and control chips as described in any one of claims 1 to 9, comprises: In response to receiving at least one test case, the host computer generates at least one verification instruction with a unified frame structure based on the at least one test case; wherein, the verification instruction includes a type identification field for the quantum measurement and control chip; The programmable processor routes and distributes the at least one verification instruction to at least one target hardware port in the at least one first hardware interface according to the type identifier field of the at least one verification instruction, so as to send at least one verification instruction to at least one quantum measurement and control chip via at least one verification card connected to at least one target hardware port; wherein, the quantum measurement and control chip is configured to generate corresponding test response data according to the verification instruction from the verification card; The programmable processor forwards at least one test response data received via the at least one target hardware port to the host computer. The host computer determines the test results of at least one quantum measurement and control chip based on the received test response data.

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