Method for testing electrical signal integrity for memory high-speed read-write process

Abstract

The application relates to a method for testing the electrical signal integrity of a memory high-speed read-write process, and relates to the technical field of memory electrical signal integrity testing, which comprises the following steps: when a read-after-write sequence or a write-after-read sequence is executed on a to-be-tested memory, DQ signals, DQS signals, clock signals and read-write command signals are synchronously collected; the time point when the last valid data bit of a previous read-write operation ends is determined according to the read-write command signals; the DQS sampling edge of a next read-write operation is determined according to the DQS signals; a bus release observation interval is set between the two; the voltage deviation of one or more DQ lines relative to a preset static voltage level range is measured; a time interval between a next read-write command sending time point and an ending time point is taken as a starting interval; the starting interval is changed and the measurement is repeated; in the case that the voltage deviation exceeds a preset threshold when the DQS sampling edge arrives, the corresponding DQ line, read-write switching sequence type and starting interval are recorded, and a test result is formed, so that the release residual influence can be located.

Description

Technical Field

[0001] This invention relates to the field of memory electrical signal integrity testing technology, specifically to a method for testing electrical signal integrity during high-speed memory read / write processes. Background Technology

[0002] In existing technologies, with the continuous increase in memory interface speeds such as DDR and LPDDR, the coordination between the data lines (DQ), data strobe signal (DQS), clock signal, and command signal during read operations, write operations, and read-write switching directly impacts the stability of the memory system. Especially in high-speed continuous access scenarios such as read-after-write and write-after-read, the DQ bus does not necessarily return to a stable static state immediately after the previous read / write operation ends. If the DQS sampling edge of the subsequent read / write operation arrives too early, driver remnants, insufficient release, pattern-related remnants, or edge-sensitive remnants from the previous operation may intrude into the sampling window of the subsequent operation, causing misjudgments, occasional errors, or insufficient margin. Existing tests often focus on the overall memory function, electrical parameters, or read / write correctness results, typically using pass / fail as the criterion for judgment. However, they lack specific identification of the formation time, duration, direction of deviation, and corresponding start-up interval of DQ line voltage deviation during read-write switching intervals.

[0003] Patent application CN118173157A discloses a comprehensive memory testing method and apparatus. It tests the memory under test using a preset test template and, after initial screening, performs comprehensive testing under various operating environments to obtain memory parameter analysis results and identify low-quality memory. While this approach can improve memory test coverage from a quality screening perspective, its focus is on the comprehensive quality evaluation and parameter lower limit analysis of memory components. It still struggles to directly reflect whether there is release residue on the DQ bus between the end of the previous valid data bit and the next DQS sampling edge during a read / write switch, and it is also difficult to pinpoint the specific DQ line, read / write switch type, and critical startup interval corresponding to the release residue.

[0004] Patent application CN112466381A discloses a test chip suitable for testing the electrical functions of the DDR3 physical layer. It configures the test mode via JTAG and generates test data automatically, enabling DDR to operate at full speed, thus facilitating the observation of the electrical performance of relevant pins in the DDR physical layer. This solution addresses the problem of low-speed interface bandwidth limitations hindering full-speed DDR testing. However, its testing objective primarily focuses on verifying the normality of the DDR3 physical layer's electrical functions. The test results are more biased towards functional correctness, error statistics, and observation of the physical layer's operating status. It does not establish an observation interval for the short process from the release of the previous read / write operation to the subsequent read / write operation in a read-after-write or write-after-read sequence, nor does it obtain the critical condition of insufficient bus release by changing the start interval of the subsequent read / write command relative to the previous end time.

[0005] Therefore, while existing memory testing technologies can achieve full-speed operation testing, comprehensive quality screening, or general signal integrity verification, they still lack a testing method that can synchronously combine the DQ signal, DQS signal, clock signal, and read / write command signal, and use the DQ voltage deviation at the arrival of the DQS sampling edge as the criterion for judgment, during the dynamic process of the DQ bus transitioning from the residual state of the previous operation to the effective sampling state of the next operation during high-speed read / write switching. If this type of release residue cannot be quantified during the testing phase, it is not only difficult to discover boundary problems that are unstable and reproducible in conventional functional testing, but also detrimental to subsequent targeted optimization of read / write scheduling intervals, sampling times, data codes, and related DQ lines. Summary of the Invention

[0006] The purpose of this invention is to provide a method for testing the electrical signal integrity during high-speed memory read and write processes, thereby addressing some of the drawbacks and shortcomings pointed out in the background art.

[0007] The present invention adopts the following technical solution to solve the above-mentioned technical problems:

[0008] When performing a read-after-write sequence or a write-after-read sequence on the memory under test, the DQ signal, DQS signal, clock signal and read / write command signal are collected synchronously. The end time of the last valid data bit of the previous read / write operation is taken as the end time according to the read / write command signal.

[0009] Based on the DQS signal, determine the DQS sampling edge corresponding to the next read / write operation, take the time period between the end time and the DQS sampling edge as the bus release observation interval, and measure the voltage deviation of one or more DQ lines relative to the preset static level range within the bus release observation interval.

[0010] The time interval between the time when the read / write command of a subsequent read / write operation is issued and the end time is used as the start interval. The start interval is changed and the voltage deviation is repeatedly measured. When the voltage deviation exceeds a preset threshold when the DQS sampling edge arrives, the corresponding DQ line, read / write switching sequence type and start interval are recorded as the test result.

[0011] Further, a first test sequence and a second test sequence are executed at the same startup interval. The first test sequence includes the previous read / write operation, and the second test sequence puts the DQ line corresponding to the previous read / write operation in a non-valid data-driven state and retains the DQS sampling edge corresponding to the subsequent read / write operation. The voltage deviation of the DQ line at the arrival of the DQS sampling edge under the first test sequence and the second test sequence are obtained respectively, and the difference between the two voltage deviations is taken as the effective voltage deviation generated by the release residue of the previous read / write operation.

[0012] Furthermore, the end data bit combinations of the previous read / write operation are respectively a high-level end combination and a low-level end combination, while keeping the subsequent read / write operation, the start interval, and the DQS sampling edge unchanged; the high-level end combination is the end data bit combination where the last valid data bit is high, and the low-level end combination is the end data bit combination where the last valid data bit is low; the voltage deviation direction and voltage deviation amount of the DQ line within the bus release observation interval are measured respectively, and when the voltage deviation directions corresponding to the two end data bit combinations are opposite, the voltage deviation amount is attributed to the data bit residual component.

[0013] Furthermore, during the process of changing the start interval, a first start interval test and a second start interval test are performed on the same DQ line, which are ordered adjacent by a preset step size. The second start interval is shorter than the first start interval. When the voltage deviation of the DQ line under the first start interval does not exceed a preset threshold, but the voltage deviation of the DQ line under the second start interval exceeds the preset threshold, the second start interval is maintained and the end data bit combination of the previous read / write operation is changed. If the voltage deviation still exceeds the preset threshold after the change, the second start interval is recorded as a bus release insufficiency interval. If the voltage deviation does not exceed the preset threshold after the change, the second start interval is used as a candidate interval for pattern-related release insufficiency intervals.

[0014] Furthermore, the high-level end combination and the low-level end combination respectively adopt end data bit combinations with opposite last bit levels and one or more bits before the last bit having the same level; when the voltage deviation direction of the DQ line changes in the opposite direction with the last bit level within the bus release observation interval, the residual component of the data bit is assigned to the last bit residual component.

[0015] Furthermore, while keeping the start interval and the DQS sampling edge unchanged, the high-level end combination and the low-level end combination are repeated two or more times consecutively; when the voltage deviation after repetition increases relative to the voltage deviation obtained in the first measurement, the residual component of the data bit is classified as the cumulative residual component.

[0016] Furthermore, within the bus release observation interval, a first measurement time and a second measurement time are selected. The time difference between the first measurement time and the end time of the previous read / write operation is less than a first preset time value, and the time difference between the second measurement time and the DQS sampling edge is less than a second preset time value. When the voltage deviation direction of the DQ line changes with the combination of the end data bits at the first measurement time and maintains the corresponding directional change relationship at the second measurement time, the voltage deviation amount corresponding to the second measurement time is taken as the residual amount of the subsequent read / write operation.

[0017] Furthermore, while maintaining the second start interval, the end data bit combination of the previous read / write operation is switched from a single-level end combination to an alternating-level end combination; the single-level end combination is an end data bit combination in which multiple consecutive valid data bits have the same level, and the alternating-level end combination is an end data bit combination in which multiple consecutive valid data bits are arranged alternately in high and low levels; if the voltage deviation of the DQ line changes from exceeding the preset threshold to not exceeding the preset threshold after the switch, then the second start interval is recorded as a pattern-related release insufficiency interval.

[0018] Furthermore, if the voltage deviation of the DQ line still exceeds the preset threshold after changing the end data bit combination of the previous read / write operation, the sampling determination time determined based on the DQS signal corresponding to the next read / write operation is delayed under the second start interval; if the voltage deviation after the delay does not exceed the preset threshold, the delay amount of the sampling determination time is recorded as the release residual sampling avoidance amount of the DQ line.

[0019] Furthermore, after obtaining the release residual sampling clearance amount, the second start interval and the changed end data bit combination are kept unchanged, and the delayed sampling determination time is backed up by a backswing amount less than the release residual sampling clearance amount; if the voltage deviation of the DQ line exceeds a preset threshold after the backswing, the time difference between the two sampling determination times before and after the backswing is recorded as the release residual edge sensitivity amount of the DQ line.

[0020] This invention synchronously acquires DQ signals, DQS signals, clock signals, and read / write command signals when the memory under test executes a read-after-write sequence or a write-after-read sequence. The time interval between the end of the last valid data bit of the previous read / write operation and the sampling edge of the DQS corresponding to the next read / write operation is used as the bus release observation interval. This allows the bus release state during the read / write switching process to be isolated from the overall functional test results, and the voltage deviation of one or more DQ lines relative to the preset static level range can be directly measured, thereby improving the pertinence and observability of release residue detection.

[0021] This invention also uses the time interval between the issuance of subsequent read / write commands and the previous end time as the start interval. By repeatedly measuring the voltage deviation by changing the start interval, when the voltage deviation exceeds a preset threshold at the arrival of the DQS sampling edge, the corresponding DQ line, read / write switching sequence type, and start interval are recorded. This allows for the determination of the critical conditions for insufficient release or residual data intruding into the subsequent read / write sampling window, facilitating the location of specific failure lines and read / write switching types. It provides a clear basis for adjusting memory control parameters, optimizing sampling edges, and verifying the reliability of high-speed memory interfaces, thereby reducing the risk of occasional errors during high-speed read / write processes. Attached Figure Description

[0022] Figure 1 This is a flowchart of the electrical signal integrity test process for high-speed memory read / write in this invention.

[0023] Figure 2 This is an effective voltage deviation identification diagram in Embodiment 1 of the present invention.

[0024] Figure 3 This is the attribution diagram of the residual end data bit in Embodiment 1 of the present invention.

[0025] Figure 4 This is a graph showing the determination of cumulative residue and intrusive sampling residue in Embodiment 1 of the present invention.

[0026] Figure 5 This is a graph showing the determination of whether the start interval exceeds the threshold in Embodiment 2 of the present invention.

[0027] Figure 6 This is the end data bit combination switching determination diagram in Embodiment 2 of the present invention.

[0028] Figure 7 This is a sampling avoidance and edge sensitivity determination diagram in Embodiment 2 of the present invention. Detailed Implementation

[0029] As attached Figure 1 As shown, this embodiment provides a method for testing the electrical signal integrity of high-speed memory read / write processes. During implementation, the memory under test (MDT) operates according to a pre-set read-after-write or write-after-read sequence, causing the memory bus to switch between read and write directions. The test equipment is connected to the signal terminals of the MDT and synchronously acquires the DQ signal, DQS signal, clock signal, and read / write command signal during the execution of the read-after-write or write-after-read sequence. The read / write command signal indicates read and write operations and their corresponding data transmission timing; the DQ signal is the data signal on the data line of the MDT, and the DQS signal is the data strobe signal corresponding to the DQ signal. The data transmission boundary corresponding to the previous read / write operation is determined by the read / write command signal, and the end time of the last valid data bit of the previous read / write operation is determined by combining the clock signal, DQS signal, and a pre-set burst length. This end time of the last valid data bit is taken as the end time, so that subsequent observation intervals can start from the actual data-driven end position, rather than solely relying on the command issuance time.

[0030] After determining the end time, the DQS sampling edge corresponding to the subsequent read / write operation is identified based on the synchronously acquired DQS signal, and the time period between the end time and the DQS sampling edge is set as the bus release observation interval. The DQS sampling edge is the valid edge used to sample and determine the DQ line level state in the subsequent read / write operation. The bus release observation interval is used to characterize the bus state change process from the end of the previous read / write operation to the sampling of the subsequent read / write operation. Within this observation interval, the test equipment measures the voltage of one or more DQ lines and compares the measured DQ line voltage with a preset static level range, thereby obtaining the voltage deviation of the DQ line relative to the preset static level range. The preset static level range can be determined based on the idle level range of the memory under test when no effective data drive is performed, the electrical specifications of the memory under test interface, or a pre-calibrated reference level range. The voltage deviation reflects whether the DQ line is still affected by residual drive, charge retention, or coupling disturbance from the previous read / write operation during the bus release phase.

[0031] During testing, the time interval between the issuance of the read / write command for the next read / write operation and its end time is set as the start interval. Multiple test conditions are created by changing the start interval. The start interval can be changed by adjusting the command issuance time of the next read / write operation, while maintaining consistency in the operating mode, power supply status, and DQ line connection status of the memory under test. Under each start interval, the corresponding read / write switching sequence is repeatedly executed, and the voltage deviation of the DQ line within the bus release observation interval is repeatedly measured. When the DQS sampling edge corresponding to the next read / write operation arrives, if the voltage deviation of the DQ line exceeds a preset threshold, it indicates that the release residue generated by the previous read / write operation has affected the sampling time of the next read / write operation. The preset threshold can be determined based on the allowable deviation within a preset static level range, the sampling tolerance of the memory under test interface, or a pre-calibrated acceptable sample deviation range. At this time, the DQ line exceeding the threshold, the corresponding read / write switching sequence type, the corresponding start interval, and the corresponding DQS sampling edge are recorded, and the recorded results are used as the electrical signal integrity test results of the memory under test during high-speed read / write switching.

[0032] Based on the above implementation, to distinguish whether the voltage deviation of the DQ line at the sampling moment of the subsequent read / write operation originates from the release residue of the previous read / write operation, a first test sequence and a second test sequence can be executed separately under the same startup interval. The first test sequence retains the previous read / write operation, ensuring that the DQ line is driven according to the corresponding data state during the previous read / write operation, and enters the bus release process after the previous read / write operation ends. The second test sequence uses the same subsequent read / write operation and the same startup interval as the first test sequence, but puts the DQ line corresponding to the previous read / write operation in a non-valid data drive state, while retaining the DQS sampling edge corresponding to the subsequent read / write operation. The non-valid data drive state means that no valid data level is output to the DQ line under test at the time position corresponding to the previous read / write operation, or the DQ line under test is kept in an idle, released, or high-impedance state to avoid the data state of the previous read / write operation effectively driving the DQ line. Thus, the second test sequence can serve as a reference sequence to reflect the reference deviation state of the DQ line at the sampling edge of the subsequent read / write operation when there is no influence of the valid data drive of the previous read / write operation.

[0033] During testing, the voltage deviation of the DQ line at the arrival of the DQS sampling edge was acquired under the first and second test sequences, respectively. For the same DQ line, the first and second test sequences used the same measurement position, the same sampling decision time, and the same preset static level range. Since the two test sequences have the same start interval and retain the same sampling conditions for the subsequent read / write operation, the difference between the two voltage deviations mainly reflects the influence of the release residue from the previous read / write operation on the voltage state of the DQ line. After subtracting the voltage deviation corresponding to the first test sequence and the voltage deviation corresponding to the second test sequence, the effective voltage deviation caused by the release residue from the previous read / write operation is obtained. In this way, the combined influence of the test environment, the subsequent read / write operation itself, and the DQS sampling edge setting on the measurement results can be reduced, thereby improving the accuracy of release residue identification.

[0034] Based on the above implementation, to further determine whether the release residue is related to the end data bit state of the previous read / write operation, different end data bit combinations can be set for comparative testing. Specifically, the end data bit combinations of the previous read / write operation are configured to form both a high-level end combination and a low-level end combination, while keeping the subsequent read / write operation, the start interval, and the DQS sampling edge unchanged. The end data bit combination is a combination of data states consisting of one or more consecutive valid data bits before the end of the previous read / write operation. A high-level end combination is a combination where the last valid data bit is high, and a low-level end combination is a combination where the last valid data bit is low. The test equipment measures the voltage deviation direction and amount of the DQ line within the bus release observation interval under both end data bit combinations. When the voltage deviation directions corresponding to the two end data bit combinations are opposite, it indicates that the residual state of the DQ line changes with the level state of the end data bit of the previous read / write operation; therefore, the corresponding voltage deviation amount is attributed to the data bit residue component.

[0035] High-level and low-level end combinations employ end data bit combinations with opposite last bit levels and one or more preceding bits having consistent levels. By keeping the data bits before the last bit consistent, the impact of changes in preceding data bits on the test results can be reduced, allowing the test results to primarily reflect the role of the last bit level in the end data bit combination. When the voltage deviation direction of the DQ line within the bus release observation interval changes in the opposite direction to the last bit level, it indicates that the residual data bit component is mainly caused by the last bit data state at the end of the previous read / write operation; therefore, the residual data bit component is classified as the last bit residual component.

[0036] While maintaining the startup interval and DQS sampling edge unchanged, the high-level end combination and the low-level end combination are repeated two or more times consecutively. The test equipment obtains the voltage deviation measured for the first time and the voltage deviation after repetition, and compares the two. When the voltage deviation after repetition is larger than the voltage deviation measured for the first time, it indicates that the continuous occurrence of the same type of end data bit combination will enhance the residual effect of the DQ line release phase. Therefore, the residual data bit component is classified as the cumulative residual component. Continuous repetition refers to making the valid data bits before the end of the previous read / write operation appear consecutively with the same end data bit combination while keeping the subsequent read / write operation, startup interval, and DQS sampling edge consistent, so as to observe the cumulative effect of the same data state on the residual DQ line release.

[0037] To determine whether residual data bits persist into the sampling phase of the next read / write operation, a first measurement time and a second measurement time can be selected within the bus release observation interval. The time difference between the first measurement time and the end time of the previous read / write operation is less than a first preset time value, used to characterize the DQ line state at the initial stage of release. The time difference between the second measurement time and the DQS sampling edge is less than a second preset time value, used to characterize the DQ line state near the sampling of the next read / write operation. The first and second preset time values ​​can be preset according to the sampling resolution of the test equipment, the read / write switching cycle of the memory under test, and the position of the DQS sampling edge. When the voltage deviation direction of the DQ line changes with the end data bit combination at the first measurement time, and maintains the corresponding directional change relationship at the second measurement time, it indicates that the residual data bits generated by the previous read / write operation have not fully dissipated within the bus release observation interval, but have continued to the vicinity of the sampling edge of the next read / write operation. In this case, the voltage deviation amount corresponding to the second measurement time is taken as the residual amount intruding into the next read / write operation.

[0038] Based on the above implementation, to determine whether the bus release is sufficient after shortening the startup interval, a first startup interval test and a second startup interval test can be performed on the same DQ line during the startup interval change process. The first startup interval and the second startup interval are ordered adjacently according to a preset step size, and the second startup interval is shorter than the first startup interval. The preset step size can be preset according to the command timing interval, clock cycle, or read / write switching test accuracy that the test equipment can adjust. The test equipment measures the voltage deviation of the DQ line under the first startup interval and the second startup interval respectively. When the voltage deviation of the DQ line under the first startup interval does not exceed the preset threshold, but the voltage deviation of the DQ line under the second startup interval exceeds the preset threshold, it indicates that after the startup interval is shortened, the bus release time after the previous read / write operation ends is insufficient for the DQ line to return to the level state that meets the sampling requirements.

[0039] After determining that the voltage deviation corresponding to the second start interval exceeds a preset threshold, the second start interval is kept unchanged, and the end data bit combination of the previous read / write operation is changed. The test device measures the voltage deviation of the DQ line again under the changed end data bit combination. If the voltage deviation still exceeds the preset threshold after the change, it indicates that the threshold exceedance phenomenon is not caused by a single end data bit combination, but is related to insufficient bus release time under the second start interval. Therefore, the second start interval is recorded as the insufficient bus release interval. If the voltage deviation does not exceed the preset threshold after the change, it indicates that the threshold exceedance phenomenon is related to the end data bit combination of the previous read / write operation. Therefore, the second start interval is used as a candidate interval for the pattern-related insufficient release interval.

[0040] While maintaining the second start interval, the end data bit combination of the previous read / write operation is switched from a single-level end combination to an alternating-level end combination. A single-level end combination is a combination of end data bits with a consistent level for multiple consecutive valid data bits, while an alternating-level end combination is a combination of end data bits with multiple consecutive valid data bits arranged alternately between high and low levels. After the switch, the test equipment again measures the voltage deviation of the DQ line when the DQS sampling edge arrives. If the voltage deviation of the DQ line changes from exceeding a preset threshold to not exceeding the preset threshold, it indicates that the original threshold-exceeding result is related to the residual code pattern formed by the single-level end combination. Therefore, the second start interval is recorded as the insufficient code pattern release interval.

[0041] If the voltage deviation of the DQ line still exceeds a preset threshold after changing the end data bit combination of the previous read / write operation, the sampling determination time determined based on the DQS signal corresponding to the subsequent read / write operation is delayed within the second start interval. The sampling determination time is used to evaluate whether the voltage deviation of the DQ line affects the sampling result of the subsequent read / write operation, and its initial position coincides with the DQS sampling edge corresponding to the subsequent read / write operation. The test equipment re-acquires the voltage deviation of the DQ line at the delayed sampling determination time. If the delayed voltage deviation does not exceed the preset threshold, it indicates that the influence of release residue on the subsequent read / write operation can be avoided by delaying the sampling determination time. Therefore, the delay amount of the sampling determination time is recorded as the release residue sampling avoidance amount of the DQ line. After obtaining the release residue sampling avoidance amount, the second start interval and the changed end data bit combination remain unchanged, and the delayed sampling determination time is backed up by a backswing amount less than the release residue sampling avoidance amount. The backswing amount can be preset according to the time adjustment resolution of the test equipment. If the voltage deviation of the DQ line exceeds the preset threshold after rollback, it indicates that the release residue is sensitive to the sampling edge position. Therefore, the time difference between the two sampling determination times before and after rollback is recorded as the release residue edge sensitivity of the DQ line.

[0042] Example 1:

[0043] This embodiment provides a method for testing the electrical signal integrity during high-speed memory read / write operations. In implementation, a testing device is connected to the DQ signal terminal, DQS signal terminal, clock signal terminal, and read / write command signal terminal of the memory under test. The memory under test operates according to a pre-set read-after-write sequence or write-after-read sequence, and the DQ signal, DQS signal, clock signal, and read / write command signal are synchronously acquired during the execution of the read-after-write sequence or write-after-read sequence.

[0044] The testing equipment identifies the data transmission segment of the previous read / write operation based on the read / write command signal, and determines the end time of the last valid data bit of the previous read / write operation by combining the clock signal and the DQS signal, taking this end time as the end time. The testing equipment determines the DQS sampling edge based on the DQS signal corresponding to the subsequent read / write operation, and uses the time period between the end time and the DQS sampling edge as the bus release observation interval. Within the bus release observation interval, the testing equipment measures the voltage of one or more DQ lines and obtains the voltage deviation of the DQ lines relative to a preset static level range.

[0045] like Figure 2 As shown, the diagonally filled area represents the bus release observation interval, the vertical dotted line represents the DQS sampling edge corresponding to the subsequent read / write operation, and the horizontal dashed line represents the preset threshold. The first test sequence curve and the second test sequence curve show a significant difference at the same DQS sampling edge. The voltage deviation corresponding to the first test sequence is 46mV, and the voltage deviation corresponding to the second test sequence is 13mV. The difference between the two is used to characterize the effective deviation caused by the residual data from the previous read / write operation at the sampling edge. Figure 2 It also shows the relative relationship between the effective voltage deviation and the 30mV preset threshold, so as to intuitively reflect whether the release residue has entered the sampling judgment position of the next read and write operation.

[0046] To distinguish whether the voltage deviation of the DQ line at the sampling moment of a subsequent read / write operation originates from the release residue of the previous read / write operation, the test device executes a first test sequence and a second test sequence under the same start interval. The start interval is the time interval between the time when the read / write command of the subsequent read / write operation is issued and the end time. The first test sequence retains the previous read / write operation, ensuring that the DQ line is driven by valid data according to the corresponding data state during the previous read / write operation, and enters the bus release process after the previous read / write operation ends. The second test sequence uses the same subsequent read / write operation, the same start interval, and the same DQS sampling edge as the first test sequence, but puts the DQ line corresponding to the previous read / write operation in a non-valid data driven state.

[0047] The non-valid data-driven state refers to not outputting a valid data level to the DQ line under test at the time position corresponding to the previous read / write operation, or keeping the DQ line under test in an idle, released, or high-impedance state, so that the second test sequence can be used as a reference sequence. Therefore, the voltage deviation measured under the second test sequence mainly reflects the influence of the test environment, the sampling conditions of the subsequent read / write operation, and the DQS sampling edge setting on the voltage state of the DQ line. The measurement difference between the first and second test sequences is used to characterize the influence of the residual data from the previous read / write operation on the DQ line.

[0048] In this embodiment, the effective voltage deviation caused by the release of residual data from the previous read / write operation is determined according to the following formula:

[0049]

[0050] in, This indicates the effective voltage deviation caused by the release of residual data from the previous read / write operation. This indicates the voltage deviation of the DQ line relative to the preset static level range when the DQS sampling edge arrives in the first test sequence. This indicates the deviation of the reference voltage relative to the preset static level range for the same DQ line under the second test sequence when the same DQS sampling edge arrives. Since the first test sequence includes the previous read / write operation, its measured deviation includes the combined effects of release residue, test environment offset, and sampling conditions of the subsequent read / write operation. The second test sequence puts the DQ line corresponding to the previous read / write operation in a non-valid data-driven state, and its measured deviation mainly reflects the effects of test environment offset and sampling conditions of the subsequent read / write operation. Therefore, when the start interval and DQS sampling edge remain the same, the difference between the two can characterize the effective voltage deviation caused by the release residue of the previous read / write operation.

[0051] In one test, the start interval was set to 1.10 ns, and the test equipment performed a first test sequence and a second test sequence on the DQ3 line. The DQ3 line measured under the first test sequence... The voltage was 46mV, and the DQ3 line was measured under the second test sequence. The value is 13mV. Substituting the above data, we get:

[0052]

[0053] The results indicate that, under the specified startup interval, the DQ3 line exhibits an effective voltage deviation of 33mV at the DQS sampling edge corresponding to the subsequent read / write operation. When this effective residual deviation exceeds a preset threshold, the test device records the corresponding DQ line, read / write switching sequence type, startup interval, and corresponding DQS sampling edge as the electrical signal integrity test result of the memory under test during high-speed read / write switching.

[0054] After identifying release remnants, to further determine whether the release remnants are related to the end data bit state of the previous read / write operation, the test equipment sets the end data bit combination of the previous read / write operation into a high-level end combination and a low-level end combination, while keeping the subsequent read / write operation, start interval, and DQS sampling edge unchanged. The high-level end combination is the end data bit combination where the last valid data bit is high, and the low-level end combination is the end data bit combination where the last valid data bit is low. The test equipment measures the voltage deviation direction and voltage deviation amount of the DQ line within the bus release observation interval under both end data bit combinations. When the voltage deviation directions corresponding to the two end data bit combinations are opposite, it indicates that the residual state of the DQ line changes with the level state of the end data bit of the previous read / write operation, and therefore the corresponding voltage deviation amount is attributed to the data bit remnant component.

[0055] like Figure 3 As shown, the voltage deviations of lines DQ3 and DQ5 under the high-level termination combination are 34mV and 27mV, respectively, while the voltage deviations of lines DQ3 and DQ5 under the low-level termination combination are -31mV and -29mV, respectively. Figure 3 The positive and negative decision lines show the deviation direction of the two types of end data bit combinations. When the end data bit combination changes from a high-level end combination to a low-level end combination, the voltage deviation direction of the measured DQ line changes from positive deviation to negative deviation. This indicates that the deviation is not simply caused by the test environment, but is related to the end data bit state of the previous read / write operation.

[0056] In one implementation, the high-level end combination and the low-level end combination each employ end data bit combinations with opposite last bit levels and one or more bits preceding the last bit having the same level. By keeping the data bits preceding the last bit consistent, the impact of changes in preceding data bits on the test results can be reduced, allowing the test results to primarily reflect the role of the last bit level in the end data bit combination. When the voltage deviation direction of the DQ line within the bus release observation interval changes in the opposite direction to the last bit level, it indicates that the residual data bit component is mainly caused by the last bit data state at the end of the previous read / write operation, and the test device classifies the residual data bit component as the last bit residual component.

[0057] In another implementation, while maintaining the startup interval and DQS sampling edge unchanged, the test equipment repeats the high-level end combination and the low-level end combination two or more times consecutively, and obtains the voltage deviation measured for the first time and the voltage deviation after repetition. When the voltage deviation after repetition increases compared to the voltage deviation measured for the first time, it indicates that the continuous occurrence of the same type of end data bit combination will enhance the residual effect of the DQ line release phase, and the test equipment classifies the residual data bit component as the cumulative residual component.

[0058] In this embodiment, the cumulative residual enhancement ratio formed after consecutively repeating the end data bit combination is determined according to the following formula:

[0059]

[0060] in, This indicates the cumulative residual enhancement ratio formed after consecutively repeating the last data bit combination. This indicates the voltage deviation measured after two or more consecutive repetitions of a high-level or low-level end combination. This indicates the voltage deviation measured when the same end data bit combination first appears. If the voltage deviation of the DQ line increases relative to the first measurement after the same end data bit combination appears consecutively, it indicates that the release residue has a cumulative characteristic; therefore, the ratio of the increase in voltage deviation after repetition to the first measurement value is used as the cumulative residue enhancement ratio.

[0061] In one test, when the low-level end combination first appeared, the test equipment measured the DQ5 line. The voltage was 28mV; after the low-level end combination was repeated three times consecutively, the test equipment measured the voltage on line DQ5. The value is 39mV. Substituting the above data, we get:

[0062]

[0063] The results show that, under the same start-up interval and the same DQS sampling edge conditions, after the continuous occurrence of low-level end combinations, the release residue of the DQ5 line is enhanced by approximately 39.29%, indicating that the release residue of the DQ line is related to the continuous occurrence of low-level end combinations. The test equipment classifies the corresponding data bit residue component as the cumulative residue component.

[0064] To determine whether the residual data bit component persists into the sampling phase of the subsequent read / write operation, the test device can also select a first measurement time and a second measurement time within the bus release observation interval. The time difference between the first measurement time and the end time of the previous read / write operation is less than a first preset time value, used to characterize the DQ line state at the initial stage of release. The time difference between the second measurement time and the DQS sampling edge is less than a second preset time value, used to characterize the DQ line state near the sampling edge of the subsequent read / write operation. When the voltage deviation direction of the DQ line changes with the end data bit combination at the first measurement time, and maintains the corresponding directional change relationship at the second measurement time, it indicates that the residual data bit generated by the previous read / write operation has not fully dissipated within the bus release observation interval, but continues to the vicinity of the sampling edge of the subsequent read / write operation. In this case, the test device uses the voltage deviation amount corresponding to the second measurement time as the residual amount intruding into the subsequent read / write operation.

[0065] like Figure 4 As shown, the bar chart indicates that the deviation after repeated combinations of ending data points increases from 28mV to 39mV, reflecting the cumulative enhancement trend after the same combination of ending data points appears consecutively; the two broken lines represent the process of the initial release residue and the near-sampling residue changing with the relative end time, respectively; the diagonal filled area represents the near-sampling stage; and the vertical dashed line represents the DQS sampling edge. Figure 4 The presence of measurable residual deviations near the sampling stage indicates that the residual data bits from the previous read / write operation did not completely disappear within the bus release observation interval, but continued until near the sampling edge of the next read / write operation. Therefore, the voltage deviation at the second measurement moment can be taken as the residual amount intruding into the next read / write operation.

[0066] Example 2:

[0067] This embodiment provides a method for testing the electrical signal integrity during high-speed memory read / write operations. Based on the synchronous acquisition of the DQ signal, DQS signal, clock signal, and read / write command signal, this embodiment further determines whether the bus release time after the previous read / write operation is sufficient to restore the DQ line to a level that meets the sampling requirements of the subsequent read / write operation by changing the start interval of the next read / write operation.

[0068] In practice, a testing device is connected to the DQ signal terminal, DQS signal terminal, clock signal terminal, and read / write command signal terminal of the memory under test (MDT), causing the MDT to operate according to a pre-set read-after-write or write-after-read sequence. The testing device determines the end time of the last valid data bit of the previous read / write operation based on the read / write command signal and uses this time as the end time. It determines the DQS sampling edge based on the DQS signal corresponding to the next read / write operation and measures the voltage deviation of the DQ line relative to a preset static level range between the end time and the DQS sampling edge.

[0069] During the process of changing the startup interval, the test equipment performs a first startup interval test and a second startup interval test on the same DQ line. The first startup interval and the second startup interval are arranged adjacently according to a preset step size, and the second startup interval is shorter than the first startup interval. The preset step size can be preset according to the command timing precision that the test equipment can adjust or the read / write switching test precision of the memory under test. During the test, the operating mode of the memory under test, the DQ line under test, the read / write switching sequence type, and the preset threshold are kept consistent to reduce the impact of non-startup interval factors on the test results.

[0070] When the voltage deviation of the DQ line does not exceed a preset threshold during the first startup interval, but exceeds the preset threshold during the second startup interval, it indicates that the bus release time after the previous read / write operation is insufficient as the startup interval shortens. To quantify the threshold-exceeding state during the second startup interval, this embodiment uses the following formula to determine the threshold-exceeding determination ratio during the second startup interval:

[0071]

[0072] in, This indicates the over-threshold determination ratio under the second start interval. This represents the voltage deviation measured on the DQ line when the DQS sampling edge arrives during the second start-up interval. This represents the preset threshold. The derivation of this formula is based on the fact that determining whether the release residue affects the sampling time requires comparing the measured voltage deviation with the allowable threshold. After ratio processing, the degree of exceeding the threshold under the second start interval can be directly obtained. When A value greater than 1 indicates that the voltage deviation during the second start-up interval exceeds a preset threshold; when If the value is not greater than 1, it indicates that the voltage deviation under the second start interval has not exceeded the preset threshold.

[0073] In one test, the test equipment performed a read-write switching test on the DQ2 line. The first start interval was set to 1.25ns. The voltage deviation of the DQ2 line at the arrival of the DQS sampling edge was measured to be 34mV, which was within the preset threshold. The voltage was 45mV, therefore no over-threshold occurred during the first startup interval. The second startup interval was then shortened to 0.95ns, and the DQ2 line was measured... The value is 63mV. Substituting the above data, we get:

[0074]

[0075] like Figure 5 As shown, the voltage deviation corresponding to the first start-up interval is 34mV, which is below the preset threshold of 45mV; the voltage deviation corresponding to the second start-up interval is 63mV, which enters the over-threshold region indicated by the slash fill. Figure 5 By comparing two sets of adjacent start-up intervals, it is shown that after the start-up interval is shortened from 1.25ns to 0.95ns, the voltage deviation of the DQ2 line at the DQS sampling edge changes from a state that does not exceed the threshold to a state that exceeds the threshold. The value is 1.40, which indicates that the second start interval needs to enter the subsequent end data bit combination switching judgment.

[0076] While keeping the second start interval unchanged, the test device changes the end data bit combination of the previous read / write operation to another set of end data bit combinations and measures the voltage deviation of the DQ2 line again when the DQS sampling edge arrives. If the voltage deviation still exceeds the preset threshold after the change, it indicates that the threshold-exceeding state is not caused by a single end data bit combination, but is related to insufficient bus release time under the second start interval. The test device records the second start interval as the insufficient bus release interval. If the voltage deviation does not exceed the preset threshold after the change, it indicates that the threshold-exceeding state is related to the end data bit combination of the previous read / write operation. The test device uses the second start interval as a candidate interval for the pattern-related insufficient release interval.

[0077] In one implementation, while maintaining the second start interval, the test device switches the end data bit combination of the previous read / write operation from a single-level end combination to an alternating-level end combination. The single-level end combination is a combination of end data bits with a consistent level for multiple consecutive valid data bits, while the alternating-level end combination is a combination of end data bits with multiple consecutive valid data bits arranged alternately between high and low levels. After the switch, the test device again measures the voltage deviation of the DQ line when the DQS sampling edge arrives. If the voltage deviation of the DQ line changes from exceeding a preset threshold to not exceeding the preset threshold, it indicates that the original threshold-exceeding state is related to the residual code pattern formed by the single-level end combination, and the test device records the second start interval as a code pattern correlation release insufficiency interval.

[0078] like Figure 6 As shown, with the second start interval maintained at 0.95ns, the voltage deviation corresponding to a single-level end combination is 63mV, and the voltage deviation corresponding to the changed end combination is 58mV. Both are higher than the preset threshold of 45mV, indicating that when only another set of end data bit combinations is changed, the DQ line is still in an over-threshold state. After switching to alternating level end combinations, the voltage deviation drops to 39mV and is lower than the preset threshold, indicating that the original over-threshold phenomenon is related to the code pattern residue formed by the single-level end combination. Figure 6 This supports the confirmation of insufficient release intervals related to the code pattern.

[0079] In another implementation, if the voltage deviation of the DQ line still exceeds a preset threshold after changing the end data bit combination of the previous read / write operation, the test device delays the sampling determination time determined based on the DQS signal corresponding to the subsequent read / write operation within the second start interval. The sampling determination time is used to evaluate whether the voltage deviation of the DQ line affects the sampling result of the subsequent read / write operation, and its initial position coincides with the DQS sampling edge corresponding to the subsequent read / write operation. If the delayed voltage deviation does not exceed the preset threshold, it indicates that delaying the sampling determination time can avoid the influence of the release residue of the previous read / write operation on the subsequent read / write operation, and the test device records the delay amount of the sampling determination time as the DQ line release residue sampling avoidance amount.

[0080] After obtaining the release residue sampling clearance amount, the test equipment keeps the second start interval and the changed end data bit combination unchanged, and backtracks the delayed sampling determination time by a clearance amount less than the release residue sampling clearance amount, and re-acquires the voltage deviation of the DQ line. If the voltage deviation of the DQ line exceeds the preset threshold again after the clearance, it indicates that the release residue is sensitive to the sampling edge position. At this time, the release residue edge sensitivity of the DQ line is determined according to the following formula:

[0081]

[0082] in, This indicates the residual edge sensitivity of the DQ line release. This indicates the delayed sampling and judgment time, and the voltage deviation measured at that time does not exceed the preset threshold. This indicates the sampling decision time at which the threshold is exceeded again after backtracking from the delayed sampling decision time. The derivation of this formula is based on the fact that, under the condition that the second start interval and the changed end data bit combination remain unchanged, if delaying the sampling decision time can eliminate the threshold exceeding, but backtracking restores the threshold exceeding, then the time difference before and after backtracking can characterize the sensitivity range of the DQ line to changes in the sampling edge position.

[0083] In one test, with a second start interval of 0.95 ns, after changing the end data bit combination, the voltage deviation of the DQ2 line was still 58 mV, exceeding the preset threshold of 45 mV. The test equipment delayed the sampling and judgment time to... At 2.18 ns, the measured voltage deviation of line DQ2 decreased to 41 mV, which did not exceed the preset threshold; subsequently, the sampling decision time was moved back to... At 2.06 ns, the measured voltage deviation of line DQ2 rose again to 47 mV, exceeding the preset threshold. Substituting the above data, we can obtain:

[0084]

[0085] like Figure 7 As shown, at a sampling decision time of 2.00 ns, the voltage deviation of line DQ2 is 58 mV, which is in an over-threshold state; the sampling decision time is rolled back to... At that time, the voltage deviation was 47mV, still higher than the preset threshold of 45mV; the sampling and judgment time was delayed to At that time, the voltage deviation dropped to 41mV, which is lower than the preset threshold. Figure 7 The area filled with diagonal lines indicates to The edge-sensitive interval between the two points has a time length of 0.12ns, indicating that the DQ line is sensitive to changes in the sampling decision time within this time range. The test equipment can record the second start interval, the changed end data bit combination, the release residual sampling avoidance amount, and the release residual edge sensitivity amount together to characterize the degree of release residual impact of the memory under test during high-speed read / write switching.

[0086] Through the above method, this embodiment can distinguish between insufficient bus release time and insufficient code pattern-related release during the test process with gradually shortened startup intervals, and further determine the release residual sampling clearance amount and release residual edge sensitivity amount, thereby providing a more specific judgment basis for evaluating the electrical signal integrity of the memory under test in high-speed read-write switching scenarios.

Claims

1. A method for testing the electrical signal integrity during high-speed memory read / write operations, characterized in that, include: When performing a read-after-write sequence or a write-after-read sequence on the memory under test, the DQ signal, DQS signal, clock signal and read / write command signal are collected synchronously. The end time of the last valid data bit of the previous read / write operation is taken as the end time according to the read / write command signal. Based on the DQS signal, determine the DQS sampling edge corresponding to the next read / write operation, take the time period between the end time and the DQS sampling edge as the bus release observation interval, and measure the voltage deviation of one or more DQ lines relative to the preset static level range within the bus release observation interval. The time interval between the time when the read / write command of a subsequent read / write operation is issued and the end time is used as the start interval. The start interval is changed and the voltage deviation is repeatedly measured. When the voltage deviation exceeds a preset threshold when the DQS sampling edge arrives, the corresponding DQ line, read / write switching sequence type and start interval are recorded as the test result.

2. The method according to claim 1, characterized in that, Under the same startup interval, a first test sequence and a second test sequence are executed respectively. The first test sequence includes the previous read / write operation, and the second test sequence puts the DQ line corresponding to the previous read / write operation in a non-valid data-driven state and retains the DQS sampling edge corresponding to the subsequent read / write operation. The voltage deviation of the DQ line at the arrival of the DQS sampling edge under the first test sequence and the second test sequence are obtained respectively, and the difference between the two voltage deviations is taken as the effective voltage deviation generated by the release residue of the previous read / write operation.

3. The method according to claim 1, characterized in that, The end data bit combinations of the previous read / write operation are respectively a high-level end combination and a low-level end combination, while keeping the subsequent read / write operation, the start interval, and the DQS sampling edge unchanged; the high-level end combination is the end data bit combination where the last valid data bit is high, and the low-level end combination is the end data bit combination where the last valid data bit is low; the voltage deviation direction and voltage deviation amount of the DQ line within the bus release observation interval are measured respectively, and when the voltage deviation directions corresponding to the two end data bit combinations are opposite, the voltage deviation amount is assigned to the data bit residual component.

4. The method according to claim 1, characterized in that, For the same DQ line, perform a first start interval test and a second start interval test arranged in a preset step size, with the second start interval being shorter than the first start interval. When the voltage deviation of the DQ line under the first start interval does not exceed a preset threshold, but the voltage deviation of the DQ line under the second start interval exceeds the preset threshold, maintain the second start interval and change the end data bit combination of the previous read / write operation. If the voltage deviation still exceeds the preset threshold after the change, record the second start interval as a bus release insufficiency interval. If the voltage deviation does not exceed the preset threshold after the change, use the second start interval as a candidate interval for pattern-related release insufficiency intervals.

5. The method according to claim 3, characterized in that, The high-level end combination and the low-level end combination respectively adopt the end data bit combination with opposite last bit level and one or more bits before the last bit level consistent; when the voltage deviation direction of the DQ line changes in the opposite direction with the last bit level in the bus release observation interval, the residual component of the data bit is assigned to the last bit residual component.

6. The method according to claim 3, characterized in that, While keeping the start interval and the DQS sampling edge unchanged, the high-level end combination and the low-level end combination are repeated two or more times consecutively; when the voltage deviation after repetition increases relative to the voltage deviation obtained in the first measurement, the residual component of the data bit is classified as the cumulative residual component.

7. The method according to claim 3, characterized in that, Within the bus release observation interval, a first measurement time and a second measurement time are selected. The time difference between the first measurement time and the end time of the previous read / write operation is less than a first preset time value, and the time difference between the second measurement time and the DQS sampling edge is less than a second preset time value. When the voltage deviation direction of the DQ line changes with the combination of the end data bits at the first measurement time, and maintains the corresponding directional change relationship at the second measurement time, the voltage deviation amount at the second measurement time is taken as the residual amount of the read / write operation after the intrusion.

8. The method according to claim 4, characterized in that, The end data bit combination of the previous read / write operation is switched from a single-level end combination to an alternating-level end combination; the single-level end combination is an end data bit combination in which multiple consecutive valid data bits have the same level, and the alternating-level end combination is an end data bit combination in which multiple consecutive valid data bits are arranged alternately with high and low levels; if the voltage deviation of the DQ line changes from exceeding the preset threshold to not exceeding the preset threshold after the switch, the second start interval is recorded as the code pattern related release insufficient interval.

9. The method according to claim 4, characterized in that, If the voltage deviation of the DQ line still exceeds the preset threshold after changing the end data bit combination of the previous read / write operation, the sampling determination time determined based on the DQS signal corresponding to the next read / write operation is delayed under the second start interval; if the voltage deviation after the delay does not exceed the preset threshold, the delay amount of the sampling determination time is recorded as the release residual sampling avoidance amount of the DQ line.

10. The method according to claim 9, characterized in that, Keeping the second start interval and the changed end data bit combination unchanged, the delayed sampling determination time is backed up by a backswing amount less than the release residual sampling avoidance amount; if the voltage deviation of the DQ line exceeds a preset threshold after the backswing, the time difference between the two sampling determination times before and after the backswing is recorded as the release residual edge sensitivity amount of the DQ line.

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