Fault response control in power converters

Abstract

This application relates to fault response control in power converters. An example power converter controller includes a driver (140) having a first input and a second input; a comparator (204) having a first input coupled to an output voltage feedback terminal, a second input coupled to an input voltage terminal, and an output; logic circuitry (138 and 206) having a fault input, a second input coupled to the output of the comparator, a first output coupled to the first input of the driver, and a second output coupled to the second input of the driver, the logic circuitry capable of: receiving a first signal at the fault input indicative of a fault event, and responsively providing a first control signal to the driver to disable a transistor (106) of a power converter (100); receiving a second signal from the comparator indicative that an input voltage of the power converter exceeds an output voltage of the power converter; and responsive to the first signal and the second signal, providing a second control signal to the driver to enable the transistor of the power converter.

Description

[0001] Cross-citation of related applications

[0002] This patent application claims the benefit of U.S. Provisional Patent Application No. 63 / 764,742, filed on February 28, 2025, which is hereby incorporated herein by reference in its entirety. Technical Field

[0003] This specification relates generally to power electronic components, and more specifically, to fault response control in power converters. Background Technology

[0004] A power converter is an electronic device that transforms electrical energy from one form to another, for example, by changing the voltage level, current level, or current type (alternating current (AC) to direct current (DC), DC to AC, or different frequencies). Power converters play a crucial role in optimizing power delivery and ensuring compatibility between power sources and electronic devices. Several types of power converters exist, including DC-DC converters (for battery-powered devices and electric vehicles), AC-DC converters or rectifiers (for power supplies in consumer electronics), DC-AC converters or inverters (for solar systems and uninterruptible power supplies), and AC-AC converters (for motor speed controls and frequency converters). Power converters are widely used in renewable energy systems, electric power transmission, consumer electronics, industrial automation, and telecommunications infrastructure to enable efficient energy use and system flexibility across various technologies. Summary of the Invention

[0005] For a system, method, and apparatus for fault response control in a power converter, an example power converter controller includes a driver having a first input and a second input. The power converter controller includes a comparator having a first input coupled to an output voltage feedback terminal, a second input coupled to an input voltage terminal, and an output. The power converter controller includes a logic circuit system having a fault input, a second input coupled to the output of the comparator, a first output coupled to the first input of the driver, and a second output coupled to the second input of the driver. The logic circuit system is capable of: receiving a first signal indicating a fault event at the fault input and responsively providing a first control signal to the driver to disable a transistor of the power converter; receiving a second signal from the comparator indicating that the input voltage of the power converter exceeds the output voltage of the power converter; and providing a second control signal to the driver to enable the transistor of the power converter in response to the first and second signals. Other examples are described.

[0006] For a system, method, and apparatus for fault response control in a power converter, an example power converter circuit includes a first transistor having a control terminal, a first terminal, and a second terminal. The power converter circuit includes a second transistor having a control terminal, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to a first reference voltage terminal. The power converter circuit includes a controller having a first output coupled to the control terminal of the first transistor and a second output coupled to the control terminal of the second transistor. The controller includes: a driver having a first input, a second input, a first output coupled to the control terminal of the first transistor, and a second output coupled to the control terminal of the second transistor; a control logic circuit system having a first input, a second input, a third input, a first output coupled to the first input of the driver, and a second output coupled to the second input of the driver; a fault logic circuit system having an input, a first output coupled to the first input of the control logic circuit system, and a second output coupled to the second input of the control logic circuit system; and a first comparator having a first output coupled to the input. The system comprises: a first input to the output voltage feedback terminal, a second input coupled to the input voltage terminal, and an output coupled to the input of the fault logic circuit system; a second comparator having a first input coupled to a first sensing terminal, a second input coupled to a second sensing terminal, and an output; a slope compensation circuit system having an output; a mixer having a first input coupled to the output of the second comparator, a second input coupled to the output of the slope compensation circuit system, and an output; a third comparator having a first input and a second input coupled to the output of the mixer, and an output coupled to the third input of the control logic circuit system; and an amplifier having a first input coupled to a second reference voltage terminal, a second input coupled to the output voltage feedback terminal, and an output coupled to the second input of the third comparator. Other examples are described.

[0007] For systems, methods, and apparatuses used for fault response control in power converters, one example system includes a loudspeaker with an input. The system includes an audio amplifier having an input and an output coupled to the input of the loudspeaker. The system includes: a power converter having an output coupled to the input of the audio amplifier; the power converter comprising: a first transistor having a control terminal, a first terminal, and a second terminal; a second transistor having a control terminal, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to a reference voltage terminal; an inductor having a first terminal and a second terminal, the first terminal being coupled to the second terminal of the first transistor and the first terminal of the second transistor; a driver having a first input, a second input, a first output coupled to the control terminal of the first transistor, and a second output coupled to the control terminal of the second transistor; a control logic circuit system having a first input, a second input, a first output coupled to the first input of the driver, and a second output coupled to the second input of the driver; a fault logic circuit system having an input, a first output coupled to the first input of the control logic circuit system, and a second output coupled to the second input of the control logic circuit system; and a comparator having a first input coupled to an output voltage feedback terminal, a second input coupled to an input voltage terminal, and an output coupled to the input of the fault logic circuit system. Other examples are described. Attached Figure Description

[0008] Figure 1 This is a block diagram of an example power converter that includes an example output stage and an example controller for controlling the fault response of one or more transistors of the output stage.

[0009] Figure 2 yes Figure 1 A block diagram of a power converter, which depicts... Figure 1 A first example implementation of a fault controller circuit system.

[0010] Figure 3 It is a description Figure 2 Example timing diagram of how the controller controls the fault response.

[0011] Figure 4A and 4B (collectively referred to as "Figure 4") is Figure 1 A block diagram of a power converter, wherein the controller includes Figure 2 The fault controller circuit system, example soft start switch and example selection circuit system.

[0012] Figure 5This is an example timing diagram depicting how the controller in Figure 4 controls the fault response.

[0013] Figure 6 It is a description Figure 2 Example state diagram of example operating states of controller 4.

[0014] Figure 7 This is a flowchart representing at least one of example machine-readable instructions or example operations, which can be executed, instantiated, or implemented by a programmable circuit system. Figure 2 Or a controller with 4.

[0015] Figure 8A and 8B (collectively referred to as "Figure 8") is Figure 1 A block diagram of a power converter, which depicts... Figure 1 A second example implementation of the fault controller circuit system.

[0016] Figure 9A and 9B (collectively referred to as "Figure 9") is Figure 1 A block diagram of a power converter, wherein the controller includes the fault controller circuit system of Figure 8, an example soft-start switch, and an example selection circuit system.

[0017] Figure 10 This is an example state diagram depicting the example operating states of the controller in Figure 8 or 9.

[0018] Figure 11A and 11B (collectively referred to as FIG11) is a flowchart illustrating at least one of example machine-readable instructions or example operations that can be executed, instantiated, or implemented by a programmable circuit system to implement the controller of FIG8 or 9.

[0019] Figure 12 This is a block diagram of an example system containing an example power converter.

[0020] Figure 13 This is a block diagram of an example processing platform containing a programmable circuit system, which is structured to execute, instantiate, or implement example machine-readable instructions or perform... Figure 7 Or, example operation 11, to implement Figure 1 , 2 Controllers of type 4, 8, or 9.

[0021] The drawings are not necessarily drawn to scale. Generally, one or more drawings and the same reference numerals in this specification refer to the same or similar features or parts (at least one of which are functional or structural). Detailed Implementation

[0022] Depending on the application using the power converter, various types of transistors can be used as switches in the power converter. For example, metal-oxide-semiconductor field-effect transistors (MOSFETs) provide efficient power conversion in high-voltage, high-frequency applications. Additionally, bipolar junction transistors (BJTs), for instance, offer high current carrying capacity, making them suitable for low-frequency, high-current applications. Insulated-gate bipolar transistors (IGBTs) can operate at high voltages and provide high current carrying capacity, making them suitable for high-voltage, high-current, and medium-frequency applications.

[0023] Field-effect transistors (FETs) can be based on a variety of semiconductors, such as silicon (Si) and gallium nitride (GaN). Generally, SiFETs are designed for lower voltage applications compared to GaN FETs, such as battery management, low-power DC-DC converters, and general-purpose switching, etc. When the gate-to-source voltage (V) of a Si FET... GS ) greater than the threshold voltage (V th When V GS > V th When the Si FET is enabled, it is turned on (or switched on) in the forward direction (forward bias) and conducts current. As a byproduct of the Si FET structure, the Si FET includes an intrinsic body diode that allows the Si FET to be "enabled" in the reverse direction (reverse bias) and conduct current.

[0024] GaN FETs offer increased efficiency at higher frequencies and have lower on-resistance and capacitance than Si FETs. Additionally, GaN FETs exhibit higher breakdown voltage and better thermal performance than Si FETs. Therefore, GaN FETs can be used in higher voltage applications than Si FETs, such as electric vehicle (EV) chargers, 5G base stations, and aerospace power systems, etc. When the gate-to-source voltage (V) of a GaN FET... GS ) greater than the threshold voltage (V th When V GS > V th When a GaN FET is enabled (or switched on) in the forward direction (forward bias), it conducts current. As a byproduct of the GaN FET structure, the GaN FET does not contain an intrinsic body diode and is a bidirectional conducting device. Therefore, the GaN FET can conduct current when a reverse bias is applied.

[0025] As described above, a Si FET includes an intrinsic body diode that conducts current when the Si FET is reverse biased. For example, when the source-to-drain voltage (V0) of the Si FET...SD When the voltage across the Si FET is sufficiently large to forward bias the intrinsic body diode, the Si FET is reverse biased and conducts current through the intrinsic body diode. Therefore, when the Si FET is reverse biased, the voltage across the Si FET is set by the voltage across the intrinsic body diode, which is approximately 0.7V. As described above, the GaN FET is a bidirectional conduction device, thus allowing it to conduct current when reverse biased. For example, when the gate-to-drain voltage of the GaN FET (V...) is... GD The voltage is greater than the threshold voltage (V) of the GaN FET. th When the GaN FET is enabled in the reverse direction (reverse bias applied), it conducts current.

[0026] Because GaN FETs do not contain an intrinsic body diode, the voltage across a reverse-biased GaN FET is not clamped below 1V as it would be in a reverse-biased Si FET. Instead, based on (1) the threshold voltage (V th ) and gate-to-source voltage (V GS The difference between (2) and (3) the product of the "on" resistance of the GaN FET under reverse bias and the current flowing through the GaN FET is used to set the voltage across the reverse-biased GaN FET. The "on" resistance of the GaN FET under reverse bias depends on the amount of current flowing through the GaN FET. Therefore, the voltage across the reverse-biased GaN FET (also known as the source-to-drain voltage (V)) is the difference between (2) and (3) the product of the "on" resistance of the GaN FET under reverse bias and the amount of current flowing through the GaN FET. SD The voltage varies depending on the amount of current flowing through the reverse-biased GaN FET. The voltage across the reverse-biased GaN FET can be as high as 2V.

[0027] A power converter includes a controller to monitor, control, and protect components such as transistors. For example, when a fault such as an overcurrent fault or an overtemperature fault is detected, the controller will shut down or disable the power converter (also known as the power converter circuit). Therefore, after a fault is detected, the transistors of the power converter will be disabled (or disconnected). Depending on the power converter's architecture, when disabled, the output voltage from the power converter may drop below the input voltage. As a result, one or more transistors of the power converter may be reverse-biased. For example, when a boost converter is disabled, the inductor of the boost converter discharges, pulling the output voltage from the power converter below the input voltage. Because the output voltage of the boost converter is less than the input voltage, the high-side transistors of the boost converter are reverse-biased.

[0028] When faults such as overcurrent or overtemperature faults occur, the load current in the power converter may be several amperes (A) (e.g., tens of amperes). Therefore, depending on the type of transistor used in the boost converter, deactivating the transistors in response to the fault may expose them to potentially damaging conditions. For example, in the case of a boost converter using a GaN FET, the GaN FET may be subjected to damaging conditions when deactivated. However, a Si FET may not be subjected to damaging conditions when deactivated. That is, the relatively large voltage drop across a reverse-biased GaN FET and the large current flowing through it may cause it to dissipate a significant amount of power, potentially damaging the device (e.g., 2V * 10A = 20 watts). Because the intrinsic body diode of a Si FET has a relatively low voltage drop (e.g., 0.7V < 2V), the Si FET may not experience such large power dissipation.

[0029] To avoid damaging the reverse-biased GaN FET, when the gate-to-drain voltage (V) of the GaN FET... GD When approaching a condition that could potentially reverse-bias a GaN FET, the examples described herein enable the GaN FET in the forward direction. For example, in a boost converter, the examples described herein enable the high-side GaN FET in the forward direction in response to the output voltage of the boost converter falling below the input voltage of the boost converter. Consequently, the voltage across the GaN FET is much lower than when reverse-biased, and even with a considerable load current, the power dissipated by the GaN FET is not at a level that could damage the GaN FET.

[0030] The examples described herein also distinguish between faults related to the control of the GaN FET and faults related to the internal supply of the controller. For example, when a fault such as an over-temperature fault occurs, the examples described herein compare the supply voltage with a reference voltage to determine whether the supply voltage is lower than the reference voltage (indicating a supply fault). In this way, the examples described herein can determine whether a fault such as an over-temperature fault is caused by, for example, improper operation of the supply circuitry or improper operation of the power converter.

[0031] Additionally, after fault clearing, the example described herein sets the slew rate for starting the power converter by clamping the soft-start pin of the power converter's controller to a voltage level equal to the feedback voltage to the controller. In the example described herein, the feedback voltage tracks the input voltage of the power converter when the high-side GaNFET of the power converter is enabled during a fault condition. In this way, the example described herein provides a smooth return to the target voltage after fault clearing in the power converter and limits the input current to the power converter to the target level.

[0032] Figure 1 This is a block diagram of an example power converter 100, including an example output stage 102 and an example controller 104 for controlling the fault response of one or more transistors of the output stage 102. Figure 1 In this example, output stage 102 includes an example high-side FET 106 (e.g., a GaN FET), an example low-side FET 108 (e.g., a GaN FET), an example inductor 110, and a first example resistor 112. Additionally, power converter 100 receives an input voltage (V) at example input voltage terminal 114. 输入 ), and provides an output voltage (V) at example output voltage terminal 116. 输出 For example, input voltage (V) 输入 The power is supplied by a DC power supply such as a battery, and the output voltage (V) 输出 It is supplied to loads such as audio amplifiers. Figure 1 In this example, the input voltage (V) is measured relative to the reference voltage at the first example reference voltage terminal 118 (GND). 输入 ) and output voltage (V 输出 For example, reference voltage terminal 118 is a ground terminal.

[0033] exist Figure 1 In the illustrated example, the high-side FET 106 and the low-side FET 108 are each implemented as a GaN FET. Figure 1 In this example, the high-side FET 106 and the low-side FET 108 each have a control terminal, a first terminal, and a second terminal. For instance, the control terminal is the gate, the first terminal is the drain, and the second terminal is the source. Figure 1 In this example, the control terminal of the high-side FET 106 is coupled to the first output of the controller 104, and the first terminal of the high-side FET 106 is coupled to the output voltage terminal 116. Additionally, the second terminal of the high-side FET 106 is coupled to the first terminal of the low-side FET 108 and the first terminal of the inductor 110.

[0034] exist Figure 1In the illustrated example, the control terminal of the low-side FET 108 is coupled to the second output of the controller 104, and the first terminal of the low-side FET 108 is coupled to the second terminal of the high-side FET 106 and the first terminal of the inductor 110. Additionally, the second terminal of the low-side FET 108 is coupled to the reference voltage terminal 118. As described above, the inductor 110 has a first terminal coupled to the second terminal of the high-side FET 106 and the first terminal of the low-side FET 108. The inductor 110 also has a second terminal coupled to the first terminal of the resistor 112.

[0035] exist Figure 1 In the illustrated example, the first terminal of resistor 112 is coupled to the second terminal of inductor 110 and the second input of controller 104. Additionally, resistor 112 has a second terminal coupled to the first input of controller 104 and the input voltage terminal 114. Figure 1 In this example, controller 104 also has a third input coupled to input voltage terminal 114 and a fourth input coupled to output voltage terminal 116. For instance, controller 104 receives an input voltage (V) at its third input. 输入 ), and receives the output voltage (V) at the fourth input of the controller 104. 输出 In the examples described herein, the fourth input of controller 104 is also referred to as the feedback pin, feedback terminal, or output voltage feedback terminal of controller 104. In some instances, controller 104 receives the input voltage (V) received at input voltage terminal 114. 输入 Different input voltages. In additional or alternative instances, controller 104 has one or more additional inputs or one or more additional outputs.

[0036] exist Figure 1 In the illustrated example, controller 104 also has a tuning terminal (T) coupled to a first terminal of example compensation network 120. For example, compensation network 120 stabilizes the feedback loop implemented by controller 104 and may include one or more capacitors or other elements. Figure 1 The example compensation network 120 also has a second terminal coupled to the reference voltage terminal 118. Figure 1 In some instances, controller 104 is implemented within an integrated circuit (IC), while output stage 102 and compensation network 120 are implemented externally to the IC. In some instances, one or more components of output stage 102 or compensation network 120 (e.g., high-side FET 106 and low-side FET 108) are implemented in the same package as controller 104 or on the same IC. In some instances, controller 104 is referred to as a power converter controller.

[0037] There are various power converters, including boost converters, buck converters, buck-boost converters, inverters, rectifiers, half-bridge converters, and full-bridge converters. Figure 1 In this example, the power converter 100 is a boost converter that steps up or increases the input voltage (V) at the input voltage terminal 114. 输入 In some instances, power converter 100 is another type of power converter, such as a DC-AC inverter containing a half-bridge. Generally, power converters can be used in a variety of applications. For example, boost converters are used in battery-powered devices to step up voltage, in solar systems to match panel output voltage, and in light-emitting diode (LED) drivers to maintain brightness.

[0038] Other applications of power converters include converting AC power to DC power for use in power supplies. For example, AC-to-DC conversion can be used in power supplies for computers, mobile devices, embedded systems, and industrial equipment. Power converters can also be used to reduce voltage in power supplies (e.g., for downstream components) and to invert DC power to AC power in solar power supplies and uninterruptible power supplies (UPS). Other applications of power converters include motor control, motor drives, induction heating, and audio amplifiers.

[0039] exist Figure 1 In the illustrated example, controller 104 includes a first example amplifier 122, an example mixer 124, an example slope compensation circuit system 126, a second example amplifier 128, and a third example amplifier 130. Figure 1 The example controller 104 also includes an example voltage divider 132, which includes a second example resistor 134 and a third example resistor 136. Figure 1 In this example, controller 104 includes example control logic circuitry system 138 (also known as gate control logic circuitry system), example driver 140, and example voltage regulator 142. Figure 1 The example controller 104 also includes an example fault controller circuitry 144 to control the output stage 102 in response to the detection of a fault event. In some instances, one or more components of the controller 104 (e.g., voltage divider 132 and voltage regulator 142) are implemented externally to the controller 104 IC. The voltage regulator 142 may be, for example, a low-dropout regulator and is an example of a voltage supply circuit.

[0040] exist Figure 1 In the illustrated example, amplifier 122 is a current-sensing amplifier (also called a current sensor) that monitors the current through resistor 112 and indicates the current through inductor 110. Figure 1In one example, the first input of amplifier 122 is coupled to the second terminal of resistor 112, and the second input of amplifier 122 is coupled to the first terminal of resistor 112. For example, the first input of amplifier 122 is coupled to the second terminal of resistor 112 via the first input of controller 104, and the second input of amplifier 122 is coupled to the first terminal of resistor 112 via the second input of controller 104. Thus, in some examples, the first and second inputs of controller 104 are referred to as the first sensing terminal and the second sensing terminal, respectively. Additionally, the output of amplifier 122 is coupled to the first input of mixer 124. In some examples, amplifier 122 has one or more additional outputs. Figure 1 In this example, mixer 124 mixes the slope-shifted signal provided by slope compensation circuitry 126 with the sensed current signal provided by amplifier 122. For instance, the slope-shifted signal provided by slope compensation circuitry 126 mitigates subharmonic oscillations in the current through inductor 110.

[0041] As described above, the first input of mixer 124 is coupled to the output of amplifier 122. Additionally, Figure 1 The example mixer 124 has a second input coupled to the output of the slope compensation circuit system 126 and an output coupled to the first input of the amplifier 128. Figure 1 In this example, mixer 124 provides a slope-compensated sensed current signal to the first input of amplifier 128. Therefore, in some instances, the output of mixer 124 is referred to as the sense terminal. As described above, the first input of amplifier 128 is coupled to the output of mixer 124. Figure 1 In one example, amplifier 128 also has an output coupled to amplifier 130 and a second input coupled to the first terminal of compensation network 120. Figure 1 The example amplifier 128 also has an output coupled to a third input of the control logic circuitry system 138. In some instances, the output of amplifier 128 is referred to as a control output. Figure 1 In one example, amplifier 128 is a pulse width modulation (PWM) comparator that compares a slope-compensated sensed current signal from mixer 124 with an error signal from amplifier 130.

[0042] exist Figure 1 In the illustrated example, amplifier 130 is an error amplifier that receives the feedback voltage (V) from voltage divider 132. 反馈 ) and the reference voltage (V) at the second example reference voltage terminal 146 参考The comparison is performed. For example, the first input of amplifier 130 is coupled to reference voltage terminal 146, and the second input of amplifier 130 is coupled to the second terminal of resistor 134 and the first terminal of resistor 136. Thus, in some instances, the first input of amplifier 130 is referred to as the reference input. Additionally, in some instances, the second input of amplifier 130 is referred to as the feedback input.

[0043] exist Figure 1 In the example described, the reference voltage (V) 参考 The target voltage is provided by the power converter 100 at the output voltage terminal 116. Based on this comparison, the amplifier 130 provides an error signal to the amplifier 128. For example, the output of the amplifier 130 is coupled to the second input of the amplifier 128 and the first terminal of the compensation network 120. Thus, in some instances, the output of the amplifier 130 is referred to as the control output.

[0044] exist Figure 1 In the illustrated example, voltage divider 132 includes resistors 134 and 136 as described above. For example, a first terminal of resistor 134 is coupled to output voltage terminal 116, and a second terminal of resistor 134 is coupled to the first terminal of resistor 136. As described above, the second terminal of resistor 134 is also coupled to the second input of amplifier 130. Figure 1 In this example, the first terminal of resistor 136 is coupled to the second terminal of resistor 134 and the second input of amplifier 130. Additionally, the second terminal of resistor 136 is coupled to reference voltage terminal 118.

[0045] As described above, amplifier 128 is a PWM comparator that compares the slope-compensated sensed current signal from mixer 124 with an error signal provided by amplifier 130. Based on this comparison, amplifier 128 generates a PWM signal and provides the PWM signal to control logic circuitry system 138. The PWM signal is used to control the switching of high-side FET 106 and low-side FET 108 to generate an output signal V. 输出 In response to the PWM signal, the control logic circuit system 138 generates a control signal and provides the control signal to the driver 140. Figure 1 In one example, the control logic circuit system 138 has a first input coupled to a first output of the fault controller circuit system 144 and a second input coupled to a second output of the fault controller circuit system 144. As described above, a third input of the control logic circuit system 138 is coupled to the output of the amplifier 128.

[0046] exist Figure 1In the illustrated example, the first output of the control logic circuit system 138 is coupled to the first input of the driver 140, and the second output of the control logic circuit system 138 is coupled to the second input of the driver 140. In some examples, the first and second outputs of the control logic circuit system 138 are referred to as the first driver output and the second driver output, respectively. Additionally, in some examples, the first, second, and third inputs of the control logic circuit system 138 are referred to as the first control input, the second control input, and the third control input, respectively.

[0047] exist Figure 1 In the illustrated example, the supply terminal of driver 140 is coupled to the output of voltage regulator 142. For example, the input of voltage regulator 142 is coupled to the input voltage terminal 114 of power converter 100 to receive the input voltage (V). 输入 Based on input voltage (V) 输入 Voltage regulator 142 provides a supply voltage to driver 140 at the supply terminal. In some instances, the output of voltage regulator 142 is referred to as the supply output or supply voltage terminal, and the supply terminal of driver 140 is referred to as the supply input. As described above, a first input of driver 140 is coupled to a first output of control logic circuitry system 138, and a second input of driver 140 is coupled to a second output of control logic circuitry system 138. Thus, in some instances, the first input and the second input of driver 140 are referred to as the first control input and the second control input, respectively.

[0048] exist Figure 1 In the illustrated example, in response to a control signal provided by the control logic circuitry system 138, the driver 140 controls at least one of the high-side FET 106 or the low-side FET 108. For example, a first output of the driver 140 is coupled to a control terminal of the high-side FET 106, and a second output of the driver 140 is coupled to a control terminal of the low-side FET 108. Thus, in some embodiments, the first output and the second output of the driver 140 are referred to as a first transistor output and a second transistor output, respectively.

[0049] As described above, amplifier 128 is a PWM comparator that provides the PWM signal to control logic circuitry system 138. PWM is a widely used control technique in power converters, particularly DC-DC and DC-AC power converters. For example, controller 104 regulates the output voltage (V) of output stage 102 by enabling and disabling (referred to as switching) the high-side FET 106 and low-side FET 108 at a high frequency and adjusting the duty cycle to control the electrical force delivered to the load. 输出(and current). In the examples described in this paper, duty cycle refers to the ratio of the "on" time of the switching cycle to the total cycle time.

[0050] exist Figure 1 In the illustrated example, a first output of the fault controller circuit system 144 is coupled to a first input of the control logic circuit system 138, and a second output of the fault controller circuit system 144 is coupled to a second input of the control logic circuit system 138. In some examples, the fault controller circuit system 144 has one or more inputs or one or more additional outputs. In the described example, the fault controller circuit system 144 protects one or more of the high-side FET 106 or the low-side FET 108 in response to detecting a fault event. For example, the fault controller circuit system 144 monitors the state of the power converter 100, monitors for overcurrent events, or monitors for overtemperature events.

[0051] In response to a detected fault event, the fault controller circuitry 144 provides a fault signal to the control logic circuitry 138. In response to the fault signal, the control logic circuitry 138 provides a first control signal to the driver 140. In response to the first control signal, the driver 140 disables the high-side FET 106 and the low-side FET 108. As described above, when the high-side FET 106 and the low-side FET 108 are disabled, the output voltage (Vboost converter) from the power converter 100 (boost converter) decreases. 输出 The voltage can be reduced to the input voltage (V) of the power converter 100. 输入 Below ) . If the output voltage (V 输出 The voltage drops to the input voltage (V) 输入 If the voltage is below a certain value, the high-side FET 106 will be reverse biased, which may damage the high-side FET 106.

[0052] Therefore, the fault controller circuit system 144 monitors the output voltage (V) from the power converter 100. 输出 ) and the input voltage (V) to the power converter 100 输入 ). Response to output voltage (V) 输出 Less than the input voltage (V) 输入 The fault controller circuitry 144 provides a fault bypass signal to the control logic circuitry 138. In response to the fault bypass signal, the control logic circuitry 138 provides a second control signal to the driver 140. In response to the second control signal, the driver 140 enables the high-side FET 106 in the forward direction. Consequently, the voltage across the high-side FET 106 is much lower than when reverse biased, and even with a considerable load current, the power dissipated by the high-side FET 106 is not at a level that could damage it.

[0053] Although the fault controller circuit system 144, or more generally, Figure 1 The controller 104 is implemented in the boost converter to protect the GaN FET, but the fault controller circuitry 144, or more generally, the controller 104, is not limited to the boost converter. Generally, the fault controller circuitry 144 can be implemented in a variety of applications, such as power converters and motor drives. In additional or alternative instances, the fault controller circuitry 144 is integrated in the same package as the GaN FET to protect it.

[0054] exist Figure 1 In this example, the high-side FET 106 and the low-side FET 108 can be depletion-mode devices and enhancement-mode devices, respectively. Furthermore, the high-side FET 106 and the low-side FET 108 can be implemented in / above a gallium-based substrate, such as a GaN substrate or a gallium arsenide (GaAs) substrate. Other embodiments of the high-side FET 106 and the low-side FET 108 are possible. For example, the high-side FET 106 and the low-side FET 108 can be implemented in / above a non-gallium-based substrate, such as a silicon (Si) substrate, a silicon carbide (SiC) substrate, or a diamond substrate.

[0055] Figure 2 yes Figure 1 A block diagram of a power converter 100, which depicts... Figure 1 A first example implementation of the fault controller circuit system 144. Figure 2 The example fault controller circuit system 144 includes an example temperature sensor 202, an example amplifier 204, and an example fault logic circuit system 206. Figure 2 In this example, the temperature sensor 202 has an output, the amplifier 204 has a first input, a second input, and an output, and the fault logic circuit system 206 has a first input, a second input, a third input, a first output, and a second output. Additionally, in Figure 2 In this example, amplifier 122 has a first output and a second output. For instance, the first output of amplifier 122 is coupled to the first input of mixer 124.

[0056] exist Figure 2 In the illustrated example, the output of temperature sensor 202 is coupled to the first input of fault logic circuit system 206. Figure 2 In this example, the first input of amplifier 204 is coupled to the input voltage terminal 114 of power converter 100. For instance, amplifier 204 receives the input voltage (V) of power converter 100 at its first input. 输入 ).exist Figure 2In this example, the second input of amplifier 204 is coupled to the output voltage terminal 116 of power converter 100. For instance, amplifier 204 receives the output voltage (V) from power converter 100 at its second input. 输出 Additionally, the output of amplifier 204 is coupled to the third input of fault logic circuit system 206.

[0057] exist Figure 2 In the illustrated example, the first input of the fault logic circuit system 206 is coupled to the output of the temperature sensor 202. Figure 2 In this example, the second input of the fault logic circuit system 206 is coupled to the second output of amplifier 122. Additionally, the third input of the fault logic circuit system 206 is coupled to the output of amplifier 204, as described above. Figure 2 In this example, the first output of the fault logic circuit system 206 is coupled to the first input of the control logic circuit system 138. Additionally, the second output of the fault logic circuit system 206 is coupled to the second input of the control logic circuit system 138.

[0058] exist Figure 2 In the illustrated example, the temperature sensor 202 is implemented by a circuit system containing semiconductor devices such as BJTs. For example, the base-to-emitter voltage (V) of the BJT... BE The base-to-emitter voltage (V) of the BJT changes predictably with temperature. Therefore, by monitoring the base-to-emitter voltage (V) of the BJT... BE Temperature sensor 202 can monitor the temperature of the circuit in which the BJT is implemented. Figure 2 In one example, the circuit is a power converter 100. If the temperature of the power converter 100 exceeds a temperature threshold (indicating an over-temperature fault), the temperature sensor 202 provides a sensor signal to the fault logic circuit system 206. For example, in response to a fault, the temperature sensor 202 asserts the sensor signal. Thus, in some instances, the temperature sensor 202 is referred to as an over-temperature detection circuit system. Additionally, in some instances, the sensor signal provided by the temperature sensor 202 is referred to as a fault signal because the sensor signal indicates a fault event has occurred.

[0059] In the examples described herein, a signal is asserted when it is in an active state. In the examples described herein, the active state of a signal is the logic value at which the signal conveys the presence of a particular state. For example, a sensor signal from temperature sensor 202 is active when a sensor signal conveys the presence of a temperature fault. Additionally, a signal can be reasserted without first retracting the assertion. For example, if the temperature of power converter 100 continuously exceeds a temperature threshold, temperature sensor 202 continuously asserts the sensor signal. In the examples described herein, asserting a signal does not necessarily imply that the signal has a logic high value. For example, an active high signal is asserted when the signal's logic value is high, and an active low signal is asserted when the signal's logic value is low.

[0060] In the examples described herein, an assertion of a signal is withdrawn when the signal is in an inactive state. In these examples, the inactive state of a signal is the logic value at which the signal conveys the absence of a particular state. For example, the sensor signal from temperature sensor 202 is in an inactive state when the sensor signal conveys the absence of a temperature fault. Furthermore, an assertion of a signal that has been withdrawn can be re-withheld without initially asserting it. For example, if the temperature of the power converter 100 remains below a temperature threshold, temperature sensor 202 continuously withdraws its assertion of the sensor signal. In the examples described herein, a signal being withdrawn from an assertion does not necessarily imply that the signal has a logic low value. For example, an assertion of an active high signal is withdrawn when the signal's logic value is low, and an assertion of an active low signal is withdrawn when the signal's logic value is high.

[0061] exist Figure 2 In the illustrated example, amplifier 122 is implemented by a circuit system including one or more operational amplifiers (op-amps). As described above, amplifier 122 monitors the current through resistor 112 and provides the sensed current signal to mixer 124. Amplifier 122 also compares the sensed current to a current threshold. If the sensed current through resistor 112 exceeds the current threshold (indicating an overcurrent fault), amplifier 122 provides a sensor signal to fault logic circuit system 206. For example, in response to a fault, amplifier 122 asserts the sensor signal. Thus, in some instances, amplifier 122 is referred to as an overcurrent detection circuit system or an overcurrent comparator. Additionally, in some instances, the sensor signal provided by amplifier 122 is referred to as a fault signal because the sensor signal indicates a fault event has occurred. In additional or alternative instances, controller 104 or fault logic circuit system 206 includes one or more additional sensors to monitor one or more additional or alternative faults, such as overvoltage faults or undervoltage faults, etc.

[0062] As described above, when a fault appears in the power converter 100, the sensors monitoring the fault (temperature sensor 202, amplifier 122, etc.) provide sensor signals to the fault logic circuit system 206. Figure 2 In this example, the fault logic circuit system 206 is implemented by a programmable circuit system as described herein. As described above, a first input of the fault logic circuit system 206 is coupled to the output of the temperature sensor 202, and a second input of the fault logic circuit system 206 is coupled to the second output of the amplifier 122. Thus, in some instances, the first and second inputs of the fault logic circuit system 206 are referred to as a first sensor input and a second sensor input, respectively. In some instances, the first and second inputs of the fault logic circuit system 206 are referred to as a first fault input and a second fault input, respectively.

[0063] exist Figure 2 In the illustrated example, in response to a sensor signal, fault logic circuitry system 206 provides a fault signal to control logic circuitry system 138. For example, in response to an asserted sensor signal, fault logic circuitry system 206 asserts a fault signal and provides the fault signal via a first output of fault logic circuitry system 206. Thus, in some instances, the first output of fault logic circuitry system 206 is referred to as a fault output. In response to the fault signal, control logic circuitry system 138 provides a first control signal to driver 140. For example, in response to the asserted fault signal, control logic circuitry system 138 cancels the assertion of the first control signal. In response to the first control signal, driver 140 disables high-side FET 106 and low-side FET 108.

[0064] In the examples described herein, the transistor is disabled when the control voltage is at a level that does not cause the transistor to conduct current. For example, the transistor is disabled when it is in off-mode operation. In the examples described herein, the transistor is enabled when the control voltage is at a level that causes the transistor to conduct current. For example, the transistor is enabled when it is in linear or saturation mode operation. In the examples described herein, the control voltage used to forward bias the negative-channel (N-channel) Si FET is the gate-to-source voltage (V0). GS The control voltage used to forward bias a positive-channel (P-channel) Si FET is the voltage from the source to the gate (V0). SG The control voltage used to forward bias the GaN FET is the gate-to-source voltage (V). GS The control voltage used to reverse bias the GaN FET is the gate-to-drain voltage (V). GD ).

[0065] exist Figure 2 In the illustrated example, amplifier 204 is implemented by a circuit system comprising one or more operational amplifiers. Figure 2 In this example, the first input of amplifier 204 is a non-inverting input, and the second input of amplifier 204 is an inverting input. As described above, the first input of amplifier 204 is coupled to the input voltage terminal 114 of power converter 100, and the second input of amplifier 204 is coupled to the output voltage terminal 116 of power converter 100. Thus, in some examples, the first input and the second input of amplifier 204 are referred to as the first power converter input and the second power converter input, respectively.

[0066] exist Figure 2 In the illustrated example, amplifier 204 is a transistor-protected comparator that compares the input voltage at the input of the first power converter with the output voltage at the input of the second power converter. Figure 2 In one example, amplifier 204 provides a transistor protection signal to the third input of fault logic circuit system 206 based on a comparison. Therefore, in some instances, the output of amplifier 204 is referred to as a control output. Figure 2 In the example, if the input voltage (V) 输入 ) is greater than or equal to the output voltage (V) 输出 If the output voltage (V) is not specified, then amplifier 204 asserts the transistor protection signal. In other words, if the output voltage (V) is not specified, then the transistor protection signal is not specified. 输出 ) less than or equal to the input voltage (V) 输入 If the input voltage (V) is true, then amplifier 204 asserts the transistor protection signal. Otherwise, if the input voltage (V) is true, then the transistor protection signal is true. 输入 () less than the output voltage (V) 输出 If the output voltage (V) is not specified, amplifier 204 will cancel the assertion transistor protection signal. In other words, if the output voltage (V) is not specified, amplifier 204 will cancel the assertion transistor protection signal. 输出 ) greater than the input voltage (V 输入 If the amplifier 204 cancels the assertion transistor protection signal, then the amplifier 204 will cancel the assertion transistor protection signal.

[0067] As described above, the third input of the fault logic circuit system 206 is coupled to the output of amplifier 204. Therefore, in some instances, the third input of the fault logic circuit system 206 is referred to as the transistor protection input. Figure 2 In one example, in response to a transistor protection signal, the fault logic circuit system 206 provides a fault bypass signal to the control logic circuit system 138. For instance, in response to an asserted transistor protection signal, the fault logic circuit system 206 asserts a fault bypass signal and provides the fault bypass signal at a second output of the fault logic circuit system 206. Thus, in some instances, the second output of the fault logic circuit system 206 is referred to as a fault bypass output.

[0068] In response to a fault bypass signal, control logic system 138 provides a second control signal to driver 140. For example, in response to an asserted fault bypass signal, control logic system 138 asserts the second control signal. In response to the second control signal, driver 140 enables high-side FET 106 in the positive direction. Thus, even if the output voltage (V) from power converter 100... 输出 The voltage is less than the input voltage (V) of the power converter 100. 输入 The high-side FET 106 will not be reverse biased. Therefore, the high-side FET 106 will not dissipate power to a level that could damage the high-side FET 106.

[0069] exist Figure 2 In the illustrated example, in response to fault clearing, the sensor signal provided to the fault logic circuit system 206 by the sensor monitoring fault is withdrawn from the assertion. For example, in response to over-temperature fault clearing (the temperature of the power converter 100 drops below a temperature threshold), the temperature sensor 202 withdraws the assertion provided to the sensor signal of the fault logic circuit system 206. Additionally, for example, in response to overcurrent fault clearing (the current through resistor 112 drops below a current threshold), the amplifier 122 withdraws the assertion provided to the sensor signal of the fault logic circuit system 206.

[0070] exist Figure 2 In the illustrated example, in response to the revoked assertion of the sensor signal, the fault logic circuit system 206 revoks the assertion of the fault signal and the fault bypass signal. Figure 2 In this example, in response to a revoked assertion fault signal and a revoked assertion fault bypass signal, the control logic circuitry 138 revoks the assertion to the second control signal of the driver 140. In response to the revoked assertion of the second control signal, the driver 140 disables the high-side FET 106. Thus, the power converter 100 can return to normal operation as specified by the feedback loop and the PWM control implemented by the controller 104.

[0071] As described above, in the event that the high-side FET 106 is deactivated in response to an exhibited fault, the fault controller circuitry 144 protects the high-side FET 106. Example faults include over-temperature and over-current faults, as well as overvoltage and undervoltage faults. In some instances, the fault controller circuitry 144 deactivates the high-side FET 106 in response to more than one fault, or more generally, deactivates the power converter 100. For example, an overcurrent fault (sensed by amplifier 122) may cause the temperature of the power converter 100 to rise and induce an overheat fault (sensed by temperature sensor 202). An overvoltage fault may also induce an overtemperature fault. Thus, the fault controller circuitry 144 protects the high-side FET 106 in response to multiple faults, individually or in combination.

[0072] Figure 3 It is a description Figure 2 Example timing diagram 300 showing how controller 104 controls fault response. Figure 3 In this example, timing diagram 300 includes a first example diagram 302, a second example diagram 304, and a third example diagram 306. Diagram 302 depicts the output voltage (V) from the power converter 100 in volts to time. 输出 The first example curve 308 and the input voltage (V) to the power converter 100 输入 The second example curve 310 is shown in Figure 304. Additionally, the third example curve 312 depicts the fault signal provided by the fault logic circuit system 206 in binary time. The fourth example curve 314 depicts the fault bypass signal provided by the fault logic circuit system 206 in binary time.

[0073] exist Figure 3 In the illustrated example, before the first example time 316 (t1), the controller 104 is in normal operating condition. For example, before time 316 (t1), the controller 104 adjusts the high-side FET 106 and the low-side FET 108 based on the reference voltage (V) at the reference voltage terminal 146. 参考 The input voltage (V) 输入 Step up to target output voltage (V) 输出 At time 316 (t1), controller 104 detects a fault and disables high-side FET 106 and low-side FET 108. For example, if temperature sensor 202 detects that the temperature of power converter 100 exceeds a temperature threshold, temperature sensor 202 asserts a sensor signal. In response to the asserted sensor signal, fault logic circuitry system 206 asserts a fault signal (graph 312), which causes controller 104 to disable high-side FET 106 and low-side FET 108.

[0074] For example, in response to an asserted fault signal, control logic circuitry 138 cancels the assertion of the first control signal. In response to the canceled assertion of the first control signal, driver 140 disables the high-side FET 106 and the low-side FET 108. Consequently, after time 316 (t1), the output voltage (V) from the power converter 100... 输出 (Curve 308) begins to decrease. As described above, amplifier 204 continuously monitors the output voltage (V) 输出 (Graph 308) and input voltage (V) 输入 (Graph 310). At the second example time 318 (t2), the controller 104 detects the output voltage (V). 输出 Less than the input voltage (V) 输入 And enable the high-side FET 106. For example, if amplifier 204 detects an output voltage (V... 输出 Less than the input voltage (V) 输入 If the transistor protection signal is asserted, then amplifier 204 asserts the transistor protection signal. In response to the asserted transistor protection signal, fault logic circuit system 206 asserts a fault bypass signal (Figure 314), which causes controller 104 to enable high-side FET 106.

[0075] For example, in response to the asserted fault bypass signal, control logic circuitry 138 asserts a second control signal. In response to the asserted second control signal, driver 140 enables high-side FET 106. Thus, after time 318 (t2), high-side FET 106 is enabled, and the output voltage (V... 输出 (Curve 308) is approximately equal to the input voltage (V) 输入 (Graph 310). Therefore, controller 104 ensures that the voltage drop across the high-side FET 106 is limited by the "on" resistance of the high-side FET 106, and is therefore much lower than the reverse bias voltage drop across the high-side FET 106. For example, if the "on" resistance of the high-side FET 106 is five milliohms (R... DS =5 mΩ) and the load current is 10A (I 负载 = 10A), then the power dissipated by the high-side FET 106 is 500 milliwatts (P = R). DS *I 负载 = 500 mW), which is much smaller than the 20 watts that the high-side FET 106 will dissipate when reverse biased.

[0076] exist Figure 3In the illustrated example, at the third example time 320 (t3), controller 104 detects that the fault has been cleared. For example, temperature sensor 202 detects that the temperature of power converter 100 is below a temperature threshold and cancels the assertion of the sensor signal. In response to the canceled assertion of the sensor signal, fault logic circuitry system 206 cancels the assertion of the fault signal (graph 312) and the fault bypass signal (graph 314). In response to the canceled assertion of the fault signal and the canceled assertion of the fault bypass signal, control logic circuitry system 138 cancels the assertion of the second control signal. In response to the canceled assertion of the second control signal, driver 140 deactivates the high-side FET 106. Thus, controller 104 can return to normal operation after time 320 (t3). For example, after time 320 (t3), controller 104 adjusts the high-side FET 106 and the low-side FET 108 based on the reference voltage (V) at reference voltage terminal 146. 参考 The input voltage (V) 输入 Step up to target output voltage (V) 输出 ).

[0077] Figure 4 is Figure 1 A block diagram of a power converter 100, wherein the controller 104 includes Figure 2 The fault controller circuit system 144, the example soft-start switch 402, and the example selection circuit system 404 are shown in Figure 4. In the example of Figure 4, the power converter 100 also includes an example capacitor 406. Additionally, in the example of Figure 4, the soft-start switch 402 has a control terminal, a first terminal, a second terminal, and a third terminal. The example selection circuit system 404 of Figure 4 has a first input, a second input, and an output. In the example of Figure 4, the capacitor 406 has a first terminal and a second terminal.

[0078] In the example illustrated in Figure 4, the control terminal of the soft-start switch 402 is coupled to the first output of the fault logic circuit system 206. In the example of Figure 4, the first terminal of the soft-start switch 402 is coupled to the example supply voltage terminal 408. For example, the soft-start switch 402 receives the supply voltage (V) at the first terminal. 供应 Therefore, in some instances, the first terminal of the soft-start switch 402 is referred to as the supply input. In the example of Figure 4, the supply voltage terminal 408 is the output of the voltage regulator 142. In additional or alternative instances, the first terminal of the soft-start switch 402 receives another voltage from another terminal.

[0079] In the example illustrated in Figure 4, the second terminal of the soft-start switch 402 is coupled to the second terminal of resistor 134, the first terminal of resistor 136, and the second input of amplifier 130. For example, the soft-start switch 402 is coupled to the feedback input of amplifier 130 and receives the feedback voltage (V).反馈 In the example of Figure 4, the third terminal of the soft-start switch 402 is coupled to the second input of the selection circuit system 404 and the first terminal of the capacitor 406. For example, the connection between the third terminal of the soft-start switch 402 and the second input of the selection circuit system 404 corresponds to the soft-start terminal (SS) of the controller 104, which is also referred to as the soft-start pin of the controller 104 in the example described herein.

[0080] In the example illustrated in Figure 4, the first input of the selection circuit system 404 is coupled to the reference voltage terminal 146. For example, the selection circuit system 404 receives the reference voltage (V) at the first input. 参考 Therefore, in some instances, the first input of the selection circuit system 404 is referred to as the reference input. In the example of Figure 4, the second input of the selection circuit system 404 is coupled to the third terminal of the soft-start switch 402 and the first terminal of the capacitor 406. Therefore, in some instances, the second input of the selection circuit system 404 is referred to as the soft-start input.

[0081] In the example illustrated in Figure 4, the output of the selection circuit system 404 is coupled to the first input of the amplifier 130. In some examples, the output of the selection circuit system 404 is referred to as the selection output. In the example of Figure 4, the first terminal of the capacitor 406 is coupled to the third terminal of the soft-start switch 402. The first terminal of the capacitor 406 is also coupled to the second input of the selection circuit system 404. In the example of Figure 4, the second terminal of the capacitor 406 is coupled to the reference voltage terminal 118.

[0082] In the example illustrated in Figure 4, when a fault appears in the power converter 100, sensors monitoring the fault (temperature sensor 202, amplifier 122, etc.) provide sensor signals to the fault logic circuit system 206. In the example of Figure 4, in response to the sensor signals, the fault logic circuit system 206 provides a fault signal to the control logic circuit system 138. For example, in response to the asserted sensor signal, the fault logic circuit system 206 asserts a fault signal and provides the fault signal to the control logic circuit system 138 and the soft-start switch 402. In response to the fault signal, the control logic circuit system 138 provides a first control signal to the driver 140. For example, in response to the asserted fault signal, the control logic circuit system 138 cancels the assertion of the first control signal. In response to the first control signal, the driver 140 disables the high-side FET 106 and the low-side FET 108.

[0083] In the example illustrated in Figure 4, the soft-start switch 402 is implemented by a semiconductor device comprising one or more transistors. For example, the soft-start switch 402 is implemented by a single-pole double-throw (SPDT) switch, which causes the third terminal of the soft-start switch 402 to be supplied with a voltage (V) at the first terminal of the soft-start switch 402. 供应 ) and the feedback voltage (V) at the second terminal of the soft start switch 402 反馈 The soft-start switch 402 switches between two states. In some instances, the soft-start switch 402 is referred to as a logic circuit system or a switch logic circuit system. As described above, the soft-start switch 402 receives a fault signal at its control terminal. When the fault signal is revoked, the soft-start switch 402 couples the second input of the selection circuit system 404 to the supply voltage (V). 供应 For example, when the fault signal is revoked, the soft-start switch 402 couples the second input of the selection circuit system 404 to the supply voltage terminal 408.

[0084] In the example illustrated in Figure 4, in response to the asserted fault signal, the soft-start switch 402 is dual-state switched, and the second input of the selection circuit system 404 is coupled to the feedback voltage (V). 反馈 For example, in response to an asserted fault signal, the soft-start switch 402 couples the second input of the selection circuit system 404 to the second terminal of resistor 134, the first terminal of resistor 136, and the second input of amplifier 130. Thus, the soft-start switch 402 couples the soft-start input of the selection circuit system 404 to the feedback input of amplifier 130. Therefore, when a fault signal is asserted, the soft-start switch 402 will provide a feedback voltage (V... 反馈 It provides a second input to the selection circuit system 404 and a first terminal of the capacitor 406.

[0085] In the example illustrated in Figure 4, the selection circuit system 404 is implemented by a programmable circuit system as described herein. In some instances, the selection circuit system 404 is referred to as a logic circuit system or a selection logic circuit system. As described above, the selection circuit system 404 receives a reference voltage (V) at reference voltage terminal 146. 参考 The voltage at the third terminal of the soft-start switch 402 and the reference voltage (V). In the example of Figure 4, the selection circuit system 404 selects the reference voltage (V) 参考 The lower of the voltage at the second input of the selection circuit system 404 and the voltage at the second input of the amplifier 130 is provided to the reference input of the amplifier 130. As described above, when the fault signal is canceled assertion, the soft-start switch 402 will supply the voltage (V) 供应 The second input to the selection circuit system 404 and the first terminal of the capacitor 406 are provided. Additionally, a supply voltage (V) is provided. 供应 ) greater than the reference voltage (V参考 Therefore, when the fault signal is canceled as asserted, the selection circuit system 404 will select the reference voltage (V). 参考 It provides a reference input to amplifier 130.

[0086] As described above, when a fault signal is asserted, the soft-start switch 402 will feed back a voltage (V). 反馈 This provides a second input to the selection circuit system 404 and a first terminal to the capacitor 406. In the example of Figure 4, during a fault condition, the feedback voltage (V) 反馈 Less than the supply voltage (V) 供应 Therefore, when a fault signal is asserted, capacitor 406 draws voltage from the supply voltage (V). 供应 Discharge to feedback voltage (V) 反馈 Additionally, during fault conditions, the feedback voltage (V) 反馈 Less than the reference voltage (V) 参考 Therefore, when a fault signal is asserted, the selection circuit system 404 discharges capacitor 406 to the feedback voltage (V). 反馈 Then the feedback voltage (V) 反馈 It provides a reference input to amplifier 130.

[0087] In the example illustrated in Figure 4, amplifier 204 directs the input voltage (V) to power converter 100. 输入 ) and the output voltage (V) from the power converter 100 输出 The comparison is performed. In the example of Figure 4, if the input voltage (V) is compared... 输入 ) is greater than or equal to the output voltage (V) 输出 If the output voltage (V) is not specified, then amplifier 204 asserts the transistor protection signal. In other words, if the output voltage (V) is not specified, then the transistor protection signal is not specified. 输出 ) less than or equal to the input voltage (V) 输入 If the input voltage (V) is true, then amplifier 204 asserts the transistor protection signal. Otherwise, if the input voltage (V) is true, then the transistor protection signal is true. 输入 () less than the output voltage (V) 输出 If the output voltage (V) is not specified, amplifier 204 will cancel the assertion transistor protection signal. In other words, if the output voltage (V) is not specified, amplifier 204 will cancel the assertion transistor protection signal. 输出 ) greater than the input voltage (V 输入 If the amplifier 204 cancels the assertion transistor protection signal, then the amplifier 204 will cancel the assertion transistor protection signal.

[0088] In the example illustrated in Figure 4, in response to a transistor protection signal, the fault logic circuit system 206 provides a fault bypass signal to the control logic circuit system 138. For example, in response to the asserted transistor protection signal, the fault logic circuit system 206 asserts a fault bypass signal and provides the fault bypass signal to the control logic circuit system 138. In response to the fault bypass signal, the control logic circuit system 138 provides a second control signal to the driver 140. For example, in response to the asserted fault bypass signal, the control logic circuit system 138 asserts the second control signal. In response to the second control signal, the driver 140 enables the high-side FET 106 in the positive direction.

[0089] When a fault exists (during a fault condition) and the high-side FET 106 is enabled (assert fault bypass signal), the output voltage (V) from the power converter 100 is... 输出 It is approximately equal to the input voltage (V) of the power converter 100. 输入 Therefore, during fault conditions, the feedback voltage (V) 反馈 ) is based on the input voltage (V) to the power converter 100 when the high-side FET 106 is enabled. 输入 Therefore, during a fault condition, the second input of the selection circuit system 404 and the first terminal of the capacitor 406 receive the input voltage (V) when the high-side FET 106 is enabled. 输入 This is a step-down version of the capacitor 406. Therefore, during fault conditions, capacitor 406 charges to the input voltage (V) when the high-side FET 106 is enabled. 输入 (a step-down version)

[0090] In the example illustrated in Figure 4, in response to fault clearing, the sensor signal provided to the fault logic circuit system 206 is revoked from the sensor assertion monitored by the fault. In response to the revoked sensor signal, the fault logic circuit system 206 revoks the assertion of both the fault signal and the fault bypass signal. In the example of Figure 4, in response to the revoked fault signal and the revoked fault bypass signal, the control logic circuit system 138 revoks the assertion of the second control signal to the driver 140. In response to the revoked second control signal, the driver 140 disables the high-side FET 106. Thus, the power converter 100 can return to normal operation as specified by the feedback loop and the PWM control implemented by the controller 104.

[0091] In the example illustrated in Figure 4, in response to a fault signal indicating a revoked assertion, the soft-start switch 402 is dual-state switched, and the second input of the selection circuit system 404 is coupled to the supply voltage (V). 供应 As described above, when a fault is present (during a fault condition), capacitor 406 charges to the feedback voltage (V). 反馈The feedback voltage is the input voltage (V) when the high-side FET 106 (assert fault bypass signal) is enabled. 输入 The step-down version. Due to the feedback voltage (V) 反馈 Less than the supply voltage (V) 供应 Therefore, when the fault condition is cleared, capacitor 406 charges until the supply voltage (V) is reached. 供应 ).

[0092] In the example illustrated in Figure 4, the selection circuit system 404 receives the reference voltage (V) at the reference voltage terminal 146. 参考 The voltage at the third terminal of the soft start switch 402 is the voltage across capacitor 406 when the fault condition is cleared. 软启动 As described above, selection circuitry 404 provides the lower of the voltages at its first and second inputs to the reference input of amplifier 130. Therefore, selection circuitry 404 selects the voltage across capacitor 406 (V... 软启动 This provides a reference input to amplifier 130 until the voltage (V) across capacitor 406 is reached. 软启动 ) greater than the reference voltage (V 参考 Until then. In the example of Figure 4, the capacitance of capacitor 406 and the internal current source of selection circuit system 404 set the voltage (V) across capacitor 406. 软启动 The conversion rate of ).

[0093] Figure 5 This is an example timing diagram 500 depicting how controller 104 in Figure 4 controls the fault response. Figure 5 In this example, timing diagram 500 includes a first example diagram 502, a second example diagram 504, a third example diagram 506, and a fourth example diagram 508. Diagram 502 depicts the voltage (V) across capacitor 406 in volts versus time. 软启动 The first example curve 510, reference voltage (V) 参考 The second example curve 512 and the third example curve 514 of the signal at the output of the selection circuit system 404.

[0094] exist Figure 5 In the illustrated example, graph 504 depicts the output voltage (V) from power converter 100 in volts versus time. 输出 The fourth example curve 516 and the input voltage (V) to the power converter 100. 输入 The fifth example curve is shown in Figure 518. Figure 5In the example, graph 506 is a sixth example curve 520 depicting the fault signal provided by the fault logic circuit system 206 in terms of binary signal time. Additionally, graph 508 is a seventh example curve 522 depicting the fault bypass signal provided by the fault logic circuit system 206 in terms of binary signal time.

[0095] exist Figure 5 In the illustrated example, before the first example time 524 (t1), the soft-start switch 402 will supply voltage (V 供应 This provides a second input to the selection circuit system 404. Thus, before time 524 (t1), capacitor 406 is charged to the supply voltage (V). 供应 It is greater than the reference voltage (V) at reference voltage terminal 146. 参考 Therefore, the selection circuit system 404 provides a reference voltage (V) at its output before time 524 (t1). 参考 Additionally, before time 524 (t1), controller 104 is in normal operating condition. For example, before time 524 (t1), controller 104 adjusts high-side FET 106 and low-side FET 108 based on the voltage at the first input of amplifier 130 (which is the reference voltage (V) as described above). 参考 Input voltage (V) 输入 Step up to target output voltage (V) 输出 ).

[0096] exist Figure 5 In the illustrated example, at time 524 (t1), controller 104 detects a fault and disables high-side FET 106 and low-side FET 108. For example, if temperature sensor 202 detects that the temperature of power converter 100 exceeds a temperature threshold, temperature sensor 202 asserts a sensor signal. In response to the asserted sensor signal, fault logic circuitry 206 asserts a fault signal (graph 520), which causes controller 104 to disable high-side FET 106 and low-side FET 108. For example, in response to the asserted fault signal, control logic circuitry 138 retracts the assertion of a first control signal. In response to the retracted assertion of the first control signal, driver 140 disables high-side FET 106 and low-side FET 108. Thus, after time 524 (t1), the output voltage (V) from power converter 100... 输出 (Graph 516) begins to decrease.

[0097] Additionally, after time 524 (t1), the soft-start switch 402 couples the second input of the selection circuit system 404 to the second terminal of resistor 134, the first terminal of resistor 136, and the second input of amplifier 130. For example, in response to an asserted fault signal, the soft-start switch 402 couples the second input of the selection circuit system 404 to the second terminal of resistor 134, the first terminal of resistor 136, and the second input of amplifier 130. Thus, when a fault signal is asserted, the soft-start switch 402 will provide a feedback voltage (V... 反馈 This provides a second input to the selection circuit system 404 and a first terminal to the capacitor 406. Therefore, after time 524 (t1), the capacitor 406 draws voltage from the supply voltage (V). 供应 Discharge to feedback voltage (V) 反馈 Once the voltage across capacitor 406 (V) 软启动 ) meets the reference voltage (V 参考 ), capacitor 406 discharges to the feedback voltage (V 反馈 The ramp rate is based on the output voltage (V). 输出 (Graph 516) Discharge rate. In some instances, capacitor 406 discharges to the feedback voltage (V 反馈 The slack rate is based on the capacitance of capacitor 406 and the internal current source of selection circuit system 404.

[0098] As described above, amplifier 204 continuously monitors the output voltage (V). 输出 (Graph 516) and input voltage (V) 输入 (Graph 518). At the second example time 526 (t2), the controller 104 detects the output voltage (V). 输出 Less than the input voltage (V) 输入 And enable the high-side FET 106. For example, if amplifier 204 detects an output voltage (V... 输出 Less than the input voltage (V) 输入 If the transistor protection signal is asserted, amplifier 204 asserts a transistor protection signal. In response to the asserted transistor protection signal, fault logic circuitry 206 asserts a fault bypass signal (Figure 522), which causes controller 104 to enable high-side FET 106. For example, in response to the asserted fault bypass signal, control logic circuitry 138 asserts a second control signal. In response to the asserted second control signal, driver 140 enables high-side FET 106.

[0099] Therefore, after time 526 (t2), the high-side FET 106 is enabled, and the output voltage (V) 输出 (Graph 516) is approximately equal to the input voltage (V)输入 (Figure 518). Therefore, controller 104 ensures that the voltage drop across the high-side FET 106 is limited by the "on" resistance of the high-side FET 106, and is therefore much lower than the reverse bias voltage drop across the high-side FET 106. For example, if the "on" resistance of the high-side FET 106 is five milliohms (R... DS =5 mΩ) and the load current is 10A (I 负载 =10A), then the power dissipated by the high-side FET 106 is 500 milliwatts (P = R). DS *I 负载 = 500 mW), which is much smaller than the 20 watts that the high-side FET106 will dissipate when reverse biased.

[0100] exist Figure 5 In the illustrated example, at the third example time 528 (t3), controller 104 detects that the fault has been cleared. For example, temperature sensor 202 detects that the temperature of power converter 100 is below a temperature threshold and cancels the assertion of the sensor signal. In response to the canceled assertion of the sensor signal, fault logic circuitry 206 cancels the assertion of the fault signal (graph 520) and the fault bypass signal (graph 522). In response to the canceled assertion of the fault signal and the canceled assertion of the fault bypass signal, control logic circuitry 138 cancels the assertion of the second control signal. In response to the canceled assertion of the second control signal, driver 140 disables the high-side FET 106.

[0101] exist Figure 5 In the illustrated example, after time 528 (t3), the soft-start switch 402 couples the second input of the selection circuit system 404 to the supply voltage terminal 408. For example, in response to a fault signal that has been revoked, the soft-start switch 402 couples the second input of the selection circuit system 404 to the supply voltage terminal 408. Thus, when the fault signal is revoked, the soft-start switch 402 supplies voltage (V... 供应 This provides a second input to the selection circuit system 404 and a first terminal to the capacitor 406. Therefore, after time 528 (t3), the capacitor 406 draws voltage from the feedback voltage (V...). 反馈 Charge to the supply voltage (V) 供应 Once the voltage across capacitor 406 (V) 软启动 ) meets the reference voltage (V 参考 ), capacitor 406 is charged to the supply voltage (V 供应 The sloping rate is based on the capacitance of capacitor 406 and the internal current source of selection circuit system 404.

[0102] exist Figure 5In the illustrated example, controller 104 can return to normal operation after time 528 (t3). For example, after time 528 (t3), controller 104 adjusts the high-side FET 106 and the low-side FET 108 to adjust the input voltage (V) based on the voltage at the first input of amplifier 130. 输入 Step up to target output voltage (V) 输出 As described above, the voltage at the first input of amplifier 130 is the smaller of the voltages at the first and second inputs of selection circuit system 404. Figure 5 In the example, after time 528 (t3), capacitor 406 receives feedback voltage (V 反馈 Charge to the supply voltage (V) 供应 As described above, the charging rate of capacitor 306 is based on the capacitance of capacitor 406 and the internal current source of selection circuit system 404. Therefore, the power converter 100 steps up to the target output voltage (V). 输出 The switching rate is based on the capacitance of capacitor 406. Once the voltage across capacitor 406 (V) is... 软启动 ) greater than the reference voltage (V 参考 The selection circuit system 404 then provides a reference voltage (V) at its output. 参考 ).

[0103] Figure 6 It is a description Figure 2 Example state diagram 600 shows an example operating state of controller 104 (or 4). Figure 6 In this example, state diagram 600 includes a first example state 602, a second example state 604, a third example state 606, and a fourth example state 608. Additionally, state 604 includes a corresponding... Figure 2 The controller 104 has a first example sub-state 604A and a second example sub-state 604B corresponding to the controller 104 in Figure 4. Figure 6 In this example, state diagram 600 begins with state 602, which represents any operational state of controller 104. For instance, state 602 represents normal operation (non-fault operation) of controller 104.

[0104] exist Figure 6 In the illustrated example, in state 602, controller 104 adjusts high-side FET 106 and low-side FET 108 based on the reference voltage (V) at reference voltage terminal 146. 参考 The input voltage (V) 输入 Step up to target output voltage (V) 输出 ).exist Figure 6In this example, when a fault is detected, controller 104 transitions from state 602 to state 604. For instance, in response to an asserted sensor signal (from temperature sensor 202, from amplifier 122, etc.), fault logic circuitry system 206 asserts a fault signal. In response to the asserted fault signal, controller 104 transitions to state 604.

[0105] exist Figure 6 In the illustrated example, state 604 is a fault state, in which controller 104 stops regulating high-side FET 106 and low-side FET 108. In sub-state 604A, controller 104 disables high-side FET 106 and low-side FET 108. For example, in response to an asserted fault signal from fault logic circuitry 206, control logic circuitry 138 retracts the assertion of a first control signal and provides the first control signal to driver 140. In response to the retracted assertion of the first control signal, driver 140 disables high-side FET 106 and low-side FET 108.

[0106] exist Figure 6 In the illustrated example, in addition to disabling the high-side FET 106 and the low-side FET 108, the controller 104 also pulls the soft-start pin of the controller 104 to the voltage at the feedback pin of the controller 104 in sub-state 604B. For example, in response to an asserted fault signal, the soft-start switch 402 couples the second input of the selection circuit system 404 and the first terminal of the capacitor 406 to the second terminal of the resistor 134, the first terminal of the resistor 136, and the second input of the amplifier 130. Depending on the state of the power converter 100, the controller 104 transitions from state 604 to state 606 or state 608.

[0107] For example, when the fault is cleared, controller 104 transitions from state 604 to state 608. Figure 6 In this example, in response to a revoked assertion from a sensor signal (from temperature sensor 202, from amplifier 122, etc.), the fault logic circuitry system 206 revoks the assertion of a fault signal. In response to the revoked assertion of a fault signal, the controller 104 transitions to state 608. Figure 6 In one example, the output voltage (V) from the power converter 100 in the presence of a fault 输出 The voltage drops to the input voltage (V) of the power converter 100. 输入When the following occurs, controller 104 transitions from state 604 to state 606. For example, when a fault exists (a fault signal is asserted), fault logic circuitry 206 asserts a fault bypass signal in response to the asserted transistor protection signal (indicating that the output voltage is less than the input voltage) from amplifier 204. In response to the asserted fault bypass signal, controller 104 transitions to state 606.

[0108] exist Figure 6 In the illustrated example, state 606 is a fault bypass state, where controller 104 enables high-side FET 106 in the positive direction to prevent damage to high-side FET 106. For example, in response to an asserted fault bypass signal from fault logic circuitry 206, control logic circuitry 138 asserts a second control signal and provides the second control signal to driver 140. In response to the asserted second control signal, driver 140 enables high-side FET 106 in the positive direction. Thus, even if the output voltage (V) from power converter 100 is not damaged... 输出 The voltage is less than the input voltage (V) of the power converter 100. 输入 The high-side FET 106 will not be reverse biased. Therefore, the high-side FET 106 will not dissipate power to a level that could damage the high-side FET 106.

[0109] exist Figure 6 In the illustrated example, when the fault is cleared, controller 104 transitions from state 606 to state 608. For example, in response to a sensor signal (from temperature sensor 202, from amplifier 122, etc.) that was revoked while in state 606, fault logic circuitry system 206 revoks the assertion of a fault signal. In response to the revoked fault signal from fault logic circuitry system 206, control logic circuitry system 138 revoks the assertion of a second control signal and provides the second control signal to driver 140. In response to the revoked second control signal, driver 140 deactivates high-side FET 106, and controller 104 returns to normal control of high-side FET 106 and low-side FET 108. For example, amplifier 128 compares a slope-compensated sense current signal provided by mixer 124 with an error signal provided by amplifier 130.

[0110] Based on the comparison, amplifier 128 generates a PWM signal and provides the PWM signal to control logic circuitry 138. In response to the PWM signal, control logic circuitry 138 provides a control signal to driver 140. In response to the control signal, driver 140 controls one or more of the high-side FET 106 or the low-side FET 108. Consequently, controller 104 adjusts the high-side FET 106 and the low-side FET 108 to adjust the input voltage (V) based on the voltage at the first input of amplifier 130. 输入 Step up to target output voltage (V) 输出 As described above, in Figure 2 In controller 104, the voltage at the first input of amplifier 130 is the reference voltage (V). 参考 Furthermore, in the controller 104 of Figure 4, the voltage at the first input of the amplifier 130 depends on the voltage across the capacitor 406 (V). 软启动 ) and reference voltage (V 参考 Which of the following is larger and more variable?

[0111] For example, when the voltage across capacitor 406 (V) 软启动 Exceeding the reference voltage (V) 参考 When the voltage at the first input of amplifier 130 is selected by circuit system 404, the voltage across capacitor 406 is converted from the voltage at the first input of amplifier 130 (V). 软启动 Switch to reference voltage (V) 参考 As described above, capacitor 406 draws voltage from the feedback voltage (V). 反馈 Charge to the supply voltage (V) 供应 The rate is based on the capacitance of capacitor 406 and the internal current source of selection circuit system 404 until the voltage (V) across capacitor 406 is reached. 软启动 ) conforms to the reference voltage (V) 参考 Until then. Therefore, the power converter rises to the target output voltage (V) in 100 steps. 输出 The conversion rate is based on the capacitance of capacitor 406.

[0112] Figure 7 This is a flowchart representing at least one of example machine-readable instructions or example operations 700, which can be executed, instantiated, or implemented by a programmable circuit system. Figure 2 Or controller 104 of type 4. Figure 7At least one of the example machine-readable instructions or example operations 700 begins at block 702, where the fault logic circuitry system 206 monitors the operation of the power converter. For example, the fault logic circuitry system 206 monitors the operation of the power converter 100 via one or more sensors, such as temperature sensor 202, and amplifier 122. At block 704, the fault logic circuitry system 206 determines whether a fault has been detected. For example, the fault logic circuitry system 206 determines whether an asserted sensor signal indicating that a fault has manifested has been received.

[0113] exist Figure 7 In the illustrated example, in response to the fault logic circuitry system 206 determining that no fault has been detected (block 704: No), at least one of the machine-readable instructions or operations 700 returns to block 702. In response to the fault logic circuitry system 206 determining that a fault has been detected (block 704: Yes), at least one of the machine-readable instructions or operations 700 proceeds to block 706. At block 706, the fault logic circuitry system 206 sets a fault state for the power converter. For example, the fault logic circuitry system 206 asserts a fault signal. At block 708, in response to the set fault state, the control logic circuitry system 138 cancels the assertion of a first control signal and provides the first control signal to the driver. In response to the canceled assertion of the first control signal, the driver disables the high-side transistor and low-side transistor of the power converter.

[0114] In some instances, at least one of the machine-readable instructions or operations 700 includes block 710. For example, when the controller 104 of FIG4 is implemented using at least one of the machine-readable instructions or operations 700, at least one of the machine-readable instructions or operations 700 includes block 710. At block 710, in response to a set fault state, soft-start switch 402 sets the soft-start terminal of the power converter to the feedback voltage. For example, in response to an asserted fault signal, soft-start switch 402 couples the soft-start input of selection circuitry 404 to the feedback input of amplifier 130, the feedback input receiving a feedback voltage (V). 反馈 ).

[0115] exist Figure 7In the illustrated example, at block 712, fault logic circuitry 206 determines whether a fault has been cleared. For example, fault logic circuitry 206 determines whether the asserted sensor signal still exists. In response to fault logic circuitry 206 determining that the fault has been cleared (block 712: Yes), at least one of machine-readable instructions or operations 700 proceeds to block 724. In response to fault logic circuitry 206 determining that the fault has not been cleared (block 712: No), at least one of machine-readable instructions or operations 700 proceeds to block 714. At block 714, amplifier 204 monitors the input voltage and output voltage of the power converter.

[0116] exist Figure 7 In the illustrated example, at block 716, amplifier 204 determines whether the output voltage is less than the input voltage. If amplifier 204 determines that the output voltage is less than the input voltage, amplifier 204 asserts a transistor protection signal. In response to amplifier 204 determining that the output voltage is not less than the input voltage (block 716: No), at least one of machine-readable instructions or operations 700 returns to block 714. In response to amplifier 204 determining that the output voltage is less than the input voltage (block 716: Yes), at least one of machine-readable instructions or operations 700 proceeds to block 718. At block 718, in response to the asserted transistor protection signal, fault logic circuitry system 206 sets the power converter to a fault bypass state. For example, fault logic circuitry system 206 asserts a fault bypass signal.

[0117] exist Figure 7 In the illustrated example, in response to the established fault bypass state, at block 720, the control logic circuitry 138 asserts a second control signal and provides the second control signal to the driver. In response to the asserted second control signal, the driver enables the high-side transistor. Thus, the high-side transistor will not be reverse-biased and is protected from dissipating power to levels that could damage the high-side transistor. Figure 7 In this example, at block 722, fault logic circuitry 206 determines whether a fault has been cleared. For instance, fault logic circuitry 206 determines whether the asserted sensor signal still exists. In response to fault logic circuitry 206 determining that the fault has not been cleared (block 722: No), at least one of machine-readable instructions or operations 700 returns to block 720.

[0118] exist Figure 7In the illustrated example, in response to the fault logic circuitry 206 determining that the fault has been cleared (block 722: Yes), at least one of the machine-readable instructions or operations 700 proceeds to block 724. At block 724, the fault logic circuitry 206 clears the fault state. For example, the fault logic circuitry 206 cancels the assertion of a fault signal. At block 726, in response to the cleared fault state, the control logic circuitry 138 cancels the assertion of a second control signal and provides the second control signal to the driver. In response to the canceled assertion of the second control signal, the driver disables the high-side transistor, and the power converter returns to normal operation. For example, the driver ramps the output voltage of the power converter to the target voltage.

[0119] As described above, when the controller 104 of FIG4 is implemented using at least one of machine-readable instructions or operation 700, the soft-start switch 402 sets the soft-start terminal of the power converter to the feedback voltage in response to a set fault state. For example, in response to a set fault state, the soft-start switch 402 couples the soft-start input of the selection circuit system 404 to the feedback input of the amplifier 130, which receives the feedback voltage. Similarly, in response to a cleared fault state, the soft-start switch 402 decouples the soft-start input of the selection circuit system 404 from the feedback input of the amplifier 130 and couples the soft-start input to the supply voltage terminal 408. Therefore, the capacitor 406 charges to the supply voltage (V). 供应 As described above, when the controller 104 of FIG4 is implemented using at least one of machine-readable instructions or operations 700, the power converter 100 steps up to the target output voltage (V). 输出 The conversion rate is based on the capacitance of capacitor 406.

[0120] Figure 8 is Figure 1 A block diagram of a power converter 100, which depicts... Figure 1 A second example embodiment of the fault controller circuit system 144 is shown in Figure 8. The example fault controller circuit system 144 of Figure 8 includes an example temperature sensor 802, a first example amplifier 804, a second example amplifier 806, and an example fault logic circuit system 808. In the example of Figure 8, the controller 104 also includes an example voltage divider 810, which includes a first example resistor 812 and a second example resistor 814.

[0121] In the example illustrated in Figure 8, temperature sensor 802 has an output, and each of amplifiers 804 and 806 has a first input, a second input, and an output. In the example of Figure 8, fault logic circuit system 808 has a first input, a second input, a third input, a fourth input, a first output, a second output, and a third output. In the example of Figure 8, each of resistors 812 and 814 has a first terminal and a second terminal. Additionally, in the example of Figure 8, amplifier 122 has a first output and a second output, and voltage regulator 142 has a first input and a second input. For example, the first output of amplifier 122 is coupled to the first input of mixer 124, and the first input of voltage regulator 142 receives the input voltage (V) at input voltage terminal 114. 输入 ).

[0122] In the example illustrated in Figure 8, the output of temperature sensor 802 is coupled to the first input of fault logic circuit system 808. Additionally, the second output of amplifier 122 is coupled to the second input of fault logic circuit system 808. In the example of Figure 8, the first input of amplifier 804 is coupled to the second terminal of resistor 812 and the first terminal of resistor 814, and the second input of amplifier 804 is coupled to example reference voltage terminal 816. Furthermore, the output of amplifier 804 is coupled to the third input of fault logic circuit system 808.

[0123] In the example illustrated in Figure 8, the first input of amplifier 806 is coupled to the input voltage terminal 114 of power converter 100. For example, amplifier 806 receives the input voltage (V) of power converter 100 at its first input. 输入 In the example of Figure 8, the second input of amplifier 806 is coupled to the output voltage terminal 116 of power converter 100. For example, amplifier 806 receives the output voltage (V) from power converter 100 at its second input. 输出 In the example of Figure 8, the output of amplifier 806 is coupled to the fourth input of fault logic circuit system 808.

[0124] In the example illustrated in Figure 8, the first input of the fault logic circuit system 808 is coupled to the output of the temperature sensor 802. In the example of Figure 8, the second input of the fault logic circuit system 808 is coupled to the second output of the amplifier 122. Additionally, the third input of the fault logic circuit system 808 is coupled to the output of the amplifier 804. In the example of Figure 8, the fourth input of the fault logic circuit system 808 is coupled to the output of the amplifier 806. Furthermore, the first output of the fault logic circuit system 808 is coupled to the first input of the control logic circuit system 138. In the example of Figure 8, the second output of the fault logic circuit system 808 is coupled to the second input of the voltage regulator 142, and the third output of the fault logic circuit system 808 is coupled to the second input of the control logic circuit system 138.

[0125] In the example illustrated in Figure 8, the first terminal of resistor 812 is coupled to the output of voltage regulator 142. In the example of Figure 8, the second terminal of resistor 812 is coupled to the first input of amplifier 804 and the first terminal of resistor 814. Additionally, the first terminal of resistor 814 is coupled to the first input of amplifier 804 and the second terminal of resistor 812. In the example of Figure 8, the second terminal of resistor 814 is coupled to reference voltage terminal 118. In the example of Figure 8, voltage divider 810 provides a supply voltage (V) between the second terminal of resistor 812 and the first terminal of resistor 814. 供应 (a step-down version)

[0126] In the example illustrated in Figure 8, the temperature sensor 802 is similar to Figure 2 The temperature sensor 802 is implemented. If the temperature of the power converter 100 exceeds a temperature threshold (indicating an over-temperature fault), the temperature sensor 802 provides a sensor signal to the fault logic circuit system 808. For example, in response to a fault, the temperature sensor 802 asserts the sensor signal. In the example of FIG8, the amplifier 122 is implemented as described above. If the sensed current through resistor 112 exceeds a current threshold (indicating an overcurrent fault), the amplifier 122 provides a sensor signal to the fault logic circuit system 808. For example, in response to a fault, the amplifier 122 asserts the sensor signal. In additional or alternative instances, the controller 104 or the fault logic circuit system 808 includes one or more additional sensors to monitor one or more additional or alternative faults, such as overvoltage faults or undervoltage faults, etc.

[0127] In the example illustrated in Figure 8, amplifier 804 is implemented by a circuit system including one or more operational amplifiers. Furthermore, the first input of amplifier 804 is a non-inverting input, and the second input of amplifier 804 is an inverting input. In the example of Figure 8, amplifier 804 is a supply state comparator that compares the supply voltage (V) at the first input of amplifier 804 with the supply state comparator. 供应 The step-down version of the amplifier 804 is related to the reference voltage (V) at the second input of the amplifier. 参考 The two inputs are compared. Thus, in some instances, the first and second inputs of amplifier 804 are referred to as the feedback input and the reference input, respectively.

[0128] In the example illustrated in Figure 8, amplifier 804 supplies the status signal (V) based on the comparison. 供应状态 This is provided to the fault logic circuit system 808. Therefore, in some instances, the output of amplifier 804 is referred to as the control output, and the third input of the fault logic circuit system 808 is referred to as the supply status input. In the example of Figure 8, if the supply voltage (V...) 供应 The step descent version is greater than or equal to the reference voltage (V). 参考 If the amplifier 804 asserts a supply status signal, then the asserted supply status signal indicates the supply voltage (V). 供应 The supply voltage (V) is at the expected level. Otherwise, if the supply voltage (V) is at the expected level. 供应 The step-down version is smaller than the reference voltage (V). 参考 If the assertion is cancelled, amplifier 804 will deprecate the supply status signal. For example, a deprecated supply status signal indicates the supply voltage (V). 供应 The voltage regulator 142 is not at the expected level and is experiencing a fault.

[0129] As described above, when a fault manifests in the power converter 100, sensors monitoring the fault (temperature sensor 802, amplifier 122, etc.) provide sensor signals to the fault logic circuit system 808. In the example of Figure 8, the fault logic circuit system 808 is implemented by a programmable circuit system as described herein. As described above, a first input of the fault logic circuit system 808 is coupled to the output of the temperature sensor 802, and a second input of the fault logic circuit system 808 is coupled to the second output of the amplifier 122. Thus, in some instances, the first and second inputs of the fault logic circuit system 808 are referred to as the first sensor input and the second sensor input, respectively.

[0130] In the example illustrated in Figure 8, in response to a sensor signal, the fault logic circuit system 808 provides a fault signal to the control logic circuit system 138. For example, in response to an asserted sensor signal, the fault logic circuit system 808 asserts a fault signal and provides the fault signal via a first output of the fault logic circuit system 808. Thus, in some instances, the first output of the fault logic circuit system 808 is referred to as a fault output. In a power converter, distinguishing between faults associated with the output stage and faults associated with the controller of the output stage helps the controller respond effectively to faults. However, distinguishing between faults associated with the output stage and faults associated with the controller of the output stage can be difficult.

[0131] For example, an overheating fault could be caused by overheating of any component of the power converter 100, not just the high-side FET 106 and the low-side FET 108. Alternatively, an overcurrent fault could be caused by overheating of the supply voltage (V) to the driver 140. 供应 The voltage drops below the expected value. Without distinguishing between faults associated with the output stage and faults associated with the output stage controller, the controller may fail to respond appropriately to the fault. Advantageously, the fault controller circuitry 144 includes one or more sensors to monitor additional characteristics of the power converter 100. For example, the fault controller circuitry 144 includes an amplifier 804 to monitor the supply voltage (V... 供应 Therefore, when a fault appears, readings from one or more sensors can be cross-referenced to determine the cause of the fault.

[0132] In the example illustrated in Figure 8, amplifier 804 supplies voltage (V) 供应 The step-down version of the reference voltage (V) at the reference voltage terminal 816. 参考 The fault logic circuit system 808 compares the faults with those associated with output stage 102, as described above. Thus, the fault logic circuit system 808 can use the supply status signal from amplifier 804 to distinguish between faults associated with output stage 102 and faults associated with voltage regulator 142. For example, in response to an asserted sensor signal, fault logic circuit system 808 asserts a fault signal and checks the supply status signal. In response to the supply status signal, fault logic circuit system 808 provides an enable signal to voltage regulator 142 at its second output. Therefore, fault controller circuit system 144 of FIG8 includes a third output that provides the enable signal to voltage regulator 142. Additionally, in some instances, the second output of fault logic circuit system 808 is referred to as a supply enable output.

[0133] In the example illustrated in Figure 8, in response to the asserted supply status signal (indicating the supply voltage (V)) 供应(At the expected level), the fault logic circuit system 808 asserts an enable signal. In response to the asserted fault signal and the asserted enable signal, the controller 104 behaves similarly to... Figure 2 The controller 104 operates to handle faults in the output stage 102. In the example of Figure 8, in response to the revoked assertion of the supply status signal (indicating the supply voltage (V)... 供应 If the voltage regulator 142 is not at the expected level, the fault logic circuit system 808 cancels the assertion enable signal. In response to the asserted fault signal and the canceled assertion enable signal, the controller 104 performs fault handling on the voltage regulator 142. In this way, the controller 104 distinguishes between faults associated with the output stage 102 and faults associated with the controller 104.

[0134] Therefore, if the supply voltage (V) 供应 If a temperature fault is observed during a crash, the fault logic circuitry 808 can determine that the cause of the temperature fault is most likely the voltage regulator 142 rather than the high load current. Therefore, the fault logic circuitry 808 can disable the voltage regulator 142 to handle the temperature fault, rather than by disabling the high-side FET 106 and the low-side FET 108. In an additional or alternative instance, the fault controller circuitry 144, or more generally, the controller 104, includes one or more additional or alternative sensors. For example, one or more additional or alternative sensors monitor one or more additional or alternative voltages or currents to facilitate the distinction between faults associated with output stage 102 and faults associated with controller 104.

[0135] In the example illustrated in Figure 8, as described above, controller 104 performs fault handling on voltage regulator 142 in response to an asserted fault signal and a revoked assertion enable signal. For example, in response to the asserted fault signal, control logic circuitry 138 revoks the assertion of a first control signal and provides the first control signal to driver 140. In response to the revoked assertion of the first control signal, driver 140 disables high-side FET 106 and low-side FET 108. In response to the revoked assertion enable signal, voltage regulator 142 is disabled. For example, in response to the revoked assertion enable signal, voltage regulator 142 stops providing the supply voltage (V) at its output. 供应 ).

[0136] In the example illustrated in Figure 8, in response to fault clearing, the sensor signal provided to the fault logic circuit system 808 by the sensor that monitors the fault is removed from the assertion. For example, in response to over-temperature fault clearing (the temperature of the power converter 100 drops below a temperature threshold), the temperature sensor 802 removes the assertion provided to the fault logic circuit system 808. Additionally, for example, in response to over-current fault clearing (the current through resistor 112 drops below a current threshold), the amplifier 122 removes the assertion provided to the sensor signal of the fault logic circuit system 808.

[0137] In the example illustrated in Figure 8, in response to the revoked assertion of a sensor signal, the fault logic circuit system 808 revoks the assertion of a fault signal and activates the assertion enable signal. In the example of Figure 8, in response to the assertion enable signal, the voltage regulator 142 is activated. For example, the voltage regulator 142 provides a supply voltage (V) at its output. 供应 In the example of Figure 8, in response to a fault signal indicating a revoked assertion, the control logic circuitry 138 provides a control signal to the driver 140 based on a feedback loop and PWM control implemented by the controller 104. In response to the control signal, the driver 140 controls one or more of the high-side FET 106 or the low-side FET 108. Thus, the power converter 100 can return to normal operation as specified by the feedback loop and the PWM control implemented by the controller 104.

[0138] Figure 9 is Figure 1 A block diagram of a power converter 100 is provided, wherein the controller 104 includes the fault controller circuit system 144 of FIG. 8, an example soft-start switch 902, and an example selection circuit system 904. In the example of FIG. 9, the power converter 100 also includes an example capacitor 906. Additionally, in the example of FIG. 9, the soft-start switch 902 has a control terminal, a first terminal, a second terminal, and a third terminal. The example selection circuit system 904 of FIG. 9 has a first input, a second input, and an output. In the example of FIG. 9, the capacitor 906 has a first terminal and a second terminal.

[0139] In the example illustrated in Figure 9, the control terminal of the soft-start switch 902 is coupled to the first output of the fault logic circuit system 808. In the example of Figure 9, the first terminal of the soft-start switch 902 is coupled to the example supply voltage terminal 908. For example, the soft-start switch 902 receives the supply voltage (V) at the first terminal. 供应 Therefore, in some instances, the first terminal of the soft-start switch 902 is referred to as the supply input. In the example of Figure 9, the supply voltage terminal 908 is the output of the voltage regulator 142. In additional or alternative instances, the first terminal of the soft-start switch 902 receives another voltage from another terminal.

[0140] In the example illustrated in Figure 9, the second terminal of the soft-start switch 902 is coupled to the second terminal of resistor 134, the first terminal of resistor 136, and the second input of amplifier 130. For example, the soft-start switch 902 is coupled to the feedback input of amplifier 130 and receives a feedback voltage (V). 反馈 In the example of Figure 9, the third terminal of the soft-start switch 902 is coupled to the second input of the selection circuit system 904 and the first terminal of the capacitor 906. For example, the connection between the third terminal of the soft-start switch 902 and the second input of the selection circuit system 904 corresponds to the soft-start terminal of the controller 104, which, in the example described herein, is also referred to as the soft-start pin of the controller 104.

[0141] In the example illustrated in Figure 9, the first input of the selection circuit system 904 is coupled to the reference voltage terminal 146. For example, the selection circuit system 904 receives the reference voltage (V) at the first input. 参考 Therefore, in some instances, the first input of the selection circuit system 904 is referred to as the reference input. In the example of Figure 9, the second input of the selection circuit system 904 is coupled to the third terminal of the soft-start switch 902 and the first terminal of the capacitor 906. Therefore, in some instances, the second input of the selection circuit system 904 is referred to as the soft-start input.

[0142] In the example illustrated in Figure 9, the output of the selection circuit system 904 is coupled to the first input of the amplifier 130. In some examples, the output of the selection circuit system 904 is referred to as the selection output. In the example of Figure 9, the first terminal of the capacitor 906 is coupled to the third terminal of the soft-start switch 902. The first terminal of the capacitor 906 is also coupled to the second input of the selection circuit system 904. In the example of Figure 9, the second terminal of the capacitor 906 is coupled to the reference voltage terminal 118.

[0143] In the example illustrated in Figure 9, the soft-start switch 902 is implemented similarly to the soft-start switch 402 of Figure 4. For example, the soft-start switch 902 is implemented by an SPDT switch, which causes the third terminal of the soft-start switch 902 to supply a voltage (V) at the first terminal of the soft-start switch 902. 供应 ) and the feedback voltage (V) at the second terminal of the soft start switch 902 反馈 The circuit system 904 switches between two states. In the example of Figure 9, the selection circuit system 904 is implemented similarly to the selection circuit system 404 of Figure 4. Additionally, the capacitor 906 is implemented similarly to the capacitor 406 of Figure 4.

[0144] In the example illustrated in Figure 9, when a fault manifests in the power converter 100, sensors monitoring the fault (temperature sensor 802, amplifier 122, etc.) provide sensor signals to the fault logic circuit system 808. As described above, the fault logic circuit system 808 also monitors the supply status signal provided by amplifier 804. In response to the asserted sensor signals and the asserted supply status signal, the controller 104 of Figure 9 operates similarly to the controller 104 of Figure 4. For example, the controller 104 disables the high-side FET 106 and the low-side FET 108, and couples the second input of the selection circuit system 404 to the feedback voltage (V). 反馈 In the example illustrated in Figure 9, in response to the asserted sensor signal and the revoked supply status signal, the controller 104 of Figure 9 operates similarly to the controller 104 of Figure 8, with the addition of a dual-state switching of the soft-start switch 902, similar to that described in Figure 4.

[0145] Figure 10 This is an example state diagram 1000 depicting an example operating state of the controller 104 in Figure 8 or 9. Figure 10 In the example, state diagram 1000 includes a first example state 1002, a second example state 1004, a third example state 1006, a fourth example state 1008, a fifth example state 1010, and a sixth example state 1012. Additionally, state 1004 includes a first example sub-state 1004A corresponding to controller 104 in Figure 8 and a second example sub-state 1004B corresponding to controller 104 in Figure 9. Figure 10 In the example, state 1010 includes a third example substate 1010A corresponding to controller 104 in Figure 8 and a fourth example substate 1010B corresponding to controller 104 in Figure 9.

[0146] exist Figure 10 In the illustrated example, state diagram 1000 begins with state 1002, which represents any operational state of controller 104. For example, state 1002 represents normal operation (non-fault operation) of controller 104. Figure 10 In this example, in state 1002, controller 104 adjusts high-side FET 106 and low-side FET 108 based on the reference voltage (V) at reference voltage terminal 146. 参考 The input voltage (V) 输入 Step up to target output voltage (V) 输出 ).exist Figure 10 In one instance, when a fault is detected and the supply status signal is revoked, the controller 104 transitions from state 1002 to state 1010.

[0147] exist Figure 10In the illustrated example, when a fault is detected and the supply status signal is asserted, the controller 104 transitions from state 1002 to state 1004. For example, in response to the asserted sensor signal (from temperature sensor 802, from amplifier 122, etc.) and the asserted supply status signal, the fault logic circuit system 808 asserts a fault signal. In response to the asserted fault signal, the controller 104 transitions to state 1004. Figure 10 In the example, state 1004 is a fault state, in which controller 104 stops regulating high-side FET 106 and low-side FET 108.

[0148] In example sub-state 1004A, controller 104 disables high-side FET 106 and low-side FET 108. For example, in response to an asserted fault signal from fault logic circuitry 808, control logic circuitry 138 retracts the assertion of a first control signal and provides the first control signal to driver 140. In response to the retracted assertion of the first control signal, driver 140 disables high-side FET 106 and low-side FET 108. In sub-state 1004B, in addition to disabling high-side FET 106 and low-side FET 108, controller 104 also pulls the soft-start pin of controller 104 to the voltage at the feedback pin of controller 104.

[0149] For example, in response to an asserted fault signal, the soft-start switch 902 couples the second input of the selection circuit system 904 and the first terminal of the capacitor 906 to the second terminal of the resistor 134, the first terminal of the resistor 136, and the second input of the amplifier 130. Depending on the condition of the power converter 100, the controller 104 transitions from state 1004 to state 1006 or state 1008. Figure 10 In this example, when the fault is cleared, controller 104 transitions from state 1004 to state 1008. For instance, in response to a revoked assertion of a sensor signal (from temperature sensor 802, from amplifier 122, etc.), fault logic circuitry system 808 revoks the assertion of a fault signal. In response to the revoked assertion of a fault signal, controller 104 transitions to state 1008.

[0150] exist Figure 10 In the illustrated example, the output voltage (V) from the power converter 100 in the presence of a fault 输出 The voltage drops to the input voltage (V) of the power converter 100. 输入When the following occurs, controller 104 transitions from state 1004 to state 1006. For example, when a fault exists (a fault signal is asserted), fault logic circuitry system 808 asserts a fault bypass signal in response to the asserted transistor protection signal (indicating that the output voltage is less than the input voltage) from amplifier 806. In response to the asserted fault bypass signal, controller 104 transitions to state 1006. Figure 10 In one instance, state 1006 is a fault bypass state, in which controller 104 enables high-side FET 106 in the positive direction to prevent damage to high-side FET 106.

[0151] For example, in response to an asserted fault bypass signal from fault logic circuitry 808, control logic circuitry 138 asserts a second control signal and provides the second control signal to driver 140. In response to the asserted second control signal, driver 140 enables high-side FET 106 in the positive direction. Thus, even if the output voltage (V) from power converter 100... 输出 The voltage is less than the input voltage (V) of the power converter 100. 输入 The high-side FET 106 will not be reverse biased. Therefore, the high-side FET 106 will not dissipate power to a level that could damage the high-side FET 106.

[0152] exist Figure 10 In the illustrated example, when the fault is cleared, controller 104 transitions from state 1006 to state 1008. For example, in response to a sensor signal (from temperature sensor 802, from amplifier 122, etc.) that was revoked while in state 1006, fault logic circuitry 808 revoks the assertion of a fault signal. In response to the revoked fault signal from fault logic circuitry 808, controller 104 transitions to state 1008. For example, in response to the revoked fault signal, control logic circuitry 138 revoks the assertion of a second control signal and provides the second control signal to driver 140. In response to the revoked second control signal, driver 140 deactivates high-side FET 106, and controller 104 returns to normal control of high-side FET 106 and low-side FET 108, as described herein.

[0153] As described above, in some instances, controller 104 transitions from state 1002 to state 1010. For example, controller 104 transitions from state 1002 to state 1010 when a fault is manifested and the supply status signal is revoked from assertion. In response to the asserted sensor signal (from temperature sensor 802, from amplifier 122, etc.) and the revoked supply status signal, fault logic circuitry 808 asserts a fault signal and revoks the assertion enable signal. In response to the asserted fault signal and the revoked assertion enable signal, controller 104 transitions to state 1010. Figure 10 In this example, state 1010 is a supply failure state, in which controller 104 stops providing the supply voltage (V). 供应 And stop regulating the high-side FET 106 and the low-side FET 108.

[0154] In example sub-state 1010A, controller 104 disables voltage regulator 142, and also disables high-side FET 106 and low-side FET 108. For example, voltage regulator 142 is disabled in response to an enable signal from fault logic circuitry 808 that has been revoked. Additionally, for example, in response to an asserted fault signal from fault logic circuitry 808, control logic circuitry 138 revoks an assertion of a first control signal and provides the first control signal to driver 140. In response to the revoked first control signal, driver 140 disables high-side FET 106 and low-side FET 108.

[0155] exist Figure 10 In the illustrated example, in addition to disabling voltage regulator 142, high-side FET 106, and low-side FET 108, controller 104 also pulls the soft-start pin of controller 104 to the voltage at the feedback pin of controller 104 in sub-state 1010B. For example, in response to an asserted fault signal, soft-start switch 902 couples the second input of selection circuitry 904 and the first terminal of capacitor 906 to the second terminal of resistor 134, the first terminal of resistor 136, and the second input of amplifier 130. Figure 10 In one instance, when the fault is cleared and the supply status signal is revoked, the controller 104 transitions from state 1010 to state 1012.

[0156] For example, when the supply status signal is revoked, the fault logic circuit system 808 revoks the assertion of the fault signal in response to the revoked sensor signal (from temperature sensor 802, from amplifier 122, etc.). In response to the revoked fault signal, the controller 104 transitions to state 1012. For example, in response to the revoked sensor signal, the fault logic circuit system 808 revoks the assertion of the fault signal, and the assertion enable signal is activated. In state 1012, the voltage regulator 142 is activated. For example, in response to the asserted enable signal, the voltage regulator 142 is activated and supplies voltage (V... 供应 ) is provided to drive 140.

[0157] exist Figure 10 In the illustrated example, in response to the asserted supply status signal, controller 104 transitions from state 1012 to state 1008. In state 1008, controller 104 returns to normal control of the high-side FET 106 and the low-side FET 108. For example, amplifier 128 compares a slope-compensated sensed current signal provided by mixer 124 with an error signal provided by amplifier 130. Based on the comparison, amplifier 128 generates a PWM signal and provides the PWM signal to control logic circuitry 138. In response to the PWM signal, control logic circuitry 138 provides a control signal to driver 140.

[0158] In response to the control signal, driver 140 controls one or more of the high-side FET 106 or the low-side FET 108. Consequently, controller 104 adjusts the high-side FET 106 and the low-side FET 108 to adjust the input voltage (V) based on the voltage at the first input of amplifier 130. 输入 Step up to target output voltage (V) 输出 In the controller 104 of Figure 8, the voltage at the first input of the amplifier 130 is the reference voltage (V). 参考 Furthermore, in the controller 104 of Figure 9, the voltage at the first input of the amplifier 130 depends on the voltage across the capacitor 906 (V). 软启动 ) and reference voltage (V 参考 Which of the following is larger and more variable?

[0159] For example, when the voltage across capacitor 906 (V) 软启动 Exceeding the reference voltage (V) 参考 When the voltage at the first input of amplifier 130 is selected by circuit system 904, the voltage across capacitor 906 is converted from the voltage at the first input of amplifier 130 (V). 软启动 Switch to reference voltage (V) 参考 In the controller 104 of Figure 9, capacitor 906 draws voltage from the feedback voltage (V). 反馈Charge to the supply voltage (V) 供应 The rate is based on the capacitance of capacitor 906 and the internal current source of selection circuit system 904 until the voltage (V) across capacitor 906 is reached. 软启动 ) conforms to the reference voltage (V) 参考 Until then. Therefore, the power converter rises to the target output voltage (V) in 100 steps. 输出 The conversion rate is based on the capacitance of capacitor 906.

[0160] Figure 11 is a flowchart illustrating at least one of example machine-readable instructions or example operations 1100, which can be executed, instantiated, or implemented by a programmable circuit system to implement the controller 104 of Figure 8 or 9. At least one of the example machine-readable instructions or example operations 1100 in Figure 11 begins at block 1102, where a fault logic circuit system 808 monitors the operation of the power converter. For example, the fault logic circuit system 808 monitors the operation of the power converter 100 via one or more sensors, such as a temperature sensor 802, and an amplifier 122. At block 1104, the fault logic circuit system 808 determines whether a fault has been detected. For example, the fault logic circuit system 808 determines whether an asserted sensor signal indicating that a fault has manifested has been received.

[0161] In the example illustrated in Figure 11, in response to the fault logic circuitry 808 determining that no fault has been detected (block 1104: No), at least one of the machine-readable instructions or operations 1100 returns to block 1102. In response to the fault logic circuitry 808 determining that a fault has been detected (block 1104: Yes), at least one of the machine-readable instructions or operations 1100 proceeds to block 1106. At block 1106, the fault logic circuitry 808 sets a fault state for the power converter. For example, the fault logic circuitry 808 asserts a fault signal. At block 1108, in response to the set fault state, the control logic circuitry 138 cancels the assertion of a first control signal and provides the first control signal to the driver. In response to the canceled assertion of the first control signal, the driver disables the high-side transistor and low-side transistor of the power converter.

[0162] In some instances, at least one of the machine-readable instructions or operations 1100 includes block 1110. For example, when the controller 104 of FIG9 is implemented using at least one of the machine-readable instructions or operations 1100, at least one of the machine-readable instructions or operations 1100 includes block 1110. At block 1110, in response to a set fault state, soft-start switch 902 sets the soft-start terminal of the power converter to the feedback voltage. For example, in response to an asserted fault signal, soft-start switch 902 couples the soft-start input of selection circuitry 904 to the feedback input of amplifier 130, the feedback input receiving a feedback voltage (V). 反馈 ).

[0163] In the example illustrated in Figure 11, at box 1112, amplifier 804 determines whether the supply voltage is at the expected level. For example, amplifier 804 determines the supply voltage (V) provided by voltage regulator 142. 供应 Is the step-down version of the voltage greater than or equal to the reference voltage (V) at the reference voltage terminal 816? 参考 If amplifier 804 determines the supply voltage (V) 供应 The step descent version is greater than or equal to the reference voltage (V). 参考 If the amplifier 804 asserts the supply status signal, then the amplifier 804 asserts the supply status signal. In response to the amplifier 804 determining that the supply voltage is at the expected level (box 1112: Yes), at least one of the machine-readable instructions or operations 1100 proceeds to box 1114.

[0164] In the example illustrated in Figure 11, at block 1114, the fault logic circuitry 808 determines whether a fault has been cleared. For example, the fault logic circuitry 808 determines whether the asserted sensor signal still exists. In response to the fault logic circuitry 808 determining that the fault has been cleared (block 1114: Yes), at least one of the machine-readable instructions or operations 1100 proceeds to block 1126. In response to the fault logic circuitry 808 determining that the fault has not been cleared (block 1114: No), at least one of the machine-readable instructions or operations 1100 proceeds to block 1116. At block 1116, the amplifier 806 monitors the input voltage and output voltage of the power converter.

[0165] In the example illustrated in Figure 11, at block 1118, amplifier 806 determines whether the output voltage is less than the input voltage. If amplifier 806 determines that the output voltage is less than the input voltage, amplifier 806 asserts a transistor protection signal. In response to amplifier 806 determining that the output voltage is not less than the input voltage (block 1118: No), at least one of machine-readable instructions or operations 1100 returns to block 1116. In response to amplifier 806 determining that the output voltage is less than the input voltage (block 1118: Yes), at least one of machine-readable instructions or operations 1100 proceeds to block 1120. At block 1120, in response to the asserted transistor protection signal, fault logic circuitry system 808 sets the power converter to a fault bypass state. For example, fault logic circuitry system 808 asserts a fault bypass signal.

[0166] In the example illustrated in Figure 11, in response to the established fault bypass state, at block 1122, control logic system 138 asserts a second control signal and provides the second control signal to the driver. In response to the asserted second control signal, the driver enables the high-side transistor. Thus, the high-side transistor will not be reverse biased and is protected from dissipating power to levels that could damage it. In the example of Figure 11, at block 1124, fault logic system 808 determines whether the fault has been cleared. For example, fault logic system 808 determines whether the asserted sensor signal still exists. In response to fault logic system 808 determining that the fault has not been cleared (block 1124: No), at least one of machine-readable instructions or operations 1100 returns to block 1122.

[0167] In the example illustrated in Figure 11, in response to the fault logic circuitry 808 determining that the fault has been cleared (block 1124: Yes), at least one of the machine-readable instructions or operations 1100 proceeds to block 1126. At block 1126, the fault logic circuitry 808 clears the fault state. For example, the fault logic circuitry 808 cancels the assertion of a fault signal. At block 1128, in response to the cleared fault state, the control logic circuitry 138 provides a first signal to the driver, and the driver, in response to the first signal, ramps the output voltage of the power converter to the target voltage. For example, in response to the cleared fault state, the control logic circuitry 138 cancels the assertion of a second control signal, and the driver, in response to the canceled assertion of the second control signal, disables the high-side transistor. Thus, the power converter returns to normal operation based on the first control signal.

[0168] As described above, when the controller 104 of FIG9 is implemented using at least one of machine-readable instructions or operation 1100, the soft-start switch 902 sets the soft-start terminal of the power converter to the feedback voltage in response to a set fault state. For example, in response to a set fault state, the soft-start switch 902 couples the soft-start input of the selection circuit system 904 to the feedback input of the amplifier 130, which receives the feedback voltage. Similarly, in response to a cleared fault state, the soft-start switch 902 decouples the soft-start input of the selection circuit system 904 from the feedback input of the amplifier 130 and couples the soft-start input to the supply voltage terminal 908. Therefore, the capacitor 906 charges to the supply voltage (V). 供应 As described above, when the controller 104 of FIG9 is implemented using machine-readable instructions or operations 1100, the power converter 100 steps up to the target output voltage (V). 输出 The conversion rate is based on the capacitance of capacitor 906.

[0169] Returning to box 1112, if amplifier 804 determines the supply voltage (V) 供应 The step-down version is smaller than the reference voltage (V). 参考 If the amplifier 804 determines that the supply voltage is not at the expected level (block 1112: No), at least one of the machine-readable instructions or operations 1100 proceeds to block 1130. At block 1130, in response to the revoked supply status signal, the fault logic circuitry system 808 revoks the assertion of a third signal and provides the third signal to the supply circuitry. For example, the fault logic circuitry system 808 revoks the assertion enable signal. In response to the revoked third signal, the supply circuitry is deactivated.

[0170] Therefore, circuits operating based on the supply voltage provided by the supply circuit are deactivated. For example, because the driver operates based on the supply voltage, the driver is deactivated. At block 1132, the fault logic circuit system 808 determines whether the fault has been cleared. For example, the fault logic circuit system 808 determines whether the asserted sensor signal still exists. In response to the fault logic circuit system 808 determining that the fault has not been cleared (block 1132: No), at least one of the machine-readable instructions or operations 1100 returns to block 1130. In response to the fault logic circuit system 808 determining that the fault has been cleared (block 1132: Yes), at least one of the machine-readable instructions or operations 1100 proceeds to block 1134.

[0171] In the example illustrated in Figure 11, at block 1134, the fault logic circuitry system 808 clears the fault state. For example, the fault logic circuitry system 808 cancels the assertion of a fault signal. As described above, since the driver operates based on the supply voltage, the driver is disabled, and the supply voltage is deactivated when the third signal is canceled. Therefore, although the fault state is cleared, the driver still cannot control the high-side transistor or the low-side transistor of the power converter, regardless of the state of the control signal from the control logic circuitry system 138. In the example of Figure 11, at block 1136, the fault logic circuitry system 808 asserts a third signal and provides the third signal to the supply circuit. For example, the fault logic circuitry system 808 asserts an enable signal. In response to the asserted third signal, the supply circuit is enabled.

[0172] In the example illustrated in Figure 11, at box 1138, amplifier 804 determines whether the supply voltage is at the expected level. For example, amplifier 804 determines the supply voltage (V... 供应 Is the step sag version greater than or equal to the reference voltage (V)? 参考 If amplifier 804 determines the supply voltage (V) 供应 The step descent version is greater than or equal to the reference voltage (V). 参考 If the amplifier 804 determines that the supply voltage is at the expected level (box 1138: Yes), at least one of the machine-readable instructions or operations 1100 returns to box 1128. If the amplifier 804 determines that the supply voltage is not at the expected level (box 1138: No), at least one of the machine-readable instructions or operations 1100 returns to box 1136.

[0173] As described above, at block 1128, control logic circuitry 138 provides a first signal to the driver, and the driver, in response to the first signal, scales the output voltage of the power converter to a target voltage. For example, in response to the supply voltage returning to the desired value, the driver may control one or more of the high-side transistors or low-side transistors of the power converter in response to a control signal from control logic circuitry 138. Therefore, in response to the supply voltage returning to the desired value, the power converter returns to normal operation based on the first control signal.

[0174] Figure 12 This is a block diagram of an example system 1200 that includes an example power converter 1202. Figure 12 In this example, system 1200 includes a power converter 1202, an example power supply 1204, an example source protection circuit system 1206, a first example amplifier 1208, and an example output device 1210. Additionally, Figure 12System 1200 includes a second example amplifier 1212, an example Sony / Philips digital interface (SPDIF) 1214, an example Universal Serial Bus (USB) interface 1216, and an example multiplexer 1218. Figure 12 In this example, the power converter 1202 has a first input, a second input, a third input, and an output, and each of the source protection circuit system 1206 and the amplifier 1212 has an input and an output. Additionally, the amplifier 1208 has a supply terminal, an input, a first output, and a second output, and each of the SPDIF 1214 and the USB interface 1216 has an output. The multiplexer 1218 has a first input, a second input, and an output.

[0175] exist Figure 12 In the illustrated example, the first input of the power converter 1202 is coupled to the output of the source protection circuit system 1206, the second input of the power converter 1202 is coupled to the first output of the amplifier 1208, and the third input of the power converter 1202 is coupled to the output of the amplifier 1212. Figure 12 In this example, the output of the power converter 1202 is coupled to the supply terminal of the amplifier 1208. Additionally, the input of the source protection circuit system 1206 is coupled to the power supply 1204, and the output of the source protection circuit system 1206 is coupled to the first input of the power converter 1202, as described above.

[0176] exist Figure 12 In the illustrated example, the supply terminal of amplifier 1208 is coupled to the output of power converter 1202, and the input of amplifier 1208 is coupled to the output of multiplexer 1218. Figure 12 In this example, the first output of amplifier 1208 is coupled to the second input of power converter 1202, and the second output of amplifier 1208 is coupled to the input of amplifier 1212. Additionally, the third output of amplifier 1208 is coupled to the input of output device 1210.

[0177] exist Figure 12 In the illustrated example, the output of SPDIF 1214 is coupled to the first input of multiplexer 1218, and the output of USB interface 1216 is coupled to the second input of multiplexer 1218. Figure 12 In this example, the first input of multiplexer 1218 is coupled to the output of SPDIF 1214, and the second input of multiplexer 1218 is coupled to the output of USB interface 1216. Additionally, the output of multiplexer 1218 is coupled to the input of amplifier 1208.

[0178] exist Figure 12In the illustrated example, power supply 1204 is a car battery. For example, power supply 1204 is a 12V battery in a vehicle. Figure 12 In this example, the source protection circuit system 1206 is implemented using circuitry such as resistors, diodes, and capacitors to limit current, suppress voltage spikes, and block reverse current associated with the power supply 1204. Additionally, Figure 12 The power converter 1202 is a GaN-based boost converter. For example, the power converter 1202 is composed of... Figure 1 The power converter 100 is implemented. Figure 12 In this example, amplifier 1208 is an audio amplifier, such as a Class D amplifier.

[0179] exist Figure 12 In the illustrated example, each of the SPDIF 1214 and USB interface 1216 can receive audio signals. Figure 12 In this example, multiplexer 1218 selects between the audio signal provided by SPDIF 1214 and USB interface 1216 in response to a control signal from a controller (not described). In response to the control signal, multiplexer 1218 provides the audio signal to amplifier 1208 on the inter-IC audio (I2S) bus. Figure 12 In one example, amplifier 1208 receives an audio signal from multiplexer 1218, amplifies the audio signal, and then provides the audio signal to output device 1210. For example, output device 1210 is a speaker.

[0180] exist Figure 12 In the illustrated example, amplifier 1208 analyzes the audio signal from multiplexer 1218 to determine the voltage required to amplify the audio signal. Based on this analysis, amplifier 1208 provides a Class H PWM signal to amplifier 1212. For example, the Class H PWM signal, when amplified, will cause power converter 1202 to provide the voltage required to amplify the audio signal. Figure 12 In this example, amplifier 1212 amplifies the Class H PWM signal and provides the amplified Class H PWM signal to power converter 1202. Additionally, amplifier 1212 provides a clock signal (Clock_Sync) to power converter 1202.

[0181] exist Figure 12 In the illustrated example, power converter 1202 is a GaN-based tracking boost converter. For instance, in response to a clock signal and an amplified Class H PWM signal, power converter 1202 steps up the voltage of power supply 1204 and converts the power signal (P...) into a voltage level. VDDThe signal is provided to amplifier 1208. Thus, amplifier 1208 can amplify the audio signal received from multiplexer 1218 and provide the amplified audio signal to output device 1210.

[0182] In the event of a fault, the controller of power converter 1202 disables power converter 1202. In some instances, power converter 1202 flags the fault to downstream devices such as amplifier 1208. For example, downstream devices may utilize internal protection circuitry to handle the fault. Alternatively, downstream devices may be able to withstand the current or voltage associated with the fault. Figure 12 In this example, power converter 1202 monitors the input voltage (at a first input) and the output voltage (at the output). As described herein, when the output voltage is lower than the input voltage, power converter 1202 enables the high-side GaN FET in the positive direction to prevent damage to the high-side GaN FET.

[0183] Although Figure 12 Example description Figure 1 The fault controller circuit system 144, or more generally, the controller 104, is for a specific application, but the fault controller circuit system 144 or the controller 104 can be used in a variety of applications. For example, as described above, power converters such as boost converters can be used in a variety of applications including battery-powered devices, solar systems, and LED drivers. Other applications include voltage stabilizers and start-stop applications. In additional or alternative examples, Figure 1 The fault controller circuit system 144, or more generally, the controller 104, can be used in a half-bridge, a motor driver, and as a protection feature of a GaNFET, etc.

[0184] Figure 13 This is a block diagram of an example programmable circuit system platform 1300, which is structured to perform one or a combination of the following: execution or instantiation. Figure 7 Or one or more of the example machine-readable instructions or example operations in 11, to implement Figure 1 , 2 Controller 104 with 4, 8, or 9 pins. Programmable circuit system platform 1300 may be, for example, a server, personal computer, workstation, self-learning machine (e.g., neural network), mobile device (e.g., mobile phone, smartphone, e.g., iPad). TMTablet computers, DVD players, CD players, digital video recorders, Blu-ray players, game consoles, personal video recorders, set-top boxes, head-mounted devices (e.g., augmented reality (AR) head-mounted devices, virtual reality (VR) head-mounted devices, etc.) or other wearable devices, or any other type of computing or electronic device.

[0185] The programmable circuit system platform 1300 of the illustrated example includes a programmable circuit system 1312. The programmable circuit system 1312 of the illustrated example is hardware. For example, the programmable circuit system 1312 may be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, or microcontrollers from any desired family or manufacturer. The programmable circuit system 1312 may be implemented by one or more semiconductor-based (e.g., silicon-based) devices. In this example, the programmable circuit system 1312 is implemented... Figure 1 Example controller 104.

[0186] The programmable circuit system 1312 of the illustrated example includes local memory 1313 (e.g., cache, registers, etc.). The programmable circuit system 1312 of the illustrated example communicates via bus 1318 with main memories 1314 and 1316, which include volatile memory 1314 and non-volatile memory 1316. The volatile memory 1314 may be implemented by one or more synchronous dynamic random access memories (SDRAM), dynamic random access memories (DRAM), RAMBUS® dynamic random access memories (RDRAM®), or any other type of RAM device. The non-volatile memory 1316 may be implemented by flash memory or any other desired type of memory device, or a combination thereof. Access to the main memories 1314 and 1316 of the illustrated example is controlled by a memory controller 1317. In some instances, the memory controller 1317 may be implemented by one or more integrated circuits, logic circuits, microcontrollers from any desired series or manufacturer, or any other type of circuit system to manage the data flow to and from the main memories 1314 and 1316.

[0187] The programmable circuit system platform 1300 of the illustrated example also includes an interface circuit system 1320. The interface circuit system 1320 can be implemented in hardware according to any type of interface standard, such as an Ethernet interface, a Universal Serial Bus (USB) interface, a Bluetooth® interface, a Near Field Communication (NFC) interface, a Peripheral Component Interconnect (PCI) interface, or a Peripheral Component Interconnect High Speed ​​(PCIe) interface.

[0188] In the illustrated example, one or more input devices 1322 are connected to the interface circuitry 1320. The input devices 1322 allow a user (e.g., a human user, a machine user, etc.) to input one or a combination of data or commands into the programmable circuitry 1312. The input devices 1322 may be implemented as one or a combination of, for example, an audio sensor, a microphone, a camera (still or video), a keyboard, buttons, a mouse, a touchscreen, a trackpad, a trackball, a dot device, or a voice recognition system.

[0189] One or more output devices 1324 are also connected to the interface circuit system 1320 of the illustrated example. The output devices 1324 may be implemented, for example, by one or a combination of a display device (e.g., a light-emitting diode (LED), an organic light-emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, an in-situ switching (IPS) display, a touchscreen, etc.), a haptic output device, a printer, or a speaker. Therefore, the interface circuit system 1320 of the illustrated example includes one or a combination of a graphics driver card, a graphics driver chip, or a graphics processor circuit system such as a GPU.

[0190] The interface circuit system 1320 of the illustrated example also includes communication devices, such as one or a combination of a transmitter, receiver, transceiver, modem, residential gateway, wireless access point, or network interface, to facilitate the exchange of data with external machines (e.g., any kind of computing device) via network 1326. Communication can be carried out via, for example, Ethernet connection, digital subscriber line (DSL) connection, telephone line connection, coaxial cable system, satellite system, line-of-sight wireless system, line-of-sight wireless system, cellular telephone system, optical connection, etc.

[0191] The programmable circuit system platform 1300 of the illustrated example also includes one or more mass storage disks or devices 1328 for storing one or more of firmware, software, or data. Examples of such mass storage disks or devices 1328 include one or more magnetic storage devices (e.g., floppy disks, drives, HDDs, etc.), optical storage devices (e.g., Blu-ray discs, CDs, DVDs, etc.), RAID systems, or solid-state storage disks or devices, such as flash memory devices and SSDs.

[0192] can be Figure 7 The machine-readable instruction 1332 implemented by the machine-readable instruction 11 may be stored in one or a combination of a mass storage device 1328, a volatile memory 1314, a non-volatile memory 1316, or at least one non-transitory computer-readable storage medium (e.g., a removable CD or DVD).

[0193] Although Figure 1 , 2 The implementation is explained in sections 4, 8, and 9. Figure 1 The example way of controller 104, but Figure 1 , 2 One or more of the elements, processes, or apparatuses described in sections 4, 8, and 9 may be combined, divided, rearranged, omitted, eliminated, or implemented in any other way. Furthermore, Figure 1 , 2 Example controller 104, any of 4, 8, or 9, may be implemented by hardware alone or by a combination of hardware, software, and firmware. Thus, for example, example controller 104 may be implemented by a programmable circuit system combined with one or more machine-readable instructions (e.g., firmware or software), processor circuit system, analog circuitry, digital circuitry, logic circuitry, programmable processor, programmable microcontroller, graphics processing unit (GPU), digital signal processor (DSP), ASIC, programmable logic device (PLD), or field-programmable logic device (FPLD) (e.g., FPGA). Furthermore, Figure 1 , 2 Example controller 104, 4, 8, or 9, may include, in addition to Figure 1 , 2 It may include one or more elements, processes or devices other than or in place of the elements, processes or devices described in 4, 8 or 9, or may include more than one of any or all of the described elements, processes and devices.

[0194] Figure 7 Or 11 shows a flowchart representing example machine-readable instructions or example operations, the example machine-readable instructions being executable by a programmable circuit system to... Figure 1 , 2 The controller 104 of any one of 4, 8, or 9 is implemented or instantiated at least one of the example operations, which can be performed by a programmable circuit system to control... Figure 1 , 2 The controller 104 implements or instantiates at least one of the following: 4, 8, or 9. Machine-readable instructions may be provided by a programmable circuit system (e.g., hereinafter referred to as...). Figure 13 The example programmable circuit system platform 1300 described herein (programmable circuit system 1312) may execute one or more executable programs or portions of one or more executable programs, or may be one or more functions or portions of functions to be implemented by the example programmable circuit system (e.g., FPGA). In some instances, machine-readable instructions cause operations, tasks, etc., to be performed or carried out in a real-world manner in an automated manner. As used herein, “automation” means without human intervention.

[0195] The program may be embodied in instructions (e.g., at least one of software or firmware) stored on one or more non-transitory computer-readable or machine-readable storage media, such as one or a combination of the following: cache memory, magnetic storage device or disk (e.g., floppy disk, hard disk drive (HDD) etc.), optical storage device or optical disk (e.g., Blu-ray disc, optical disc (CD), digital versatile disc (DVD) etc.), redundant array of independent disks (RAID), register, ROM, solid-state drive (SSD), SSD memory, non-volatile memory (e.g., electrically erasable programmable read-only memory (EEPROM), flash memory, etc.), volatile memory (e.g., any type of random access memory (RAM) etc.), or any other storage device or storage disk. The instructions of the non-transitory computer-readable or machine-readable media may be programmed or executed by a programmable circuit system located in one or more hardware devices, but the entire program or a portion thereof may alternatively be implemented or instantiated or embodied in dedicated hardware by one or more hardware devices other than the programmable circuit system. Machine-readable instructions can be distributed across multiple hardware devices or executed by two or more hardware devices (e.g., server and client hardware devices). For example, client hardware devices can be implemented by endpoint client hardware devices (e.g., hardware devices associated with at least one of a human user or a machine user) or intermediate client hardware device gateways (e.g., radio access networks (RANs)) that facilitate communication between the server and endpoint client hardware devices. Similarly, non-transitory computer-readable storage media can comprise one or more media. Additionally, although references... Figure 7The flowchart illustrated in 11 describes an example program, but many other methods of implementing the example controller 104 can be used alternatively. For example, the execution order of one or more blocks of the flowchart can be changed, or some of the described blocks can be changed, eliminated, or combined. Additionally or alternatively, any or all blocks of the flowchart may be implemented by one or more hardware circuits (e.g., processor circuitry, discrete analog circuitry, discrete digital circuitry, integrated analog circuitry, integrated digital circuitry, FPGA, ASIC, comparator, operational amplifier, logic circuitry, etc.) that are structured to perform the corresponding operations without executing software or firmware. Programmable circuitry systems may be distributed across different network locations or local to one or more hardware devices (e.g., a single-core processor (e.g., a single-core CPU), a multi-core processor (e.g., a multi-core CPU, XPU, etc.)). As used herein, programmable circuitry systems comprise any type of circuitry that can be programmed to perform the desired function, such as one or a combination of a CPU or FPGA. A programmable circuit system may include: one or more CPUs and one or more FPGAs located in the same package (e.g., the same integrated circuit (IC) package or in two or more separate housings); one or more CPUs or FPGAs in a single machine; one or more CPUs or FPGAs distributed across multiple servers in a server rack; or multiple processors distributed across one or more server racks. Alternatively or additionally, in any of the contexts described above, a programmable circuit system may include a programmable logic device (PLD), a general-purpose array logic (GAL) device, a programmable array logic (PAL) device, a complex programmable logic device (CPLD), a simple programmable logic device (SPLD), a microcontroller unit (MCU), a system-on-a-chip (PSoC), or any combination thereof.

[0196] The machine-readable instructions described herein can be stored in one or more of the following formats: compressed format, encrypted format, segmented format, compiled format, executable format, and encapsulated format. The machine-readable instructions described herein can be stored as data (e.g., computer-readable data, machine-readable data, one or more bits (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), bit streams (e.g., computer-readable bit streams, machine-readable bit streams, etc.)) or data structures (e.g., portions of instructions, code, representations of code, etc.), which can be used to create, manufacture, or produce machine-executable instructions. For example, machine-readable instructions can be segmented and stored on one or more storage devices, disks, or computing devices (e.g., servers) located at the same or different locations within a network or network set (e.g., in the cloud, edge devices, etc.). Machine-readable instructions may require one or more of the following to be installed, modified, adapted, updated, combined, supplemented, configured, decrypted, decompressed, decapsulated, distributed, redistributed, compiled, etc., so that the machine-readable instructions can be directly read, interpreted, or executed by a computing device or other machine. For example, machine-readable instructions may be stored individually in multiple portions compressed, encrypted, or stored on separate computing devices, wherein the portions, when decrypted, decompressed, or combined, form an implementation that together can form a set of one or more computer-executable or machine-executable instructions for one or more functions or operations of a program such as those described herein.

[0197] In another instance, machine-readable instructions may be stored in a state that allows them to be read by a programmable circuit system, but additional libraries (e.g., dynamic link libraries (DLLs)), software development kits (SDKs), application programming interfaces (APIs), etc., are required to execute the machine-readable instructions on a particular computing device or another device. In yet another instance, the machine-readable instructions or their corresponding programs may need to be configured (e.g., storage settings, data input, recorded network addresses, etc.) before they can be executed wholly or partially. Therefore, machine-readable, computer-readable, or machine-readable media as used herein may contain one or a combination of instructions and programs, regardless of the specific format or state of the machine-readable instructions or programs.

[0198] The machine-readable instructions described in this article can be represented by any past, present, or future instruction set language, scripting language, programming language, etc. For example, machine-readable instructions can be represented using any of the following languages: C, C++, C-Sharp, etc.

[0199] As mentioned above, Figure 7Example operations of 11 may be implemented using executable instructions (e.g., at least one of computer-readable or machine-readable instructions) stored on one or more non-transitory computer-readable or machine-readable media. As used herein, the terms non-transitory computer-readable media, non-transitory computer-readable storage media, non-transitory machine-readable media, and non-transitory machine-readable storage media are expressly defined to include any type of computer-readable storage device or disk, excluding propagation signals and transmission media. Examples of such non-transitory computer-readable media, non-transitory computer-readable storage media, non-transitory machine-readable media, or non-transitory machine-readable storage media include one or more optical storage devices, magnetic storage devices, HDDs, flash memory, read-only memory (ROM), CDs, DVDs, caches, any type of RAM, registers, or any other storage device or disk, wherein information is stored for any duration (e.g., extended time period, permanent, transient, temporary buffer, cached information). As used herein, the terms "non-transitory computer-readable storage device" and "non-transitory machine-readable storage device" are defined as comprising any physical (mechanical, magnetic, electromechanical, or electrical) hardware designed to retain information for a period of time, excluding the propagation of signals and the transmission medium. Examples of non-transitory computer-readable storage devices or non-transitory machine-readable storage devices include one or a combination of the following: any type of random access memory, any type of read-only memory, solid-state memory, flash memory, optical disk, magnetic disk, disk drive, or redundant array of independent disks (RAID) system. As used herein, the term "device" refers to a physical structure, such as one or a combination of the following: mechanical, electromechanical, or electrical equipment, hardware, or circuitry that may or may not be configured by, or manufactured to execute, computer-readable instructions, machine-readable instructions, etc.

[0200] "Including" and "comprising" (and all their forms and tenses) are used herein as open terms. Therefore, whenever a claim uses any form of "including" or "comprising" (e.g., includes, includes, comprising, having, etc.) as a preamble or in any type of claim statement, additional elements, terms, etc., may be present without exceeding the scope of the corresponding claim or statement. As used herein, when the phrase "at least" is used as a transitional term, for example, in the preamble of a claim, it is open in the same way as the terms "including" and "comprising" are open. As used herein in the context of describing structures, components, items, objects, and things, the phrase "at least one of A and B" means an embodiment comprising any one of: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, projects, objects, and things, the phrase “at least one of A or B” means an implementation that includes any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. As used herein in the context of describing the implementation or execution of processes, instructions, actions, activities, etc., the phrase “at least one of A or B” means an implementation that includes any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing the execution or performance of processes, instructions, actions, activities, etc., the phrase “at least one of A or B” means an implementation that includes any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.

[0201] As used herein, singular references (e.g., “a(a)”, “an”, “first”, “second”, etc.) do not exclude plurals. As used herein, the term “a(a)” or “an” refers to one or more of the objects mentioned. The terms “a(a) or an,” “one or more,” and “at least one” are used interchangeably herein. Furthermore, although listed separately, multiple components, elements, or actions may be performed by, for example, the same entity or object. Additionally, while individual features may be included in different instances or claims, these features may be combined, and their inclusion in different instances or claims does not imply that at least one of the combinations of features is impractical or disadvantageous.

[0202] As used herein, unless otherwise indicated, a connection reference (e.g., fitting, coupling, connection, and joining) may include an intermediate member between elements referenced by at least one of the connection references between those elements or by their relative movement. Thus, a connection reference does not necessarily imply that two elements are directly connected or fixed to each other.

[0203] Unless otherwise specifically stated, descriptive terms such as “first,” “second,” and “third” are used herein without intending to or otherwise indicate priority, physical order, arrangement, or any sorting in the list, but are used only as markers or arbitrary names to distinguish elements in order to facilitate understanding of the described instance. In some instances, the descriptive term “first” may be used to refer to an element in a particular embodiment, while the same element may be referred to in the technical solution by different descriptive terms such as “second” or “third.” In such instances, these descriptive terms are used only to clearly identify those elements within the context of the specification (e.g., within the claims), in which elements may otherwise share the same name.

[0204] As used herein, the phrase “communication” includes variations thereof, encompassing one or a combination of direct communication or indirect communication through one or more intermediate components, and does not require direct physical (e.g., wired) communication or constant communication, but also includes selective communication at at least one of periodic intervals, predetermined intervals, non-periodic intervals, or one-off events.

[0205] As used herein, a “programmable circuit system” may include: (i) one or more special-purpose circuits (e.g., special-purpose circuits (ASICs)) that are structured to perform specific operations and include one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), or (ii) one or more general-purpose semiconductor-based circuits that can be programmed with instructions to perform one or more specific functions or operations and include one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuit systems include programmable microprocessors, such as: a central processing unit (CPU) capable of executing first instructions to perform one or more operations or functions; a field-programmable gate array (FPGA) programmable with second instructions to configure or structure at least one of the FPGAs, thereby instantiating one or more operations or functions corresponding to the first instructions; a graphics processing unit (GPU) capable of executing first instructions to perform one or more operations or functions; a digital signal processor (DSP) capable of executing first instructions to perform one or more operations or functions; an XPU; a network processing unit (NPU); one or more microcontrollers capable of executing first instructions to perform one or more operations or functions; or an integrated circuit, such as an application-specific integrated circuit (ASIC). For example, an XPU can be implemented by a heterogeneous computing system that includes various types of programmable circuit systems (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc., and any combination thereof) and configuration technologies (e.g., application programming interfaces (APIs)) that can distribute computing tasks to any one or more types of programmable circuit systems that are suitable and can be used to perform the computing tasks.

[0206] As used herein, an integrated circuit / circuit system can be understood as one or more semiconductor packages containing one or more circuit elements, such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example, an integrated circuit can be implemented as one or more of an ASIC, FPGA, chip, microchip, programmable circuit system, semiconductor substrate coupling multiple circuit elements, system-on-a-chip (SoC), etc.

[0207] In this specification, the term "coupled" may encompass a connection, communication, or signaling path that enables the functional relationship to be consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B via a direct connection; or (b) in a second instance, device A is coupled to device B via an intermediate component C, wherein the intermediate component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via a control signal generated by device A.

[0208] A device “configured to” perform a task or function may be configured (e.g., programmed or hardwired at least) to perform the function during manufacturing by the manufacturer, or may be configured (or reconfigurable) by the user after manufacturing to perform the function or at least other additional or alternative functions. The configuration may be performed by at least one of the device’s firmware or software programming, by at least one of the construction or layout of the device’s hardware components and interconnects, or by a combination thereof.

[0209] As used herein, the terms “terminal,” “node,” “interconnect,” “pin,” and “lead” are used interchangeably. Unless specifically stated otherwise, these terms are generally used to refer to interconnections or ends between device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components.

[0210] In this specification and claims, the “circuit system” described may include one or more circuits. A circuit or device described herein as including certain components may be substantially adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., one or a combination of resistors, capacitors, or inductors), or one or more sources (e.g., at least one of voltage sources or current sources) may substantially include only semiconductor elements within a single physical device (e.g., at least one of a semiconductor die or integrated circuit (IC) package) and may be adapted to be coupled at manufacturing time or after manufacturing time, for example by at least one of an end user or a third party, to at least some of the passive elements or sources to form the described structure.

[0211] The circuits described herein can be reconfigured to include replacement components to provide functionality at least partially similar to that available before the component replacement. Unless otherwise stated, components shown as resistors generally represent one or more elements coupled in at least one of series or parallel to provide the amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may alternatively be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may actually be multiple resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor. While some elements in the described examples are included in the integrated circuit and others are outside the integrated circuit, in other examples, additional or fewer features may be incorporated into the integrated circuit. Additionally, some or all features described as being outside the integrated circuit may be included in the integrated circuit, and some features described as being inside the integrated circuit may be incorporated outside the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that are at least one of the following: (i) incorporated in / above a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated in the same module; or (iv) incorporated in / on the same printed circuit board.

[0212] The use of the phrase “grounding” in the foregoing description includes at least one of chassis grounding, ground wire grounding, floating grounding, virtual grounding, digital grounding, general grounding, or any other form of grounding connection applicable to or suited to the teachings of this specification.

[0213] As used herein, “approximately,” “about,” and “substantially” modify their subject / value to identify the potential for variation in real-world applications. For example, “approximately,” “about,” and “substantially” may modify dimensions or values ​​that may be imprecise due to at least one of manufacturing tolerances or other real-world defects. Unless otherwise stated, “about,” “approximately,” or “substantially” preceding a value indicates + / - 10% of said value, or, if the value is zero, a reasonable range of values ​​near zero.

[0214] As should be understood from the above, example systems, devices, articles, and methods for fault protection of GaN DC-DC converters have been described. For example, in the case of a boost converter, in the event of a fault, the described systems, devices, articles, and methods protect the high-side FET of the power converter from excessive power dissipation by enabling the high-side FET after the output voltage from the power converter drops below the input voltage of the power converter.

[0215] To achieve smooth fault exit behavior, the example described herein clamps the soft-start pin of the power converter to an equal value to the output voltage during a fault. When the fault is cleared, the example described herein ramps the output voltage to a target voltage defined by a capacitor coupled to the soft-start pin. The example described also monitors the controller's internal supply voltage to differentiate fault behavior.

[0216] The described systems, apparatus, articles, and methods improve the efficiency of computing devices by preventing damage to power FETs during faults, reducing disturbances in the output voltage of the power converter upon fault exit, and reducing inrush current to the load upon fault exit. Furthermore, system design is simplified when implementing the examples described herein because no external components to the power converter are required to protect the high-side FETs from damage during faults. The described systems, apparatus, articles, and methods also relate to one or more improvements in the operation of machines such as computers or other electronic, electromechanical, or mechanical devices.

[0217] Modifications to the described examples are possible within the scope of the claims, and other examples are also possible.

Claims

1. A power converter controller, comprising: A driver having a first input and a second input; A comparator having a first input coupled to an output voltage feedback terminal, a second input coupled to an input voltage terminal, and an output; as well as A logic circuit system having a fault input, a second input coupled to the output of the comparator, a first output coupled to the first input of the driver, and a second output coupled to the second input of the driver, the logic circuit system being capable of: The driver receives a first signal indicating a fault event at the fault input and responsively provides a first control signal to the driver to disable the transistor of the power converter. Receive a second signal from the comparator indicating that the input voltage of the power converter exceeds the output voltage of the power converter; as well as In response to the first signal and the second signal, a second control signal is provided to the driver to enable the transistor of the power converter.

2. The power converter controller of claim 1, further comprising an overcurrent detection circuit system having an output coupled to the fault input.

3. The power converter controller according to claim 2, wherein the comparator is a first comparator, and the overcurrent detection circuit system comprises: The second comparator has a first input coupled to a first sensing terminal, a second input coupled to a second sensing terminal, and an output coupled to the fault input.

4. The power converter controller of claim 1, further comprising an over-temperature detection circuit system having an output coupled to the fault input.

5. The power converter controller according to claim 4, wherein the over-temperature detection circuit system includes a temperature sensor.

6. The power converter controller of claim 1, wherein the comparator is a first comparator, and the power converter controller further comprises: The second comparator has a first input coupled to a supply voltage terminal, a second input coupled to a reference voltage terminal, and an output coupled to a supply state input of the logic circuit system.

7. The power converter controller according to claim 1, wherein the logic circuit system is a first logic circuit system, the comparator is a first comparator, and the power converter controller further comprises: A second comparator has a first input, a second input, and an output, wherein the first input of the second comparator is coupled to a sensing terminal, and the output of the second comparator is coupled to a third input of the logic circuit system. An amplifier having a first input, a second input, and an output, wherein the first input of the amplifier is coupled to the output voltage feedback terminal, and the output of the amplifier is coupled to the second input of a second comparator; A second logic circuit system has a first input, a second input, and an output. The first input of the second logic circuit system is coupled to a reference voltage terminal, the second input of the second logic circuit system is coupled to a soft-start terminal, and the output of the second logic circuit system is coupled to the second input of the amplifier. as well as A third logic circuit system has a first input coupled to a third output of the first logic circuit system, a second input coupled to a supply voltage terminal, a third input coupled to the output voltage feedback terminal, and an output coupled to the second input of the second logic circuit system.

8. The power converter controller of claim 1, wherein the comparator is a first comparator, and the power converter controller further comprises: The second comparator has a first input coupled to a first sensing terminal, a second input coupled to a second sensing terminal, and an output; A slope compensation circuit system with an output; A mixer having a first input coupled to the output of the second comparator, a second input coupled to the output of the slope compensation circuit system, and an output; A third comparator has a first input, a second input, and an output, wherein the first input of the third comparator is coupled to the output of the mixer, and the output of the third comparator is coupled to the third input of the logic circuit system; as well as An amplifier having a first input coupled to a reference voltage terminal, a second input coupled to the output voltage feedback terminal, and an output coupled to the second input of the third comparator.

9. The power converter controller of claim 8, further comprising an over-temperature detection circuit system having an output coupled to the fault input.

10. The power converter controller of claim 9, wherein the logic circuit system is a first logic circuit system, and the power converter controller further comprises: A second logic circuit system having a first input, a second input, and an output, wherein the first input of the second logic circuit system is coupled to the reference voltage terminal, the second input of the second logic circuit system is coupled to the soft-start terminal, and the output of the second logic circuit system is coupled to the first input of the amplifier; as well as A third logic circuit system has a first input coupled to a third output of the first logic circuit system, a second input coupled to a supply voltage terminal, a third input coupled to the output voltage feedback terminal, and an output coupled to the second input of the second logic circuit system.

11. The power converter controller of claim 10, wherein the reference voltage terminal is a first reference voltage terminal, and the power converter controller further includes a fourth comparator having a first input coupled to the supply voltage terminal, a second input coupled to the second reference voltage terminal, and an output coupled to the supply state input of the logic circuit system.

12. A power converter circuit, comprising: The first transistor has a control terminal, a first terminal, and a second terminal; The second transistor has a control terminal, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to the first reference voltage terminal. as well as A controller having a first output coupled to the control terminal of the first transistor and a second output coupled to the control terminal of the second transistor, the controller comprising: A driver having a first input, a second input, a first output coupled to the control terminal of the first transistor, and a second output coupled to the control terminal of the second transistor; A control logic circuit system having a first input, a second input, a third input, a first output coupled to the first input of the driver, and a second output coupled to the second input of the driver; A fault logic circuit system having an input, a first output coupled to a first input of the control logic circuit system, and a second output coupled to a second input of the control logic circuit system; A first comparator has a first input coupled to an output voltage feedback terminal, a second input coupled to an input voltage terminal, and an output coupled to the input of the fault logic circuit system; The second comparator has a first input coupled to a first sensing terminal, a second input coupled to a second sensing terminal, and an output; A slope compensation circuit system with an output; A mixer having a first input coupled to the output of the second comparator, a second input coupled to the output of the slope compensation circuit system, and an output; A third comparator has a first input and a second input coupled to the output of the mixer, and an output coupled to the third input of the control logic circuit system; and An amplifier having a first input coupled to a second reference voltage terminal, a second input coupled to the output voltage feedback terminal, and an output coupled to the second input of the third comparator.

13. The power converter circuit of claim 12, wherein the input of the fault logic circuit system is a first input, and the controller further includes an over-temperature detection circuit system having an output coupled to a second input of the fault logic circuit system.

14. The power converter circuit of claim 13, wherein the over-temperature detection circuit system includes a temperature sensor.

15. The power converter circuit according to claim 13, further comprising: A selection logic circuit system having a first input, a second input, and an output, wherein the first input of the selection logic circuit system is coupled to a second reference voltage terminal, the second input of the selection logic circuit system is coupled to a soft-start terminal, and the output of the selection logic circuit system is coupled to the first input of the amplifier; as well as A switching logic circuit system having a first input coupled to the first output of the fault logic circuit system, a second input coupled to the supply voltage terminal, a third input coupled to the output voltage feedback terminal, and an output coupled to the second input of the selection logic circuit system.

16. The power converter circuit of claim 15, wherein the power converter circuit further comprises a fourth comparator having a first input coupled to the supply voltage terminal, a second input coupled to the third reference voltage terminal, and an output coupled to the third input of the fault logic circuit system.

17. A system comprising: A loudspeaker that has an input; An audio amplifier having an input and an output coupled to the input of the speaker; as well as A power converter having an output coupled to the input of the audio amplifier, the power converter comprising: The first transistor has a control terminal, a first terminal, and a second terminal; The second transistor has a control terminal, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to a reference voltage terminal. An inductor having a first terminal and a second terminal, the first terminal being coupled to the second terminal of the first transistor and the first terminal of the second transistor; A driver having a first input, a second input, a first output coupled to the control terminal of the first transistor, and a second output coupled to the control terminal of the second transistor; A control logic circuit system having a first input, a second input, a first output coupled to the first input of the driver, and a second output coupled to the second input of the driver; A fault logic circuit system having an input, a first output coupled to a first input of the control logic circuit system, and a second output coupled to a second input of the control logic circuit system; and A comparator having a first input coupled to an output voltage feedback terminal, a second input coupled to an input voltage terminal, and an output coupled to the input of the fault logic circuit system.

18. The system of claim 17, wherein the input of the fault logic circuit system is a first input, the comparator is a first comparator, and the power converter further comprises: A temperature sensor having an output coupled to a second input of the fault logic circuit system; The second comparator has a first input coupled to a first sensing terminal, a second input coupled to a second sensing terminal, and an output; A slope compensation circuit system with an output; A mixer having a first input coupled to the output of the second comparator, a second input coupled to the output of the slope compensation circuit system, and an output; A third comparator has a first input and a second input coupled to the output of the mixer, and an output coupled to a third input of the control logic circuit system; as well as An amplifier having a first input coupled to a second reference voltage terminal, a second input coupled to the output voltage feedback terminal, and an output coupled to the second input of the third comparator.

19. The system of claim 18, wherein the power converter further comprises: A selection logic circuit system having a first input, a second input, and an output, wherein the first input of the selection logic circuit system is coupled to a second reference voltage terminal, the second input of the selection logic circuit system is coupled to a soft-start terminal, and the output of the selection logic circuit system is coupled to the first input of the amplifier; as well as A switching logic circuit system having a first input coupled to the first output of the fault logic circuit system, a second input coupled to the supply voltage terminal, a third input coupled to the output voltage feedback terminal, and an output coupled to the second input of the selection logic circuit system.

20. The system of claim 19, wherein the power converter further comprises a fourth comparator having a first input coupled to the supply voltage terminal, a second input coupled to the third reference voltage terminal, and an output coupled to the third input of the fault logic circuit system.

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