Power factor correction circuit and current sampling method of control chip

Abstract

The application provides a power factor correction circuit and a current sampling method of a control chip, the power factor correction circuit comprising a control chip and a compensation circuit, the compensation circuit compensating the amplitude of an input current sampling signal by extracting the input voltage amplitude of a power factor correction module and performing negative proportional adjustment, the compensation amplitude being proportional to the input voltage amplitude; further, the compensation circuit obtains a reference signal same as the input current waveform through a first divider to limit the amplitude of the compensated voltage signal, the application stabilizes the amplitude of the compensated signal at a suitable amplitude through a first adder; meanwhile, the application introduces an output signal through a second multiplier, so that the compensation value is adjusted with the output power when the output power changes, to ensure that the voltage signal amplitude finally input into the ISENSE pin remains consistent under different output power conditions, thereby ensuring the THD of the input current.

Description

Technical Field

[0001] This invention belongs to the field of electronic circuit technology, specifically relating to a current sampling method for a power factor correction circuit and control chip. Background Technology

[0002] Currently, active power factor correction (APFC) technology is mainly used in general high-power power supply products. This technology can be implemented through analog control based on a "dedicated analog chip + external compensation loop". It is the most mature and widely used solution in AC-DC solutions. In the dedicated analog chip, the control chip based on average current control enables PFC to operate in continuous current conduction mode (CCM), resulting in smaller input current ripple, naturally reducing harmonic distortion, and stronger current stability under load fluctuations. Therefore, PFC has the advantages of easy suppression of electromagnetic interference and high power factor (PF) in this mode. However, when using this type of chip, its current sampling pin ISENSE is suitable for handling a certain amplitude of sampling voltage. When the input voltage is high or the load is light, the voltage signal amplitude generated by the sampling resistor is too low, approaching the offset voltage and noise limit of the chip's current amplifier, resulting in a decrease in signal-to-noise ratio, deterioration of current sampling accuracy, insufficient current loop control gain, and easy occurrence of current tracking lag and increased waveform distortion at the voltage zero crossing point, which increases total harmonic distortion (THD) and deteriorates the power factor.

[0003] Currently, analog control schemes using "dedicated analog chips + peripheral compensation loops" all suffer from the problem of decreased THD of PFC input current when the input voltage is too high. Many solutions address the issue of decreased THD of PFC input current when operating in CRM mode by directly compensating for the conduction time of the main switch at the zero-crossing point of the input voltage. The control chip has a ZCD pin, which can be directly configured.

[0004] Existing technologies mainly address the issue of input current THD variation in PFC operating in CRM (Critical Current Mode), and are not applicable to PFC operating in CCM (Continuous Current Mode). Furthermore, compensation for PFC operating in CRM does not require current signal extraction, and therefore cannot be applied to PFC operating in CCM.

[0005] In addition, if the PFC output is not discharged in time after power failure, the residual high voltage will be sent to the PFC chip through voltage division when it is quickly turned on in a short period of time. This will cause the voltage sampling circuit to make a deviation, which can easily cause startup oscillation or instability. Furthermore, abnormal voltage stress will accelerate capacitor aging, reduce the overall reliability and service life of the power supply, and the presence of high voltage residual voltage will pose a risk of electric shock to people.

[0006] The information disclosed in this background section is only intended to enhance the understanding of the background technology of this application, and therefore may include prior art that is not known to those skilled in the art. Summary of the Invention

[0007] This invention addresses the aforementioned problems in the prior art by proposing a current sampling method for a power factor correction circuit and control chip, thus resolving the technical problem of deteriorating THD of the PFC input current when using average current control in CCM mode.

[0008] To achieve the above-mentioned objectives, the present invention employs the following technical solution: A power factor correction circuit includes a power factor correction module, a control chip, and a compensation circuit. The compensation circuit is connected to the current sampling signal pin of the control chip. The compensation circuit includes: An input voltage conditioning circuit is used to negatively proportionally adjust the amplitude of the input voltage of the power factor correction module. An input current sampling circuit is used to sample the input current of the power factor correction module through an input sampling resistor; The first adder is used to perform addition processing on the outputs of the input current sampling circuit and the input voltage conditioning circuit; The first inverting proportional circuit is used to perform inverting proportional adjustment on the input voltage of the power factor correction module; The second inverting proportional circuit is used to invert and proportionally adjust the output of the input current sampling circuit. The first multiplier is used to receive the outputs of the first and second inverting proportional circuits and perform multiplication. The first divider is used to perform division on the output of the first multiplier and the reference voltage; A subtractor is used to perform subtraction on the outputs of the first divider and the first adder; An output current sampling circuit is used to sample the output current of the power factor correction module through an output sampling resistor; The second divider is used to perform division on the reference voltage for amplitude adjustment and the output of the output current sampling circuit. The second multiplier is used to perform multiplication on the output of the subtractor and the output of the second divider; The second adder is used to add the outputs of the first adder and the second multiplier and then output a signal to the current sampling signal pin of the control chip.

[0009] In the power factor correction circuit described above, the input voltage conditioning circuit receives the input voltage v from the power factor correction module. rec And by performing a negative proportional adjustment, k1v is obtained. rec ; The input sampling resistor R sense1Connected between the rectifier bridge and the power factor correction module ground, the input current sampling circuit obtains a sampled input voltage signal of -i after sampling. in R sense1 ; The output signal of the first adder after adding the outputs of the input current sampling circuit and the input voltage conditioning circuit is -i. in R sense1 +k1v rec ; The first inverting proportional circuit affects the input voltage v of the power factor correction module. rec K3V is obtained by performing inverse proportional adjustment. rec ; The second inverting proportional circuit outputs -i to the input current sampling circuit. in R sense1 k4i is obtained by performing an inverse proportional adjustment; The first adder performs addition processing on the outputs of the input current sampling circuit and the input voltage conditioning circuit to obtain -i in R sense1 +k1v rec ; The first multiplier multiplies the outputs of the first and second inverting proportional circuits to obtain k. p P in ; The first divider performs a division operation on the first multiplier and the reference voltage to obtain k. p P in / v REF ; The subtractor subtracts the output of the first divider and the output of the first adder to obtain k. p P in / v REF -(-i in R sense1 +k1v rec ); The output sampling resistor R sense2 Connected between the power factor correction module ground and the load, the output current sampling circuit obtains a sampled output voltage signal of V. sense2 =IoR sense2 ; The second divider divides the amplitude-adjustable reference voltage and the output of the output current sampling circuit to obtain k. I V REF / v sense2 ; The second multiplier multiplies the output of the subtractor and the output of the second divider to obtain k. IV REF / v sense2 [k p P in / v REF -(-i in R sense1 +k1v rec )]; The second adder performs addition on the outputs of the first adder and the second multiplier to obtain the signal sent to the current sampling signal pin of the control chip: -i in R sense1 +k1v rec +k I V REF / v sense2 [k p P in / v REF -(-i in R sense1 +k1v rec )].

[0010] The power factor correction circuit described above includes a discharge circuit, which comprises a depletion-mode NMOS transistor Q and a first power resistor R. se Second power resistor R disc The normally closed relay T, the drain and gate of the depletion-type NMOS transistor Q are connected to the two ends of the load, and a first power resistor R is connected in series between the gate and source of the depletion-type NMOS transistor Q. se Second power resistor R disc The normally closed relay's switching section is connected in parallel to the first power resistor R. se When the power factor correction module is powered on, the normally closed relay is energized and disconnects the switching part; when the power factor correction module is powered off, the normally closed relay is de-energized and the switching part is normally closed. The first power resistor R... se The resistance is greater than that of the second power resistor R. disc The resistance value.

[0011] A current sampling method for a power factor correction circuit control chip, the method comprising: Input voltage conditioning involves negatively proportionally adjusting the amplitude of the input voltage to the power factor correction module to obtain the input voltage conditioning signal. Input current sampling: The input current of the power factor correction module is sampled through the input sampling resistor to obtain the input current sampling signal; The first addition process involves adding the input voltage conditioning signal and the input current sampling signal to obtain the first addition processing signal; The first inverting proportional adjustment is performed on the input voltage of the power factor correction module to obtain the first inverting proportional adjustment signal; The second inverting proportional adjustment is performed on the input current sampling signal to obtain the second inverting proportional adjustment signal; The first multiplication process involves multiplying the first inverting proportional control signal and the second inverting proportional control signal to obtain the first multiplication processed signal. The first division process involves dividing the first multiplication signal and the reference voltage to obtain the first division signal. Subtraction processing involves subtracting the first division processing signal and the first addition processing signal to obtain a subtraction processing signal; Output current sampling: The output current of the power factor correction module is sampled through the output sampling resistor to obtain the output current sampling signal; The second division process involves dividing the amplitude-adjusted reference voltage and the output current sampling signal to obtain the second division processed signal. The second multiplication process involves multiplying the subtraction signal and the second division signal to obtain the second multiplication signal. The second addition process adds the first addition signal and the second multiplication signal together and outputs the result to the current sampling signal pin of the control chip.

[0012] The current sampling method for the power factor correction circuit control chip described above includes: The input voltage v of the power factor correction module rec A negative proportional adjustment is performed to obtain the input voltage conditioning signal k1v. rec ; Input sampling resistor R sense1 Connected between the rectifier bridge and the power factor correction module ground, through the input sampling resistor R sense1 The input current of the power factor correction module is sampled, and the resulting input current sampling signal is -i. in R sense1 ; The input voltage conditioning signal k1v rec and input current sampling signal -i in R sense1 The output signal after addition is -i in R sense1 +k1v rec ; The input voltage v of the power factor correction module rec The first inverting proportional adjustment is performed to obtain the first inverting proportional adjustment signal k3v. rec ; The input current sampling signal -i in R sense1 Perform inverse proportional adjustment to obtain the second inverse proportional adjustment signal k4i; The input current sampling signal -i in R sense1 and input voltage conditioning signal k1v rec The first addition signal -i is obtained by performing addition processing. in R sense1 +k1v rec ; The first inverting proportional adjustment signal k3v rec The first multiplication signal k is obtained by multiplying the second inverting proportional adjustment signal k4i. p P in ; The first multiplication process signal k p P in and reference voltage v REF The first division signal k is obtained by performing division. p P in / v REF ; The first division processing signal k p P in / v REF and the first addition signal (-i) in R sense1 +k1v rec Subtraction is performed to obtain the subtraction signal k. p P in / v REF -(-i in R sense1 +k1v rec ); Through the output sampling resistor R sense2 The output current of the power factor correction module is sampled to obtain the output current sampling signal V. sense2 =IoR sense2 ; The reference voltage k for amplitude adjustment I V REF and output current sampling signal V sense2 The second division signal k is obtained by performing division. I V REF / v sense2 ; Subtraction processing signal k p P in / v REF -(-i in R sense1+k1v rec ) and the second division processing signal k I V REF / v sense2 The second multiplication signal k is obtained by performing multiplication. I V REF / v sense2 [k p P in / v REF -(-i in R sense1 +k1v rec )]; The outputs of the first addition signal and the second multiplication signal are added together to obtain the current sampling signal pin of the control chip, which is: -i in R sense1 +k1v rec +k I V REF / v sense2 [k p P in / v REF -(-i in R sense1 +k1v rec )].

[0013] Compared with the prior art, the advantages and positive effects of the present invention are as follows: The power factor correction circuit of the present invention includes a control chip and a compensation circuit. The compensation circuit is connected to the current sampling signal pin of the control chip. The compensation circuit includes an input voltage conditioning circuit, an input current sampling circuit, a first adder, a first inverting proportional circuit, a second inverting proportional circuit, a first multiplier, a first divider, a subtractor, an output current sampling circuit, a second divider, a second multiplier, and a second adder. The input voltage conditioning circuit is used to negatively proportionally adjust the input voltage amplitude of the power factor correction module; the input current sampling circuit is used to sample the input current of the power factor correction module through an input sampling resistor; the first adder is used to add the outputs of the input current sampling circuit and the input voltage conditioning circuit; the second adder... First, the second inverting proportional circuit performs inverting proportional adjustment on the input voltage and the output of the input current sampling circuit of the power factor correction module, respectively; the first multiplier performs multiplication on the outputs of the first and second inverting proportional circuits, and the first divider performs division on the output of the first multiplier and the reference voltage; the subtractor performs subtraction on the outputs of the first divider and the first adder; the output current sampling circuit samples the output current of the power factor correction module through the output sampling circuit; the second divider performs division on the reference voltage of amplitude adjustment and the output of the output current sampling circuit; the second multiplier performs multiplication on the outputs of the subtractor and the second divider; and the second adder performs addition on the outputs of the first adder and the second multiplier, and then outputs a signal to the current sampling signal pin of the control chip. The compensation circuit in this invention compensates for the amplitude of the input current sampling signal by extracting the input voltage amplitude from the power factor correction module and adjusting it proportionally. The compensation amplitude is directly proportional to the input voltage amplitude; that is, a small input voltage amplitude corresponds to a large input current, resulting in a small compensation amplitude, and a large input voltage amplitude corresponds to a small input current, resulting in a large compensation amplitude. Furthermore, the compensation circuit obtains a reference signal with the same waveform as the input current through a first divider to limit the amplitude of the compensated voltage signal. This invention stabilizes the amplitude of the compensated signal at a suitable amplitude using a first adder. Simultaneously, an output signal is introduced through a second multiplier, so that the compensation value adjusts with the output power as the output power changes, ensuring that the amplitude of the voltage signal finally sent to the ISENSE pin remains consistent under different output power conditions, thereby guaranteeing the THD of the input current.

[0014] Other features and advantages of the present invention will become clearer after reading the detailed embodiments of the invention in conjunction with the accompanying drawings. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of a power factor correction circuit applicable to a specific embodiment of the present invention.

[0017] Figure 2 This is a schematic diagram of the rectifier bridge and power factor correction module in a specific embodiment of the present invention.

[0018] Figure 3 This is a schematic diagram of a power factor correction circuit according to a specific embodiment of the present invention.

[0019] Figure 4 This is a schematic diagram of a power factor correction circuit according to another specific embodiment of the present invention.

[0020] Figure 5 A compensation diagram when the input voltage is slightly biased towards the intermediate voltage value.

[0021] Figure 6 A compensation diagram when the input voltage is significantly biased towards the intermediate voltage value.

[0022] Figure 7 This is a diagram illustrating the first compensation value being less than the limit.

[0023] Figure 8 for Figure 7 The compensation diagram is generated by subtracting the first compensation value from the limit signal.

[0024] Figure 9 This is a diagram illustrating the first compensation value exceeding the limit.

[0025] Figure 10 for Figure 9 The compensation diagram is generated by subtracting the first compensation value from the limit signal.

[0026] Figure 11 This is a schematic diagram of the discharge circuit for a power factor correction circuit.

[0027] Figure 12 This is a schematic diagram of the current limiting function in the discharge circuit. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings.

[0029] This embodiment uses input voltage feedforward to compensate for the amplitude of the voltage signal across the sampling resistor, ensuring that the voltage fed into the control chip is within a reasonable range. At the same time, an output capacitor discharge circuit is added, which can be used as a dummy load during normal operation. After the PFC is powered off, it automatically discharges the output capacitor with a fixed proportion of current.

[0030] This embodiment is applied to situations such as Figure 1 As shown, the 90VAC-264VAC wide-range AC input is rectified and then fed into the input side of the PFC main power section. Its input current and output voltage are fed back to the control chip for drive control. For the control chip, the amplitude of the received current sampling signal should be within a certain range, and the corresponding pin often has a built-in clamping circuit. That is, the amplitude of the current sampling signal cannot exceed its limit; otherwise, the signal will be clamped, affecting the PFC output.

[0031] To ensure that the current sampling signal amplitude remains appropriate across a wide input voltage range and does not exceed the limit, this embodiment adds a compensation circuit to the front end of the ISENSE pin of the control chip's current sampling signal. Specific details of the PFC circuit and the control compensation circuit can be found in [link to documentation]. Figures 2-3 Current amplitude compensation compensates for the sampled current amplitude by extracting and conditioning the rectified input voltage. The compensation amplitude is proportional to the input voltage amplitude; that is, a small input voltage amplitude corresponds to a large input current, resulting in a small compensation amplitude, and a large input voltage amplitude corresponds to a small input current, resulting in a large compensation amplitude.

[0032] like Figure 3 As shown, a power factor correction circuit includes a rectifier bridge, a power factor correction module, a control chip, and a compensation circuit. The compensation circuit is connected to the current sampling signal pin of the control chip. The compensation circuit includes an input voltage conditioning circuit, an input current sampling circuit, and a first adder.

[0033] The input voltage conditioning circuit is used to negatively proportionally adjust the input voltage amplitude of the power factor correction module.

[0034] The input current sampling circuit is used to sample the input current of the power factor correction module through the input sampling resistor.

[0035] The first adder is used to add the outputs of the input current sampling circuit and the input voltage conditioning circuit, and then output the signal to the current sampling signal pin of the control chip.

[0036] The input voltage conditioning circuit receives the input voltage V from the power factor correction module. rec And by performing a negative proportional adjustment, k1v is obtained. rec ; Input sampling resistor R sense1Connected between the rectifier bridge and the power factor correction module ground, the input current sampling circuit obtains an input current sampling signal of -i after sampling. in R sense1 ; The output signal of the first adder after adding the outputs of the input current sampling circuit and the input voltage conditioning circuit is -i. in R sense1 +k1v rec .

[0037] When the PFC output power is fixed, the input current changes with the input voltage, and the current flows through the input sampling resistor R. sense1 The voltage signal -i obtained after sampling in R sense1 The amplitude will also constantly change. A small amplitude will result in a low signal-to-noise ratio, making it impossible for the signal sent to the control chip to be accurately identified, thus affecting the input current THD. An excessively large amplitude will exceed the pin limit, causing the input current to be clipped. In this embodiment, the PFC input voltage signal is introduced into the input current sampling signal and added to the input current sampling signal, i.e., the sampling signal is -i. in R sense1 +k1v rec , where k1 < 0.

[0038] The optimal current sampling signal amplitude is considered when the input voltage is at its midpoint. The degree of compensation varies depending on how much the input voltage deviates from the midpoint. With a constant input power (Pin), as the positive deviation of the input voltage from the midpoint gradually increases, the decrease in input current gradually increases, and the current sampling signal amplitude -i... in R sense1 Absolute value |-i in R sense1 | The rate of decrease gradually increases. For example Figure 5 and Figure 6 As shown in the figure, the dashed line represents the amplitude of the current sampling signal (voltage signal) when the input voltage is at the intermediate voltage, and the solid line represents the amplitude of the current sampling signal (voltage signal) when the input voltage signal is positively biased. Figure 5 This diagram illustrates compensation when the input voltage is only slightly biased to the middle voltage value. For example, with a median voltage of 220V and a forward bias input voltage of 225V, the forward bias value is 5V, which is a small amplitude. Figure 6 This diagram illustrates compensation when the input voltage is significantly forward biased from the midpoint. For example, with a midpoint voltage of 220V and a forward bias input voltage of 240V, the forward bias is 20V, which is a large amplitude. It can be seen that... Figure 5 Required compensation range v 补偿2 Smaller, corresponding to k1v rec Smaller; Figure 6 Required compensation range v 补偿1 Larger, corresponding to k1vrec The value is relatively large, indicating that the compensation can be appropriately adjusted based on the degree of input voltage deviation. Therefore, when the input voltage is large, the input current will decrease, -i in R sense1 Absolute value |-i in R sense1 | decreases, while term k1v rec Absolute value |k1v rec | Increasing the value can compensate for the current sampling signal.

[0039] A current sampling method for a power factor correction circuit control chip, comprising: Input voltage conditioning involves negatively proportionally adjusting the amplitude of the input voltage to the power factor correction module to obtain the input voltage conditioning signal. Input current sampling: The input current of the power factor correction module is sampled through the input sampling resistor to obtain the input current sampling signal; The first addition process adds the input voltage conditioning signal and the input current sampling signal to obtain the first addition processing signal, and outputs the first addition processing signal to the current sampling signal pin of the control chip.

[0040] In some embodiments, the current sampling method of the power factor correction circuit control chip includes: The input voltage v of the power factor correction module rec A negative proportional adjustment is performed to obtain the input voltage conditioning signal k1v. rec ; Input sampling resistor R sense1 Connected between the rectifier bridge and the power factor correction module ground, through the input sampling resistor R sense1 The input current of the power factor correction module is sampled, and the resulting input current sampling signal is -i. in R sense1 ; The input voltage conditioning signal k1v rec and input current sampling signal -i in R sense1 The output signal after addition is -i in R sense1 +k1v rec .

[0041] In some embodiments, it is also necessary to consider that the compensated amplitude cannot exceed the limit. Therefore, the rectified voltage and input current are extracted separately, passed through an inverting proportional circuit, and then fed into a multiplier circuit to obtain a signal proportional to the input power. When the power remains constant, the amplitude of this signal remains unchanged, ensuring that the amplitude of the sampled signal is almost constant. To maintain the constant amplitude of the current sampling signal for different output power levels, feedback signals for the input voltage and input current are introduced. As the output power increases, at least one of the input current and input voltage feedback signals will increase, which can act as negative feedback to ensure that the signal amplitude is almost constant or slightly reduced.

[0042] like Figure 4 As shown, the compensation circuit includes an input voltage conditioning circuit, an input current sampling circuit, a first adder, a first inverting proportional circuit, a second inverting proportional circuit, a first multiplier, a first divider, a subtractor, an output current sampling circuit, a second divider, a second multiplier, and a second adder.

[0043] The input voltage conditioning circuit is used to negatively proportionally adjust the input voltage amplitude of the power factor correction module.

[0044] The input current sampling circuit is used to sample the input current of the power factor correction module through the input sampling resistor.

[0045] The first adder is used to add the outputs of the input current sampling circuit and the input voltage conditioning circuit.

[0046] The first inverting proportional circuit is used to adjust the input voltage of the power factor correction module in an inverting proportional manner.

[0047] The second inverting proportional circuit is used to adjust the output of the input current sampling circuit in an inverting proportional manner.

[0048] The first multiplier is used to receive the outputs of the first and second inverting proportional circuits and perform multiplication.

[0049] The first divider is used to perform division on the output of the first multiplier and the reference voltage.

[0050] The subtractor is used to perform subtraction on the outputs of the first divider and the first adder.

[0051] The output current sampling circuit is used to sample the output current of the power factor correction module through the output sampling resistor.

[0052] The second divider is used to perform division on the output of the amplitude-adjustable reference voltage and the output current sampling circuit.

[0053] The second multiplier is used to multiply the outputs of the subtractor and the second divider.

[0054] The second adder is used to add the outputs of the first adder and the second multiplier and then output a signal to the current sampling signal pin of the control chip.

[0055] The input voltage conditioning circuit receives the input voltage V from the power factor correction module. rec And by performing a negative proportional adjustment, k1v is obtained. rec .

[0056] Input sampling resistor R sense1 Connected between the rectifier bridge and the power factor correction module ground, the input current sampling circuit obtains a sampled input voltage signal of -i. in R sense1 .

[0057] The first inverting proportional circuit controls the input voltage v of the power factor correction module. rec K3V is obtained by performing inverse proportional adjustment. rec .

[0058] The second inverting amplifier circuit outputs -i to the input current sampling circuit. in R sense1 K4i is obtained by performing inverse proportional adjustment.

[0059] The first adder performs addition on the outputs of the input current sampling circuit and the input voltage conditioning circuit to obtain -i. in R sense1 +k1v rec .

[0060] The first multiplier multiplies the outputs of the first and second inverting proportional circuits to obtain k. p P in .

[0061] The first divider performs a division operation on the first multiplier and the reference voltage to obtain k. p P in / v REF .

[0062] The subtractor subtracts the output of the first divider from the output of the first adder to obtain k. p P in / v REF -(-i in R sense1 +k1v rec ).

[0063] Output sampling resistor R sense2Connected between the power factor correction module ground and the load, the output current sampling circuit obtains a sampled output voltage signal of V. sense2 =IoR sense2 .

[0064] The second divider divides the reference voltage for amplitude adjustment and the output of the output current sampling circuit to obtain k. I V REF / v sense2 .

[0065] The second multiplier multiplies the outputs of the subtractor and the second divider to obtain k. I V REF / v sense2 [k p P in / v REF -(-i in R sense1 +k1v rec )].

[0066] The second adder performs addition on the outputs of the first adder and the second multiplier to obtain the signal sent to the current sampling signal pin of the control chip: -i in R sense1 +k1v rec +k I V REF / v sense2 [k p P in / v REF -(-i in R sense1 +k1v rec )].

[0067] To ensure the compensated signal amplitude stabilizes at a suitable value, a reference signal with the same waveform is needed to limit it, denoted as v. lim This is used as a limit reference. The rectified input voltage and current are sampled and fed into the multiplication circuit, while being divided by the reference voltage to obtain v. lim =kP in / V REF It can be seen that when the output power remains constant, this limit remains almost unchanged, and the output current also does not change. The sampled voltage signal v sense2 Also remain fixed, with V REF After being fed into the divider, a voltage signal k is obtained that is inversely proportional to the output current value. I V REF / v sense2 The final signal sent to the ISENSE pin is: -i in Rsense1 +k1v rec +k I V REF / v sense2 [k p P in / v REF -(-i in R sense1 +k1v rec )].

[0068] In the formula -i in R sense1 +k1v rec This value is denoted as the value after the first compensation. The magnitude of this value differs from the limit value v in actual operation. lim There is a difference; this value differs from the limit value v. lim The difference is as follows Figure 7 and Figure 9 As shown, Figure 7 This is a diagram illustrating the first compensation value being less than the limit. Figure 9 This diagram illustrates the first compensation value exceeding the limit, where the solid line represents the value after the first compensation and the dashed line represents the limit.

[0069] At this point, a second compensation is needed, k I V REF / v sense2 [k p P in / v REF -(-i in R sense1 +k1v rec [)] is the compensation value for the second time. Item k I V REF / v sense2 [k p P in / v REF -(-i in R sense1 +k1v rec The part is divided into two parts: the coefficient part k. I V REF / v sense2 Compared with the comparison part [k] p P in / v REF -(-i in R sense1 +k1v rec When the output power is constant, P in The output current remains basically unchanged, and the output current sampling signal v is obtained by sampling the output current. sense2Since the coefficient is fixed when the output power is constant, only the comparison part needs to be considered. If the value after the first compensation does not reach the limit (e.g.) Figure 7 (as shown), k p P in / v REF -(-i in R sense1 +k1v rec The output is positive, meaning the comparison section will generate a positive compensation signal (e.g., Figure 8 As shown), this signal will be superimposed on the sampled signal again, causing the sampled signal to finally approach the limit value; when the sampled signal after the first compensation exceeds the limit signal amplitude (as shown), Figure 9 ), k p P in / v REF -(-i in R sense1 +k1v rec The output is negative, that is, a negative compensation signal is generated (such as...). Figure 10 As shown), this signal will be superimposed on the sampled signal again, causing the sampled signal to finally approach the limit. When the output power changes, the coefficient part k I V REF / v sense2 This will come into play; as the output power increases, the input power increases accordingly, and the comparison part [k] will play a role. p P in / v REF -(-i in R sense1 +k1v rec k in ] p P in / v REF It will increase, meaning the limit will increase, assuming the input voltage remains constant, -i in R sense1 The absolute value of |-i in R sense1 | increases, thus (-i in R sense1 +k1v rec The absolute value of the term |-i in R sense1 +k1v rec |Increases because the change in input current is smaller than the change in input power, i.e., k p P in / v REF The change is greater than -i in R sense1 This will increase the difference in the comparison part. Therefore, it is necessary to adjust the error to reduce it accordingly, that is, the coefficient part k I V REF / vsense2 It works. When the output power increases, the output current sampling voltage v sense2 The coefficient part k increases accordingly. I V REF / v sense2 This reduces the compensation value as the output power increases, ensuring that the final voltage signal amplitude sent to the ISENSE pin remains consistent.

[0070] A current sampling method for a power factor correction circuit control chip includes: Input voltage conditioning involves negatively proportionally adjusting the amplitude of the input voltage to the power factor correction module to obtain the input voltage conditioning signal. Input current sampling: The input current of the power factor correction module is sampled through the input sampling resistor to obtain the input current sampling signal; The first addition process involves adding the input voltage conditioning signal and the input current sampling signal to obtain the first addition processing signal; The first inverting proportional adjustment is performed on the input voltage of the power factor correction module to obtain the first inverting proportional adjustment signal. The second inverting proportional adjustment is performed on the input current sampling signal to obtain the second inverting proportional adjustment signal; The first multiplication process involves multiplying the first inverting proportional control signal and the second inverting proportional control signal to obtain the first multiplication processed signal. The first division process involves dividing the first multiplication signal and the reference voltage to obtain the first division signal. Subtraction processing: Subtract the first division processing signal and the first addition processing signal to obtain the subtraction processing signal; Output current sampling: The output current of the power factor correction module is sampled through the output sampling resistor to obtain the output current sampling signal; The second division process involves dividing the amplitude-adjusted reference voltage and the output current sampling signal to obtain the second division processed signal. The second multiplication process multiplies the subtraction signal and the second division signal to obtain the second multiplication signal. The second addition process adds the first addition signal and the second multiplication signal together and outputs the result to the current sampling signal pin of the control chip.

[0071] The input voltage v of the power factor correction module rec A negative proportional adjustment is performed to obtain the input voltage conditioning signal k1v. rec ; Input sampling resistor R sense1Connected between the rectifier bridge and the power factor correction module ground, through the input sampling resistor R sense1 The input current of the power factor correction module is sampled, and the resulting input current sampling signal is -i. in R sense1 ; The input voltage conditioning signal k1v rec and input current sampling signal -i in R sense1 The output signal after addition is -i in R sense1 +k1v rec ; The input voltage v of the power factor correction module rec The first inverting proportional adjustment is performed to obtain the first inverting proportional adjustment signal k3v. rec ; Sample the input current signal -i in R sense1 Perform inverse proportional adjustment to obtain the second inverse proportional adjustment signal k4i; The first inverting proportional adjustment signal k3v rec The first multiplication signal k is obtained by multiplying the second inverting proportional adjustment signal k4i. p P in ; The first multiplication process signal k p P in and reference voltage v REF The first division signal k is obtained by performing division. p P in / v REF ; Processing signal k for the first division p P in / v REF and the first addition signal (-i) in R sense1 +k1v rec Subtraction is performed to obtain the subtraction signal k. p P in / v REF -(-i in R sense1 +k1v rec ); Through the output sampling resistor R sense2 The output current of the power factor correction module is sampled to obtain the output current sampling signal V. sense2 =IoR sense2 ; The reference voltage k for amplitude adjustment I V REFand output current sampling signal V sense2 The second division signal k is obtained by performing division. I V REF / v sense2 ; Subtraction processing signal k p P in / v REF -(-i in R sense1 +k1v rec ) and the second division processing signal k I V REF / v sense2 The second multiplication signal k is obtained by performing multiplication. I V REF / v sense2 [k p P in / v REF -(-i in R sense1 +k1v rec )]; The outputs of the first addition signal and the second multiplication signal are added together to obtain the current sampling signal pin of the control chip, which is: -i in R sense1 +k1v rec +k I V REF / v sense2 [k p P in / v REF -(-i in R sense1 +k1v rec )].

[0072] In some embodiments, the selection of the ratio k1 must satisfy k1=(v lim +i in R sense1 ) / v recp , where v recp =√2×v rec In V REF Once determined, the choice of k3 and k4 can be made by first determining the value of k4, which can actually be between 0.9 and 1.1. The value of k3 can be determined according to the formula k3 = v lim V REF / P in k4 calculates that v lim The value can be selected according to the chip datasheet. k I After determining other parameters, k can be determined; in some embodiments, k I = (vsense2 / V REF )[ v lim -(-i in R sense1 +k1v rec )] / [k p P in / v REF -(-i in R sense1 +k1v rec ).

[0073] like Figure 11 As shown, the power factor correction circuit includes a discharge circuit, which includes a depletion-type NMOS transistor Q and a first power resistor R. se Second power resistor R disc The normally closed relay T and the drain and gate of the depletion-type NMOS transistor Q are connected to the load R. load At both ends, a first power resistor R is connected in series between the gate and source of the depletion-type NMOS transistor Q. se Second power resistor R disc The switching part of the normally closed relay T is connected in parallel to the first power resistor R. se When the power factor correction module is powered on, the normally closed relay is energized and opens the switching section; when the power factor correction module is powered off, the normally closed relay is de-energized and the switching section closes. The first power resistor R... se The resistance is greater than that of the second power resistor R. disc The resistance value. In some embodiments, the first power resistor R se The resistance value and the second power resistor R disc The resistance values ​​differ by four orders of magnitude.

[0074] When the PFC is powered on, the normally closed relay T is energized and opens its normally closed contact. At this time, the two power resistors are connected in series with the gate and source of the MOSFET Q. Since the depletion-type NMOS transistor is normally open, a portion of the output current flows through the MOSFET Q and through the resistor R. disc and R se The current then flows back to PGND from the gate. The threshold voltage of MOSFET Q is V. TH (<0), at this time the current limit of the MOSFET path is |V TH | / (R disc +R se ), because R se With a very high resistance and a very low current limiting value, the resistor consumes almost no power. When the PFC is de-energized, the normally closed relay T loses power, and its normally closed contact closes, energizing the high-resistance power resistor R. se A short circuit occurs, at which point only the small-value power resistor R remains in the circuit. disc At this time, the current limit of the MOSFET path is |V TH| / R disc The current is relatively large, which can quickly discharge the charge from the output capacitor. A schematic diagram of the discharge current is shown below. Figure 12 As shown.

[0075] The discharge method of the power factor correction circuit is as follows: When the power factor correction module is powered on, the normally closed relay is energized and the switching part is opened; when the power factor correction module is powered off, the normally closed relay is de-energized and the switching part is normally closed.

[0076] The key point of this embodiment is to prevent the input current THD from deteriorating due to changes in the amplitude of the input current sampling signal under wide input voltage and wide output power conditions of PFC. By introducing input voltage feedforward and output current sampling, the amplitude of the PFC input current sampling signal is regulated. Voltage feedforward and output current are used to control the amplitude of the input current sampling signal, so that it is always kept at a reasonable amplitude, thereby ensuring that the input current THD of the PFC circuit using average current control reaches the optimal level.

[0077] The key feature of the discharge circuit is that it can discharge itself after power is cut off without the need for other signal control. The circuit structure is simple and highly reliable.

[0078] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions claimed by the present invention.

Claims

1. A power factor correction circuit, comprising a power factor correction module, a control chip, and a compensation circuit, characterized in that, The compensation circuit is connected to the current sampling signal pin of the control chip, and the compensation circuit includes: An input voltage conditioning circuit is used to negatively proportionally adjust the amplitude of the input voltage of the power factor correction module. An input current sampling circuit is used to sample the input current of the power factor correction module through an input sampling resistor; The first adder is used to perform addition processing on the outputs of the input current sampling circuit and the input voltage conditioning circuit; The first inverting proportional circuit is used to perform inverting proportional adjustment on the input voltage of the power factor correction module; The second inverting proportional circuit is used to invert and proportionally adjust the output of the input current sampling circuit. The first multiplier is used to receive the outputs of the first and second inverting proportional circuits and perform multiplication. The first divider is used to perform division on the output of the first multiplier and the reference voltage; A subtractor is used to perform subtraction on the outputs of the first divider and the first adder; An output current sampling circuit is used to sample the output current of the power factor correction module through an output sampling resistor; The second divider is used to perform division on the reference voltage for amplitude adjustment and the output of the output current sampling circuit. The second multiplier is used to perform multiplication on the output of the subtractor and the output of the second divider; The second adder is used to add the outputs of the first adder and the second multiplier and then output a signal to the current sampling signal pin of the control chip.

2. The power factor correction circuit according to claim 1, characterized in that, The input voltage conditioning circuit receives the input voltage v from the power factor correction module. rec And by performing a negative proportional adjustment, k1v is obtained. rec ; The input sampling resistor R sense1 Connected between the rectifier bridge and the power factor correction module ground, the input current sampling circuit obtains a sampled input voltage signal of -i after sampling. in R sense1 ; The output signal of the first adder after adding the outputs of the input current sampling circuit and the input voltage conditioning circuit is -i. in R sense1 +k1v rec ; The first inverting proportional circuit affects the input voltage v of the power factor correction module. rec K3V is obtained by performing inverse proportional adjustment. rec ; The second inverting proportional circuit outputs -i to the input current sampling circuit. in R sense1 k4i is obtained by performing an inverse proportional adjustment; The first adder performs addition processing on the outputs of the input current sampling circuit and the input voltage conditioning circuit to obtain -i in R sense1 +k1v rec ; The first multiplier multiplies the outputs of the first and second inverting proportional circuits to obtain k. p P in ; The first divider performs a division operation on the first multiplier and the reference voltage to obtain k. p P in / v REF ; The subtractor subtracts the output of the first divider and the output of the first adder to obtain k. p P in / v REF -(-i in R sense1 +k1v rec ); The output sampling resistor R sense2 Connected between the power factor correction module ground and the load, the output current sampling circuit obtains a sampled output voltage signal of V. sense2 =IoR sense2 ; The second divider divides the amplitude-adjustable reference voltage and the output of the output current sampling circuit to obtain k. I V REF / v sense2 ; The second multiplier multiplies the output of the subtractor and the output of the second divider to obtain k. I V REF / v sense2 [k p P in / v REF -(-i in R sense1 +k1v rec )]; The second adder performs addition on the outputs of the first adder and the second multiplier to obtain the signal sent to the current sampling signal pin of the control chip: -i in R sense1 +k1v rec +k I V REF / v sense2 [k p P in / v REF -(-i in R sense1 +k1v rec )].

3. The power factor correction circuit according to any one of claims 1-2, characterized in that, The power factor correction circuit includes a discharge circuit, which includes a depletion-type NMOS transistor Q and a first power resistor R. se Second power resistor R disc The normally closed relay T, the drain and gate of the depletion-type NMOS transistor Q are connected to the two ends of the load, and a first power resistor R is connected in series between the gate and source of the depletion-type NMOS transistor Q. se Second power resistor R disc The switching section of the normally closed relay is connected in parallel to the first power resistor R. se When the power factor correction module is powered on, the normally closed relay is energized and disconnects the switching part; when the power factor correction module is powered off, the normally closed relay is de-energized and the switching part is normally closed. The first power resistor R... se The resistance is greater than that of the second power resistor R. disc The resistance value.

4. A current sampling method for a power factor correction circuit control chip, characterized in that, The method includes: Input voltage conditioning involves negatively proportionally adjusting the amplitude of the input voltage to the power factor correction module to obtain the input voltage conditioning signal. Input current sampling: The input current of the power factor correction module is sampled through the input sampling resistor to obtain the input current sampling signal; The first addition process involves adding the input voltage conditioning signal and the input current sampling signal to obtain the first addition processing signal; The first inverting proportional adjustment is performed on the input voltage of the power factor correction module to obtain the first inverting proportional adjustment signal; The second inverting proportional adjustment is performed on the input current sampling signal to obtain the second inverting proportional adjustment signal; The first multiplication process involves multiplying the first inverting proportional control signal and the second inverting proportional control signal to obtain the first multiplication processed signal. The first division process involves dividing the first multiplication signal and the reference voltage to obtain the first division signal. Subtraction processing involves subtracting the first division processing signal and the first addition processing signal to obtain a subtraction processing signal; Output current sampling: The output current of the power factor correction module is sampled through the output sampling resistor to obtain the output current sampling signal; The second division process involves dividing the amplitude-adjusted reference voltage and the output current sampling signal to obtain the second division processed signal. The second multiplication process involves multiplying the subtraction signal and the second division signal to obtain the second multiplication signal. The second addition process adds the first addition signal and the second multiplication signal together and outputs the result to the current sampling signal pin of the control chip.

5. The current sampling method for the power factor correction circuit control chip according to claim 4, characterized in that, The method includes: The input voltage v of the power factor correction module rec A negative proportional adjustment is performed to obtain the input voltage conditioning signal k1v. rec ; Input sampling resistor R sense1 Connected between the rectifier bridge and the power factor correction module ground, through the input sampling resistor R sense1 The input current of the power factor correction module is sampled, and the resulting input current sampling signal is -i. in R sense1 ; The input voltage conditioning signal k1v rec and input current sampling signal -i in R sense1 The output signal after addition is -i in R sense1 +k1v rec ; The input voltage v of the power factor correction module rec The first inverting proportional adjustment is performed to obtain the first inverting proportional adjustment signal k3v. rec ; The input current sampling signal -i in R sense1 Perform inverse proportional adjustment to obtain the second inverse proportional adjustment signal k4i; The input current sampling signal -i in R sense1 and input voltage conditioning signal k1v rec The first addition signal -i is obtained by performing addition processing. in R sense1 +k1v rec ; The first inverting proportional adjustment signal k3v rec The first multiplication signal k is obtained by multiplying the second inverting proportional adjustment signal k4i. p P in ; The first multiplication process signal k p P in and reference voltage v REF The first division signal k is obtained by performing division. p P in / v REF ; The first division processing signal k p P in / v REF and the first addition signal (-i) in R sense1 +k1v rec Subtraction is performed to obtain the subtraction signal k. p P in / v REF -(-i in R sense1 +k1v rec ); Through the output sampling resistor R sense2 The output current of the power factor correction module is sampled to obtain the output current sampling signal V. sense2 =IoR sense2 ; The reference voltage k for amplitude adjustment I V REF and output current sampling signal V sense2 The second division signal k is obtained by performing division. I V REF / v sense2 ; Subtraction processing signal k p P in / v REF -(-i in R sense1 +k1v rec ) and the second division processing signal k I V REF / v sense2 The second multiplication signal k is obtained by performing multiplication. I V REF / v sense2 [k p P in / v REF -(-i in R sense1 +k1v rec )]; The outputs of the first addition signal and the second multiplication signal are added together to obtain the current sampling signal pin of the control chip, which is: -i in R sense1 +k1v rec +k I V REF / v sense2 [k p P in / v REF -(-i in R sense1 +k1v rec )].

Images