A decoding method based on low-density parity-check code, electronic device and medium

Abstract

The application discloses a decoding method based on a low-density parity-check code, an electronic device and a medium, and relates to the technical field of computers. The method comprises the following steps: acquiring a to-be-decoded code word sequence; determining the column weight corresponding to each code word in the to-be-decoded code word sequence based on a preset check matrix; dividing the code words based on the column weights to obtain at least one code word set; performing a flip operation on the code words in each code word set in turn based on the check matrix according to a preset code word set polling order until a first preset condition is met, stopping polling each code word set, and acquiring a decoding sequence corresponding to the to-be-decoded code word sequence. According to the application, each code word in the to-be-decoded code word sequence is divided based on the check matrix, and the strategy of alternately flipping the code word sets is adopted, so that the error correction efficiency is improved and the convergence speed is accelerated.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a decoding method, electronic device and medium based on low-density parity-check codes. Background Technology

[0002] Driven by artificial intelligence, big data, and cloud computing, the amount of stored data is experiencing explosive growth, making NAND flash memory the core storage medium due to its high density, low power consumption, and high throughput. With the increase in 3D stacking layers and the development of multi-level storage technologies such as Triple-Level Cell (TLC) and Quad-Level Cell (QLC), flash memory capacity continues to expand. However, problems such as charge leakage, inter-layer crosstalk, and narrowing cell threshold voltage lead to a significant increase in bit error rate, placing higher demands on error control coding. Low-Density Parity-Check (LDPC) codes, due to their sparse parity matrix and error correction performance approaching the Shannon limit, are currently the core error correction technology for NAND. However, bit-flipping algorithms based on LDPC codes still suffer from slow iterative convergence and poor decoding reliability. Specifically, bit-flipping algorithms based on low-density parity-check codes uniformly traverse and process all codeword bits during decoding. Error correction uses a global flipping threshold throughout, consistently comparing the number of individual codeword bits that do not satisfy the parity check equation with the magnitude of this global flipping threshold as the basis for bit-flipping determination. This leads to problems such as slow iterative convergence and poor decoding reliability. Taking a parity-check matrix containing both column-weight 3 and column-weight 5 codewords as an example, column-weight 5 codewords are associated with more parity check equations, and under normal conditions, the cardinality of those not satisfying the parity check equations is naturally higher. If the same global flipping threshold is used to determine bit-flipping, two situations are likely to occur: If the global flipping threshold is set too low, high-column-weight bits are likely to trigger flips frequently, resulting in a large number of normal bits being incorrectly flipped, introducing additional errors, and the iteration oscillates back and forth, failing to converge slowly. If the global flipping threshold is set too high, a small number of real errors in low-column-weight codewords that do not satisfy the parity check cannot meet the flipping condition, and persistent errors remain for a long time, requiring more iterations to correct. Summary of the Invention

[0003] This application provides a decoding method, electronic device, and medium based on low-density parity-check codes, to at least solve the problems of slow iterative convergence and poor decoding reliability of LDPC codes.

[0004] This application provides a decoding method based on low-density parity-check codes, the method comprising: Obtain the codeword sequence to be decoded; Based on the preset parity check matrix, determine the column weight corresponding to each codeword in the codeword sequence to be decoded; Based on the weight of each column, each codeword is divided to obtain at least one codeword set; According to the preset codeword set polling order, based on the parity check matrix, the codewords in each codeword set are flipped sequentially until the first preset condition is met, at which point the polling of each codeword set stops, and the decoding sequence corresponding to the codeword sequence to be decoded is obtained.

[0005] This application also provides a decoding device based on low-density parity-check codes, comprising: The acquisition module is used to acquire the codeword sequence to be decoded; The determination module is used to determine the column weight corresponding to each codeword in the codeword sequence to be decoded based on a preset check matrix; The partitioning module is used to partition each codeword based on the weight of each column, so as to obtain at least one codeword set; The flipping module is used to perform flipping operations on the codewords in each codeword set in a preset polling order based on the parity check matrix, until the first preset condition is met, at which point the polling of each codeword set stops, and the decoding sequence corresponding to the codeword sequence to be decoded is obtained.

[0006] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for implementing the steps of any of the above-described decoding methods based on low-density parity-check codes when executing the computer program.

[0007] This application also provides a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, it implements the steps of any of the above-described decoding methods based on low-density parity-check codes.

[0008] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described decoding methods based on low-density parity-check codes.

[0009] This application divides codewords based on the column weights determined by the parity-check matrix, forming sets of codewords with different error correction characteristics. Then, bit-flipping error correction is iteratively performed on each set of codewords through a preset polling order. Compared with the decoding method that processes all codewords uniformly and corrects errors with a fixed threshold, this method adapts to the error characteristics and error correction rules of codewords with different column weights by polling each set of codewords differently, reducing redundant iterations and invalid bit flips, improving decoding accuracy, accelerating convergence speed, and solving the problem of unbalanced high and low column weight bit error correction in the decoding process of irregular LDPC codes. Attached Figure Description

[0010] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 A flowchart illustrating a decoding method based on low-density parity-check codes provided in this application embodiment; Figure 2 A schematic diagram illustrating a data storage format for a parity check matrix provided in an embodiment of this application; Figure 3 This is a schematic diagram illustrating the process of storing the verification matrix provided in an embodiment of this application; Figure 4 A schematic diagram of a bit-flipping decoder provided in an embodiment of this application; Figure 5 A performance comparison chart showing the decoding method based on low-density parity-check code provided in this application embodiment and the decoding method using traditional decoding methods, respectively; Figure 6 A schematic diagram of the structure of a decoding device based on low-density parity-check code provided in an embodiment of this application; Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0012] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0013] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0014] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0015] First, the application scenarios of the embodiments of this application will be introduced by way of example.

[0016] Driven by artificial intelligence, big data, and cloud computing technologies, the demand for data storage and transmission continues to grow. NAND flash memory, with its advantages of high storage density, excellent throughput, low power consumption, and high integration, is widely used in data centers, mobile terminals, and embedded storage. In recent years, the continuous development of NAND flash memory technology has led to a breakthrough in 3D stacking layers, exceeding 500 layers. Simultaneously, the widespread adoption of multi-level storage technologies such as Triple-Level Cell (TLC) and Quad-Level Cell (QLC) has significantly increased the storage capacity of single flash memory chips, meeting the demand for large-capacity data storage. However, physical defects such as charge leakage, inter-layer crosstalk, and narrowing of cell threshold voltage distribution exacerbate the bit error rate of flash memory cells, resulting in a significant decrease in the reliability of stored data. Therefore, in this scenario, higher requirements are placed on the error correction capabilities of error control coding technology.

[0017] Low-Density Parity-Check (LDPC) codes, with their advantages of sparse parity-check matrices, low decoding / decoding complexity, and error correction performance approaching the Shannon limit, have become the core error control coding scheme in NAND flash memory. Among them, the bit-flipping decoding algorithm, as a classic hard-decision decoding algorithm for LDPC codes, features simple hardware implementation, low computational load, low decoding latency, and controllable power consumption. It has become the preferred small-core decoding scheme in NAND flash memory big.LITTLE error correction schemes, enabling fast decoding and error correction when the number of error bits is small in the early stages of NAND flash memory lifespan, while saving decoder power consumption.

[0018] However, the bit-flipping decoding scheme is only applicable to regular LDPC code scenarios. It has obvious technical defects in irregular LDPC code scenarios adapted to NAND flash memory, such as serious error correction imbalance problems, a large number of invalid flips and false error flips during the decoding process, which not only reduces the decoding accuracy, but also causes problems such as slow iteration convergence speed and redundant iterations.

[0019] In view of this, embodiments of this application provide a decoding method based on low-density parity-check codes to solve the aforementioned problems of unbalanced error correction, low decoding accuracy, slow iterative convergence speed, and redundant iteration times.

[0020] It should be noted that the decoding method based on low-density parity-check (LDPC) codes provided in this embodiment of the invention can be executed by a device for decoding based on LPC codes. This device can be implemented as part or all of an electronic device through software, hardware, or a combination of both. The electronic device can be a server or a terminal. In this embodiment, the server can be a single server or a server cluster composed of multiple servers. The terminal can be a smartphone, personal computer, tablet computer, wearable device, or other intelligent hardware device such as a smart robot. The following method embodiments will use an electronic device as an example for illustration.

[0021] According to an embodiment of the present invention, a decoding method based on low-density parity-check codes is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0022] Figure 1 This is a flowchart of a decoding method based on a low-density parity-check code according to an embodiment of the present invention. Figure 1 As shown, the process includes: S101, Obtain the codeword sequence to be decoded.

[0023] Specifically, the codeword sequence to be decoded is a binary bit data stream transmitted through the channel. For example, the codeword sequence to be decoded consists of 0 and 1 bits. The codeword sequence to be decoded includes information bits and parity bits, where the information bits store valid data. The parity bits are redundant error-correcting data added during the encoding of the information bits to verify and correct bit errors during transmission and storage.

[0024] S102, based on the preset check matrix, determine the column weight corresponding to each codeword in the codeword sequence to be decoded.

[0025] Specifically, the parity check matrix is ​​a sparse matrix pre-set during the LDPC encoding process, which serves as the basis for decoding.

[0026] Column weight refers to the number of non-zero elements in the column corresponding to a single codeword in the parity-check matrix, i.e., the number of parity-check equations that the codeword participates in. A larger column weight indicates that the codeword participates in more parity-check constraints. In the embodiments of this application, column weight reflects the parity-check constraint capability and error characteristics of the corresponding codeword, providing a basis for subsequent codeword partitioning and differentiated flip error correction, thereby solving the problem of unbalanced error correction in irregular LDPC. It can be understood that the codeword whose column weight is determined is the information bit in the codeword sequence to be decoded.

[0027] S103, based on the weight of each column, divide each codeword to obtain at least one codeword set.

[0028] Specifically, the codeword verification constraints and error patterns differ among different codeword sets.

[0029] For example, each codeword is divided into a high-column-weight codeword set and a low-column-weight codeword set. Codewords with column weights higher than a preset column weight threshold are assigned to the high-column-weight codeword set, and codewords with column weights lower than the preset column weight threshold are assigned to the low-column-weight codeword set. The preset column weight threshold can be determined based on the column weight of each codeword's corresponding column in the parity check matrix. For example, the maximum column weight among the column weights of each codeword's corresponding column can be used as the preset column weight threshold. Alternatively, the average column weight can be obtained by averaging the column weights of all codewords' corresponding columns in the parity check matrix, and this average column weight can be used as the preset column weight threshold. Of course, multiple preset column weight intervals can also be set to divide each codeword into multiple codeword sets to accommodate complex and irregular LDPC codes with various column weights.

[0030] Considering the significant differences in bit error correction characteristics among codewords with different column weights, codewords with high column weights have more verification constraints and a higher number of errors (i.e., error weights) in the verification equations corresponding to the verification matrix, making them prone to repeated flipping and oscillations. Conversely, codewords with low column weights have fewer verification constraints and lower error weights, making them prone to incomplete error correction and residual errors. Therefore, in this embodiment, codewords are divided based on their column weights to form multiple codeword sets, providing an accurate basis for subsequent differentiated polling of the codeword sets.

[0031] S104. According to the preset codeword set polling order, based on the parity check matrix, perform the flip operation on the codewords in each codeword set in turn until the first preset condition is met, stop polling each codeword set, and obtain the decoding sequence corresponding to the codeword sequence to be decoded.

[0032] Specifically, the preset codeword set polling order refers to the preset order in which each codeword set is iteratively processed. Taking multiple codeword sets, including a high-column duplicate codeword set and a low-column duplicate codeword set, as an example, the high-column duplicate codeword set is processed in odd-numbered rounds, and the low-column duplicate codeword set is processed in even-numbered rounds. Of course, the number of polling rounds for each codeword set can also be set according to actual needs.

[0033] The flip operation refers to flipping the bits of a codeword between 0 and 1 to correct errors.

[0034] The first preset condition serves as the criterion for terminating the polling iteration. For example, the first preset condition is that all codewords satisfy the corresponding parity check equation in the parity check matrix. The first preset condition can also be that the number of polling iterations reaches a preset number, thus avoiding infinite polling. Therefore, the resulting decoded sequence is a valid codeword sequence that has undergone multiple rounds of reverse error correction on the codeword set, eliminating bit errors and satisfying the parity check specification.

[0035] For example, taking multiple codeword sets including a high-column-weight codeword set and a low-column-weight codeword set as an example, the codeword sets are iteratively flipped alternately in the order of high-column-weight set and low-column-weight set. Each round processes one codeword set, that is, the flipping operation is performed on some or all of the codewords in one codeword set. The other codeword set counts the number of codewords in the set that do not meet the check equation (also known as error weight) and does not perform flipping, so as to maximize the avoidance of invalid flipping and false error flipping. For example, the high-column-weight set is processed in the first round, the low-column-weight set is processed in the second round, and the high-column-weight set is processed again in the third round, and so on.

[0036] For example, codeword sets with high error probabilities can be prioritized for polling to adapt to scenarios with high error rates in the later stages of flash memory lifespan. The number of polling rounds can also be dynamically adjusted based on the results of each round of verification, prioritizing codeword sets with severe errors to adapt to different error distribution scenarios.

[0037] Considering the different error correction constraints and capabilities of codewords with different column weights, globally and synchronously flipping all codewords would lead to repeated oscillations in codewords with high column weights and incomplete error correction or invalid flips in codewords with low column weights. Therefore, in this embodiment, based on the column weight of each codeword determined by the parity check matrix, each codeword is divided into codeword sets with different error correction characteristics. Then, bit flipping error correction is iteratively performed on each codeword set through a preset polling order. Compared with the decoding method of uniformly processing all codewords and using a fixed threshold for error correction, this method adapts to the error characteristics and error correction rules of codewords with different column weights by polling each codeword set differently, reducing redundant iterations and invalid bit flips, improving decoding accuracy, accelerating convergence speed, and solving the problem of unbalanced bit error correction between high and low column weights in the decoding process of irregular LDPC codes.

[0038] In some embodiments, based on the foregoing embodiments, according to a preset codeword set polling order, and based on a check matrix, the codewords in each codeword set are sequentially flipped until a first preset condition is met, at which point the polling of each codeword set is stopped, and the decoding sequence corresponding to the codeword sequence to be decoded is obtained. Specifically, this includes the following: a1, when the codeword in the (i+1)th codeword set is determined to be flipped based on the polling order of the preset codeword set, the i-th codeword sequence is verified based on the check matrix to obtain the (i+1)th check result.

[0039] Here, the i-th codeword sequence is the codeword sequence generated after performing a flip operation on the codewords in the i-th codeword set, where i is a positive integer greater than 1. In other words, the i-th codeword sequence is the codeword sequence obtained after the flip operation was completed in the previous polling round, and is used as the input codeword sequence for the current loop round.

[0040] Specifically, the (i+1)th codeword set is used as the target codeword set to be processed in the current iteration round. For example, if the current iteration is even, it corresponds to the lower column of the repeated codeword set.

[0041] For example, the (i+1)th check result is the check vector obtained after checking the i-th codeword sequence. It consists of several 0s and 1s. 0 represents that the corresponding check equation has no error, that is, it satisfies the check equation. 1 represents that the corresponding check equation has a bit error, that is, it does not satisfy the check equation.

[0042] a2, based on the (i+1)th verification result, determines the number of the first type corresponding to each codeword in the (i+1)th codeword set.

[0043] The first type of quantity is the number of times the corresponding codeword does not satisfy the check equation in the (i+1)th check result.

[0044] Specifically, the encoding process of LDPC codes ensures that the transmitted codeword sequence c is orthogonal to the parity-check matrix H, that is, it satisfies c·H. =0. After passing through a noisy channel, the codeword sequence y obtained by the receiver may have bit errors, i.e., y = c + e, where e is the error pattern. At this time, the above orthogonality relationship is broken, i.e., the syndrome s = y·H ≠0. Each non-zero component of the syndrome s corresponds to a non-satisfied check equation. The first type of quantity refers to the number of non-satisfied check equations corresponding to each codeword in the (i+1)th codeword set of the current loop. Here, the number of non-satisfied check equations corresponding to a codeword refers to the number of errors or non-compliance in the check equations in which the codeword participates, which can also be called the error weight of the codeword.

[0045] The larger the number of the first category, the higher the probability of error for the corresponding codeword. For example, if the current (i+1)th set is a set of high-column duplicate codewords, and a certain high-column duplicate codeword is associated with 3 check equations, if 2 of the check equations in the current check result do not meet the constraints, then the number of the first category for this codeword is 2, which means that this codeword currently has a high probability of error.

[0046] a3, based on the quantity of each first type, determines the first type target codeword in the (i+1)th codeword set.

[0047] Specifically, the first type of target codeword refers to the suspected error bit in the (i+1)th codeword set that has a high probability of error in the current polling round and meets the flipping judgment condition.

[0048] In one possible implementation, the first type of target codeword is determined as follows: b1, retrieve the i-th verification result.

[0049] The i-th verification result is the verification result obtained by verifying the i-1 codeword sequence based on the verification matrix.

[0050] b2, based on the i-th verification result, determine the number of the second type corresponding to each codeword in the (i+1)-th codeword set.

[0051] The second type of quantity is the number of times the corresponding codeword does not satisfy the check equation in the i-th check result.

[0052] Specifically, the second type of quantity refers to the number of times each codeword in the codeword set corresponding to the current polling round does not satisfy the verification equation in the previous round of verification results, which represents the severity of the error of the codeword in the previous iteration.

[0053] The first type of quantity in a single round can only reflect the instantaneous error state of the codeword in the current round. The second type of quantity is used to identify the real error bits that continue to err across multiple rounds.

[0054] b3, based on the quantity of each second category and the quantity of each first category, determine the target codeword of the first category.

[0055] Optionally, based on the quantity of each second category and the quantity of each first category, the target codeword of the first category is determined, specifically including the following steps: First, the maximum value among the quantities in the second category is determined as the threshold for the quantity in the first category.

[0056] Specifically, the maximum value among the second-class quantities is taken as the maximum value that does not satisfy the check equation in the previous polling round, reflecting the historical highest error rate in the codeword set corresponding to the current polling round. In this way, based on the second-class quantities, the threshold is guaranteed to match the column weight characteristics of the current codeword set, realizing differentiated threshold configuration for high and low class column weights, making the flipping judgment criterion more suitable for the actual error patterns of the current codeword set.

[0057] Then, based on the first category quantity threshold and the quantity of each first category, the first category target codeword is determined.

[0058] For example, in the (i+1)th codeword set, the codewords corresponding to the first type of quantity that reach the first type of quantity threshold are determined as the first type of target codewords.

[0059] For example, in the (i+1)th codeword set, codewords whose quantity in the first category is equal to the first category quantity threshold are identified as first category target codewords.

[0060] In this way, compared with the method of using a fixed threshold, the flip threshold of the current round is determined by the verification result of the previous round of query, the flip threshold is determined by the historical verification result, and the current verification result is used to determine the first type of target codeword, which accurately filters out the real erroneous codewords. At the same time, it realizes the differentiated judgment flip standard for different codeword sets, solves the problem of unbalanced error correction of high and low column heavy bits of irregular LDPC codes, improves the accuracy of error bit screening, reduces invalid flip and erroneous flip operations, and speeds up the convergence speed.

[0061] Optionally, for each codeword, the first type quantity and the second type quantity are weighted and summed to obtain the weighted quantity of the codeword. The codewords in the (i+1)th codeword set are sorted according to their respective weighted quantities, and the codeword with the larger weighted quantity is selected as the first type target codeword.

[0062] In this way, by combining the verification results of the previous round and using the verification results of the two rounds of polling to filter the first type of target codewords, the accuracy of error bit identification is further improved and the decoding performance is optimized.

[0063] In another possible implementation, the first type of target codeword is determined as follows: First, obtain the preset quantity threshold from the preset storage area.

[0064] Here, the preset quantity threshold can be a fixed quantity threshold, or it can be a quantity threshold that is updated in real time based on the polling rounds.

[0065] Then, based on the preset quantity threshold and the quantity of each first category, the target codeword of the first category is determined.

[0066] For example, in the (i+1)th codeword set, the codewords corresponding to the first type of quantity that reaches a preset quantity threshold are determined as the first type of target codewords. Alternatively, the codewords corresponding to the first type of quantity that is equal to the preset quantity threshold are determined as the first type of target codewords.

[0067] Optionally, the method provided in this application embodiment also includes the following: After flipping the bits of the first type of target codeword in the i-th codeword sequence to generate the (i+1)-th codeword sequence, the maximum value among the quantities of each first type is counted. This maximum value is compared with the quantity threshold in the preset storage area at the current time. When the maximum value is greater than the quantity threshold in the preset storage area at the current time, the quantity threshold in the preset storage area is updated to this maximum value. This is used in the next polling round to determine the first type of target codeword in the (i+2)-th codeword set based on the quantities of each first type in the next round and the quantity threshold in the preset storage area.

[0068] In this way, the maximum value of all first-type quantities in the current round is counted in real time and compared with the quantity threshold in the preset storage area. When the maximum value is larger, the quantity threshold in the preset storage area is updated synchronously. This allows the updated quantity threshold in the preset storage area to be used to filter first-type target codewords in the next round of querying. This achieves dynamic change of the threshold, thereby adapting to the actual error rate in each round of querying, achieving accurate filtering of target codewords, and accelerating the decoding iteration convergence speed.

[0069] Optionally, the method provided in this application embodiment also includes the following: Retrieve the verification results for all iterations corresponding to the (i+1)th codeword set before the current iteration. For each verification result, count the number of times each codeword in the (i+1)th codeword set of that verification result does not satisfy the verification equation. Take the maximum value among the numbers of times each codeword in the (i+1)th codeword set of all verification results does not satisfy the verification equation, and determine this as the preset threshold.

[0070] In this way, by obtaining historical error characteristics through multiple rounds of verification results, the preset quantity threshold can be adapted to the long-term real error level of the codeword set, thereby improving decoding accuracy.

[0071] In another possible implementation, the codewords of the first type with a larger number in the set can be selected as the first type of target codewords according to a preset ratio.

[0072] a4 performs a bit flipping operation on the first type of target codeword in the i-th codeword sequence to generate the (i+1)-th codeword sequence. When the codeword in the (i+2)-th codeword set is determined to be flipped based on the preset codeword set polling order, the (i+1)-th codeword sequence is verified based on the parity check matrix to generate the (i+2)-th codeword sequence. This process continues until the first preset condition is met, at which point the polling of each codeword set stops, and the decoding sequence corresponding to the codeword sequence to be decoded is obtained.

[0073] Specifically, bit flipping refers to flipping the state of bits in a binary codeword, i.e., changing 0 to 1 and 1 to 0, thereby correcting bit errors.

[0074] For example, when there are multiple first-class target codewords, the first-class target codewords can be flipped one by one, or the flipping operation can be performed on multiple first-class target codewords at the same time to improve the convergence speed.

[0075] In this embodiment, each codeword set is polled in turn, and the latest verification result is generated in real time by verifying the codeword sequence obtained from the previous polling. The error status of the current codeword set is matched, realizing the individual error correction of a single codeword set. This avoids problems such as uneven bit error correction and invalid flipping process in different codeword sets, speeds up the decoding iteration convergence speed, and reduces the number of redundant iterations.

[0076] In one possible implementation, the first preset condition is determined to be met when the number of polling reaches a preset number of polling, or when the codeword sequence after the flip operation satisfies all the check equations in the check matrix.

[0077] This application does not specify a particular number of preset polling times; these can be set according to actual circumstances.

[0078] In some embodiments, based on any of the foregoing embodiments, the method provided in this application further includes the following: First, based on the preset codeword set polling order, a flip operation is performed on the j-th codeword set in the current polling round to obtain the j-th codeword sequence. Then, based on the parity check matrix, the j-th codeword sequence is checked to obtain the check result of the j-th codeword sequence.

[0079] Then, based on the verification result of the j-th codeword sequence, the number of codes that do not satisfy the verification equation is counted for each codeword in the j-th codeword sequence.

[0080] Next, for each codeword set, the number of codes that do not satisfy the parity check equation for each codeword belonging to that codeword set is summed to obtain the total number of codes in that codeword set.

[0081] Finally, based on the total number of codeword sets, the codeword set for the next polling round is determined.

[0082] In one possible implementation, the codeword set with the largest total number is determined as the codeword set for the next polling round. This prioritizes correcting the codeword set with the most severe error accumulation. For example, if the total number of low-column-weighted codewords is 42 and the total number of high-column-weighted codewords is 11, the low-column-weighted codeword set is determined to have more errors, and the next polling round will prioritize processing the low-column-weighted codeword set.

[0083] In this embodiment, the polling order of the preset codeword set is no longer a fixed polling order, but a polling order determined based on the verification result of the codeword sequence in the previous polling round. After completing the flip-correction of a certain codeword set in each round, a real-time verification result is obtained by performing a full verification on the updated codeword sequence. By statistically analyzing the error weights of each codeword in the codeword set that do not meet the verification equation, the total number of errors in each codeword set is accumulated. Thus, the codeword set to be processed in the next polling round is dynamically determined based on the total number of errors in the codeword set. This achieves adaptive adjustment of the polling order based on the error degree of each codeword set. For example, codeword sets with higher total number of errors are processed first, reducing redundant and invalid iterations and accelerating the convergence speed.

[0084] In some embodiments, based on any of the foregoing embodiments, polling of each codeword set is stopped, and a decoding sequence corresponding to the codeword sequence to be decoded is obtained, specifically including the following method steps: First, stop polling each codeword set and obtain the codeword sequence generated in the last polling round.

[0085] Specifically, when the first preset condition is met during the decoding process, the polling of each codeword set is terminated, and the next codeword set flipping operation is not initiated. The last polling round refers to the last valid codeword set polling round before the first preset condition is met, in which the corresponding codeword set has completed error correction updates. The codeword sequence generated in the last polling round refers to the latest codeword sequence obtained after verification and judgment, and the flipping of the first type of target codeword, in the last complete polling iteration.

[0086] For example, if the maximum number of iterations is preset to 10 rounds, when the decoding iteration reaches the 8th round, the codeword sequence has completely satisfied all check equations, triggering the termination condition and stopping the subsequent 9th and 10th rounds of polling. At this point, the last round that is completely executed is the 8th round. Obtaining the codeword sequence generated after the 8th round of iteration update is the codeword sequence generated in the last polling round.

[0087] For example, if the maximum number of iterations is preset to 10 rounds, and the codeword sequence still does not satisfy all the check equations when the decoding iteration reaches the 10th round, then the last round that is completely executed is the 10th round. Obtaining the codeword sequence generated after the 10th round of iteration update is the codeword sequence generated in the last polling round.

[0088] Then, based on the codeword sequence generated in the last polling round, the decoding sequence is determined.

[0089] In one possible implementation, when the codeword sequence generated in the last polling round satisfies all the check equations corresponding to the check matrix, the codeword sequence generated in the last polling round is determined as the decoding sequence.

[0090] Continuing with the example of a maximum preset number of iterations of 10 rounds, where the codeword sequence fully satisfies all check equations when the decoding iteration reaches the 8th round, the codeword sequence generated in the 8th round of querying is determined as the decoding sequence.

[0091] In another possible implementation, the decoding sequence is determined as follows: c1: When it is determined from the parity check matrix that the codeword sequence generated in the last polling round does not satisfy all the parity check equations, obtain the parity check result in the last polling round.

[0092] c2, based on the verification result in the last polling round, performs a flipping operation on the codeword sequence generated in the last polling round to obtain the decoded sequence.

[0093] Optionally, the decoded sequence can be obtained as follows: d1, in the current flipping round, based on the check matrix, verifies the codeword sequence generated in the last polling round to obtain the verification result of the current flipping round.

[0094] Here, the verification result of the current flip round is the verification result of the codeword sequence generated in the last polling round obtained using the verification matrix.

[0095] d2, based on the verification result of the current flipping round and the verification result of the last polling round, performs a flipping operation on the codeword sequence generated in the last polling round to obtain the flipped codeword sequence.

[0096] In one possible scenario, the codeword sequence generated in the last polling round is flipped as follows to obtain the flipped codeword sequence: First, based on the verification results in the last polling round, the second category quantity threshold is determined.

[0097] Specifically, the second type of quantity threshold is a flipping judgment standard applicable to all codewords in the flipping round, unlike the first type of quantity threshold which only applies to the corresponding codeword set.

[0098] For example, based on the verification results in the last polling round, the fourth category quantity corresponding to each codeword in the codeword set corresponding to the last polling round is counted. The fourth category quantity is the number of codewords that do not satisfy the verification equation in the verification results of the last polling round. The maximum value among these fourth categories is determined as the second category quantity threshold.

[0099] Then, based on the second type of quantity threshold and the verification result of the current flipping round, the codeword sequence generated in the last polling round is flipped to obtain the flipped codeword sequence.

[0100] In this way, after correcting errors in the codeword set separately, in the global error correction scenario, the flipping standard is determined by the historical verification results, and the flipping operation is determined by the current verification result, thereby improving the error correction accuracy and convergence efficiency of the flipping rounds.

[0101] For example, the codeword sequence generated in the last polling round is flipped as follows to obtain the flipped codeword sequence: First, based on the verification results of the current flip round, determine the number of the third category corresponding to each codeword in the codeword sequence to be decoded.

[0102] The third category is the number of codewords that do not satisfy the verification equation in the current flipping round's verification result.

[0103] Then, based on the thresholds for each third type of quantity and the second type of quantity, a flipping operation is performed on the codeword sequence generated in the last polling round to obtain the flipped codeword sequence.

[0104] In this embodiment, the codewords in the codeword sequence generated in the last polling round whose third-type quantity reaches the second-type quantity threshold are flipped to obtain a flipped codeword sequence. Alternatively, the codewords whose third-type quantity equals the second-type quantity threshold can also be flipped to obtain a flipped codeword sequence.

[0105] In another possible scenario, the codeword that does not satisfy at least one check equation in both check results is identified as the second type of target codeword. The bits of the second type of target codeword are flipped to obtain the flipped codeword sequence.

[0106] d3. When the flipped codeword sequence does not satisfy all the parity check equations corresponding to the parity check matrix, proceed to the next flipping round. Based on the parity check matrix, the flipped codeword sequence is checked again to obtain a new parity check result. Based on the new parity check result and the parity check result of the current flipping round, the flipped codeword sequence is flipped again until the second preset condition is met, then the flipping operation is stopped and the decoded sequence is obtained.

[0107] Specifically, the second preset condition is the termination condition for the flipping round after the codeword set polling is completed. For example, the second preset condition is that all codewords in the codeword sequence to be decoded satisfy all check equations. The second preset condition can also be to forcibly terminate the flipping iteration when a preset number of flipping rounds is reached, thus avoiding an infinite flipping loop.

[0108] In this embodiment, two types of iterations are performed. The first type involves iterating through the codeword sets one by one. In each iteration, only one codeword set is flipped, while other codeword sets are not flipped, until a first preset condition is met, resulting in the codeword sequence generated in the last iteration. In the second type of iteration, the codewords are not differentiated by column weight. Based on the codeword sequence generated in the last iteration, all codewords are flipped, and flipping operations are performed until a second preset condition is met, resulting in the final decoded sequence. This approach aims to correct errors as much as possible and improve decoding accuracy.

[0109] In this way, based on the iterative polling of the codeword set, further refined error correction is performed on the remaining errors. During the refined error correction process, the codeword flipping is constrained by combining the data from the two rounds of verification, filtering out pseudo-error flipping caused by random noise in the flash memory, accurately identifying the real errors, improving the decoding convergence capability and error correction accuracy of irregular LDPC codes in scenarios with high error rates and complex error distributions, making up for the error correction blind spots of the iterative polling of the codeword set, and comprehensively improving the reliability of data decoding.

[0110] In some embodiments, before performing the flipping operation on the codewords in each codeword set according to the preset codeword set polling order and based on the parity check matrix, the method provided in this application embodiment further includes the following: First, obtain the verification matrix.

[0111] Secondly, the parity check matrix is ​​split into multiple sub-matrices.

[0112] Specifically, based on the matrix structure characteristics of the parity-check matrix, the complete parity-check matrix is ​​decomposed into multiple submatrices of the same size. It can be understood that each submatrix has independent shifting properties. For example, a 32×64 quasi-cyclic parity-check matrix can be split according to a 4×4 block rule to obtain several 4×4 submatrices.

[0113] Next, based on each submatrix, a base matrix corresponding to the check matrix is ​​generated.

[0114] Specifically, the base matrix is ​​used to characterize the basic topological result of the verification matrix and the block arrangement rules of the submatrices.

[0115] For example, the shift parameters of all submatrices are cleared to zero, leaving only the matrix placeholder structure, thus obtaining the base matrix.

[0116] Next, obtain the position information, shift value, and column weight of the submatrix corresponding to the first matrix value in the check matrix.

[0117] The first matrix value is any matrix value in the base matrix.

[0118] Specifically, the position information of the submatrix indicates its arrangement within the parity check matrix. For example, the position information of the submatrix includes its row and column index coordinates within the parity check matrix. The shift value, as a cyclic shift offset parameter within the submatrix, characterizes the cyclic shift rule of the bits within the submatrix. The column weight of the submatrix refers to the total number of valid 1 elements in the codeword column containing the submatrix, guaranteeing the number of parity check equations associated with that codeword.

[0119] Then, based on the column weights of the submatrix corresponding to the first matrix value in the check matrix, the set of codewords corresponding to the first matrix value is determined.

[0120] The method for determining the codeword set based on the column weights of the submatrix is ​​similar to the specific implementation in S103, and will not be repeated here.

[0121] Finally, the position information of the submatrix corresponding to the first matrix value in the check matrix, the shift value, and the codeword set identifier corresponding to the first matrix value are stored in the preset storage area.

[0122] The codeword set identifier corresponding to the first matrix value is used to indicate the codeword set corresponding to the first matrix value.

[0123] Considering the characteristics of LDPC codes used in NAND flash memory, such as quasi-cyclic (i.e., shift matrices where the submatrices are identity matrices), long codewords (i.e., code lengths in the tens of thousands), and high code rates (i.e., greater than 0.8), directly storing the complete parity check matrix would require massive storage resources. Even with sparsity optimization, it would still consume a large amount of on-chip RAM or registers, leading to increased hardware costs and power consumption. Simultaneously, storing and retrieving massive amounts of data would significantly reduce data transmission speed and prolong the decoding process latency, especially for irregular parity check matrices. Therefore, in this embodiment, the parity check matrix is ​​split into multiple submatrices, and a corresponding base matrix is ​​constructed based on these submatrices. The position information, shift values, and column weight characteristics of each submatrix, as well as the codeword set determined based on the column weight, are stored as parameters in a preset storage area. Compared to directly storing the complete parity check matrix, only a small number of submatrix positions, shift values, and codeword set identifiers need to be stored, significantly reducing storage resource overhead and decoding power consumption.

[0124] It is understood that, during the decoding process, before determining the column weight corresponding to each codeword in the codeword sequence to be decoded based on a preset parity check matrix, the method provided in this application embodiment further includes the following: The position information and shift value of each matrix value in the submatrix corresponding to the parity check matrix, as well as the codeword set identifier corresponding to the first matrix value, are read from the preset storage area. Based on the position information, shift value, and codeword set identifier corresponding to each matrix value, the parity check matrix is ​​reconstructed.

[0125] Figure 2This is a schematic diagram of a data storage format for a parity check matrix. The storage logic stores data column-by-column in units of the base matrix. Each column storage unit synchronously records the codeword set identifier corresponding to the first matrix value, as well as the position information and shift value of the submatrix corresponding to that first matrix value. The codeword set identifier is marked with a single bit; a bit value of 0 indicates that the corresponding block / column is a high-column heavy codeword set, and a bit value of 1 indicates that the corresponding block / column is a low-column heavy codeword set. A single column of stored data consists of multiple sets of binary units with identical bit widths. Each set of units stores the position information and shift value of a submatrix, and the position information and shift value within all sets occupy a fixed and equal bit width. If the number of valid submatrix sets corresponding to a certain block / column is less than the preset number of storage sets, the idle position information and shift value fields without valid parameters are uniformly filled with all 1 bits to complete the bit width alignment. For irregular LDPC codes with only two types of column weights, let the total bit width of a single set of position information and shift value be M, and n sets of storage units be reserved for a single column. Then the total bit width X of a single column satisfies X = nM + 1. The highest bit is the codeword set identifier. If the highest bit interval [X-1:X-2] is 0, it means that the block belongs to the high-column repeated codeword set. The [X-3:X-3-M] bit interval stores the position information and shift value of the submatrix corresponding to the first matrix value of the column. The [X-4-M:X-4-2M] bit interval stores the position information and shift value of the submatrix corresponding to the second matrix value of the column, and the remaining parameters are arranged sequentially.

[0126] Figure 3 This is a schematic diagram illustrating the parity check matrix storage process. First, the parity check matrix is ​​split into multiple sub-matrices, and a base matrix is ​​generated based on these sub-matrices, while a preset column weight threshold is set. Second, all matrix values ​​within the base matrix are traversed, and the position information, shift value, and column weight of the corresponding sub-matrix for each matrix value are extracted. Third, the column weight of the sub-matrix is ​​compared to the preset column weight threshold. That is, the codeword set to which the corresponding matrix value belongs is determined based on the column weight of each sub-matrix and the preset column weight threshold. When the column weight is greater than or equal to the preset threshold, a codeword set identifier of 0 is assigned; when the column weight is less than the preset threshold, a codeword set identifier of 1 is assigned. Next, the position information and shift value of the corresponding sub-matrix for all matrix values ​​within the current block are counted row by row. If the corresponding codeword set identifier is 1 (i.e., a low column weight set), the free position information and shift value fields without valid sub-matrix parameters need to be padded with all 1 bits to complete bit width alignment. Finally, the position information and shift value of the corresponding sub-matrix for each matrix value, along with the matched codeword set identifier, are written to a preset storage area, thereby generating standardized storage data containing codeword classification identifiers, sub-matrix positions, and shift parameters.

[0127] The above mainly describes the solution provided by the embodiments of this application from a methodological perspective.

[0128] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0129] Figure 4 This is a schematic diagram of a bit-flipping decoder. Figure 4 As shown, the bit-flipping decoder includes a parity check matrix information processing module, a parity check calculation module, an error weight statistics module, a bit-flipping module, a flipping threshold selection module, and a decoded codeword module.

[0130] The parity check matrix information processing module is mainly responsible for preprocessing the parity check matrix in the preset storage area, extracting its column weight identifier and non-zero information of the column, so as to convert the matrix into a format that can be directly called by subsequent modules for subsequent matrix calculation, error weight statistics and bit flipping processes.

[0131] The verification calculation module is used to perform the adjoint c·H The calculation and verification decision are performed. If the syntactic expression is all zero, it means there is no error in the codeword sequence, and the codeword sequence is output. If the syntactic expression is not all zero, it means there is an error in the codeword. In this case, the reversed codeword is sent back to the decoder to repeat the decoding process until the verification result passes or the preset number of times is reached.

[0132] The error weight statistics module calculates the error weight (i.e., the number of codewords that failed the check equation) for each codeword (i.e., information bits) in each iteration. It compares the error weights of high-weight and low-weight regions based on the column weight identifier, selecting the maximum error weight for each region. After a preset number of polls, it compares the selected maximum error weights for high-weight and low-weight regions to select the global maximum error weight. Before each iteration, after recording the maximum error weights of the high-weight and low-weight regions from the previous iteration, it initializes the temporary values ​​for the maximum error weights of the high-weight and low-weight regions.

[0133] The bit-flipping module determines whether to flip the information of the current codeword based on the error weight value and the number threshold (also known as the flipping threshold) corresponding to each codeword. In this scheme, a strategy of alternating flipping of low-column-weight regions and high-column-weight regions is adopted. That is, in odd-numbered decoding iterations, only the high-column-weight regions are bit-flipped according to the relationship between the error weight value and the number threshold, while the low-column-weight regions remain unchanged; in even-numbered decoding iterations, only the low-column-weight regions are bit-flipped according to the relationship between the error weight value and the number threshold, while the high-column-weight regions remain unchanged.

[0134] The flip threshold selection module is based on the recorded maximum error weight. Within a preset number of polling iterations, the maximum error weight corresponding to the high / low column weight regions after the previous iteration is used as the threshold for the number of high / low column weight regions in the current iteration. That is, within the preset number of iterations, in odd-numbered iterations, the maximum error weight of the high column weight region calculated in the previous iteration is used as the threshold for the number of high column weight regions in the current iteration, and no threshold is selected for the number of low column weight regions; in even-numbered iterations, the maximum error weight of the low column weight region calculated in the previous iteration is used as the threshold for the number of low column weight regions in the current iteration, and no threshold is selected for the number of high column weight regions. When the number of iterations exceeds the preset number of polling iterations, the global maximum error weight obtained from the previous comparison is used as the corresponding threshold for the current iteration.

[0135] The codeword module after decoding is used to store the information after bit flipping. When decoding is successful or the preset number of flipping rounds is reached, the codeword is output. When decoding fails and the preset number of flipping rounds is not reached, the codeword enters the next iteration.

[0136] The decoding method provided in this application is illustrated below with a specific embodiment, which includes the following steps: e1, initialize the BF decoder, configure the parity check matrix, initialize the quantity thresholds corresponding to the high / low column weight regions, load the parity check matrix, and count the column weight of each column in the base matrix; set the preset polling count and preset flipping count, and initialize the odd / even iteration count flag and the preset polling count flag.

[0137] e2 receives the codeword sequence to be decoded, verifies the codeword sequence to be decoded based on the parity check matrix, and obtains the verification result.

[0138] e3 determines whether the current iteration is an odd or even number of iterations. If it is an odd number of iterations, the odd / even iteration count flag is increased; if it is an even number of iterations, the flag is decreased. It also determines whether the number of polling iterations is within a preset number of polling iterations. If it is greater than the preset number of polling iterations, the preset number of polling iterations flag is increased.

[0139] e4 stores the maximum error weight of the high / low column weight region calculated in the previous polling round into the maximum error weight register of the high / low column weight region, and then sets the temporary value of the maximum error weight of the high / low column weight region to 0. If the preset polling number flag is high, the global maximum error weight is selected based on the maximum error weight of the high / low column weight region and stored in the register.

[0140] e5, for each codeword, execute the following operations sequentially or in parallel.

[0141] e5.1, calculate the error weight value corresponding to the codeword.

[0142] e5.2, based on whether the column weight identifier corresponding to the codeword is high column weight or low column weight, compare the error weight value with the maximum error weight value of the corresponding column weight region temporarily stored in the register. If it is greater than the temporarily stored maximum error weight value, update the maximum error weight value of the region; otherwise, the maximum error weight value of the region remains unchanged.

[0143] In e5.3, for large column-weighted regions in odd-numbered iterations, when the preset polling count flag is low, the maximum error weight value corresponding to the high column-weighted region in the register is used as the quantity threshold; when the preset polling count flag is high, the global maximum error weight value in the register is used as the quantity threshold. The error weight in the verification result calculated in e2 is compared with the quantity threshold to determine whether to flip the codeword. For low column-weighted regions in odd-numbered iterations, the threshold selection and comparison process is skipped.

[0144] In e5.4, for low-column-weight regions in even-numbered iterations, when the preset polling count flag is low, the maximum error weight value corresponding to the low-column-weight region in the register is used as the quantity threshold; when the preset polling count flag is high, the global maximum error weight value in the register is used as the quantity threshold. The error weight in the verification result calculated in e2 is compared with the quantity threshold to determine whether to flip the codeword. For high-column-weight regions in even-numbered iterations, the threshold selection and comparison process is skipped.

[0145] e6. Calculate whether the reversed codeword sequence satisfies all the parity check equations in the parity check matrix. If it does, stop decoding. Otherwise, repeat steps e3 to e6 until decoding is successful or the preset number of polling rounds is reached, and then proceed to the subsequent global flip rounds until the preset number of flip rounds is reached.

[0146] Figure 5 This chart compares the performance of the decoding method based on low-density parity-check codes provided in this application with that of traditional decoding methods. The method provided in this application uses alternating flipping of high and low codeword sets, completing a full bit-flipping operation every two rounds. Using an example matrix with a code rate of 0.9 and column weights of 4 and 5, the performance comparison with traditional methods shows that the method provided in this application achieves a lower frame error rate at the same original bit error rate. In other words, the method provided in this application can improve the bit-flipping (BF) error correction performance of decoders for irregular LDPC codes.

[0147] This application also provides a decoding device based on a low-density parity-check code, which is used to implement the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that performs a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0148] This embodiment provides a decoding device based on low-density parity-check codes, such as... Figure 6 As shown, it includes: The acquisition module 601 is used to acquire the codeword sequence to be decoded; The determination module 602 is used to determine the column weight corresponding to each codeword in the codeword sequence to be decoded based on a preset check matrix; The partitioning module 603 is used to partition each codeword based on the weight of each column to obtain at least one codeword set; The flipping module 604 is used to perform flipping operations on the codewords in each codeword set in a preset polling order based on the parity check matrix until the first preset condition is met, then stop polling each codeword set and obtain the decoding sequence corresponding to the codeword sequence to be decoded.

[0149] In one possible implementation, the flipping module 604 is specifically used to, when it is determined, based on the polling order of the preset codeword set to perform a flipping operation on the codewords in the (i+1)th codeword set, verify the i-th codeword sequence based on the parity check matrix to obtain the (i+1)th verification result, where the i-th codeword sequence is the codeword sequence generated after performing the flipping operation on the codewords in the i-th codeword set, and i is a positive integer greater than 1; Based on the (i+1)th check result, determine the number of the first category corresponding to each codeword in the (i+1)th codeword set, where the number of the first category is the number of the corresponding codewords that do not satisfy the check equation in the (i+1)th check result; Based on the quantity of each first type, the target codeword of the first type is determined in the (i+1)th codeword set; The bits of the first type of target codeword in the i-th codeword sequence are flipped to generate the (i+1)-th codeword sequence. When the flipping operation is performed on the codeword in the (i+2)-th codeword set based on the preset codeword set polling order, the (i+1)-th codeword sequence is verified based on the parity check matrix to generate the (i+2)-th codeword sequence. This process continues until the first preset condition is met, at which point the polling of each codeword set stops, and the decoding sequence corresponding to the codeword sequence to be decoded is obtained.

[0150] In one possible implementation, the flipping module 604 is specifically used to obtain the i-th verification result, wherein the i-th verification result is the verification result obtained by verifying the i-1 codeword sequence based on the verification matrix; Based on the i-th verification result, determine the second type quantity corresponding to each codeword in the (i+1)-th codeword set, where the second type quantity is the number of codewords that do not satisfy the verification equation in the i-th verification result; Based on the quantity of each second category and the quantity of each first category, the target codeword of the first category is determined.

[0151] In one possible implementation, the flipping module 604 is specifically used to determine the maximum value among the second type of quantities as the threshold value of the first type of quantity. Based on the first category quantity threshold and the quantity of each first category, the first category target codeword is determined.

[0152] In one possible implementation, the flipping module 604 is specifically used to determine the codewords corresponding to the first type of quantity that reach the first type of quantity threshold in the (i+1)th codeword set as the first type of target codewords.

[0153] In one possible implementation, the flip module 604 is specifically used to stop polling each codeword set and obtain the codeword sequence generated in the last polling round; The decoding sequence is determined based on the codeword sequence generated in the last polling round.

[0154] In one possible implementation, the flipping module 604 is specifically used to determine the codeword sequence generated in the last polling round as the decoding sequence when it is determined from the parity check matrix that the codeword sequence generated in the last polling round satisfies all the parity check equations corresponding to the parity check matrix. or, When it is determined from the parity check matrix that the codeword sequence generated in the last polling round does not satisfy all the parity check equations, the parity check result of the last polling round is obtained; based on the parity check result of the last polling round, the codeword sequence generated in the last polling round is flipped to obtain the decoded sequence.

[0155] In one possible implementation, the flipping module 604 is specifically used to, in the current flipping round, verify the codeword sequence generated in the last polling round based on the verification matrix, and obtain the verification result of the current flipping round; Based on the verification result of the current flipping round and the verification result of the last polling round, the codeword sequence generated in the last polling round is flipped to obtain the flipped codeword sequence. When the flipped codeword sequence does not satisfy all the parity check equations corresponding to the parity check matrix, the next flipping round is entered. Based on the parity check matrix, the flipped codeword sequence is checked again to obtain a new parity check result. Based on the new parity check result and the parity check result of the current flipping round, the flipped codeword sequence is flipped again until the second preset condition is met, the flipping operation is stopped, and the decoded sequence is obtained.

[0156] In one possible implementation, the flipping module 604 is specifically used to determine the second type of quantity threshold based on the verification result in the last polling round; Based on the second type of quantity threshold and the verification result of the current flipping round, the codeword sequence generated in the last polling round is flipped to obtain the flipped codeword sequence.

[0157] In one possible implementation, the flipping module 604 is specifically used to determine the number of third categories corresponding to all codewords in the codeword sequence to be decoded based on the verification result of the current flipping round, wherein the number of third categories is the number of codewords that do not satisfy the verification equation in the verification result of the current flipping round. Based on the thresholds for each third and second category quantity, a flipping operation is performed on the codeword sequence generated in the last polling round to obtain the flipped codeword sequence.

[0158] In one possible implementation, the flipping module 604 is specifically used to determine that the first preset condition is met when the number of polling reaches a preset number of polling, or when the codeword sequence after performing the flipping operation satisfies all the check equations in the check matrix.

[0159] In one possible implementation, the device further includes a storage module for obtaining a check matrix before performing a flip operation on the codewords in each codeword set according to a preset codeword set polling order and based on the check matrix. The verification matrix is ​​split into multiple sub-matrices; Based on each submatrix, generate the basis matrix corresponding to the verification matrix; Obtain the position information, shift value, and column weight of the submatrix corresponding to the first matrix value in the check matrix, where the first matrix value is any matrix value in the base matrix; Based on the column weights of the submatrix corresponding to the first matrix value in the parity check matrix, determine the set of codewords corresponding to the first matrix value; The position information of the submatrix corresponding to the first matrix value in the check matrix, the shift value, and the codeword set identifier corresponding to the first matrix value are stored in a preset storage area. The codeword set identifier corresponding to the first matrix value is used to indicate the codeword set corresponding to the first matrix value.

[0160] The apparatus provided in this application divides each codeword based on the column weight of each codeword determined by the parity check matrix, forming a set of codewords with different error correction characteristics. Then, bit flip error correction is iteratively performed on each set of codewords through a preset polling order. Compared with the decoding method of uniformly processing all codewords and correcting errors with a fixed threshold, this method adapts to the error characteristics and error correction rules of codewords with different column weights by polling each set of codewords differently, reduces redundant iterations and invalid bit flips, improves decoding accuracy, speeds up convergence, and solves the problem of unbalanced high and low column weight bit error correction in the decoding process of irregular LDPC codes.

[0161] For a description of the features in the corresponding embodiment of the decoding device based on low-density parity check code, please refer to the relevant description of the corresponding embodiment of the decoding method based on low-density parity check code, which will not be repeated here.

[0162] Embodiments of this application also provide an electronic device, such as... Figure 7 As shown, it includes a memory 10 and a processor 20. The memory 10 stores a computer program, and the processor 20 is configured to run the computer program to perform the steps in any of the above-described embodiments of the decoding method based on low-density parity-check codes.

[0163] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above embodiments of the decoding method based on low-density parity-check codes when running.

[0164] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0165] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described embodiments of the decoding method based on low-density parity-check codes.

[0166] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above embodiments of the decoding method based on low-density parity-check codes.

[0167] Any of the components, modules, units, parts, methods, and operations described herein can be implemented using software, firmware, hardware (e.g., fixed logic circuitry), manual processing, or any combination thereof. Alternatively or additionally, any functionality described herein can be executed at least in part by one or more hardware logic components, such as, but not limited to, a central processing unit (CPU), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), an application-specific standard product (ASSP), a system-on-a-chip (SoC), a complex programmable logic device (CPLD), a microprocessor (MCU), etc. The terms "system," "computing device," or "apparatus" as used herein encompass various means, devices, and machines for processing data, including, for example, one or more programmable processors, computers, SoCs, or combinations thereof. The apparatus may also include code that creates an execution environment for the computer program in question, such as code constituting processor firmware, a protocol stack, a database management system, an operating system, a cross-platform runtime environment, a virtual machine, or one or more combinations thereof. The aforementioned computer program (also known as a program, software, software application, app, script, or code) can be written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages, and can be deployed in any form, including as a standalone program or as a module, component, subroutine, object, or other unit suitable for a computing environment.

[0168] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0169] The foregoing has provided a detailed description of a decoding method, electronic device, and medium based on low-density parity-check codes provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only intended to aid in understanding the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A decoding method based on low-density parity-check codes, characterized in that, The method includes: Obtain the codeword sequence to be decoded; Based on a preset check matrix, the column weight corresponding to each codeword in the codeword sequence to be decoded is determined; Based on the column weights, each codeword is divided to obtain at least one codeword set; According to the preset codeword set polling order, based on the verification matrix, the codewords in each codeword set are sequentially flipped until the first preset condition is met, at which point the polling of each codeword set is stopped, and the decoding sequence corresponding to the codeword sequence to be decoded is obtained. The step of performing a flipping operation on the codewords in each codeword set according to a preset codeword set polling order and based on the parity check matrix, until a first preset condition is met, stopping the polling of each codeword set, and obtaining the decoding sequence corresponding to the codeword sequence to be decoded, includes: When it is determined, based on the polling order of the preset codeword set, to perform a flip operation on the codeword in the (i+1)th codeword set, the i-th codeword sequence is verified based on the verification matrix to obtain the (i+1)th verification result, wherein the i-th codeword sequence is the codeword sequence generated after performing the flip operation on the codeword in the i-th codeword set, and i is a positive integer greater than 1; Based on the (i+1)th verification result, determine the first category quantity corresponding to each codeword in the (i+1)th codeword set, wherein the first category quantity is the number of codewords that do not satisfy the verification equation in the (i+1)th verification result; Based on the quantity of each of the first categories, the target codewords of the first category are determined in the (i+1)th codeword set; The bits of the first type of target codeword in the i-th codeword sequence are flipped to generate the (i+1)-th codeword sequence. When it is determined, based on the preset codeword set polling order, that the codeword in the (i+2)-th codeword set is to be flipped, the (i+1)-th codeword sequence is verified based on the parity check matrix to generate the (i+2)-th codeword sequence. This process continues until the first preset condition is met, at which point the polling of each codeword set stops, and the decoding sequence corresponding to the codeword sequence to be decoded is obtained. After performing a bit flipping operation on the first type of target codeword in the i-th codeword sequence to generate the (i+1)-th codeword sequence, the maximum value among the quantities of each first type is counted. This maximum value is compared with the quantity threshold in the preset storage area at the current time. When the maximum value is greater than the quantity threshold in the preset storage area at the current time, the quantity threshold in the preset storage area is updated to the maximum value. This is used to determine the first type of target codeword in the (i+2)-th codeword set in the next round of querying based on the quantities of each first type in the next round and the quantity threshold in the preset storage area.

2. The method according to claim 1, characterized in that, The step of determining the first type of target codeword in the (i+1)th codeword set based on the quantity of each of the first types includes: Obtain the i-th verification result, wherein the i-th verification result is the verification result obtained by verifying the (i-1)-th codeword sequence based on the verification matrix; Based on the i-th verification result, determine the second type quantity corresponding to each codeword in the (i+1)-th codeword set, wherein the second type quantity is the number of codewords that do not satisfy the verification equation in the i-th verification result; Based on the quantity of each of the second type and the quantity of each of the first type, the target codeword of the first type is determined.

3. The method according to claim 2, characterized in that, The step of determining the first type of target codeword based on the quantity of each of the second type and the quantity of each of the first type includes: The maximum value among all the quantities in the second category is determined as the threshold for the quantity in the first category; Based on the first category quantity threshold and the quantity of each of the first categories, the first category target codewords are determined.

4. The method according to claim 3, characterized in that, The step of determining the first type of target codeword based on the first type quantity threshold and the quantity of each of the first types includes: In the (i+1)th codeword set, the codewords corresponding to the first type of quantity that reach the first type of quantity threshold are determined as the first type of target codewords.

5. The method according to any one of claims 1-4, characterized in that, The step of stopping polling each of the codeword sets and obtaining the decoding sequence corresponding to the codeword sequence to be decoded includes: Stop polling each set of codewords and obtain the codeword sequence generated in the last polling round; The decoding sequence is determined based on the codeword sequence generated in the last polling round.

6. The method according to claim 5, characterized in that, Determining the decoding sequence based on the codeword sequence generated in the last polling round includes: When it is determined from the verification matrix that the codeword sequence generated in the last polling round satisfies all the verification equations corresponding to the verification matrix, the codeword sequence generated in the last polling round is determined as the decoding sequence; or, When it is determined based on the verification matrix that the codeword sequence generated in the last polling round does not satisfy all the verification equations, the verification result in the last polling round is obtained; based on the verification result in the last polling round, a flipping operation is performed on the codeword sequence generated in the last polling round to obtain the decoded sequence.

7. The method according to claim 6, characterized in that, The step of performing a flipping operation on the codeword sequence generated in the last polling round based on the verification result in the last polling round to obtain the decoded sequence includes: In the current flipping round, based on the verification matrix, the codeword sequence generated in the last polling round is verified to obtain the verification result of the current flipping round; Based on the verification result of the current flipping round and the verification result of the last polling round, a flipping operation is performed on the codeword sequence generated in the last polling round to obtain the flipped codeword sequence. When the flipped codeword sequence does not satisfy all the check equations corresponding to the check matrix, the next flipping round is entered to check the flipped codeword sequence again based on the check matrix to obtain a new check result. Based on the new check result and the check result of the current flipping round, the flipped codeword sequence is flipped again until the second preset condition is met, the flipping operation is stopped, and the decoded sequence is obtained.

8. The method according to claim 7, characterized in that, The step of performing a flip operation on the codeword sequence generated in the last polling round, based on the verification result of the current flipping round and the verification result of the last polling round, yields a flipped codeword sequence, including: Based on the verification results in the last polling round, determine the second category quantity threshold; Based on the second type of quantity threshold and the verification result of the current flipping round, a flipping operation is performed on the codeword sequence generated in the last polling round to obtain the flipped codeword sequence.

9. The method according to claim 8, characterized in that, Based on the second type of quantity threshold and the verification result of the current flipping round, a flipping operation is performed on the codeword sequence generated in the last polling round to obtain the flipped codeword sequence, including: Based on the verification result of the current flip round, the third category quantity corresponding to each codeword in the codeword sequence to be decoded is determined, wherein the third category quantity is the number of codewords that do not satisfy the verification equation in the verification result of the current flip round. Based on the thresholds for the third type of quantity and the second type of quantity, a flipping operation is performed on the codeword sequence generated in the last polling round to obtain the flipped codeword sequence.

10. The method according to any one of claims 1-4, characterized in that, The method further includes: When the number of polling reaches the preset number of polling, or when the codeword sequence after the flip operation satisfies all the check equations in the check matrix, it is determined that the first preset condition is met.

11. The method according to any one of claims 1-4, characterized in that, Before performing the flipping operation on the codewords in each codeword set sequentially according to the preset codeword set polling order and based on the verification matrix, the method further includes: Obtain the verification matrix; The verification matrix is ​​split into multiple sub-matrices; Based on each of the sub-matrices, a base matrix corresponding to the verification matrix is ​​generated; Obtain the position information, shift value, and column weight of the submatrix corresponding to the first matrix value in the verification matrix, wherein the first matrix value is any matrix value in the base matrix; Based on the column weights of the submatrix corresponding to the first matrix value in the check matrix, determine the codeword set corresponding to the first matrix value; The position information and shift value of the submatrix corresponding to the first matrix value in the parity matrix, as well as the codeword set identifier corresponding to the first matrix value, are stored in a preset storage area. The codeword set identifier corresponding to the first matrix value is used to indicate the codeword set corresponding to the first matrix value.

12. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the decoding method based on low-density parity-check codes as described in any one of claims 1-11 when executing the computer program.

13. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, it implements the steps of the decoding method based on low-density parity-check codes as described in any one of claims 1-11.

14. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the decoding method based on low-density parity-check codes as described in any one of claims 1-11.

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