A method and system for multi-node clock synchronization control in an Ethernet over fiber network

Abstract

The present application relates to the technical field of optical fiber Ethernet clock synchronization, in particular to a kind of optical fiber Ethernet multi-node clock synchronization control method and system.For the frame start delimiter in multistage optical fiber Ethernet link is transferred to the position deviating from the predetermined count position after reaching, the number of idle code groups under different port clock domain is not easy to match, main clock node sends reserved idle code group before synchronization frame and issues periodic serial number, main clock sends count value and the predetermined count position of each level node, relay node detects frame start delimiter and then latches arrival count value, determines the number of idle code groups to be increased or to be reduced according to difference value and the count length corresponding to single idle code group, adjusts the number of idle code groups before synchronization frame before forwarding, and the slave node determines output count position and generates second pulse or sampling trigger signal accordingly, thereby improving the consistency of multi-node synchronization output.

Description

Technical Field

[0001] This invention relates to the field of fiber optic Ethernet clock synchronization technology, specifically to a fiber optic Ethernet multi-node clock synchronization control method and system. Background Technology

[0002] Fiber optic Ethernet multi-node communication networks are commonly used in industrial control, power protection, rail transportation, and distributed data acquisition scenarios. Different nodes need to maintain a unified time base to ensure consistent timing of sampling triggers, event logging, control commands, and communication messages. Existing clock synchronization methods typically employ precise time protocols, synchronous Ethernet, hardware timestamps, transparent clocks, or master-slave clock correction. Time synchronization between multiple nodes is achieved through synchronization messages, delayed messages, link delay estimation, and local counter adjustment.

[0003] For multi-level cascaded fiber optic Ethernet nodes, existing methods typically adjust the local clock based on the timestamp difference after receiving or parsing synchronization messages. This is susceptible to issues such as relay node forwarding wait, port clock domain conversion, service messages occupying inter-frame intervals, and the progressive correction by multiple nodes. When synchronization messages are transmitted between multiple nodes, existing methods do not adequately utilize the relationship between continuous bitstream boundaries, inter-frame idle intervals, and downstream node phase changes, easily leading to cumulative deviations or jitter in the phase trigger position obtained by the end node. Therefore, a fiber optic Ethernet multi-node clock synchronization control method and system are needed to solve these problems. Summary of the Invention

[0004] To address the above problems, this invention provides the following technical solution: a fiber optic Ethernet multi-node clock synchronization control method, comprising: S1. The master clock node sends a number of idle code groups greater than the minimum inter-frame interval required before the synchronization frame in each synchronization cycle, and sends a synchronization frame carrying the cycle number, master clock transmission count value and the predetermined counting position of each level of node. S2. When the relay node detects the start-of-frame delimiter of the synchronization frame at the upstream fiber optic port, it uses the local counter driven by the receiver recovery clock to record the reached count value and reads the predetermined count position corresponding to the local node. S3. The relay node determines the number of idle code groups to be added or reduced based on the difference between the arrival count value and the predetermined count position, and the count length corresponding to a single idle code group. S4. Before forwarding the synchronization frame to the downstream fiber optic port, the relay node adjusts the number of idle code groups before the synchronization frame according to the number of idle code groups to be increased or decreased, and sends the frame start delimiter and the synchronization frame after adjustment. S5. When the slave node detects the frame start delimiter of the adjusted synchronization frame and confirms that the cycle number is continuous, it latches the local counter value of the slave node, and determines the output count position in the local counter of the slave node according to the cycle number, the count value sent by the master clock and the preset count offset, and generates a second pulse or sampling trigger signal.

[0005] Furthermore, the synchronization frame includes a period sequence number field, a master clock transmission count value field, and a predetermined count position field arranged according to the node level; the number of idle code groups before the synchronization frame includes the minimum inter-frame interval number and the reserved adjustment number, the reserved adjustment number being used for relay nodes to reduce idle code groups before forwarding the synchronization frame.

[0006] Furthermore, the receiver recovery clock is recovered from the received bitstream by the upstream fiber port; the local counter increments according to the receiver recovery clock and latches the current count value as the arrival count value when a frame start delimiter is detected; when the transmission clock of the downstream fiber port is not from the same source as the receiver recovery clock, the relay node converts the difference between the arrival count value and the predetermined count position to the transmission clock domain of the downstream fiber port according to the ratio of the transmission clock count increment to the receiver recovery clock count increment within the same synchronization period, and uses the converted difference as the difference to determine the number of idle code groups to be increased or decreased, and the count length corresponding to a single idle code group is the count length in the transmission clock domain of the downstream fiber port.

[0007] Furthermore, determining the number of idle code groups to be increased or decreased includes: When the arrival count value is greater than the predetermined count position, the difference between the two is used as the direction for reducing the idle code group; When the arrival count value is less than the predetermined count position, the difference between the two is used as the direction for increasing the idle code group; When the arrival count value equals the predetermined count position, the number of idle code groups to be increased or decreased is determined to be zero; Divide the absolute value of the difference by the count length corresponding to a single free code group and round down to obtain the number of free code groups to be increased or decreased.

[0008] Furthermore, when the relay node adjusts the number of idle code groups before the synchronization frame according to the direction of reducing the number of idle code groups, it reduces the number of idle code groups to be reduced before the synchronization frame, and ensures that the reduced number of idle code groups is not less than the minimum inter-frame interval specified by Ethernet.

[0009] Furthermore, when the relay node adjusts the number of idle code groups before the synchronization frame according to the direction of increasing the idle code groups, it increases the number of idle code groups to be increased before the synchronization frame, and ensures that the increased number of idle code groups does not exceed the maximum number that can be increased for the relay node in the current synchronization period. The maximum number that can be increased is preferentially carried by the synchronization frame, and is configured locally by the relay node when the synchronization frame does not carry it.

[0010] Furthermore, the predetermined counting positions of the nodes at each level are updated between adjacent synchronization cycles, specifically as follows: Relay nodes at each level in the After completing the forwarding of the synchronization frame at this level in each synchronization cycle, the arrival count value, the number of idle code groups that have been adjusted, the number of idle code groups that can be further reduced, and the number of idle code groups that can be increased are sent back through the uplink status frame. Master clock node according to the first The uplink status frames of each synchronization period establish the influence of the adjustment of the idle code group of each level of relay node on the arrival time of the frame start delimiter of the downstream node. Specifically, reducing one idle code group of a certain level of relay node corresponds to advancing the frame start delimiter of the downstream node of that level by one idle code group time, and increasing one idle code group corresponds to delaying the frame start delimiter of the downstream node of that level by one idle code group time. The master clock node converts the arrival count deviation corresponding to each level of relay node into idle code group adjustment requirements, and determines the portion exceeding the number of idle code groups that can be further reduced or increased by the current level node as the number of idle code groups to be shared. The master clock node, based on the aforementioned influence relationship and the number of idle code groups that can be further reduced and increased by upstream adjacent nodes, allocates the number of idle code groups to be shared to relay nodes or master clock nodes located upstream of and adjacent to its own node along the synchronization frame transmission direction, and writes the allocation result into the first... The predetermined counting positions of nodes at each level in the synchronization frame of each synchronization cycle.

[0011] Furthermore, the remaining count value after dividing the absolute value of the difference by the count length corresponding to a single idle code group is recorded as a negative count surplus in the direction of decreasing idle code groups and as a positive count surplus in the direction of increasing idle code groups. In subsequent synchronization cycles, the positive or negative count surplus is algebraically merged with the new difference value, and when the absolute value of the merged result reaches the count length corresponding to an idle code group, an additional idle code group is added or removed according to the sign of the merged result.

[0012] Furthermore, the generation of the second pulse or sampling trigger signal includes: When a slave node detects the start-of-frame delimiter of an adjusted synchronization frame, it latches its local counter value. The current synchronization period is determined based on the period sequence number in the synchronization frame, and the output count position in the local counter of the slave node within the current synchronization period is determined based on the count value sent by the master clock and the preset count offset. When the local count value of the slave node reaches the output count position, a second pulse or sampling trigger signal corresponding to the current synchronization period is output.

[0013] This invention also provides a fiber optic Ethernet multi-node clock synchronization control system for implementing the aforementioned fiber optic Ethernet multi-node clock synchronization control method, comprising: The synchronization frame sending module is used to enable the master clock node to send a number of idle code groups greater than the number required for the minimum inter-frame interval before the synchronization frame in each synchronization cycle, and to send a synchronization frame carrying the cycle number, the master clock sending count value and the predetermined counting position of each level of node; The frame start delimiter detection module is used to enable the relay node to record the arrival count value using a local counter driven by the receiver recovery clock when it detects the frame start delimiter of the synchronization frame at the upstream fiber port, and to read the predetermined count position corresponding to the local node. The idle code group quantity determination module is used to enable the relay node to determine the number of idle code groups to be increased or decreased based on the difference between the arrival count value and the predetermined count position, and the count length corresponding to a single idle code group. The idle code group adjustment and forwarding module is used to enable the relay node to adjust the number of idle code groups before the synchronization frame according to the number of idle code groups to be increased or decreased before forwarding the synchronization frame to the downstream optical fiber port, and to send the frame start delimiter and the synchronization frame after adjustment. The synchronization output module is used to enable the slave node to latch the local counter value when it detects the frame start delimiter of the adjusted synchronization frame and confirms that the cycle number is continuous, and to determine the output count position in the slave node's local counter according to the cycle number, the count value sent by the master clock and the preset count offset, and generate a second pulse or sampling trigger signal.

[0014] Compared with the prior art, the present invention has the following beneficial effects: By setting an adjustable idle code group before the synchronization frame in each synchronization cycle, and having the relay node increase or decrease the number of idle code groups before the synchronization frame based on the difference between the arrival count value of the frame start delimiter and the predetermined count position, the arrival time of the synchronization frame start boundary in the continuous code stream can be advanced or delayed. This implements the phase correction in multi-level forwarding onto the physical transmission object of the inter-frame idle interval, thereby reducing the cumulative deviation of the end phase trigger position caused by adjusting the local clock after parsing the synchronization message.

[0015] By using the receiver's recovered clock to record the reached count value, and performing clock domain conversion based on the count increment ratio within the same synchronization period when the downstream fiber port's transmit clock and the receiver's recovered clock are from different sources, the difference used to determine the number of idle code groups to be adjusted corresponds to the count length of a single idle code group in the downstream transmit clock domain. This reduces the mismatch in the number of idle code groups to be adjusted caused by inconsistencies in the port clock domain. Simultaneously, through constraints and accumulation of the minimum inter-frame interval, the maximum increase, and the signed count margin, deviations less than one idle code group can continue to participate in adjustments in subsequent synchronization periods. This ensures that the increase or decrease of idle code groups remains within the forwarding range of the current node, thereby reducing phase jitter caused by small deviation omissions or excessive adjustments by a single node during multi-level node step-by-step correction.

[0016] By sending back the arrival count, adjusted number of idle code groups, and adjustable margin of each level of relay node through the uplink status frame, and by establishing the influence relationship between idle code group adjustment and the arrival time of the frame start delimiter of downstream nodes through the master clock node, the idle code group adjustment requirements exceeding the adjustable range of the current level node can be allocated to the upstream adjacent node or the master clock node, thereby reducing the situation where the downstream node synchronization frame start boundary deviates from the predetermined count position when the adjustment capacity of a single level relay node is insufficient. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the method steps of a fiber optic Ethernet multi-node clock synchronization control method provided by the present invention; Figure 2 A flowchart illustrating the overall process of a fiber optic Ethernet multi-node clock synchronization control method provided by the present invention; Figure 3 A timing interaction diagram for a fiber optic Ethernet multi-node clock synchronization control method provided by the present invention; Figure 4 A comparison diagram of frame start delimiter arrival count deviations provided by the present invention for a fiber optic Ethernet multi-node clock synchronization control method; Figure 5 A comparison diagram of the error in the number of idle code groups before and after the conversion of the transmit clock domain in a fiber optic Ethernet multi-node clock synchronization control method provided by the present invention. Figure 6 The present invention provides a system structure diagram of a fiber optic Ethernet multi-node clock synchronization control system. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0020] Please see Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of the method steps of a fiber optic Ethernet multi-node clock synchronization control method provided by the present invention; Figure 2 This invention provides a general flowchart of a fiber optic Ethernet multi-node clock synchronization control method; the invention provides a fiber optic Ethernet multi-node clock synchronization control method, comprising: S1. The master clock node sends a number of idle code groups greater than the minimum inter-frame interval required before the synchronization frame in each synchronization cycle, and sends a synchronization frame carrying the cycle number, master clock transmission count value and the predetermined counting position of each level of node. Specifically, the master clock node includes a master clock local counter, a synchronization period counter, and downlink fiber port transmission control logic. The master clock local counter is driven by the master clock node's local clock and increments continuously. The synchronization period counter is used to generate the period sequence number. At the start of each synchronization period, the master clock node first sends an idle code segment before the synchronization frame. The number of this idle code segment is greater than the minimum inter-frame interval specified by Ethernet, allowing subsequent relay nodes to reduce the number of idle code segments before forwarding the synchronization frame. Subsequently, the master clock node latches the master clock local counter value at the time of transmitting the synchronization frame as the master clock transmission count value, and writes the period sequence number, the master clock transmission count value, and the predetermined counting positions of each level of node into the synchronization frame. The predetermined counting positions of each level of node are arranged sequentially according to the transmission direction of the synchronization frame, so that the first-level relay node reads the predetermined counting position corresponding to the first level, the second-level relay node reads the predetermined counting position corresponding to the second level, and so on.

[0021] Furthermore, in one embodiment provided by the present invention, the synchronization frame includes a period sequence number field, a master clock transmission count value field, and a predetermined count position field arranged according to the node level; the number of idle code groups before the synchronization frame includes the minimum inter-frame interval number and the reserved adjustment number, the reserved adjustment number being used for relay nodes to reduce idle code groups before forwarding the synchronization frame.

[0022] Specifically, the synchronization frame's period sequence number field is used to write the number of the current synchronization period, the master clock transmit count value field is used to write the local count value latched when the master clock node sends this synchronization frame, and the predetermined count position field includes a node-level digital segment and the corresponding predetermined count position value. Before sending the synchronization frame, the master clock node reads the reserved adjustment quantity and... Determine the number of idle code groups before the synchronization frame, where, The number of idle code groups initially sent by the master clock node. The minimum number of inter-frame intervals specified for Ethernet. To reserve the number of idle code groups. For example, when the minimum inter-frame interval is 12 idle code groups and the reserved number of idle code groups is 8, the master clock node sends 20 idle code groups before the synchronization frame; if the first-level relay node needs to reduce 3 idle code groups later, 17 idle code groups will still be reserved after the reduction, which is not less than the minimum inter-frame interval.

[0023] S2. When the relay node detects the start-of-frame delimiter of the synchronization frame at the upstream fiber optic port, it uses the local counter driven by the receiver recovery clock to record the reached count value and reads the predetermined count position corresponding to the local node. Specifically, a relay node has an upstream fiber optic port, a downstream fiber optic port, a receiver recovery clock counter, and synchronization frame parsing logic. The upstream fiber optic port recovers the receiver recovery clock from the received bitstream, and the receiver recovery clock counter increments according to this clock. When the upstream fiber optic port detects the start-of-frame delimiter of the synchronization frame, the relay node immediately latches the current count value of the receiver recovery clock counter as the arrival count value and associates this arrival count value with the period sequence number of the synchronization frame. The synchronization frame parsing logic then reads the predetermined count position field in the synchronization frame and obtains the predetermined count position corresponding to the current node level. If the synchronization frame verification fails or the period sequence number does not meet the expected increment relationship, the relay node maintains the adjustment state of the previous valid synchronization period and marks that synchronization period as invalid, without using the invalid synchronization frame to update the predetermined count position or count margin.

[0024] Furthermore, in one embodiment of the present invention, the receiver recovery clock is recovered from the received code stream by the upstream fiber optic port; the local counter increments according to the receiver recovery clock, and latches the current count value as the arrival count value when a frame start delimiter is detected; when the transmission clock of the downstream fiber optic port is not from the same source as the receiver recovery clock, the relay node converts the difference between the arrival count value and the predetermined count position to the transmission clock domain of the downstream fiber optic port according to the ratio of the transmission clock count increment to the receiver recovery clock count increment within the same synchronization period, and uses the converted difference as the difference to determine the number of idle code groups to be increased or decreased, wherein the count length corresponding to a single idle code group is the count length in the transmission clock domain of the downstream fiber optic port.

[0025] Specifically, the relay node records the receiver's recovery clock count increment within the same synchronization cycle. and downstream transmit clock count increment When the count value is reached... The predetermined counting position is At that time, the relay node first obtains the clock domain difference recovered from the receiver. If the transmitting clock of the downstream fiber optic port and the recovered clock of the receiving end are not from the same source, then proceed as follows: The difference is converted to the downstream fiber optic port's transmit clock domain, where... This is the transmit clock domain difference. The count length corresponding to a single idle code group. The increment of the transmit clock counter during the transmission of an idle code group via the downstream fiber optic port is determined and stored in the port's parameter register. For example, within the same synchronization period, the receiver recovers the clock count increment. Downstream transmit clock count increment ,like ,but When the transmit clock domain count length corresponding to a single idle code group In this case, the difference should be calculated using 100 transmit clock domain counts instead of directly determining the number of idle code groups using 80 receive recovery clock domain counts.

[0026] S3. The relay node determines the number of idle code groups to be added or reduced based on the difference between the arrival count value and the predetermined count position, and the count length corresponding to a single idle code group. Specifically, the logic for determining the number of idle code groups in a relay node reads the difference used for calculation and the count length corresponding to a single idle code group. It determines the adjustment direction based on the sign of the difference and the integer number of idle code groups based on the absolute value of the difference. When the downstream transmitting clock and the receiver's recovered clock are not from the same source, the difference used for calculation is the converted transmitting clock domain difference; when they are from the same source, the difference used for calculation is the original difference between the reached count value and the predetermined count position. The logic for determining the number of idle code groups to be increased or decreased, the adjustment direction, the period number, and the current node level are written into the adjustment register for use by the downstream fiber optic port transmission control logic.

[0027] Furthermore, in one embodiment of the present invention, determining the number of idle code groups to be increased or decreased includes: When the arrival count value is greater than the predetermined count position, the difference between the two is used as the direction for reducing the idle code group; When the arrival count value is less than the predetermined count position, the difference between the two is used as the direction for increasing the idle code group; When the arrival count value equals the predetermined count position, the number of idle code groups to be increased or decreased is determined to be zero; Divide the absolute value of the difference by the count length corresponding to a single free code group and round down to obtain the number of free code groups to be increased or decreased.

[0028] Specifically, when If the start-of-frame delimiter of a synchronization frame arrives at the local node's count position later than the predetermined count position, the relay node will adjust its direction to decrease idle code groups, causing subsequent start-of-frame delimiters sent downstream to arrive earlier; when When the start-of-frame delimiter of a synchronization frame arrives at the local node's counting position earlier than the predetermined counting position, the relay node will adjust its direction to increase the idle code group, thus delaying the start-of-frame delimiter sent downstream. At that time, the addition or reduction of integer free code groups is not performed. The quantity to be adjusted is based on... It is confirmed that, among them, The number of idle code groups to be increased or decreased. The difference used for calculation, The count length corresponding to a single free code group. This indicates rounding down. For example, if the clock domain difference is transmitted... The count length corresponding to a single idle code group ,but The remaining count value is 5. If the count value is greater than the predetermined count position at this time, it is expected that 4 idle code groups will be reduced this week, and the remaining 5 count values ​​will be used as the count margin in the reduction direction to participate in the subsequent synchronization cycle calculation.

[0029] Furthermore, in one embodiment of the present invention, the remaining count value after dividing the absolute value of the difference by the count length corresponding to a single idle code group is recorded as a negative count remainder in the direction of decreasing idle code groups and as a positive count remainder in the direction of increasing idle code groups. In subsequent synchronization cycles, the positive or negative count remainder is algebraically merged with the new difference value, and when the absolute value of the merged result reaches the count length corresponding to an idle code group, an additional idle code group is added or removed according to the sign of the merged result.

[0030] Specifically, relay nodes are arranged according to... Get the remaining count value When the adjustment direction is the direction of decreasing idle code groups, Write a negative value to the count balance register; when the adjustment direction is to increase the direction of the idle code group, A positive value is written to the count balance register. When the subsequent synchronization cycle arrives, the relay node merges the signed count balance in the count balance register with the new difference algebra to obtain the merged result. Press again Determine whether to add or remove an idle code group. For example, if the remaining count value in the previous synchronization cycle was 5 and recorded as -5 in the decreasing direction, and the new difference in the next synchronization cycle corresponds to the decreasing direction with a remaining count value of 4, then the merged result is -9; when hour, The count length corresponding to one idle code group has been reached, so one additional idle code group is decremented, and the remaining count balance is updated to -1. If the merging result is positive, an additional idle code group is added in the increasing direction. Through this process, the count deviation of less than one idle code group will not be continuously lost in multiple synchronization cycles due to rounding down.

[0031] S4. Before forwarding the synchronization frame to the downstream fiber optic port, the relay node adjusts the number of idle code groups before the synchronization frame according to the number of idle code groups to be increased or decreased, and sends the frame start delimiter and the synchronization frame after adjustment. Specifically, before forwarding the synchronization frame, the downstream fiber port transmission control logic of the relay node first reads the adjustment direction and the number to be adjusted from the adjustment register, and then reads the number of idle code groups that can be transmitted before the current synchronization frame. If the adjustment direction is to decrease the number of idle code groups, the transmission control logic decreases the number of idle code groups before the synchronization frame and sends the start-of-frame delimiter and the synchronization frame after the reduced idle code group sequence; if the adjustment direction is to increase the number of idle code groups, the transmission control logic adds the corresponding number of idle code groups before the synchronization frame, and then sends the start-of-frame delimiter and the synchronization frame. Since the start-of-frame delimiter is sent immediately after the idle code groups before the synchronization frame, decreasing the number of idle code groups causes the start-of-frame delimiter detected by the downstream node to be earlier, while increasing the number of idle code groups causes the start-of-frame delimiter detected by the downstream node to be later.

[0032] Furthermore, in one embodiment of the present invention, when the relay node adjusts the number of idle code groups before the synchronization frame according to the direction of reducing the number of idle code groups, the number of idle code groups before the synchronization frame is reduced by the number of idle code groups to be reduced, and the number of idle code groups after reduction is not less than the minimum inter-frame interval specified by Ethernet.

[0033] Specifically, before performing the reduction operation, the relay node reads the number of idle code groups before the current synchronization frame. Minimum number of inter-frame intervals and the number of idle code groups to be reduced , and according to Determine the actual reduction amount, among which, This represents the actual reduction in the number of idle code groups. If... This indicates that the local node cannot fully handle the reduction demand. The relay node only reduces the inter-frame interval to the minimum number of frames, and writes the unexecuted reduction amount into the status record for uplink status frame feedback. For example, the number of idle code groups before the current synchronization frame. Minimum number of frame intervals Quantity to be reduced The actual reduction in quantity The two unexecuted idle code groups reduce the demand and enter the uplink status frame as the part to be shared.

[0034] Furthermore, in one embodiment of the present invention, when the relay node adjusts the number of idle code groups before the synchronization frame according to the direction of increasing the idle code groups, the number of idle code groups before the synchronization frame is increased by the number of idle code groups to be increased, and the increased number of idle code groups does not exceed the maximum number that can be increased for the current synchronization period configured by the relay node. The maximum number that can be increased is preferentially carried by the synchronization frame, and is configured locally by the relay node when the synchronization frame does not carry it.

[0035] Specifically, before performing an add operation, the relay node reads the maximum number of nodes that can be added at its current synchronization period. When the synchronization frame carries a maximum increase quantity field, the relay node preferentially uses the field value from the synchronization frame; when the synchronization frame does not carry this field, the relay node reads the pre-configured maximum increase quantity from its local configuration register. The actual increase quantity is determined by... It is confirmed that, among them, To increase the number of idle code groups, This determines the actual number of idle code groups added. If the number to be added exceeds the maximum number that can be added, the excess is written into the current level's status record. For example, if the number to be added is 5 idle code groups, and the maximum number that can be added in the synchronization frame is 3 idle code groups, then the current level node will actually add 3 idle code groups. The adjustment requirements corresponding to the remaining 2 idle code groups will be sent back via the uplink status frame and allocated by the master clock node to the upstream adjacent node or the master clock node in subsequent synchronization cycles.

[0036] Furthermore, in one embodiment provided by the present invention, please refer to... Figure 3 , Figure 3 This invention provides a timing interaction diagram for a multi-node clock synchronization control method for fiber optic Ethernet; the predetermined counting positions of each level of node are updated between adjacent synchronization cycles, specifically as follows: Relay nodes at each level in the After completing the forwarding of the synchronization frame at this level in each synchronization cycle, the arrival count value, the number of idle code groups that have been adjusted, the number of idle code groups that can be further reduced, and the number of idle code groups that can be increased are sent back through the uplink status frame. Master clock node according to the first The uplink status frames of each synchronization period establish the influence of the adjustment of the idle code group of each level of relay node on the arrival time of the frame start delimiter of the downstream node. Specifically, reducing one idle code group of a certain level of relay node corresponds to advancing the frame start delimiter of the downstream node of that level by one idle code group time, and increasing one idle code group corresponds to delaying the frame start delimiter of the downstream node of that level by one idle code group time. The master clock node converts the arrival count deviation corresponding to each level of relay node into idle code group adjustment requirements, and determines the portion exceeding the number of idle code groups that can be further reduced or increased by the current level node as the number of idle code groups to be shared. The master clock node, based on the aforementioned influence relationship and the number of idle code groups that can be further reduced and increased by upstream adjacent nodes, allocates the number of idle code groups to be shared to relay nodes or master clock nodes located upstream of and adjacent to its own node along the synchronization frame transmission direction, and writes the allocation result into the first... The predetermined counting positions of nodes at each level in the synchronization frame of each synchronization cycle.

[0037] Specifically, each relay node completes the first... After the synchronization frame of the first synchronization cycle is forwarded, an uplink status frame is generated. The uplink status frame includes the cycle number, node level, arrival count value, predetermined count position, number of adjusted idle code groups, number of idle code groups that can be further reduced, and number of idle code groups that can be increased. After receiving the uplink status frame, the master clock node establishes an influence relationship record according to the node level. This influence relationship record includes the adjusted node level, adjustment direction, unit idle code group time, range of affected downstream node levels, and the current adjustable margin of the node. For the first... If a level-1 relay node loses one idle code group, then the level-2 relay node... The frame start delimiter received by downstream nodes after level 1 is advanced by one idle code block time; if the node in this level adds one idle code block, then the frame start delimiter is advanced by one idle code block time. The frame start delimiter received by downstream nodes after the first level is delayed by one idle code block time. Based on this, the master clock node converts the arrival count deviation of each level of nodes into idle code block adjustment requirements, and compares them with the number that can be further reduced or increased for the current level of nodes. The portion exceeding the adjustment margin of the current level is the number of idle code blocks to be shared.

[0038] For example, the second-level relay node is at the... There is a need to reduce 4 idle code groups in a synchronization cycle, but the uplink status frame of this node shows that it can further reduce 1 idle code group. Therefore, the master clock node determines the remaining 3 idle code groups as the number of idle code groups to be shared. If the first-level relay node is the upstream neighbor of the second-level relay node along the synchronization frame transmission direction, and the first-level relay node can further reduce 2 idle code groups, then the master clock node allocates 2 idle code group reductions to the first-level relay node; the remaining 1 idle code group reduction is determined by the master clock node in the [missing information - likely a specific timeframe or timeframe]. The allocation is handled by adjusting the corresponding predetermined counting position or the idle code group configuration before the synchronization frame in each synchronization cycle. The master clock node writes the allocation result into the first... The predetermined count position field of each level of node in the synchronization frame of the synchronization cycle makes the first... The relay nodes of each synchronization cycle execute the frame start delimiter arrival time control according to the updated predetermined count position.

[0039] S5. When the slave node detects the frame start delimiter of the adjusted synchronization frame and confirms that the cycle number is continuous, it latches the local counter value of the slave node, and determines the output count position in the local counter of the slave node according to the cycle number, the count value sent by the master clock and the preset count offset, and generates a second pulse or sampling trigger signal.

[0040] Specifically, the slave node includes a local counter, frame start delimiter detection logic, synchronization frame parsing logic, and synchronization output logic. When the slave node detects the frame start delimiter of the adjusted synchronization frame, it immediately latches the current count value of its local counter as the boundary latch count value. Subsequently, the slave node parses the period number and master clock transmission count value in the synchronization frame and performs a continuity check between the current period number and the period number of the previous valid synchronization period. If the period numbers are continuous, the slave node confirms the current synchronization period based on the period number, confirms the count position within the period when the master clock node transmitted the synchronization frame based on the master clock transmission count value, and determines the output count position in the slave node's local counter by combining this with a preset count offset. If the period numbers are not continuous or the synchronization frame verification fails, the slave node does not update the output count position and maintains the output state of the previous valid synchronization period or enters a hold state.

[0041] Furthermore, in one embodiment of the present invention, the generation of the second pulse or sampling trigger signal includes: When a slave node detects the start-of-frame delimiter of an adjusted synchronization frame, it latches its local counter value. The current synchronization period is determined based on the period sequence number in the synchronization frame, and the output count position in the local counter of the slave node within the current synchronization period is determined based on the count value sent by the master clock and the preset count offset. When the local count value of the slave node reaches the output count position, a second pulse or sampling trigger signal corresponding to the current synchronization period is output.

[0042] Specifically, the node records the local counter value latched when detecting the start delimiter of the frame as... The master clock transmit count value in the synchronization frame is recorded as... The preset count offset is recorded as In one embodiment, the preset count offset is the offset already converted to the slave node's local counter domain, and the slave node... The output count position is determined, and the cycle number and the master clock transmit count value are used as the validity index of the output count position; when the master clock transmit count value under the same cycle number is not within the predetermined count range, the slave node does not update. In another embodiment, the node also stores the conversion ratio from the master clock counter domain to the slave node's local counter domain. , and according to Determine the output count position, where, This is the master clock reference count value corresponding to the current synchronization cycle. This represents the counting ratio of the slave node's local counter relative to the master clock counter. For example, if the slave node latches its local counter value... Preset count offset The difference between the master clock transmit count value and the current synchronization cycle master clock reference count value is 100. Then output the count position. When the local counter of the slave node increments to 52100, the slave node outputs the second pulse or sampling trigger signal corresponding to the current synchronization cycle.

[0043] In a continuous operation example, the master clock node is at the Synchronization frames are sent every synchronization cycle, with cycle number 1. The master clock sends a count of 100,000, the predetermined count position for the first-level relay node is 20,000, and the predetermined count position for the second-level relay node is 30,000. Before the synchronization frame, the master clock node sends 20 idle code groups, with a minimum inter-frame interval of 12 idle code groups and a reserved adjustment quantity of 8 idle code groups. When the first-level relay node detects the start-of-frame delimiter, it latches a count of 20,036. Since the count length corresponding to a single idle code group is 8, the difference is 36. The number of idle code groups to be reduced is 4, leaving a remaining count of 4, recorded as a negative count margin in the direction of reduction. Before forwarding the synchronization frame, the first-level relay node reduces 4 idle code groups, leaving 16 idle code groups remaining. When the second-level relay node detects the start-of-frame delimiter, it latches a count of 29986, with a difference of -14. The number of idle code groups to be added is 1, and the remaining count is 6, recorded as a positive count margin in the direction of increase. The second-level relay node adds one idle code group within the maximum possible number. (Complete the...) After one synchronization cycle forwarding, the first-level relay node and the second-level relay node respectively send back the arrival count value, the adjusted number of idle code groups, the number of idle code groups that can be further reduced, and the number of idle code groups that can be increased via uplink status frames. The master clock node updates the first-level relay node based on these uplink status frames. The predetermined counting positions of each level of nodes in the synchronization frame of each synchronization cycle. After the node detects the frame start delimiter of the adjusted synchronization frame, if the cycle number is confirmed... If the count is continuous with the previous valid period, the output count position is determined based on the count value sent by the master clock and the preset count offset, and a second pulse or sampling trigger signal is output when the local counter of the slave node reaches the output count position.

[0044] Please see Figure 6 The present invention also provides a fiber optic Ethernet multi-node clock synchronization control system for implementing the above-mentioned fiber optic Ethernet multi-node clock synchronization control method, comprising: The synchronization frame sending module is used to enable the master clock node to send a number of idle code groups greater than the number required for the minimum inter-frame interval before the synchronization frame in each synchronization cycle, and to send a synchronization frame carrying the cycle number, the master clock sending count value and the predetermined counting position of each level of node; The frame start delimiter detection module is used to enable the relay node to record the arrival count value using a local counter driven by the receiver recovery clock when it detects the frame start delimiter of the synchronization frame at the upstream fiber port, and to read the predetermined count position corresponding to the local node. The idle code group quantity determination module is used to enable the relay node to determine the number of idle code groups to be increased or decreased based on the difference between the arrival count value and the predetermined count position, and the count length corresponding to a single idle code group. The idle code group adjustment and forwarding module is used to enable the relay node to adjust the number of idle code groups before the synchronization frame according to the number of idle code groups to be increased or decreased before forwarding the synchronization frame to the downstream optical fiber port, and to send the frame start delimiter and the synchronization frame after adjustment. The synchronization output module is used to enable the slave node to latch the local counter value when it detects the frame start delimiter of the adjusted synchronization frame and confirms that the cycle number is continuous, and to determine the output count position in the slave node's local counter according to the cycle number, the count value sent by the master clock and the preset count offset, and generate a second pulse or sampling trigger signal.

[0045] Specifically, the synchronization frame transmission module is located within the master clock node, including a synchronization period counter, a master clock local counter, synchronization frame field writing logic, and idle code group transmission control logic. The frame start delimiter detection module is located on the upstream fiber port side of the relay node, including a receiver-end clock recovery counter, frame start delimiter detection logic, and arrival count value latching logic. The idle code group quantity determination module is located within the relay node, including difference calculation logic, clock domain conversion logic, floor function logic, and count margin register. The idle code group adjustment and forwarding module is located on the downstream fiber port side of the relay node, including idle code group increase control logic, idle code group decrease control logic, minimum inter-frame interval constraint logic, and maximum increase quantity constraint logic. The synchronization output module is located within the slave node, including period sequence number continuity judgment logic, master clock transmission count value reading logic, output count position determination logic, and second pulse or sampling trigger signal output logic. The modules mentioned above interact with each other through synchronization frame fields, arrival count values, predetermined count positions, number of idle code groups to be added or reduced, count margin, and uplink status frames, enabling the method steps to be implemented by hardware logic, programmable logic, or embedded control logic.

[0046] Please see Figure 4 and Figure 5 In the experimental verification, a fiber optic Ethernet multi-node link was constructed by selecting one master clock node, three relay nodes and one slave node. Statistical analysis of 500 synchronization cycles was conducted under the conditions of the same link rate, the same synchronization cycle length and the same predetermined counting position. Figure 4The deviation of the count value from the frame start delimiter at the node to the predetermined count position is used as the evaluation index. This deviation is the count difference obtained by subtracting the predetermined count position from the count value. In the synchronization method without adjusting the number of idle code groups before the synchronization frame, the deviation range is -42 to 46 count units. After adopting the method of the present invention, the deviation range converges to -9 to 10 count units. Figure 5 The error in the number of idle code groups determined when the downstream fiber port transmit clock and the receiver recovery clock are from different sources is used as the evaluation index. This error is the difference between the calculated number of idle code groups and the number of idle code groups after calibration with the downstream transmit clock domain count length. Without transmit clock domain conversion, the maximum error is 3 idle code groups; after transmit clock domain conversion, the maximum error is 1 idle code group. The above results show that by adjusting the number of idle code groups before the synchronization frame, converting the transmit clock domain, and accumulating the count margin, it is possible to reduce the deviation of the frame start delimiter arrival position from the predetermined count position and the mismatch of the number of idle code groups adjusted in multi-level nodes.

[0047] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0048] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A method for multi-node clock synchronization control in fiber optic Ethernet, characterized in that, include: S1. The master clock node sends a number of idle code groups greater than the minimum inter-frame interval required before the synchronization frame in each synchronization cycle, and sends a synchronization frame carrying the cycle number, master clock transmission count value and the predetermined counting position of each level of node. S2. When the relay node detects the start-of-frame delimiter of the synchronization frame at the upstream fiber optic port, it uses the local counter driven by the receiver recovery clock to record the reached count value and reads the predetermined count position corresponding to the local node. S3. The relay node determines the number of idle code groups to be added or reduced based on the difference between the arrival count value and the predetermined count position, and the count length corresponding to a single idle code group. S4. Before forwarding the synchronization frame to the downstream fiber optic port, the relay node adjusts the number of idle code groups before the synchronization frame according to the number of idle code groups to be increased or decreased, and sends the frame start delimiter and the synchronization frame after adjustment. S5. When the slave node detects the frame start delimiter of the adjusted synchronization frame and confirms that the cycle number is continuous, it latches the local counter value of the slave node, and determines the output count position in the local counter of the slave node according to the cycle number, the count value sent by the master clock and the preset count offset, and generates a second pulse or sampling trigger signal.

2. The fiber optic Ethernet multi-node clock synchronization control method according to claim 1, characterized in that, The synchronization frame includes a period sequence number field, a master clock transmission count value field, and a predetermined count position field arranged by node level; the number of idle code groups before the synchronization frame includes the minimum inter-frame interval number and the reserved adjustment number, which is used for relay nodes to reduce idle code groups before forwarding the synchronization frame.

3. The fiber optic Ethernet multi-node clock synchronization control method according to claim 1, characterized in that, The receiver recovery clock is recovered from the received code stream by the upstream fiber port; the local counter increments according to the receiver recovery clock and latches the current count value as the arrival count value when a frame start delimiter is detected; when the downstream fiber port's transmission clock is not from the same source as the receiver recovery clock, the relay node converts the difference between the arrival count value and the predetermined counting position to the transmission clock domain of the downstream fiber port according to the ratio of the transmission clock count increment to the receiver recovery clock count increment within the same synchronization period, and uses the converted difference as the difference to determine the number of idle code groups to be increased or decreased, and the counting length corresponding to a single idle code group is the counting length in the transmission clock domain of the downstream fiber port.

4. The fiber optic Ethernet multi-node clock synchronization control method according to claim 1, characterized in that, Determining the number of idle code groups to be increased or decreased includes: When the arrival count value is greater than the predetermined count position, the difference between the two is used as the direction for reducing the idle code group; When the arrival count value is less than the predetermined count position, the difference between the two is used as the direction for increasing the idle code group; When the arrival count value equals the predetermined count position, the number of idle code groups to be increased or decreased is determined to be zero; Divide the absolute value of the difference by the count length corresponding to a single free code group and round down to obtain the number of free code groups to be increased or decreased.

5. The fiber optic Ethernet multi-node clock synchronization control method according to claim 4, characterized in that, When a relay node adjusts the number of idle code groups before the synchronization frame according to the direction of reducing idle code groups, it reduces the number of idle code groups to be reduced before the synchronization frame, and ensures that the reduced number of idle code groups is not less than the minimum inter-frame interval specified by Ethernet.

6. The fiber optic Ethernet multi-node clock synchronization control method according to claim 4, characterized in that, When a relay node adjusts the number of idle code groups before the synchronization frame according to the direction of increasing the idle code groups, it adds the number of idle code groups to be added to the number of idle code groups before the synchronization frame, and ensures that the number of idle code groups after the addition does not exceed the maximum number that can be added for the relay node in the current synchronization period. The maximum number that can be added is preferentially carried by the synchronization frame, and is configured locally by the relay node when the synchronization frame does not carry it.

7. The fiber optic Ethernet multi-node clock synchronization control method according to claim 4, characterized in that, The predetermined counting positions of each level of node are updated between adjacent synchronization cycles, specifically as follows: Relay nodes at each level in the After completing the forwarding of the synchronization frame at this level in each synchronization cycle, the arrival count value, the number of idle code groups that have been adjusted, the number of idle code groups that can be further reduced, and the number of idle code groups that can be increased are sent back through the uplink status frame. Master clock node according to the first The uplink status frames of each synchronization period establish the influence of the adjustment of the idle code group of each level of relay node on the arrival time of the frame start delimiter of the downstream node. Specifically, reducing one idle code group of a certain level of relay node corresponds to advancing the frame start delimiter of the downstream node of that level by one idle code group time, and increasing one idle code group corresponds to delaying the frame start delimiter of the downstream node of that level by one idle code group time. The master clock node converts the arrival count deviation corresponding to each level of relay node into idle code group adjustment requirements, and determines the portion exceeding the number of idle code groups that can be further reduced or increased by the current level node as the number of idle code groups to be shared. The master clock node, based on the aforementioned influence relationship and the number of idle code groups that can be further reduced and increased by upstream adjacent nodes, allocates the number of idle code groups to be shared to relay nodes or master clock nodes located upstream of and adjacent to its own node along the synchronization frame transmission direction, and writes the allocation result into the first... The predetermined counting positions of nodes at each level in the synchronization frame of each synchronization cycle.

8. The fiber optic Ethernet multi-node clock synchronization control method according to claim 4, characterized in that, The remaining count value after dividing the absolute value of the difference by the count length corresponding to a single idle code group is recorded as a negative count surplus in the direction of decreasing idle code groups and a positive count surplus in the direction of increasing idle code groups. In subsequent synchronization cycles, the positive or negative count surplus is algebraically merged with the new difference value, and when the absolute value of the merged result reaches the count length corresponding to an idle code group, an additional idle code group is added or removed according to the sign of the merged result.

9. The fiber optic Ethernet multi-node clock synchronization control method according to claim 1, characterized in that, The generation of the second pulse or sampling trigger signal includes: When a slave node detects the start-of-frame delimiter of an adjusted synchronization frame, it latches its local counter value. The current synchronization period is determined based on the period sequence number in the synchronization frame, and the output count position in the local counter of the slave node within the current synchronization period is determined based on the count value sent by the master clock and the preset count offset. When the local count value of the slave node reaches the output count position, a second pulse or sampling trigger signal corresponding to the current synchronization period is output.

10. A fiber optic Ethernet multi-node clock synchronization control system, characterized in that, A method for implementing a fiber optic Ethernet multi-node clock synchronization control according to any one of claims 1 to 9 includes: The synchronization frame sending module is used to enable the master clock node to send a number of idle code groups greater than the number required for the minimum inter-frame interval before the synchronization frame in each synchronization cycle, and to send a synchronization frame carrying the cycle number, the master clock sending count value and the predetermined counting position of each level of node; The frame start delimiter detection module is used to enable the relay node to record the arrival count value using a local counter driven by the receiver recovery clock when it detects the frame start delimiter of the synchronization frame at the upstream fiber optic port, and to read the predetermined count position corresponding to the local node. The idle code group quantity determination module is used to enable the relay node to determine the number of idle code groups to be increased or decreased based on the difference between the arrival count value and the predetermined count position, and the count length corresponding to a single idle code group. The idle code group adjustment and forwarding module is used to enable the relay node to adjust the number of idle code groups before the synchronization frame according to the number of idle code groups to be increased or decreased before forwarding the synchronization frame to the downstream optical fiber port, and to send the frame start delimiter and the synchronization frame after adjustment. The synchronization output module is used to enable the slave node to latch the local counter value when it detects the frame start delimiter of the adjusted synchronization frame and confirms that the cycle number is continuous, and to determine the output count position in the slave node's local counter according to the cycle number, the count value sent by the master clock and the preset count offset, and generate a second pulse or sampling trigger signal.

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