Method of forming a power semiconductor device

Abstract

The application provides a forming method of a power semiconductor device, comprising: providing a power semiconductor device; bonding a front surface of the device to a carrier through a temporary bonding glue layer, and exposing a back electrode forming side surface; performing a first removal treatment on the back electrode forming side surface, and obtaining a state parameter of the back electrode forming side surface after the first removal treatment; determining a removal target and a process constraint of a second removal treatment according to the state parameter, and determining a process parameter of the second removal treatment according to the removal target and the process constraint; performing the second removal treatment on the back electrode forming side surface according to the process parameter; and performing a third removal treatment on the back electrode forming side surface after the second removal treatment, so as to form a contact surface for back electrode metallization. By using the technical scheme, the surface roughness and the surface defect state of the back electrode forming side surface can be effectively improved, and the contact stability of the back electrode is improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing technology, and more particularly to a method for forming a power semiconductor device. Background Technology

[0002] Vertical power semiconductor devices typically include a source structure and a gate structure located on the front side of the device, and a drain structure located on the back side of the device wafer. When the device is turned on, current flows from the source side to the drain side along the thickness direction of the device.

[0003] To reduce the drain-side substrate resistance, decrease the device on-resistance, and improve the heat dissipation path, it is typically necessary to thin the back side of the device wafer on the drain side. However, current thinning process capabilities still need improvement. Summary of the Invention

[0004] In view of this, the present disclosure provides a method for forming a power semiconductor device, which can effectively improve the surface roughness and surface defect state of the back electrode forming side surface, thereby improving the contact stability of the back electrode.

[0005] To achieve the above objectives, the present disclosure provides the following technical solutions.

[0006] In a first aspect, embodiments of this disclosure provide a method for forming a power semiconductor device, comprising: A power semiconductor device is provided, the power semiconductor device having a front side and a back side electrode formed opposite to the front side; The front side of the device is bonded to the substrate using a temporary bonding adhesive layer, and the back electrode is exposed to form a side surface; A first removal process is performed on the back electrode forming side surface to thin the back electrode forming side surface to the middle remaining thickness, and the state parameters of the back electrode forming side surface after the first removal process are obtained. The removal target and process constraints of the second removal process are determined based on the state parameters, and the process parameters of the second removal process are determined based on the removal target and the process constraints. The second removal process is performed on the side surface of the back electrode according to the process parameters described above; After the second removal process, a third removal process is performed on the side surface of the back electrode to form a contact surface for metallization of the back electrode.

[0007] Optionally, the first removal process includes mechanical pre-thinning, the second removal process includes plasma dry etching, and the third removal process includes fine polishing. Wherein, the mechanical pre-thinning process is used to remove a first thickness of semiconductor material from the back electrode forming side surface; the plasma dry etching process is used to remove at least a portion of the back damage layer remaining after the mechanical pre-thinning process, and to trim the back electrode forming side surface to the remaining thickness after etching; the fine polishing process is used to reduce the surface roughness and / or surface defect density after the plasma dry etching process; the removal thickness of the first removal process is greater than the removal thickness of the second removal process, and the removal thickness of the second removal process is greater than the removal thickness of the third removal process.

[0008] Optionally, obtaining the state parameters of the side surface where the back electrode is formed includes: The local remaining thickness at multiple locations on the side surface where the back electrode is formed is detected within the thickness detection area, and the current minimum remaining thickness and thickness non-uniformity are determined based on the local remaining thickness at the multiple locations, wherein the thickness non-uniformity is the difference between the maximum and minimum values ​​of the local remaining thickness at the multiple locations. Detect the surface quality parameters of the side surface where the back electrode is formed within the surface detection area; At least a portion of the current minimum remaining thickness, the thickness non-uniformity, and the surface quality parameters are used as state parameters for the side surface of the back electrode formation.

[0009] Optionally, determining the removal target of the second removal process based on the state parameters includes: determining the backside damage removal allowance based on the surface quality parameters, wherein the backside damage removal allowance is used to characterize the thickness of the backside material that needs to be removed by the second removal process after the first removal process; and determining the removal target of the second removal process based on the backside damage removal allowance, the current minimum remaining thickness, the thickness non-uniformity, the preset target remaining thickness range, and the reserved removal amount of the third removal process. Determining the process constraints of the second removal process based on the state parameters includes: determining a thickness safety constraint based on the current minimum remaining thickness, the thickness non-uniformity, the preset target remaining thickness range, and the reserved removal amount of the third removal process; determining a surface quality constraint based on the surface quality parameters and the preset target surface quality range; determining a bonding safety constraint based on at least one of the temporary bonding adhesive layer's tolerance temperature, tolerance time, peel risk threshold, and thermal stability parameters; and using at least one of the thickness safety constraint, the surface quality constraint, and the bonding safety constraint as the process constraints of the second removal process.

[0010] Optionally, determining the backside damage removal allowance based on the surface quality parameters includes: Before performing the second removal process, local diagnostic etching is performed in the diagnostic detection area of ​​the back electrode forming side surface to obtain local diagnostic etching results; wherein, the diagnostic detection area is located in the edge area, scribe line area or non-functional device area of ​​the back electrode forming side surface; The amount of back-side damage removed is determined based on the local diagnostic etching results; wherein, the local diagnostic etching results include at least one of the following: surface roughness after diagnostic etching, surface defect density, residual crack amount, residual pit amount, residual scratch amount, local residual thickness, and local etching rate.

[0011] Optionally, performing local diagnostic etching on the diagnostic detection area of ​​the side surface where the back electrode is formed to obtain local diagnostic etching results includes: Multiple detection sub-regions are selected within the diagnostic detection area; The method of making the multiple detection sub-regions have different cumulative etching removal thicknesses includes: forming a masking structure on the multiple detection sub-regions, and removing the masking structure in stages, setting different opening sequences, setting different exposure times, or setting different local etching cycle numbers, so that the multiple detection sub-regions obtain different cumulative etching removal thicknesses under the same diagnostic etching conditions. After completing the local diagnostic etching, the diagnostic status parameters of the multiple detection sub-regions are detected respectively; Different cumulative etching removal thicknesses are correlated with corresponding diagnostic status parameters to obtain the local diagnostic etching results.

[0012] Optionally, determining the removal target of the second removal process includes: The lower limit of removal for the second removal process is determined based on the remaining amount of damage removed from the back side. The removal upper limit of the second removal process is determined based on the current minimum remaining thickness, the thickness non-uniformity, the lower limit of the preset target remaining thickness range, the reserved removal amount of the third removal process, and the etching thickness safety margin. The etching thickness safety margin is determined based on the thickness non-uniformity or includes at least a portion of the thickness non-uniformity. When the lower limit of removal is not greater than the upper limit of removal, the thickness range between the lower limit of removal and the upper limit of removal is determined as the removal target of the second removal process; When the lower limit of removal is greater than the upper limit of removal, perform supplementary detection, adjust the reserved removal amount of the third removal process, adjust the remaining thickness range of the preset target, or stop the subsequent etching process.

[0013] Optionally, determining the process parameters for the second removal process based on the removal target and the process constraints includes: Multiple candidate plasma dry etching process windows are established, and the candidate plasma dry etching process windows include at least one of the following: radio frequency power, bias power, cavity pressure, etching gas flow rate, etching gas ratio, stage temperature, back-side cooling conditions, and etching time. Obtain at least one of the following for each candidate plasma dry etching process window: predicted etching removal amount, predicted etching rate, predicted etching uniformity, predicted remaining thickness after etching, predicted surface roughness after etching, predicted surface defect density after etching, predicted process temperature, and predicted bonding failure risk. Determine whether each candidate plasma dry etching process window meets the removal target and the process constraints; From the candidate plasma dry etching process window that satisfies the removal target and the process constraints, the candidate plasma dry etching process window is selected as the process parameter for the second removal process based on at least one of the following evaluation indicators: predicted bonding failure risk, predicted etching uniformity, predicted post-etching surface roughness, and predicted post-etching surface defect density.

[0014] Optionally, the formation method satisfies one or more of the following: The first removal process includes at least one of diamond wheel grinding, single-sided back grinding, double-sided grinding, or mechanical polishing; The second removal process uses a fluorine-containing etching gas, which includes at least one of SF6, CF4, CHF3, or NF3; the auxiliary gas for the second removal process includes at least one of O2, Ar, He, or N2. The third removal process includes at least one of chemical mechanical polishing, colloidal silica polishing, or low-pressure fine polishing.

[0015] Optionally, the forming method further includes: After performing the third removal process, a drain electrode and a plug electrically connected to the drain electrode are formed on the contact surface; wherein the back electrode side back surface is one of the drain side back surface, the collector side back surface, or the cathode side back surface. After performing the third removal process, the substrate is removed.

[0016] In the method for forming a power semiconductor device provided by this invention, on the one hand, by supporting the front side of the device with a carrier wafer, the risk of warping, cracking, or breakage of the power semiconductor device during the back-side thinning, etching, and polishing processes can be reduced. On the other hand, by obtaining the state parameters of the back electrode formation side surface after the first removal process, and determining the removal target and process constraints of the second removal process based on the state parameters, the process parameters of the second removal process can be adjusted in real time according to the actual thickness and surface condition. This reduces the risks of insufficient back-side damage removal, excessive etching, insufficient local residual thickness, and subsequent poor back-side electrode contact. By performing a third removal process, the surface roughness and surface defect state of the back electrode formation side surface can be improved, thereby forming a contact surface suitable for back electrode metallization and improving the contact stability of the back electrode. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the structure of a vertical power semiconductor device; Figure 2 This is a flowchart of a method for forming a power semiconductor device according to an embodiment of this disclosure. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0019] For vertical power semiconductor devices, the on-resistance typically includes multiple components such as channel resistance, JFET region resistance, drift region resistance, and substrate resistance on the back electrode side.

[0020] The substrate resistance on the back electrode side is related to the remaining thickness of the semiconductor material on the back electrode side. When the semiconductor material on the back electrode side is thicker, the series resistance on the drain side, collector side, or cathode side is larger, which is not conducive to reducing the on-resistance of the device.

[0021] See Figure 1 , Figure 1 This is a schematic diagram of the structure of a vertical power semiconductor device.

[0022] like Figure 1 As shown, a vertical power semiconductor device includes a source, a gate, and a drain. The source is located on the upper surface of the device, the drain is located on the lower surface of the device, and the gate is located between the source and is used to control the conduction state of the channel region.

[0023] Furthermore, Figure 1 The diagram also illustrates the composition of the device's on-resistance, which includes the source region resistance R. n+ Channel resistance R ch Accumulation region resistance R acc JFET region resistance R JFET Drift region resistance R drift and drain resistance R drain The resistors mentioned above are distributed along the conduction current path of the device and together constitute the conduction resistance of the device.

[0024] Specifically, when the device is in the on state, the carriers on the source side first pass through the highly doped source region, correspondingly forming the source region resistance R. n+ Subsequently, charge carriers pass through the channel region formed by the gate control, correspondingly forming the channel resistance R. ch Subsequently, charge carriers enter the accumulation region below or near the gate, forming the corresponding accumulation region resistance R. acc .

[0025] Furthermore, charge carriers are transported into the device through the current contraction region between adjacent bulk regions. This region can be equivalent to a JFET region, and a corresponding JFET region resistance R is formed. JFET Subsequently, charge carriers enter the drift region vertically. The drift region is used to withstand the reverse voltage in the device's off-state state and forms a corresponding drift region resistance R in the on-state state. drift Finally, charge carriers enter the drain through the substrate region or drain contact region on the drain side, correspondingly forming the drain resistance R. drain .

[0026] Therefore, the on-resistance of a vertical power semiconductor device is: R n+ +R ch +R acc +R JFET +R drift +R drain .

[0027] In HV VDMOS devices, the substrate thickness is relatively thick (e.g., up to 200µm), resulting in high resistance and thus high Rresistance in high-voltage devices. drift It becomes the main resistance loss.

[0028] Referring to Table 1, when BV=30 increases to BV=600V (corresponding to high voltage conditions), R... drift The percentage increased from 31% to 97%.

[0029] In other words, Figure 1 In the schematic structure, when under high pressure, R drift It becomes the main resistance loss.

[0030]

[0031] Table 1 Comparison of Resistance Loss with Voltage Therefore, during the formation of power semiconductor devices, it is usually necessary to thin the back electrode side surface (i.e., the back side of the substrate) to reduce the back electrode side resistance and provide a contact surface for subsequent back electrode metallization.

[0032] In actual processes, mechanical grinding is used for back-side thinning. While this method offers high material removal efficiency, it can easily introduce surface defects such as cracks, pits, scratches, grinding marks, chipping, residual stress, or damaged layers onto the back electrode side. Direct metallization of the back electrode can easily lead to unstable ohmic contacts, increased leakage current, chip crack propagation, or decreased package reliability.

[0033] In some solutions, after mechanical grinding, plasma dry etching is used to remove the back-side damage layer, and then fine polishing is used to form the back-side contact surface.

[0034] However, the inventors discovered in actual processes that plasma dry etching has higher uncertainties compared to mechanical grinding and fine polishing. For example, the actual etching rate of plasma dry etching is affected by factors such as gas flow rate, gas ratio, RF power, bias power, cavity pressure, stage temperature, back-side cooling status, wafer warpage, and temporary bonding status.

[0035] Meanwhile, different batches of wafers exhibit variations in surface roughness, residual damage layer thickness, and thickness inhomogeneity after mechanical pre-thinning. Therefore, if the same etching process parameters are consistently used, issues such as insufficient removal of backside damage, excessive etching, localized over-thinning, excessively high surface roughness after etching, thermal failure of temporary bonding adhesive layers, or exacerbated warping of the bonding structure may occur.

[0036] Based on this, embodiments of this application provide a method for forming a power semiconductor device. This method employs a first removal process, a second removal process, and a third removal process in sequence to thin the back side of the back electrode. The first removal process can be used for rapid thinning; the second removal process is used for controlled etching based on the actual state parameters after the first removal process; and the third removal process is used to improve the back surface state after the second removal process to form a contact surface suitable for back electrode metallization.

[0037] Specifically, this embodiment does not simply set a fixed etching time. Instead, after the first removal process, it acquires the state parameters of the back side electrode and determines the removal target and process constraints of the second removal process based on these state parameters. Then, it determines the process parameters of the second removal process based on the removal target and process constraints. Therefore, the second removal process can be adjusted according to the actual back side state of different wafers, different regions, or different batches, thereby reducing the risk of insufficient back side damage removal and over-etching.

[0038] To enable those skilled in the art to have a clearer understanding of the technical concepts, principles and effects contained in this application, a detailed description is provided below with reference to the accompanying drawings, specific embodiments and specific application scenarios.

[0039] See Figure 2 , Figure 2 This is a flowchart illustrating a method for forming a power semiconductor device according to an embodiment of this disclosure. Figure 2 As shown, the forming method may include steps S201 to S206.

[0040] S201, a power semiconductor device is provided, the power semiconductor device having a front side and a back side electrode forming a side surface opposite to the front side.

[0041] In some embodiments, the power semiconductor device may be a silicon wafer, a silicon carbide wafer, a gallium nitride wafer, a gallium oxide wafer, or other wafers suitable for manufacturing power semiconductor devices.

[0042] A power semiconductor device may include multiple power semiconductor device units, each of which may be a power MOSFET, IGBT, power diode, Schottky diode, junction barrier Schottky diode, or other vertically conducting power device.

[0043] In this embodiment, the front side of the device refers to the side where a front device structure has been formed or is to be formed.

[0044] For example, the front side of the device may have at least one of the following: gate structure, source region, body region, source metal layer, interlayer dielectric layer, passivation layer, and termination protection structure.

[0045] The back electrode forming side surface refers to the side that needs to be thinned later and used to form the back electrode metal layer (e.g., drain).

[0046] For power MOSFETs, the back electrode forming side surface can be referred to as the drain-side back surface; for IGBTs, the back electrode forming side surface can be referred to as the collector-side back surface; for power diodes, the back electrode forming side surface can be referred to as the cathode-side back surface.

[0047] As a specific example, the power semiconductor device is a silicon carbide power MOSFET wafer. The initial thickness of the wafer (which can be considered as a substrate) is about 200 μm. The front side of the device has already formed the gate structure, source metal layer and passivation protection layer, while the back side is the drain side to be thinned.

[0048] S202, the front side of the device is bonded to the substrate through a temporary bonding adhesive layer, and the back electrode is exposed to form a side surface.

[0049] In some embodiments, the wafer is used to support power semiconductor devices during back-side thinning, reducing the risk of warping, cracking, or breakage of the wafer during thinning, etching, polishing, and cleaning processes.

[0050] The carrier can be a glass carrier, a silicon carrier, a ceramic carrier, or other support sheet with mechanical support capabilities and the ability to withstand the temperature of subsequent processes.

[0051] Temporary bonding adhesive is used to temporarily fix the front side of the device to the substrate.

[0052] The temporary bonding adhesive layer may include heat-release adhesives, UV-release adhesives, BCB adhesives, polyimide adhesives, wax-based temporary bonding materials, or other debondable temporary bonding materials. The temporary bonding adhesive layer shall have sufficient adhesive strength to withstand the mechanical stress, thermal stress, or plasma environment during the subsequent first, second, and third removal processes.

[0053] As an example, a temporary bonding adhesive is first spin-coated on the front side of the device at a spin speed of 800 rpm to 3000 rpm, with a temporary bonding adhesive layer thickness of 5 μm to 50 μm.

[0054] Subsequently, pre-baking is performed at 90°C to 150°C to remove some of the solvent and improve the uniformity of the adhesive layer.

[0055] Then, the front side of the device is aligned and bonded to the glass substrate, and bonding is performed at 150°C to 220°C and 0.2MPa to 2MPa for a bonding time of 1 min to 10 min.

[0056] As an example, bonding can be performed at 200°C and 1 MPa for approximately 5 minutes. After bonding, the front side of the device is supported by a substrate, while the back electrode side is exposed to the outside for subsequent back electrode removal.

[0057] In some embodiments, to avoid air bubbles in the temporary bonding adhesive layer, bonding can be performed in a vacuum environment, or a slow heating and gradual pressurization process can be performed after bonding. The warpage, number of air bubbles, and edge adhesive layer integrity of the bonded structure can also be detected after bonding. If large-area air bubbles are detected or the warpage exceeds a preset threshold, the wafer can be rebonded or rejected.

[0058] S203, perform a first removal process on the back electrode forming side surface to thin the back electrode forming side surface to the middle remaining thickness, and obtain the state parameters of the back electrode forming side surface after the first removal process.

[0059] In some embodiments, the first removal process is used to rapidly remove a large thickness of semiconductor material from the back side of the back electrode. The first removal process can be a mechanical pre-thinning process, and includes at least one of diamond wheel grinding, single-sided back grinding, double-sided grinding, or mechanical polishing.

[0060] The intermediate remaining thickness refers to the thickness of the semiconductor material remaining in the power semiconductor device after the first removal process. This intermediate remaining thickness is typically greater than the final target remaining thickness in order to reserve removal margin for subsequent second and third removal processes.

[0061] Specifically, mechanical pre-thinning is used to remove a first thickness of semiconductor material from the side surface where the back electrode is formed.

[0062] As a specific example, for a silicon carbide power MOSFET wafer with an initial thickness of about 200 μm, a diamond grinding wheel can be used to rough grind the back side of the drain, reducing the wafer thickness from about 200 μm to about 100 μm.

[0063] The rough grinding process can be divided into two stages: the first stage uses a coarser-grit grinding wheel, such as #2000 to #4000, to quickly remove approximately 70μm to 90μm of thickness; the second stage uses a finer-grit grinding wheel, such as #6000 to #8000, to lightly dress the back surface and further remove approximately 5μm to 20μm of thickness. Deionized water can be used for cooling and rinsing during the grinding process to reduce grinding temperature rise and remove grinding debris.

[0064] In some embodiments, after performing the first removal process, it is possible to obtain the state parameters of the back side of the back electrode.

[0065] The state parameters are used to characterize the actual state of the back electrode forming side surface after the first removal process.

[0066] In this embodiment, obtaining the state parameters of the back electrode forming side surface includes: detecting the local remaining thickness at multiple locations on the back electrode forming side surface within a thickness detection area, and determining the current minimum remaining thickness and thickness non-uniformity based on the local remaining thickness at the multiple locations, wherein the thickness non-uniformity is the difference between the maximum and minimum values ​​of the local remaining thickness at the multiple locations; detecting the surface quality parameters of the back electrode forming side surface within a surface detection area; and using at least a portion of the current minimum remaining thickness, the thickness non-uniformity, and the surface quality parameters as the state parameters of the back electrode forming side surface.

[0067] Specifically, the local residual thickness at multiple locations on the side surface where the back electrode is formed can be detected within the thickness detection area, and the current minimum residual thickness and thickness non-uniformity can be determined based on the local residual thickness at multiple locations. The thickness non-uniformity can be the difference between the maximum and minimum local residual thicknesses at the multiple locations.

[0068] As a specific example, nine thickness measurement points can be selected on the back electrode forming side surface, including the wafer center point, four measurement points at approximately half the radius, and four measurement points near the wafer edge. The remaining thickness at each measurement point is measured using a non-contact thickness gauge, infrared thickness gauge, white light interferometer, or capacitive thickness gauge.

[0069] If the current minimum remaining thickness is measured to be 98 μm and the current maximum remaining thickness is 104 μm, then the thickness non-uniformity is 6 μm.

[0070] In some embodiments, surface quality parameters of the back electrode forming side surface can be detected within the surface detection area. Surface quality parameters may include at least one of surface roughness, surface defect density, crack residue, pit residue, scratch residue, grinding mark residue, and residual damage layer thickness.

[0071] As a specific example, the surface roughness of the side surface on which the back electrode is formed can be detected using a white light interferometer, an atomic force microscope, or a contact profilometer.

[0072] If the detected Ra value is 80 nm, then this Ra value can be used as the surface quality parameter in the state parameters.

[0073] Cracks, pits, and scratches can be detected using optical microscopes, scanning electron microscopes, or automated defect detection equipment, and the surface defect density can be calculated based on the number of defects per unit area.

[0074] For example, if 20 cracks or pits are detected within a 1 mm² detection area, the surface defect density can be calculated as 20 cracks / mm². For edge chipping defects, the number of defects per unit edge length can also be used for statistical analysis.

[0075] In some embodiments, at least a portion of the current minimum remaining thickness, thickness non-uniformity, and surface quality parameters can be correlated with the position coordinates of the side surface where the back electrode is formed to form state parameters with spatial distribution information. For example, a thickness distribution map, roughness distribution map, or defect density distribution map can be formed to subsequently determine the removal targets and process constraints of the second removal process.

[0076] Thus, by acquiring the status parameters, the degree of damage on the back side after the first removal process can be determined, providing a basis for determining the remaining amount of damage removal on the back side and the removal target of the second removal process. Therefore, the second removal process can simultaneously consider thickness safety and damage removal requirements, improving the accuracy of process control.

[0077] S204, determine the removal target and process constraints of the second removal process based on the state parameters, and determine the process parameters of the second removal process based on the removal target and the process constraints.

[0078] In this embodiment, the second removal process includes plasma dry etching. The removal target of the second removal process is used to define the thickness or thickness range of the backside material to be removed in the second removal process. The process constraints of the second removal process are used to define the process conditions that need to be met during or after the second removal process, such as at least one of thickness safety constraints, surface quality constraints, and bonding safety constraints.

[0079] Specifically, plasma dry etching is used to remove at least a portion of the back-side damage layer remaining after the mechanical pre-thinning process, and to trim the back-side electrode forming side surface to the remaining thickness after etching.

[0080] In some embodiments, by performing a first removal process, a status parameter can be obtained. Based on this status parameter, the removal target and process constraints can be further determined.

[0081] The following examples illustrate how to determine the removal target and process constraints. Determining the removal target of the second removal process based on the state parameters includes: A1) Determine the backside damage removal allowance based on the surface quality parameters. The backside damage removal allowance is used to characterize the thickness of the backside material that needs to be removed by the second removal process after the first removal process.

[0082] In some embodiments, the surface quality parameters can reflect the morphology of the back side after the first removal treatment. Based on the surface quality parameters, the amount of damage removal residue on the back side can be further determined.

[0083] In one example, step A1) may include: performing local diagnostic etching in a diagnostic detection area on the back electrode forming side surface before performing the second removal process to obtain a local diagnostic etching result; wherein the diagnostic detection area is located in an edge region, scribe line region, or non-functional device region on the back electrode forming side surface; determining the back damage removal allowance based on the local diagnostic etching result; wherein the local diagnostic etching result includes at least one of the following: surface roughness after diagnostic etching, surface defect density, crack residue, pit residue, scratch residue, local remaining thickness, and local etching rate.

[0084] Specifically, before performing the second removal process, a local diagnostic etching is performed to determine the results of the local diagnostic etching. Further, the amount of backside damage removal is determined based on the results of the local diagnostic etching.

[0085] For example, multiple detection sub-regions are selected in the diagnostic detection area; the multiple detection sub-regions are made to have different cumulative etching removal thicknesses, including: forming a masking structure on the multiple detection sub-regions, and removing the masking structure in stages, setting different opening sequences, setting different exposure times, or setting different local etching cycle numbers, so that the multiple detection sub-regions obtain different cumulative etching removal thicknesses under the same diagnostic etching conditions; after completing the local diagnostic etching, the diagnostic status parameters of the multiple detection sub-regions are detected respectively; the different cumulative etching removal thicknesses are associated with the corresponding diagnostic status parameters to obtain the local diagnostic etching results.

[0086] By removing the masking structure in stages, setting different opening sequences, different exposure times, or different local etching cycle numbers, multiple etching removal thickness points can be easily obtained, thus forming a diagnostic result similar to an etching depth gradient. This allows for the correlation between different cumulative etching removal thicknesses and diagnostic state parameters, enabling the determination of the etching thickness required when back-side damage is essentially eliminated or surface quality tends to stabilize. This more accurately determines the remaining back-side damage removal amount, reducing the risk of insufficient or excessive etching during the subsequent second removal process.

[0087] A2) Determine the removal target of the second removal process based on the back damage removal allowance, the current minimum remaining thickness, the thickness unevenness, the preset target remaining thickness range, and the reserved removal amount of the third removal process.

[0088] In some embodiments, after determining the amount of damage to be removed on the back side, the removal target of the second removal process is further determined.

[0089] In one example, step A2) may include: determining the lower limit of the second removal process based on the back-side damage removal allowance; determining the upper limit of the second removal process based on the current minimum remaining thickness, the thickness non-uniformity, the lower limit of the preset target remaining thickness range, the reserved removal amount of the third removal process, and the etching thickness safety margin, wherein the etching thickness safety margin is determined based on the thickness non-uniformity, or includes at least a portion of the thickness non-uniformity; when the lower limit of removal is not greater than the upper limit of removal, determining the thickness range between the lower limit of removal and the upper limit of removal as the removal target of the second removal process; when the lower limit of removal is greater than the upper limit of removal, performing supplementary detection, adjusting the reserved removal amount of the third removal process, adjusting the preset target remaining thickness range, or stopping subsequent etching processes.

[0090] In step A2), by setting a lower removal limit, the second removal process can be guaranteed to remove at least a sufficient thickness of material to improve the backside damage, reducing the risk of residual backside damage layer. By setting an upper removal limit, the second removal process can be guaranteed not to result in insufficient remaining thickness in some areas due to over-etching, and necessary removal space can be reserved for the third removal process. By determining the etching thickness safety margin based on the thickness non-uniformity, or including at least a portion of the thickness non-uniformity, a more conservative etching control strategy can be adopted when the thickness non-uniformity is large after the first removal process, thereby reducing the risk of over-etching weak areas.

[0091] Accordingly, determining the process constraints of the second removal process based on the state parameters includes: determining a thickness safety constraint based on the current minimum remaining thickness, the thickness non-uniformity, the preset target remaining thickness range, and the reserved removal amount of the third removal process; determining a surface quality constraint based on the surface quality parameters and the preset target surface quality range; determining a bonding safety constraint based on at least one of the temporary bonding adhesive layer's tolerance temperature, tolerance time, peel risk threshold, and thermal stability parameters; and using at least one of the thickness safety constraint, the surface quality constraint, and the bonding safety constraint as the process constraints of the second removal process.

[0092] For example, local diagnostic etching is performed in the diagnostic detection area on the back electrode formation side surface to obtain local diagnostic etching results, and then the back damage removal allowance is determined based on the local diagnostic etching results. The diagnostic detection area can be located in the edge area, scribe line area, or non-active device area of ​​the back electrode formation side surface to avoid affecting the final performance of the active device area.

[0093] As a concrete example, four detection sub-regions can be selected within the dicing area. A thin film of photoresist, silicon oxide, silicon nitride, or metal is formed on each of these four sub-regions as a masking structure. By removing the masking structure in stages, setting different opening sequences, different exposure times, or different local etching cycles, the four detection sub-regions can achieve cumulative etching removal thicknesses of 5 μm, 10 μm, 15 μm, and 20 μm respectively under the same diagnostic etching conditions.

[0094] The diagnostic etching conditions can be achieved using SF6 / O2 plasma. For example, the SF6 flow rate is 50 sccm to 150 sccm, the O2 flow rate is 5 sccm to 30 sccm, the RF power is 300 W to 1000 W, the bias power is 0 W to 100 W, and the cavity pressure is 10 mTorr to 100 mTorr.

[0095] After completing the local diagnostic etching, the diagnostic status parameters of the four detection sub-regions are measured respectively. The diagnostic status parameters may include at least one of the following: surface roughness after diagnostic etching, surface defect density, crack residue, pit residue, scratch residue, local remaining thickness, and local etching rate. By correlating different cumulative etching removal thicknesses with the corresponding diagnostic status parameters, the local diagnostic etching results can be obtained.

[0096] For example, when the cumulative etching removal thickness is 5 μm, scratches and cracks are still noticeable, with Ra of 60 nm; when the cumulative etching removal thickness is 10 μm, the number of cracks is significantly reduced, with Ra of 35 nm; when the cumulative etching removal thickness is 15 μm, the cracks are almost completely removed, with Ra of 22 nm; when the cumulative etching removal thickness is 20 μm, Ra only decreases to 20 nm, and the surface state changes tend to stabilize. Therefore, it can be determined that an etching removal thickness of approximately 15 μm is sufficient to essentially remove the backside damage layer introduced by the first removal process. In this case, 15 μm can be defined as the backside damage removal margin, or the sum of 15 μm and a diagnostic safety margin of 2 μm to 5 μm can be defined as the backside damage removal margin, for example, 18 μm.

[0097] After determining the amount of damage removal on the back side, the removal target of the second removal process can be determined based on the amount of damage removal on the back side, the current minimum remaining thickness, the amount of thickness unevenness, the preset target remaining thickness range, and the amount of removal reserved in the third removal process.

[0098] Specifically, the lower limit of the second removal process is determined based on the amount of damage removed from the back side; the upper limit of the second removal process is determined based on the current minimum remaining thickness, the lower limit of the preset target remaining thickness range, the reserved removal amount of the third removal process, and the safety margin of the etching thickness.

[0099] The etching thickness safety margin can be determined based on the thickness non-uniformity, or may include at least a portion of the thickness non-uniformity. When the lower removal limit is not greater than the upper removal limit, the thickness range between the lower and upper removal limits can be defined as the removal target of the second etching process. When the lower removal limit is greater than the upper removal limit, supplementary detection, adjustment of the reserved removal amount for the third etching process, adjustment of the preset target remaining thickness range, or cessation of subsequent etching processes can be performed.

[0100] As a specific example, after the first removal process, the current minimum remaining thickness is 100 μm, the preset target remaining thickness range is 38 μm to 45 μm, the reserved removal amount for the third removal process is 5 μm, the backside damage removal allowance is 20 μm, and the etching thickness safety margin is 3 μm. In this case, the lower limit of the second removal process can be 20 μm, and the upper limit of the second removal process can be 100 μm - 38 μm - 5 μm - 3 μm, i.e., 54 μm. Therefore, the removal target of the second removal process can be 20 μm to 54 μm. In actual execution, approximately 40 μm can be removed, reducing the wafer thickness from approximately 100 μm to approximately 60 μm.

[0101] If the lower removal limit is greater than the upper removal limit, it indicates that the second removal process in the current wafer state is insufficient to fully remove backside damage and cannot guarantee thickness safety. In this case, supplementary detection can be performed, the reserved removal amount of the third removal process can be adjusted, the preset target remaining thickness range can be adjusted, or subsequent etching processes can be stopped. For example, when the backside damage removal allowance is diagnosed as 35μm, but the current minimum remaining thickness is only 70μm, and the final target remaining thickness lower limit is 40μm and the reserved removal amount of the third removal process is 10μm, the space that the second removal process can remove is insufficient. In this case, the reserved removal amount of the third removal process can be reduced, the damage removal allowance can be reconfirmed, or the wafer can be identified as an abnormal wafer.

[0102] When determining the removal target of the second removal process, process constraints for the second removal process can also be determined based on state parameters. Specifically, thickness safety constraints can be determined based on the current minimum remaining thickness, thickness non-uniformity, preset target remaining thickness range, and the reserved removal amount for the third removal process; surface quality constraints can be determined based on surface quality parameters and preset target surface quality range; and bonding safety constraints can be determined based on at least one of the following: the tolerance temperature, tolerance time, peel risk threshold, and thermal stability parameters of the temporary bonding adhesive layer. Thus, at least one of the thickness safety constraints, surface quality constraints, and bonding safety constraints can be used as process constraints for the second removal process.

[0103] Thickness safety constraints are used to prevent the wafer from becoming too thin after the second removal process. For example, the lower limit of the remaining thickness after the second removal process can be determined based on the lower limit of the preset target remaining thickness range, the reserved removal amount for the third removal process, and the etching thickness safety margin. If the lower limit of the preset target remaining thickness range is 38 μm, the reserved removal amount for the third removal process is 5 μm, and the etching thickness safety margin is 3 μm, then the lower limit of the remaining thickness after the second removal process can be set to 46 μm.

[0104] Surface quality constraints are used to control the surface state after the second removal process. For example, the upper limit of surface roughness and / or the upper limit of surface defect density after the second removal process can be determined based on a preset target surface quality range. If the final contact surface requires Ra to be no greater than 5 nm, and the third removal process is expected to reduce Ra by approximately 20 nm, then the upper limit of Ra after the second removal process can be set to 25 nm. Similarly, the upper limit of surface defect density after the second removal process can be determined based on a preset target upper limit of surface defect density and a defect density correction margin for the third removal process.

[0105] Bond safety constraints are used to prevent thermal failure of the temporary bond adhesive layer or instability of the bond structure. For example, the upper limit of the process temperature and the upper limit of the temperature rise rate for the second removal process can be determined based on the thermal failure temperature of the temporary bond adhesive layer, the allowable process temperature of the substrate, the bond strength of the temporary bond adhesive layer, and the warpage of the bond structure. If the thermal failure temperature of the temporary bond adhesive layer is 230°C and the allowable process temperature of the substrate is 250°C, the upper limit of the process temperature in the second removal process can be set to no higher than 200°C or 210°C to allow for a safety margin. If the warpage of the bond structure is large, the upper limit of the temperature rise rate can be reduced to prevent further increase in thermal stress.

[0106] Further, the process parameters for the second removal process are determined based on the removal target and the process constraints.

[0107] S205, Perform the second removal process on the side surface of the back electrode according to the process parameters.

[0108] In some embodiments, the second removal process includes plasma dry etching. Plasma dry etching may employ a fluorinated etching gas, which includes at least one of SF6, CF4, CHF3, or NF3. The auxiliary gas may include at least one of O2, Ar, He, or N2. The process parameters of the second removal process may include at least one of RF power, bias power, cavity pressure, etching gas flow rate, etching gas ratio, stage temperature, backside cooling conditions, and etching time.

[0109] In some embodiments, step S205 may include: Multiple candidate plasma dry etching process windows are established, and the process window that meets the removal target and process constraints is selected from these windows. Each candidate process window can correspond to different etching rates, etching uniformity, post-etching residual thickness, post-etching surface roughness, post-etching surface defect density, process temperature, and bonding failure risk.

[0110] As a concrete example, the following candidate process window can be created: Candidate process window A: SF6 flow rate 100 sccm, O2 flow rate 10 sccm, cavity pressure 30 mTorr, RF power 800 W, bias power 50 W, stage temperature 20 °C, etching time 20 min.

[0111] Candidate process window B: SF6 flow rate 80 sccm, O2 flow rate 15 sccm, cavity pressure 50 mTorr, RF power 600 W, bias power 30 W, stage temperature 10 °C, etching time 30 min.

[0112] Candidate process window C: SF6 flow rate 120 sccm, Ar flow rate 30 sccm, cavity pressure 20 mTorr, RF power 1000 W, bias power 80 W, stage temperature 20 °C, etching time 15 min.

[0113] For example, based on historical process databases, test piece calibration results, etching rate models, temperature models, or online monitoring results, the predicted etching removal amount, predicted etching rate, predicted etching uniformity, predicted remaining thickness after etching, predicted surface roughness after etching, predicted surface defect density after etching, predicted process temperature, and predicted bonding failure risk for each candidate process window can be obtained.

[0114] If candidate process window C has a high etching rate but a predicted process temperature close to the thermal safety limit of the temporary bonding adhesive layer and a high predicted risk of bonding failure, then candidate process window C can be excluded. If both candidate process window A and candidate process window B meet the removal objective, but candidate process window B has better predicted etching uniformity and a lower predicted risk of bonding failure, then candidate process window B can be selected as the process parameter for the second removal treatment.

[0115] In some embodiments, a candidate plasma dry etching process window that meets the removal target and process constraints can be selected as the process parameter for the second removal process based on at least one evaluation index among predicted bond failure risk, predicted etching uniformity, predicted post-etched surface roughness, and predicted post-etched surface defect density. For example, a candidate process window with a lower predicted bond failure risk and a higher predicted etching uniformity can be preferentially selected; alternatively, a candidate process window with a lower predicted post-etched surface roughness or a lower predicted post-etched surface defect density can be selected, provided that thickness safety constraints and bond safety constraints are met.

[0116] In some embodiments, the second removal process can also be performed in stages. For example, the damage layer removal etching can be performed first according to the first etching sub-process, and then the thickness trimming etching can be performed according to the second etching sub-process. The first etching sub-process can have a higher etching rate to quickly remove the backside damage layer formed by the first removal process; the second etching sub-process can have a lower etching rate or lower bias power to improve thickness control accuracy and reduce etching-induced damage.

[0117] As a concrete example, a first etching process can be used to remove approximately 25 μm of back-side material, employing a high SF6 flow rate and high RF power. Subsequently, the remaining thickness and surface roughness in the middle of the wafer are inspected. Then, a second etching process is used to remove approximately 15 μm of back-side material, reducing the bias power and etching rate. By segmenting the etching process, the final etching thickness control accuracy can be improved while ensuring effective back-side damage removal.

[0118] S206, after the second removal process, a third removal process is performed on the side surface of the back electrode to form a contact surface for metallization of the back electrode.

[0119] In this embodiment, the third removal process is used to reduce the surface roughness and / or surface defect density after the second removal process, and to form a contact surface suitable for back electrode metallization. The third removal process may include at least one of chemical mechanical polishing, colloidal silica polishing, or low-pressure fine polishing.

[0120] As a specific example, after the second removal process, the remaining wafer thickness is approximately 60 μm. Low-pressure fine polishing of the back electrode formation side surface using colloidal silica polishing slurry can further reduce the wafer thickness to approximately 40 μm. The polishing pressure can be from 0.5 psi to 3 psi, the polishing disk speed can be from 30 rpm to 120 rpm, and the polishing slurry flow rate can be from 50 mL / min to 300 mL / min. The third removal process can remove approximately 5 μm to 20 μm of back material and reduce the Ra of the back electrode formation side surface to, for example, below 5 nm, while also reducing the amount of residual cracks, pits, and scratches.

[0121] In some embodiments, the third removal process can be performed in conjunction with endpoint detection. For example, the remaining thickness after the third removal process can be determined by online thickness detection or offline sampling. When the remaining thickness is detected to fall within a preset target remaining thickness range, such as 38 μm to 45 μm, the third removal process can be stopped. If the surface roughness or surface defect density still does not meet the target requirements after the third removal process, supplementary fine polishing or surface cleaning can be performed.

[0122] After performing the third removal process, a drain electrode and a plug electrically connected to the drain electrode are formed on the contact surface; wherein the back electrode side back surface is one of the drain side back surface, the collector side back surface, or the cathode side back surface.

[0123] And, after performing the third removal process, the substrate is removed. That is, the bond between the temporary bonding adhesive layer and the substrate is released as needed, and residual cleaning, dicing, and encapsulation processes are performed.

[0124] As can be seen from the above embodiments, the formation method of this application employs three removal processes to complete the thinning and trimming of the back electrode formation side surface. The first removal process is used to improve material removal efficiency; the second removal process includes plasma dry etching, and the removal target, process constraints, and process parameters are dynamically determined based on the state parameters after the first removal process; the third removal process is used to improve the roughness and defect state of the contact surface. Since the parameters of the second removal process are determined based on actual state parameters, rather than fixed empirical parameters, the risks of insufficient back electrode damage removal, excessive etching, uneven thickness, temporary bonding failure, and poor back electrode contact can be reduced.

[0125] It is understood that the above embodiments provide multiple implementation schemes, which can be combined and cross-referenced without conflict, thereby extending to various possible implementation schemes. For example, the first removal process can employ a combination of different mechanical thinning methods; the second removal process can employ different fluorine-containing gas systems or segmented etching strategies; the third removal process can employ different fine polishing processes; and the back electrode metal layer can adopt different metal stacking structures depending on the device type. These can all be considered as implementation schemes disclosed in the embodiments of this application.

[0126] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a power semiconductor device, characterized in that, include: A power semiconductor device is provided, the power semiconductor device having a front side and a back side electrode formed opposite to the front side; The front side of the device is bonded to the substrate using a temporary bonding adhesive layer, and the back electrode is exposed to form a side surface; A first removal process is performed on the back electrode forming side surface to thin the back electrode forming side surface to the middle remaining thickness, and the state parameters of the back electrode forming side surface after the first removal process are obtained. The removal target and process constraints of the second removal process are determined based on the state parameters, and the process parameters of the second removal process are determined based on the removal target and the process constraints. The second removal process is performed on the side surface of the back electrode according to the process parameters described above; After the second removal process, a third removal process is performed on the side surface of the back electrode to form a contact surface for metallization of the back electrode.

2. The forming method according to claim 1, characterized in that, The first removal process includes mechanical pre-thinning, the second removal process includes plasma dry etching, and the third removal process includes fine polishing. Wherein, the mechanical pre-thinning process is used to remove a first thickness of semiconductor material from the back electrode forming side surface; the plasma dry etching process is used to remove at least a portion of the back damage layer remaining after the mechanical pre-thinning process, and to trim the back electrode forming side surface to the remaining thickness after etching; the fine polishing process is used to reduce the surface roughness and / or surface defect density after the plasma dry etching process; the removal thickness of the first removal process is greater than the removal thickness of the second removal process, and the removal thickness of the second removal process is greater than the removal thickness of the third removal process.

3. The forming method according to claim 1, characterized in that, The process of obtaining the state parameters of the side surface formed by the back electrode includes: The local remaining thickness at multiple locations on the side surface where the back electrode is formed is detected within the thickness detection area, and the current minimum remaining thickness and thickness non-uniformity are determined based on the local remaining thickness at the multiple locations, wherein the thickness non-uniformity is the difference between the maximum and minimum values ​​of the local remaining thickness at the multiple locations. Detect the surface quality parameters of the side surface where the back electrode is formed within the surface detection area; At least a portion of the current minimum remaining thickness, the thickness non-uniformity, and the surface quality parameters are used as state parameters for the side surface of the back electrode formation.

4. The forming method according to claim 3, characterized in that, The step of determining the removal target of the second removal process based on the state parameters includes: determining the back damage removal allowance based on the surface quality parameters, wherein the back damage removal allowance is used to characterize the thickness of the back material that needs to be removed by the second removal process after the first removal process; and determining the removal target of the second removal process based on the back damage removal allowance, the current minimum remaining thickness, the thickness non-uniformity, the preset target remaining thickness range, and the reserved removal amount of the third removal process. Determining the process constraints of the second removal process based on the state parameters includes: determining a thickness safety constraint based on the current minimum remaining thickness, the thickness non-uniformity, the preset target remaining thickness range, and the reserved removal amount of the third removal process; determining a surface quality constraint based on the surface quality parameters and the preset target surface quality range; determining a bonding safety constraint based on at least one of the temporary bonding adhesive layer's tolerance temperature, tolerance time, peel risk threshold, and thermal stability parameters; and using at least one of the thickness safety constraint, the surface quality constraint, and the bonding safety constraint as the process constraints of the second removal process.

5. The forming method according to claim 4, characterized in that, The step of determining the back-side damage removal allowance based on the surface quality parameters includes: Before performing the second removal process, local diagnostic etching is performed in the diagnostic detection area of ​​the back electrode forming side surface to obtain local diagnostic etching results; wherein, the diagnostic detection area is located in the edge area, scribe line area or non-functional device area of ​​the back electrode forming side surface; The amount of back-side damage removed is determined based on the local diagnostic etching results; wherein, the local diagnostic etching results include at least one of the following: surface roughness after diagnostic etching, surface defect density, residual crack amount, residual pit amount, residual scratch amount, local residual thickness, and local etching rate.

6. The forming method according to claim 5, characterized in that, The process of performing local diagnostic etching in the diagnostic detection area on the side surface formed by the back electrode to obtain local diagnostic etching results includes: Multiple detection sub-regions are selected within the diagnostic detection area; The method of making the multiple detection sub-regions have different cumulative etching removal thicknesses includes: forming a masking structure on the multiple detection sub-regions, and removing the masking structure in stages, setting different opening sequences, setting different exposure times, or setting different local etching cycle numbers, so that the multiple detection sub-regions obtain different cumulative etching removal thicknesses under the same diagnostic etching conditions. After completing the local diagnostic etching, the diagnostic status parameters of the multiple detection sub-regions are detected respectively; Different cumulative etching removal thicknesses are correlated with corresponding diagnostic status parameters to obtain the local diagnostic etching results.

7. The forming method according to claim 4, characterized in that, Determining the removal target of the second removal process includes: The lower limit of removal for the second removal process is determined based on the remaining amount of damage removed from the back side. The removal upper limit of the second removal process is determined based on the current minimum remaining thickness, the thickness non-uniformity, the lower limit of the preset target remaining thickness range, the reserved removal amount of the third removal process, and the etching thickness safety margin. The etching thickness safety margin is determined based on the thickness non-uniformity or includes at least a portion of the thickness non-uniformity. When the lower limit of removal is not greater than the upper limit of removal, the thickness range between the lower limit of removal and the upper limit of removal is determined as the removal target of the second removal process; When the lower limit of removal is greater than the upper limit of removal, perform supplementary detection, adjust the reserved removal amount of the third removal process, adjust the remaining thickness range of the preset target, or stop the subsequent etching process.

8. The forming method according to claim 1, characterized in that, Determining the process parameters for the second removal treatment based on the removal target and the process constraints includes: Multiple candidate plasma dry etching process windows are established, and the candidate plasma dry etching process windows include at least one of the following: radio frequency power, bias power, cavity pressure, etching gas flow rate, etching gas ratio, stage temperature, back-side cooling conditions, and etching time. Obtain at least one of the following for each candidate plasma dry etching process window: predicted etching removal amount, predicted etching rate, predicted etching uniformity, predicted remaining thickness after etching, predicted surface roughness after etching, predicted surface defect density after etching, predicted process temperature, and predicted bonding failure risk. Determine whether each candidate plasma dry etching process window meets the removal target and the process constraints; From the candidate plasma dry etching process window that satisfies the removal target and the process constraints, the candidate plasma dry etching process window is selected as the process parameter for the second removal process based on at least one of the following evaluation indicators: predicted bonding failure risk, predicted etching uniformity, predicted post-etching surface roughness, and predicted post-etching surface defect density.

9. The forming method according to claim 2, characterized in that, Meet one or more of the following conditions: The first removal process includes at least one of diamond wheel grinding, single-sided back grinding, double-sided grinding, or mechanical polishing; The second removal process uses a fluorine-containing etching gas, which includes at least one of SF6, CF4, CHF3, or NF3; the auxiliary gas for the second removal process includes at least one of O2, Ar, He, or N2. The third removal process includes at least one of chemical mechanical polishing, colloidal silica polishing, or low-pressure fine polishing.

10. The forming method according to claim 1, characterized in that, Also includes: After performing the third removal process, a drain electrode and a plug electrically connected to the drain electrode are formed on the contact surface; wherein the back electrode side back surface is one of the drain side back surface, the collector side back surface, or the cathode side back surface. After performing the third removal process, the substrate is removed.

Images