A kind of anti single particle effect semi-super junction planar gate silicon carbide VDMOS and preparation method

Abstract

The application provides a kind of anti-single particle effect's semi-super junction planar gate silicon carbide VDMOS and preparation method, it relates to semiconductor technical field, the method includes: in silicon carbide substrate lower side face deposition metal, forms drain metal layer, epitaxial growth on silicon carbide substrate, forms drift layer;Epitaxial growth on the drift layer, form n region;Form barrier layer, etching barrier layer forms via, ion implantation, forms p region, n+ region, p+ region, p-type well region and n++ source region;Reform barrier layer, etching forms via, deposit, form gate insulating dielectric layer;Reform barrier layer, etching barrier layer forms via, deposit, form gate metal layer;Reform barrier layer, etching barrier layer forms via, deposit, form source metal layer, remove barrier layer, complete preparation;It has excellent anti-radiation performance, low conduction loss and high process compatibility, suitable for aerospace, aviation and other radiation environment under high-voltage power switch application.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semi-superjunction planar gate silicon carbide VDMOS resistant to single-event effects and its fabrication method. Background Technology

[0002] Silicon carbide (SiC), as a third-generation wide-bandgap semiconductor material, possesses excellent properties such as high critical breakdown field strength, good thermal conductivity, and high saturated electron drift velocity, making it an ideal choice for fabricating high-voltage, high-frequency, and low-loss power devices. Planar-gate silicon carbide VDMOS (Vertical Double-diffused Metal-Oxide-Semiconductor Field-Effect-Transistor) devices, due to their simple structure and relatively mature manufacturing process, have broad application prospects in the field of medium- and high-voltage power conversion.

[0003] In the design of silicon carbide VDMOS devices, there is an inherent contradiction between on-resistance and breakdown voltage. Traditional VDMOS devices rely on a lightly doped n-type drift region to withstand reverse voltage, but this inevitably leads to increased on-resistance. To overcome this limitation, a superjunction structure has been introduced into silicon carbide VDMOS devices. The superjunction structure introduces p-pillar regions alternating with the n-type drift region, causing mutual depletion between the p-pillar and n-type regions during reverse blocking. This significantly increases the doping concentration of the n-type region without reducing the breakdown voltage, effectively reducing the on-resistance. However, the superjunction structure presents a serious reliability vulnerability to single-event effects—when heavy ions or other radiating particles are incident on the device, the p-pillar regions form a through-path from the gate structure to the n+ substrate, leading to single-event burn-out or single-event gate penetration failure modes, severely impacting the reliability of the device in radiation environments such as aerospace.

[0004] Currently, hardening measures for single-event effects in silicon carbide VDMOS devices mainly focus on process optimization, such as reducing the gate oxide thickness and optimizing the channel doping distribution. While these methods can improve the device's radiation resistance to some extent, they often come at the cost of sacrificing electrical performance and lack effective means to suppress the p-pillar punch-through problem unique to superjunction structures. Therefore, how to effectively improve the device's resistance to single-event effects while maintaining the low on-resistance advantage of superjunction structures is a pressing technical challenge in this field. Summary of the Invention

[0005] The technical problem to be solved by this invention is to provide a semi-superjunction planar gate silicon carbide VDMOS and its fabrication method that resists single-event effects. By setting a low-doped drift layer at the bottom of the p-region of the semi-superjunction structure as a buffer region, the device effectively suppresses the p-region's penetration into the substrate during single-event radiation, avoiding damage to the n+ substrate and significantly improving the device's single-event reliability. At the same time, the synergistic effect of the gradient doping structure and the semi-superjunction structure effectively reduces the device's on-resistance while ensuring high voltage withstand capability. In addition, the p+ region is set around the outside of the cell and simultaneously contacts the p-region and n+ region, which can suppress the mutual influence between cells and enhance the freewheeling capability of the parasitic diode. This invention has excellent radiation resistance, low conduction loss and high process compatibility, and is suitable for high-voltage power switching applications in radiation environments such as aerospace and aviation.

[0006] In a first aspect, the present invention provides a semi-superjunction planar gate silicon carbide VDMOS resistant to single-event effects and a method for its fabrication, comprising the following steps: Step 1: Deposit metal on the lower side of a silicon carbide substrate to form a drain metal layer, and epitaxially grow a drift layer on the silicon carbide substrate. Step 2: Epitaxial growth is performed on the drift layer to form the n-region; Step 3: Form a barrier layer above the n-region, etch the barrier layer to form a via, and implant ions to form the p-region; Step 4: Remove the barrier layer from Step 3, reform the barrier layer, etch the barrier layer to form vias, and implant ions to form n+ regions; Step 5: Remove the barrier layer from Step 4, reform the barrier layer, etch the barrier layer to form vias, and implant ions to form p+ regions; Step 6: Remove the barrier layer from Step 5, reform the barrier layer, etch the barrier layer to form vias, and implant ions to form a p-type well region; Step 7: Remove the barrier layer from Step 6, reform the barrier layer, etch the barrier layer to form vias, and implant ions to form the n++ source region; Step 8: Remove the barrier layer from Step 7, reform the barrier layer, etch the barrier layer to form vias, and deposit to form the gate insulating dielectric layer; Step 9: Remove the barrier layer from Step 8, reform the barrier layer, etch the barrier layer to form vias, and deposit to form the gate metal layer; Step 10: Remove the barrier layer from step 9, reform the barrier layer, etch the barrier layer to form vias, deposit the source metal layer, remove the barrier layer, and complete the fabrication.

[0007] Furthermore, the doping concentration of the drift layer is less than the doping concentration of the n-region, and the doping concentration of the n-region is less than the doping concentration of the n+ region.

[0008] Furthermore, the width of the p+ region is greater than the width of the p region.

[0009] Furthermore, the width of the n-th region is equal to the width of the n+th region.

[0010] Furthermore, the doping concentration of the p-region is greater than the doping concentration of the drift layer; and the doping concentration of the p-region is greater than the doping concentration of the n-region.

[0011] Secondly, the present invention provides a semi-superjunction planar gate silicon carbide VDMOS resistant to single-event effects, wherein the silicon carbide VDMOS is prepared by the preparation method of the semi-superjunction planar gate silicon carbide VDMOS resistant to single-event effects described in the first aspect.

[0012] The advantages of this invention are: 1. This invention provides a low-doped drift layer beneath the p-region of a superjunction structure, wherein the p-region does not extend to the bottom of the drift layer, forming a semi-superjunction structure. When radiation particles such as heavy ions are incident on the device, the single-event effect has the most severe impact on the p-region. The low-doped drift layer at the bottom of the p-region can effectively buffer the excessive charge generated by single-event injection, suppress the punch-through effect from the p-region to the silicon carbide substrate, and avoid irreversible damage to the silicon carbide substrate. This significantly improves the device's single-event burn-out and single-event gate penetration tolerance under space radiation environment, and significantly improves the device's single-event reliability.

[0013] 2. This invention employs a gradient doping structure where the n-type doping concentration gradually increases longitudinally from the drift layer to the n-region and then to the n+ region. The drift layer uses a lower doping concentration to ensure that the device can withstand high voltages without premature breakdown during reverse blocking. The n-region has a higher doping concentration and forms a superjunction structure with the p-region, utilizing the lateral charge compensation effect of the superjunction to further improve the breakdown voltage and reduce the on-resistance in this region. The n+ region has an even higher doping concentration, further reducing the resistive component in the current path. Through the synergistic optimization of the gradient doping and semi-superjunction structure, this invention can effectively reduce the on-resistance of the device within a breakdown voltage range of 1KV to 3KV, achieving a better trade-off between breakdown voltage and on-resistance.

[0014] 3. Compared to the full superjunction structure where the p-region extends through the entire drift layer, the p-region of this invention does not extend to the bottom of the drift layer, retaining the low-doped drift layer as a buffer region. This semi-superjunction structure retains the core advantages of the superjunction structure, such as increasing the doping concentration of the n-region and reducing the on-resistance, while avoiding the single-particle punch-through risk caused by the p-pillars directly penetrating the substrate in the full superjunction structure. It also reduces the need for complex processes such as deep trench etching or high-energy multiple ion implantations, lowering manufacturing difficulty and cost, and possessing good process compatibility and feasibility.

[0015] 4. In this invention, the p+ region is located on the outside of the device cell, forming an enclosing structure for the p-type well region and the n++ source region. This layout can effectively suppress electrical crosstalk between adjacent cells, avoid latch-up or false triggering during switching transients or under irradiation, and improve the operational stability and consistency of the device array. Simultaneously, the p+ region is in direct contact with both the p-region and the n+ region, increasing the effective pn junction area of ​​the parasitic body diode, improving the injection efficiency and freewheeling capability of the body diode, and enabling the device to operate safely and reliably under harsh conditions such as inductive load switching.

[0016] 5. This invention achieves a reduction in cell size while maintaining low on-resistance and low gate charge by meticulously designing and matching the dimensions and doping concentration of key regions in the device cell (including the width of the JFET region, the width and thickness of the p-type well region, the distribution position of the n+ source region, and the overlap between the gate metal and the n+ source region). This effectively reduces the conduction loss and switching loss of the device, improves the power density and switching speed of the device, and is suitable for high-frequency, high-voltage, and high-power-density power conversion applications. Attached Figure Description

[0017] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0018] Figure 1 This is a cross-sectional view of a semi-superjunction planar gate silicon carbide VDMOS that resists single-event effects according to the present invention.

[0019] Figure 2 This is a cross-sectional view of the process of a semi-superjunction planar gate silicon carbide VDMOS resistant to single-event effects according to the present invention. Figure 1 .

[0020] Figure 3 This is a cross-sectional view of the process of a semi-superjunction planar gate silicon carbide VDMOS resistant to single-event effects according to the present invention. Figure 2 .

[0021] Figure 4 This is a cross-sectional view of the process of a semi-superjunction planar gate silicon carbide VDMOS resistant to single-event effects according to the present invention. Figure 3 .

[0022] Figure 5 This is a cross-sectional view of the process of a semi-superjunction planar gate silicon carbide VDMOS resistant to single-event effects according to the present invention. Figure 4 .

[0023] Figure 6 This is a cross-sectional view of the process of a semi-superjunction planar gate silicon carbide VDMOS resistant to single-event effects according to the present invention. Figure 5 .

[0024] Figure 7This is a cross-sectional view of the process of a semi-superjunction planar gate silicon carbide VDMOS resistant to single-event effects according to the present invention. Figure 6 .

[0025] Figure 8 This is a cross-sectional view of the process of a semi-superjunction planar gate silicon carbide VDMOS resistant to single-event effects according to the present invention. Figure 7 .

[0026] Figure 9 This is a cross-sectional view of the process of a semi-superjunction planar gate silicon carbide VDMOS resistant to single-event effects according to the present invention. Figure 8 .

[0027] Figure 10 This is a cross-sectional view of the process of a semi-superjunction planar gate silicon carbide VDMOS resistant to single-event effects according to the present invention. Figure 9 .

[0028] Figure 11 This is a cross-sectional view of the process of a semi-superjunction planar gate silicon carbide VDMOS resistant to single-event effects according to the present invention. Figure 10 . Detailed Implementation

[0029] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0031] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "in contact with," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.

[0032] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figures and other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as “below,” “under,” or “below” other elements or features would be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein are interpreted accordingly.

[0033] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0034] like Figures 1 to 11 As shown, this application provides a method for fabricating a semi-superjunction planar gate silicon carbide VDMOS resistant to single-event effects, comprising the following steps: Step 1: Deposit metal on the lower side of silicon carbide substrate 1 to form drain metal layer 7, and epitaxially grow drift layer 2 on silicon carbide substrate 1. Step 2: Epitaxial growth is performed on the drift layer 2 to form the n-region 3; Step 3: Form a barrier layer a above the n region 3, etch the barrier layer a to form a via, and implant ions to form the p region 31; Step 4: Remove the barrier layer a from step 3, reform the barrier layer a, etch the barrier layer a to form a via, and implant ions to form the n+ region 32. Step 5: Remove the barrier layer a from step 4, reform the barrier layer a, etch the barrier layer a to form a via, and implant ions to form the p+ region 35. Step 6: Remove the barrier layer a from step 5, reform the barrier layer a, etch the barrier layer a to form a via, and implant ions to form a p-type well region 33; Step 7: Remove the barrier layer a from step 6, reform the barrier layer a, etch the barrier layer a to form a via, and implant ions to form the n++ source region 34. Step 8: Remove the barrier layer a from step 7, reform the barrier layer a, etch the barrier layer a to form a via, and deposit to form the gate insulating dielectric layer 4. Step 9: Remove the barrier layer a from step 8, reform the barrier layer a, etch the barrier layer a to form a via, and deposit to form the gate metal layer 5. Step 10: Remove the barrier layer a from step 9, reform the barrier layer a, etch the barrier layer a to form a via, deposit and form the source metal layer 6, remove the barrier layer a, and complete the fabrication.

[0035] In this embodiment, preferably, the doping concentration of the drift layer 2 is less than the doping concentration of the n-region 3, and the doping concentration of the n-region 3 is less than the doping concentration of the n+ region 32.

[0036] In this embodiment, preferably, the width of the p+ region 35 is greater than the width of the p region 31.

[0037] In this embodiment, preferably, the width of the n-region 3 is equal to the width of the n+region 32.

[0038] In this embodiment, preferably, the doping concentration of the p-region 31 is greater than the doping concentration of the drift layer 2; and the doping concentration of the p-region 31 is greater than the doping concentration of the n-region 3.

[0039] like Figure 1 As shown, the silicon carbide VDMOS obtained by the above manufacturing method includes: Silicon carbide substrate 1; Drift layer 2, the lower side of which is connected to the upper side of the silicon carbide substrate 1; n-region 3, the lower side of which is connected to the upper side of the drift layer 2; n-region 3 is provided with p-region 31, n+ region 32, p-type well region 33, n++ source region 34 and p+ region 35, the lower side of p-region 31 is connected to the upper side of the drift layer 2; the inner side of p-region 31 is connected to n+ region 32; the lower side of p+ region 35 is connected to p-region 31 and n+ region 32 respectively; the lower side of p-type well region 33 is connected to n+ region 32, the inner side of p+ region 35 is connected to the outer side of p-type well region 33 and the outer side of n++ source region 34 respectively, the inner side of p-type well region 33 is connected to n+ region 32; n+ region 32 is convex, the lower side and inner side of n++ source region 34 are both connected to p-type well region 33. Gate insulating dielectric layer 4, the lower side of which is connected to the n++ source region 34, the p-type well region 33 and the n+ region 32 respectively; Gate metal layer 5, the lower side of which is connected to the upper side of gate insulating dielectric layer 4; Source metal layer 6, which is connected to the p+ region 35 and the n++ source region 34 respectively; And, drain metal layer 7, the lower side of the silicon carbide substrate 1 is connected to the upper side of the drain metal layer 7.

[0040] In another embodiment of the present invention, the silicon carbide substrate 1 is n-type, and the drift layer 2 is n-type; the doping concentration of the n+ silicon carbide substrate 1 is 5-10e18cm. -3 The doping concentration of the n-type drift layer 2 is 5-10e16cm. -3 The doping concentration of p-region 31 is 6-10e17cm. -3 The doping concentration of n-region 3 is 1-5e17cm. -3 The doping concentration of n+ region 32 is 6-10e17cm. -3 The doping concentration of p+ region 35 is 6-10e18cm. -3 The doping concentration of the p-type well region 33 is 6-10e17cm. -3 The doping concentration of the n++ source region 34 is 5-10e18cm. -3 The gate insulating dielectric layer 4 is a high-k dielectric such as silicon dioxide or hafnium dioxide, and the gate metal layer 5 and the source metal layer 6 are one or more alloys of copper, nickel and aluminum. The doping concentration of the silicon carbide substrate 1 is to ensure that a low-resistance ohmic contact is formed with the drain metal layer 7, thereby reducing the overall on-resistance of the device. There are two aspects to consider regarding the doping concentration of the n-type drift layer 2. First, since there is no lateral breakdown structure in this region, the doping concentration should be lower to avoid large electric field breakdown in this region. Second, the doping concentration should be increased as much as possible under limited conditions to reduce the on-resistance of the device. The doping structure of n-region 3 and p-region 31 is a superjunction structure. There is a lateral breakdown voltage structure in this region, so the doping concentration of n-region can be effectively increased. The doping concentration of p-region 31 should be matched with that of n-region 3 to maximize the efficiency of the superjunction structure. Since the superjunction structure does not extend from the gate structure to the silicon carbide substrate 1 region of the device, this structure is called a semi-superjunction structure. The doping concentration of region 32 in the n+ region is higher than that in region 3. This is to ensure the width of the JFET region without affecting the switching characteristics of the device, thereby ensuring that the on-resistance of the device does not increase while reducing the device size. The doping concentration of region 33 in the p-type well region is to comprehensively ensure the low gate charge of the device, reduce the switching loss of the device, improve the switching speed of the device and reduce the leakage current. A higher doping concentration of region 33 in the p-type well region results in a lower leakage current but a higher gate charge, and vice versa. The doping concentration of the p+ region 35 serves two purposes: first, to form a parasitic pn junction body diode in the device, which has a greater current carrying capacity and can ensure the freewheeling capability of the device body diode; second, to form a lateral pn junction breakdown structure near the top of the gate, thereby avoiding the electric field concentration at the gate structure. The n++ source region 34 is to reduce the source resistance of the device. The thickness of the n-type silicon carbide substrate 1 is 1 μm, which is to ensure support during the device fabrication process. The thickness of the n-type drift layer 2 is 10-30 μm, because this structure can be applied to different withstand voltage ranges of 1KV-3KV. The withstand voltage range is mainly affected by the thickness of the n-type drift layer 2 and the structural thickness of the n-type region 3 and the p-type region 31. The width of the p+ region 35 of the device cell is 1.7 μm and the thickness is 1 μm. This width and the doping concentration are matched to ensure the contact area between the p+ region 35 and the source metal layer 6 and the n+ region 32, thereby realizing the large current freewheeling of the parasitic diode of the device. Its thickness is to ensure the lateral diffusion of the space charge region during reverse breakdown, thereby improving the breakdown voltage of the device and ensuring the gate reliability of the device. The p+ region 35 is in direct contact with the n++ source region 34 and the p-type well region 33. The p-type well region 33 has a width of 1.3 μm and a thickness of 1 μm. This is to ensure the switching and breakdown voltage characteristics of the device while reducing the width of the JFET region (including the n-region). The thickness and width affect the breakdown voltage and off-state current. Sufficient thickness and width are necessary to ensure the off-state characteristics of the device. Too thick and too wide will affect the on-state characteristics of the device. The width of the source metal layer 6 in the device cell is 2.5 μm and the thickness is 500 nm. This is to ensure the contact area between the source metal layer 6 and the p+ region 35 and the n++ source region 34, and to reduce the source contact resistance. The n++ source region 34 of the device cell has a width of 1μm and a thickness of 500nm. It is distributed on the side of the p-type well region 33 away from the gate. The side of the n++ source region 34 away from the gate is in direct contact with the p+ region 35. The farthest distance from the p-type well region 33 on the side close to the gate is 300nm. This is to ensure low ohmic contact resistance with the source metal layer 6 and to ensure current capability. The maximum width of the n+ region 32 of the device is 5μm, the maximum thickness is 2μm, and the minimum width is 1μm. The minimum width is the minimum distance in the middle of the p-type well region 33. This distance is to achieve low on-resistance while ensuring the small size of the device cell. The maximum width is across the p-region 31, which can ensure the body diode characteristics of the device. The width of the device cell gate insulating dielectric layer 4 is 2μm. The width is to ensure that the conductive channel of the device is distributed directly below the gate metal layer 5. The thickness is 50nm. This is determined by the characteristics of silicon carbide material and is a comprehensive consideration of the device's gate control capability and gate reliability. The thickness of the gate metal layer 5 in the device cell is 500nm and the width is 1.8μm. The width of the overlap of the gate metal layer 5 with the n++ source region 34 on the edge side is 100nm. This overlap can avoid the gate metal layer 5 not being distributed directly above the p-type well region 33 due to process errors, thus ensuring the gate control capability of the device and ensuring the low resistance of the conductive channel. The n-type drift layer 2 has a thickness of 5 μm. This is to ensure that the device can suppress the continued movement of the p-region 31 to the silicon carbide substrate 1 after a single particle incident. If it is too thick, it will affect the on-resistance characteristics of the device; if it is too thin, it will affect the suppression effect on single particles. The width of p-region 31 is 1 μm, and its thickness is adjusted according to the change in the voltage withstand range of the device; The width of region n3 of the device is the same as the maximum width of region n+32, which is 2μm. This is a comprehensive consideration of the superjunction structure achieved by the intersection with the structure of region p31 of the device and the doping concentration.

[0041] The device adopts a structure with progressively increasing n-type doping in the n-type drift layer 2, n-region 3, and n+ region 32, which can minimize the on-resistance of the device while ensuring the device's withstand voltage. The n-type drift layer 2 and n-region 3 of the device are formed by two epitaxial layers. A p-region 31 is prepared in the n-region 3 to form a superjunction structure. Since the p-region 31 does not extend to the n-type drift layer 2, the structure is a semi-superjunction structure. Under single-event effect conditions, the single-event effect is most severe in the p region 31. The low-doped n-type drift layer 2 at its bottom can buffer the single-event effect, thereby avoiding direct damage to the silicon carbide substrate 1 and improving the single-event reliability of the device. The p+ region 35 of the device surrounds the p-type well region 33 and the n++ source region 34 outside the device cell, which can effectively suppress the mutual influence between the cells. The p+ region 35 of the device is in contact with both the p+ region 31 and the n+ region 32, which can improve the freewheeling capability of the parasitic diode.

[0042] While specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and not intended to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A method for fabricating a semi-superjunction planar gate silicon carbide VDMOS resistant to single-event effects, characterized in that: Includes the following steps: Step 1: Deposit metal on the lower side of a silicon carbide substrate to form a drain metal layer, and epitaxially grow a drift layer on the silicon carbide substrate. Step 2: Epitaxial growth is performed on the drift layer to form the n-region; Step 3: Form a barrier layer above the n-region, etch the barrier layer to form a via, and implant ions to form the p-region; Step 4: Remove the barrier layer from Step 3, reform the barrier layer, etch the barrier layer to form vias, and implant ions to form n+ regions; Step 5: Remove the barrier layer from Step 4, reform the barrier layer, etch the barrier layer to form vias, and implant ions to form p+ regions; Step 6: Remove the barrier layer from Step 5, reform the barrier layer, etch the barrier layer to form vias, and implant ions to form a p-type well region; Step 7: Remove the barrier layer from Step 6, reform the barrier layer, etch the barrier layer to form vias, and implant ions to form the n++ source region; Step 8: Remove the barrier layer from Step 7, reform the barrier layer, etch the barrier layer to form vias, and deposit to form the gate insulating dielectric layer; Step 9: Remove the barrier layer from Step 8, reform the barrier layer, etch the barrier layer to form vias, and deposit to form the gate metal layer; Step 10: Remove the barrier layer from step 9, reform the barrier layer, etch the barrier layer to form vias, deposit the source metal layer, remove the barrier layer, and complete the fabrication.

2. The method for fabricating a semi-superjunction planar gate silicon carbide VDMOS resistant to single-event effects as described in claim 1, characterized in that: The doping concentration of the drift layer is less than the doping concentration of the n region, and the doping concentration of the n region is less than the doping concentration of the n+ region.

3. The method for fabricating a semi-superjunction planar gate silicon carbide VDMOS resistant to single-event effects as described in claim 1, characterized in that: The width of the p+ region is greater than the width of the p region.

4. The method for fabricating a semi-superjunction planar gate silicon carbide VDMOS resistant to single-event effects as described in claim 1, characterized in that: The width of region n is equal to the width of region n+.

5. The method for fabricating a semi-superjunction planar gate silicon carbide VDMOS resistant to single-event effects as described in claim 1, characterized in that: The doping concentration in the p-region is greater than the doping concentration in the drift layer; and the doping concentration in the p-region is greater than the doping concentration in the n-region.

6. A semi-superjunction planar gate silicon carbide VDMOS resistant to single-event effects, characterized in that, The silicon carbide VDMOS is prepared by the preparation method described in any one of claims 1 to 5.

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