Fin FET device and method of manufacturing the same

Abstract

The application discloses a Fin FET device and a manufacturing method thereof. The Fin FET device comprises a semiconductor substrate, a fin structure on the semiconductor substrate, the fin structure comprising a first part and a second part below the first part, an STI structure between adjacent second parts, a gate stack structure across the first part, in contact with the sidewall and the top of the first part respectively, and a source region and a drain region on the first part and on both sides of the gate stack structure. The gate stack structure comprises a gate dielectric and a gate conductor, the gate dielectric comprising a first gate dielectric with a first thickness and a second gate dielectric with a second thickness, the second gate dielectric covering the top surface of the first part and the upper sidewall of the first part, the first gate dielectric covering the lower sidewall of the first part, and the second thickness being greater than the first thickness.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a FinFET device and its manufacturing method. Background Technology

[0002] FinFET (Fin Field-Effect Transistor) is a novel complementary metal-oxide-semiconductor (CMOS) transistor developed to address the short-channel effects encountered by traditional planar transistors at the nanoscale. FinFET is a three-dimensional transistor structure whose design allows for maintaining transistor performance and switching characteristics in a smaller size.

[0003] The basic structure of a FinFET consists of a vertical silicon fin, resembling a fin, surrounded by a gate on both sides and top. This fin forms the channel of the transistor, with the source and drain located on either side of the fin. Compared to traditional planar transistors, FinFETs significantly enhance channel control, effectively suppressing short-channel effects, especially as process nodes shrink to below 22nm. The core advantages of FinFETs are primarily low power consumption, manifested in excellent electrostatic control, reduced leakage current, and significantly lower standby power consumption; high performance, characterized by higher drive current and switching speed, suitable for high-frequency applications; and miniaturization, supporting smaller process nodes (such as 7nm and 5nm), thus continuing Moore's Law.

[0004] While FinFETs, as an advanced transistor structure, offer significant advantages in performance and power consumption, their three-dimensional structure and miniaturization process also introduce specific risks of leakage and breakdown. Because the fin-shaped structure of a FinFET is surrounded by the gate conductor on three sides, the electric field strength is high on the top surface of the fin, the sidewalls adjacent to the top surface, and the apex between the top surface and the sidewalls. This concentrated electric field in these areas accelerates the degradation of the gate oxide layer, leading to time-dependent dielectric breakdown (TDDB). As process nodes shrink, the gate oxide layer becomes thinner, making manufacturing defects (such as interface states and pinholes) more likely to occur, resulting in increased leakage current or even direct breakdown. Summary of the Invention

[0005] In view of the above problems, the purpose of this application is to provide a Fin FET device and a method for manufacturing the same, which optimizes the overall electric field distribution of the device, reduces leakage current, and improves the breakdown electric field by setting the thickness of the second gate dielectric in the upper part of the channel region to a larger value, thereby improving the performance of the device.

[0006] According to one aspect of the present invention, a Fin FET device is provided, comprising: a semiconductor substrate; a fin structure located on the semiconductor substrate, the fin structure including a first portion and a second portion located below the first portion; an STI structure located on the semiconductor substrate and between adjacent second portions; a gate stack structure spanning the first portion and contacting the sidewalls and top of the first portion respectively; and a source region and a drain region located on the first portion and on both sides of the gate stack structure; wherein the gate stack structure includes a gate dielectric and a gate conductor, the gate dielectric including a first gate dielectric having a first thickness and a second gate dielectric having a second thickness, the second gate dielectric covering the top surface of the first portion and the upper sidewall of the first portion; the first gate dielectric covering the lower sidewall of the first portion, and the second thickness being greater than the first thickness.

[0007] Optionally, the gate dielectric further includes a transition gate dielectric with a third thickness, the transition gate dielectric being located between the first gate dielectric and the second gate dielectric, the third thickness being greater than the first thickness and less than the second thickness.

[0008] Optionally, the end of the transition gate dielectric closer to the second gate dielectric has a greater thickness than the end closer to the first gate dielectric.

[0009] According to another aspect of the present invention, a method for manufacturing a Fin FET device is provided, comprising: forming a fin structure in a semiconductor substrate, the fin structure including a first portion and a second portion located below the first portion; forming an STI structure between the second portions; forming a gate stack structure spanning the first portion and contacting the sidewalls and top of the first portion respectively; forming a source region and a drain region located in the first portion and on both sides of the gate stack structure; wherein the gate stack structure includes a gate dielectric and a gate conductor, the gate dielectric including a first gate dielectric having a first thickness and a second gate dielectric having a second thickness, the second gate dielectric covering the top surface of the first portion and the upper sidewall of the first portion; the first gate dielectric covering the lower sidewall of the first portion, and the second thickness being greater than the first thickness.

[0010] Optionally, a porous structure is formed on the upper part of the first portion while forming the STI structure; the method of forming the gate stack structure includes: forming a dielectric layer, wherein the upper part of the porous first portion has a greater adsorption capacity for the precursor compared to the lower part of the first portion, and the thickness of the dielectric layer formed on the upper part of the first portion is greater than the thickness of the dielectric layer formed on the lower part of the first portion; forming a structural layer; etching the structural layer and the dielectric layer to form a gate conductor and a gate dielectric.

[0011] Optionally, the method of forming a porous structure on the upper part of the first portion while forming the STI structure includes: forming a first hard mask layer on top of the fin structure; forming an isolation dielectric layer that fills the gaps between the fin structures and whose top is flush with the top of the first hard mask layer; etching back the isolation dielectric layer to expose the upper part of the first portion; electrochemically etching the exposed upper part of the first portion to form a porous structure on the upper part of the first portion; and continuing to etch back the isolation dielectric layer to form the STI structure.

[0012] Optionally, the gate dielectric further includes a transition gate dielectric with a third thickness, the transition gate dielectric being located between the first gate dielectric and the second gate dielectric, the third thickness being greater than the first thickness and less than the second thickness.

[0013] Optionally, the method of forming the transition gate dielectric includes: forming a first dielectric layer and a first structural layer, the first dielectric layer covering the surface of the STI structure and the lower sidewall of the first portion, the first structural layer covering the surface of the first dielectric layer, and the top of the first structural layer being flush with the top of the first dielectric layer covering the lower sidewall of the first portion, the first dielectric layer having a first thickness; forming a second dielectric layer and a second structural layer, the second dielectric layer covering the upper sidewall of the first portion and the top surface of the first portion, the second structural layer covering the surface of the second dielectric layer, and having a lateral cut exposing the second dielectric layer between the bottom of the second dielectric layer and the top of the first structural layer, the second dielectric layer having a second thickness greater than the first thickness; laterally etching the second dielectric layer on the exposed sidewall of the first portion through the lateral cut to reduce the thickness of the second dielectric layer, forming a transition dielectric layer, the thickness of the transition dielectric layer being greater than the first thickness and less than the second thickness; etching the first dielectric layer, the second dielectric layer, and the transition dielectric layer to form the first gate dielectric, the second gate dielectric, and the transition gate dielectric, respectively.

[0014] Optionally, the method of forming the first dielectric layer and the first structural layer includes: forming a first dielectric layer that conformally covers the surface of the STI structure, the top of the first portion, and the sidewalls of the first portion; forming a first structural layer that fills the space between the first portions and extends above the first portions; etching back the first structural layer to expose the first dielectric layer covering the top of the first portion and the first dielectric layer covering the upper sidewalls of the first portion; and removing the exposed first dielectric layer using the first structural layer as a mask to expose the upper sidewalls of the first portion and the top surface of the first portion.

[0015] Optionally, the method of forming the second dielectric layer and the second structural layer includes: forming a second dielectric layer that covers the surface of the first structural layer, the top of the exposed first portion, and the sidewalls of the exposed first portion; forming a second structural layer that conformally covers the surface of the second dielectric layer; selectively removing the second structural layer while retaining the second structural layer on the top of the first portion and the sidewalls of the first portion; and removing the exposed second dielectric layer using the second structural layer as a mask and the first structural layer as an etch stop layer.

[0016] The unexpected technical effect of this application is:

[0017] In this embodiment, the thickness of the second gate dielectric in the upper part of the channel region is set to be relatively large, which optimizes the overall electric field distribution of the device, reduces leakage current, and increases the breakdown electric field, thereby improving the performance of the device.

[0018] In a preferred embodiment, a transition gate dielectric is formed between the first gate dielectric and the second gate dielectric, thereby avoiding abrupt changes in the electric field distribution caused by the abrupt change in thickness between the first gate dielectric and the second gate dielectric.

[0019] In a preferred embodiment, the end of the transition gate dielectric 1093 closest to the second gate dielectric 1092 has a larger thickness than the end closest to the first gate dielectric 1091, which further reduces the thickness gradient between the first gate dielectric and the transition gate dielectric, as well as the thickness gradient between the transition gate dielectric and the second gate dielectric.

[0020] In a preferred embodiment, by forming a porous structure on the upper part of the first part of the fin-shaped structure, the upper part of the porous first part has a greater adsorption capacity for precursors than the lower part of the first part during the subsequent formation of the dielectric layer. This results in more precursors reacting to form an oxide layer on the upper part of the first part. Therefore, the thickness of the dielectric layer formed on the upper part of the first part is greater than the thickness of the dielectric layer in other parts.

[0021] In a preferred embodiment, the thickness of the second dielectric layer is reduced by forming a lateral cut that exposes one end of the second dielectric layer near the first dielectric layer, and by etching the exposed second dielectric layer through the lateral cut, thereby forming a transition dielectric layer with a third thickness. Attached Figure Description

[0022] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0023] Figure 1a A schematic diagram of a conventional FinFET device is shown;

[0024] Figure 1b It shows Figure 1a Cross-sectional view along the AA direction;

[0025] Figure 2 It shows Figure 1a and Figure 1b The diagram shows a current simulation of the FinFET device.

[0026] Figure 3 A cross-sectional schematic diagram of an exemplary Fin FET device provided in an embodiment of this application is shown;

[0027] Figures 4a to 4m This is a schematic diagram illustrating the steps of an exemplary FinFET device manufacturing method provided in this application embodiment, wherein:

[0028] Figure 4a This illustration shows a schematic diagram of a first hard mask layer formed on a semiconductor substrate according to an embodiment of this application;

[0029] Figure 4b This diagram illustrates an embodiment of the present application in which an auxiliary structure is formed on a first hard mask layer.

[0030] Figure 4c A schematic diagram of the formation of the second hard mask layer according to an embodiment of this application is shown;

[0031] Figure 4d A schematic diagram of the sidewall formation according to an embodiment of this application is shown;

[0032] Figure 4e A schematic diagram of the removal of auxiliary structures according to an embodiment of this application is shown;

[0033] Figure 4f This illustration shows a schematic diagram of a fin-shaped structure formed in a semiconductor substrate according to an embodiment of this application;

[0034] Figure 4g This illustration shows a schematic diagram of the formation of an isolation medium layer according to an embodiment of this application;

[0035] Figure 4h This illustration shows a schematic diagram of an embodiment of the present application where the isolation dielectric layer is etched back to expose the upper part of the first portion;

[0036] Figure 4i A schematic diagram of a porous structure formed in the upper part of the first portion according to an embodiment of this application is shown;

[0037] Figure 4j A schematic diagram of the STI structure formed according to an embodiment of this application is shown;

[0038] Figure 4kA schematic diagram of the dielectric layer formed according to an embodiment of this application is shown;

[0039] Figure 4l A schematic diagram of the structural layer formed according to an embodiment of this application is shown;

[0040] Figure 4m A schematic diagram illustrating the formation of the gate conductor and gate dielectric according to an embodiment of this application is shown;

[0041] Figure 5 A cross-sectional schematic diagram of another exemplary Fin FET device provided in an embodiment of this application is shown;

[0042] Figures 6a to 6l yes Figure 5 A schematic diagram illustrating the steps of the manufacturing process of a FinFET device;

[0043] Figure 6a This illustration shows a schematic diagram of the formation of an isolation medium layer according to an embodiment of this application;

[0044] Figure 6b A schematic diagram of the STI structure formed according to an embodiment of this application is shown;

[0045] Figure 6c This illustration shows a schematic diagram of the formation of the first dielectric layer according to an embodiment of this application;

[0046] Figure 6d This illustration shows a schematic diagram of the formation of the first structural layer according to an embodiment of this application;

[0047] Figure 6e This illustration shows a schematic diagram of the etching back of the first structural layer according to an embodiment of this application;

[0048] Figure 6f This illustration shows a schematic diagram of the first dielectric layer etched and exposed according to an embodiment of the present application to expose the upper sidewall of the first portion and the top surface of the first portion;

[0049] Figure 6g This illustration shows a schematic diagram of the formation of the second dielectric layer according to an embodiment of this application;

[0050] Figure 6h This illustration shows a schematic diagram of the formation of the second structural layer according to an embodiment of this application;

[0051] Figure 6i This illustration shows a schematic diagram of the selective removal of the second structural layer according to an embodiment of this application;

[0052] Figure 6j This illustration shows a schematic diagram of an embodiment of the present application where the second structural layer is used as a mask and the first structural layer is used as an etch stop layer to remove the exposed second dielectric layer;

[0053] Figure 6kThis illustration shows a schematic diagram of the formation of the third structural layer according to an embodiment of this application;

[0054] Figure 6l A schematic diagram illustrating the formation of the gate conductor and gate dielectric according to an embodiment of this application is shown;

[0055] Explanation of reference numerals in the attached figures: 101-Semiconductor substrate; 101a-Fin structure; 101a-1-First part; 101a-2-Second part; 102-First hard mask layer; 103-Auxiliary structure; 104-Second hard mask layer; 104a-Sidewall; 105-Isolation dielectric layer; 105a-STI structure; 107-Well region; 109-Gate dielectric; 1091-First gate dielectric; 1092-Second gate dielectric; 1093-Transition gate dielectric; 109a-Dielectric layer; 1091a-First dielectric layer; 1092a-Second dielectric layer; 110-Gate conductor; 110a-Structural layer; 1101-First structural layer; 1102-Second structural layer; 111-Source region; 112-Drain region; 113-Channel region; uc-Lateral notch. Detailed Implementation

[0056] The present application will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown.

[0057] When describing the structure of a device, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above another layer or region, or that it contains other layers or regions between it and another layer or region. Furthermore, if the device is flipped, the layer or region will be located "below" or "under" another layer or region.

[0058] To describe a situation where it is located directly on another layer or another area, this article will use the expressions "directly on top of" or "on and adjacent to".

[0059] Unless otherwise specified below, the various parts of a semiconductor device may be made of materials well known to those skilled in the art. Semiconductor materials include, for example, group III-V semiconductors such as gallium arsenide (GaAs) and gallium nitride (GaN), group IV-IV semiconductors such as silicon carbide (SiC), group II-VI compound semiconductors such as cadmium sulfide (CdS) and cadmium telluride (CdTe), and group IV semiconductors such as silicon (Si) and germanium (Ge). The gate conductor may be formed of various conductive materials, such as a metal layer, a doped polysilicon layer, or a stacked gate conductor comprising a metal layer and a doped polysilicon layer, or other conductive materials such as TaC, TiN, TaSiN, HfSiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, and PtSi. x The gate dielectric can be composed of Ni3Si, Pt, Ru, W, and combinations of various conductive materials. The gate dielectric can be made of SiO2 or materials with a dielectric constant greater than SiO2, such as oxides, nitrides, oxynitrides, silicates, aluminates, and titanates. Furthermore, the gate dielectric can be formed not only of materials known to those skilled in the art, but also of materials developed in the future for use as gate dielectrics.

[0060] This application may be presented in various forms, some of which will be described below.

[0061] Figure 1a A schematic diagram of a conventional FinFET device is shown. Figure 1b It shows Figure 1a Cross-sectional view along the AA direction.

[0062] like Figure 1a and Figure 1b As shown, the Fin FET device includes a semiconductor substrate 101, a fin structure, an STI (Shallow Trench Isolation) structure 105a, and a gate stack structure.

[0063] The fin structure is located on the semiconductor substrate 101, and in the first direction (e.g. Figure 1a (Extending in the Y-axis direction). In this embodiment, the semiconductor substrate 101 is etched to form a fin structure on the semiconductor substrate 101, that is, the semiconductor substrate 101 and the fin structure are made of the same material, and the semiconductor substrate 101 and the fin structure can be selected from any one of the semiconductor layer, the doped well region, the doped epitaxial semiconductor layer or a combination thereof.

[0064] The fin structure includes a first portion and a second portion located below the first portion. The second portion of the fin structure is doped to form well regions 107, and adjacent well regions 107 are filled with an isolation dielectric layer to form an STI structure 105a, i.e., adjacent well regions 107 are isolated via the STI structure 105a. The gate stack structure is in a second direction intersecting the first direction (e.g., ...). Figure 1a and Figure 1b Extending along the X-axis, the gate stack structure spans the first portion of the fin structure, contacting the sidewalls and top of the first portion, respectively. The gate stack structure surrounds the first portion to form the channel region 113 of the device. The first portions on either side of the channel region 113 are doped to form the source region 111 and drain region 112. The doping type of the source region 111 and drain region 112 is opposite to that of the well region 107. For example, for an N-type MOSFET, the well region 107 is P-type doped, and the source region 111 and drain region 112 are N-type doped; for a P-type MOSFET, the well region 107 is N-type doped, and the source region 111 and drain region 112 are P-type doped. The gate stack structure includes a gate dielectric 109 and a gate conductor 110, and the gate dielectric 109 separates the gate conductor 110 from the first portion of the fin structure. The lower surface of the gate stack structure is in contact with the STI structure 105a. Specifically, the gate dielectric 109 on the lower surface of the gate stack structure is in contact with the STI structure 105a.

[0065] Figure 2 It shows Figure 1a and Figure 1b The current simulation diagram of the FinFET device shown is as follows: Figure 2 As shown, because the fin structure of the FinFET is surrounded on three sides by the gate conductor 110, the electric field intensity is high on the top surface of the fin structure, the sidewalls adjacent to the top surface, and the apex corner between the top surface and the sidewalls. This concentrated electric field in these areas accelerates the degradation of the gate oxide layer, leading to time-dependent dielectric breakdown (TDDB). Furthermore, Figure 2 (a) shows the gate voltage V G Simulation diagram of current at 0V. Figure 2 (b) shows the gate voltage V G Simulation diagram of current at 0.25V. Figure 2 (c) shows the gate voltage V G Simulation diagram of current at 0.5V. Figure 2 (d) shows the gate voltage V G The simulation diagram shows the current at 0.75V. Figure 2 (e) shows the gate voltage V GThe current simulation diagram at 1.0V further reveals that as the gate voltage increases, the electric field intensity becomes more concentrated on the top surface of the fin structure and the part of the sidewall adjacent to the top surface, and is particularly concentrated at the apex between the top surface and the sidewall.

[0066] Figure 3 The illustration shows a cross-sectional schematic diagram of an exemplary FinFET device provided in an embodiment of this application, as shown below. Figure 3 As shown, with Figure 1a and Figure 1b Unlike the Fin FET device shown, in this embodiment, the gate dielectric 109 includes a first gate dielectric 1091 with a first thickness and a second gate dielectric 1092 with a second thickness. The second gate dielectric 1092 covers the upper surface of the channel region 113, including the top surface of the channel region 113 and the upper sidewall of the channel region 113. The first gate dielectric 1091 covers the lower sidewall of the channel region 113 and is located between the gate conductor 110 and the STI structure 105a. The thickness of the second gate dielectric 1092 (second thickness) is greater than the thickness of the first gate dielectric 1091 (first thickness).

[0067] In this embodiment, the thickness of the second gate dielectric 1092 in the upper part of the channel region 113 is set to be relatively large, which optimizes the overall electric field distribution of the device, reduces leakage current, and improves the breakdown electric field, thereby improving the performance of the device.

[0068] Corresponding to Figure 3 In addition to the Fin FET device provided, this application also provides a method for manufacturing the Fin FET device, the method comprising:

[0069] Step S110: Form a fin structure in a semiconductor substrate;

[0070] Step S120: Form an STI structure between the fin-shaped structures, and simultaneously form a porous structure on the upper part of the first part of the fin-shaped structure;

[0071] Step S130: Form a gate dielectric and a gate conductor, wherein the gate dielectric includes a first gate dielectric and a second gate dielectric, the second gate dielectric covers the top surface of the channel region and the upper sidewall of the channel region; the first gate dielectric covers the lower sidewall of the channel region, and the thickness of the second gate dielectric is greater than the thickness of the first gate dielectric.

[0072] Step S140: Form source region and drain region.

[0073] Figures 4a to 4m This is a schematic diagram illustrating the steps of an exemplary FinFET device manufacturing method provided in this application embodiment. The following is in conjunction with... Figures 4a to 4m right Figure 3 The manufacturing method of the Fin FET device shown is described in detail.

[0074] like Figures 4a to 4f As shown, in step S110, a fin structure 101a is formed in the semiconductor substrate 101.

[0075] See Figure 4a A first hard mask layer 102 is formed on the semiconductor substrate 101. Specifically, the first hard mask layer 102 covers the surface of the semiconductor substrate 101. In this embodiment, the semiconductor substrate 101 is single-crystal silicon or silicon-on-insulator (SOI), and the first hard mask layer 102 is an oxide layer, a nitride layer, or a mixed stack of oxide and nitride layers. Figure 4a In the illustrated embodiment, the first hard mask layer 102 includes an oxide layer (e.g., a silicon oxide layer) and a nitride layer (e.g., a silicon nitride layer) stacked sequentially.

[0076] See Figure 4b An auxiliary structure 103 is formed on the first hard mask layer 102.

[0077] In this step, an auxiliary layer is formed on the first hard mask layer 102. A patterned photoresist is formed on the auxiliary layer using photolithography, and the auxiliary layer is etched via the patterned photoresist to form an auxiliary structure 103. The auxiliary structure 103 defines the position of the subsequently formed sidewalls 104a, ultimately defining the position of the fin structure 101a. In this embodiment, the material of the auxiliary structure 103 is, for example, polycrystalline silicon.

[0078] See Figure 4c A second hard mask layer 104 is formed. Specifically, the second hard mask layer 104 is formed using a deposition process, and the second hard mask layer 104 conformally covers the surface of the first hard mask layer 102 and the top surface and sidewalls of the auxiliary structure 103. In this embodiment, the second hard mask layer 104 is, for example, an oxide layer.

[0079] See Figure 4d The sidewall 104a is formed. Specifically, the second hard mask layer 104 is etched using an etching process. The second hard mask layer 104 on the surface of the first hard mask layer 102 and the second hard mask layer 104 on the top surface of the auxiliary structure 103 are removed, while the second hard mask layer 104 on the sidewall of the auxiliary structure 103 is retained, forming the sidewall 104a. In this embodiment, for example, a dry etching process is used to etch the second hard mask layer 104. During the dry etching process, the first hard mask layer 102 serves as a protective layer for the semiconductor substrate 101, preventing over-etching damage to the surface of the semiconductor substrate 101.

[0080] See Figure 4e After forming the sidewall 104a, the auxiliary structure 103 is removed.

[0081] See Figure 4f The first hard mask layer 102 and the semiconductor substrate 101 are etched via sidewall 104a to form a fin structure 101a in the semiconductor substrate 101. The fin structure 101a includes a first portion 101a-1 and a second portion 101a-2. The first portion 101a-1 is used to form the source region, drain region, and channel region between the source and drain regions of the device; the second portion 101a-2 is used to form the well region of the device. Simultaneously with the formation of the fin structure 101a, the sidewall 104a is also etched away, or a separate etching step is used to remove the sidewall 104a.

[0082] It is worth noting that in some embodiments, the method further includes doping the second portion 101a-2 with a corresponding type of dopant to form a well region 107 in the second portion 101a-2. This embodiment will not be described in detail here.

[0083] like Figures 4g to 4j As shown, in step S120, an STI structure 105a is formed between the second part 101a-2 of the fin structure, while a porous structure is formed on the upper part of the first part of the fin structure.

[0084] See Figure 4g An isolation dielectric layer 105 is formed, which fills the gap between the fin structures 101a and covers the top of the first hard mask layer 102. Then, the isolation dielectric layer 105 on top of the first hard mask layer 102 is removed by CMP (Chemical Mechanical Planarization) process, so that the top of the isolation dielectric layer 105 is flush with the top of the first hard mask layer 102.

[0085] See Figure 4h The isolation dielectric layer 105 is etched back to remove the upper portion of the isolation dielectric layer 105 of the first portion 101a-1, thereby exposing the upper portion of the first portion 101a-1, while the lower portion of the first portion 101a-1 and the second portion 101a-2 remain covered by the isolation dielectric layer 105. In this step, for example, dry etching is used to etch back the isolation dielectric layer 105, wherein the first hard mask layer 102 serves as a protective layer for the fin structure 101a to prevent damage to the fin structure 101a during the etch back process.

[0086] Next, the first hard mask layer 102 on top of the fin structure 101a is removed, exposing the top surface of the first part 101a-1 and the sidewalls of the upper part of the first part 101a-1.

[0087] See Figure 4iElectrochemical etching is performed on the upper part of the exposed first portion 101a-1 to form a porous structure on the upper part of the first portion 101a-1. In this step, the semiconductor structure is placed in an HF (hydrofluoric acid) based electrolyte for electrochemical etching, wherein the semiconductor substrate 101 acts as the anode and undergoes an oxidation reaction to form a nanoscale porous structure on the upper part of the exposed first portion 101a-1.

[0088] See Figure 4j Continue etching back the isolation dielectric layer 105 to form the STI structure 105a.

[0089] In this step, the isolation dielectric layer 105 is etched back to remove the isolation dielectric layer 105 between the first portions 101a-1, while retaining the isolation dielectric layer 105 between the second portions 101a-2. The isolation dielectric layer 105 between the second portions 101a-2 forms an STI structure 105a, which is located between the second portions 101a-2 of the adjacent fin structures 101a, exposing the first portion 101a-1 of the fin structures 101a.

[0090] In this step, for example, dry etching or wet etching is used to etch back the isolation dielectric layer 105. In one embodiment, a wet etching process is used to etch back the isolation dielectric layer to ensure the integrity of the porous structure at the top of the first portion 101a-1. In another embodiment, a dry etching process is used to etch back the isolation dielectric layer to ensure the uniformity of the thickness of the STI structure 105a.

[0091] In step S130, a gate dielectric and a gate conductor are formed. The gate dielectric includes a first gate dielectric and a second gate dielectric. The second gate dielectric covers the top surface of the channel region and the upper sidewall of the channel region. The first gate dielectric covers the lower sidewall of the channel region. The thickness of the second gate dielectric is greater than the thickness of the first gate dielectric. Figures 4k to 4m As shown.

[0092] like Figure 4k As shown, a dielectric layer 109a is formed.

[0093] In this step, for example, atomic layer deposition (ALD) is used to deposit a dielectric layer 109a on the surface of the first part 101a-1 of the fin structure 101a. The principle of ALD is to deposit a film layer (such as SiO2 or high-k material HfO2) on the fin surface by alternately introducing precursor gases. The specific steps include: the precursor A adsorbs onto the surface of the target structure, the excess precursor is purged with an inert gas, and a reactive gas (such as O3 or H2O) is introduced to react with the precursor to form a film. This process is repeated to form a film layer of the desired thickness. The film layer formed by ALD has ultra-high uniformity and step coverage, making it suitable for 3D structures. Furthermore, the thickness of the film layer formed by ALD can be precisely controlled (sub-nanometer level).

[0094] Furthermore, the upper part of the first portion 101a-1 has a porous structure. Compared with the lower part of the first portion 101a-1, the porous upper part of the first portion 101a-1 has a greater adsorption capacity for precursors, resulting in more precursors reacting to form an oxide layer in the upper part of the first portion 101a-1. Therefore, the thickness of the dielectric layer 109a formed in the upper part of the first portion 101a-1 is greater than the thickness of the dielectric layer 109a in other parts.

[0095] The dielectric layer 109a formed through the above steps includes a first dielectric layer 1091a and a second dielectric layer 1092a. The first dielectric layer 1091a covers the lower sidewall of the first portion 101a-1, and the second dielectric layer 1092a covers the upper sidewall of the first portion 101a-1 and the top surface of the first portion 101a-1. The thickness of the second dielectric layer 1092a is greater than the thickness of the first dielectric layer 1091a.

[0096] like Figure 4l As shown, structural layer 110a is formed.

[0097] like Figure 4m As shown, the structural layer 110a is etched to form the gate conductor 110. Further, the first dielectric layer 1091a and the second dielectric layer 1092a are etched to form the gate dielectric 109, which is located between the gate conductor 110 and the fin structure 101a.

[0098] Next, the source region and the drain region are formed.

[0099] Figure 5A cross-sectional schematic diagram of another exemplary FinFET device provided in an embodiment of this application is shown. (As...) Figure 5 As shown, unlike the FinFET device shown in Figure 4, in this embodiment, the gate dielectric includes a first gate dielectric 1091, a second gate dielectric 1092, and a transition gate dielectric 1093. The second gate dielectric 1092 covers the top surface of the channel region and the upper sidewall of the channel region; the first gate dielectric 1091 covers the lower sidewall of the channel region, and the transition gate dielectric 1093 is located between the first gate dielectric 1091 and the second gate dielectric 1092. The first gate dielectric 1091 has a first thickness, the second gate dielectric 1092 has a second thickness, and the transition gate dielectric 1093 has a third thickness, wherein the second thickness is greater than the first thickness, and the third thickness is greater than the first thickness but less than the second thickness.

[0100] In this embodiment, a transition gate dielectric 1093 is formed between the first gate dielectric 1091 and the second gate dielectric 1092, avoiding abrupt changes in electric field distribution caused by the abrupt change in thickness between the first gate dielectric 1091 and the second gate dielectric 1092. In one embodiment, the end of the transition gate dielectric 1093 closest to the second gate dielectric 1092 has a larger thickness than the end closest to the first gate dielectric 1091.

[0101] Corresponding to Figure 5 In addition to the provided Fin FET device, this application also provides a method for manufacturing the Fin FET device. The manufacturing method includes:

[0102] Step S210: Form a fin structure in a semiconductor substrate;

[0103] Step S220: Forming STI structures between the fin-shaped structures;

[0104] Step S230: Form a gate dielectric and a gate conductor, wherein the gate dielectric includes a first gate dielectric, a second gate dielectric, and a transition gate dielectric, the second gate dielectric covers the top surface of the channel region and the upper sidewall of the channel region; the first gate dielectric covers the lower sidewall of the channel region, and the transition gate dielectric is located between the first gate dielectric and the second gate dielectric. The first gate dielectric has a first thickness, the second gate dielectric has a second thickness, and the transition gate dielectric has a third thickness, wherein the second thickness is greater than the first thickness, and the third thickness is greater than the first thickness and less than the second thickness.

[0105] Step S240: Form source region and drain region.

[0106] Figures 6a to 6l yes Figure 5The diagram illustrates the steps involved in manufacturing a FinFET device. The following section combines... Figures 6a to 6l The manufacturing method of the Fin FET device provided in the embodiments of this application will be described in detail.

[0107] In step S210, a fin structure 101a is formed in the semiconductor substrate 101. In this embodiment, the step of forming the fin structure is the same as the step shown in step S110, as detailed below. Figures 4a to 4f This embodiment will not be described in detail here. Execution Figures 4a to 4f After the steps shown, perform the steps shown in 6a to 6l.

[0108] like Figure 6a and Figure 6b As shown, in step S220, an STI structure 105a is formed between the second portions 101a-2 of the fin structure.

[0109] See Figure 6a An isolation dielectric layer 105 is formed, which fills the gap between the fin structures 101a and covers the top of the first hard mask layer 102. Then, the isolation dielectric layer 105 on top of the first hard mask layer 102 is removed by CMP (Chemical Mechanical Planarization) process, so that the top of the isolation dielectric layer 105 is flush with the top of the first hard mask layer 102.

[0110] See Figure 6b The isolation dielectric layer 105 is etched back to remove the isolation dielectric layer 105 between the first portions 101a-1, while retaining the isolation dielectric layer 105 between the second portions 101a-2. The isolation dielectric layer 105 between the second portions 101a-2 forms an STI structure 105a, which is located between the second portions 101a-2 of the adjacent fin structures 101a, exposing the first portion 101a-1 of the fin structures 101a.

[0111] In this step, for example, dry etching is used to etch back the isolation dielectric layer 105, wherein the first hard mask layer 102 serves as a protective layer for the fin structure 101a to prevent damage to the fin structure 101a during the etch back process. During the etch back process of the isolation dielectric layer 105, the first hard mask layer 102 on top of the fin structure 101a is also etched away, or a separate etching step is used to remove the first hard mask layer 102 on top of the fin structure 101a.

[0112] In step S230, a gate dielectric and a gate conductor are formed. The gate dielectric includes a first gate dielectric, a second gate dielectric, and a transition gate dielectric. The second gate dielectric covers the top surface of the channel region and the upper sidewall of the channel region. The first gate dielectric covers the lower sidewall of the channel region. The transition gate dielectric is located between the first and second gate dielectrics. The thickness of the second gate dielectric is greater than the thickness of the first gate dielectric. The transition gate dielectric has a third thickness, which is greater than the first thickness but less than the second thickness. Figures 6c to 6l As shown.

[0113] See Figure 6c The first dielectric layer 1091a is formed.

[0114] In this step, for example, a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process is used to form a first dielectric layer 1091a. The first dielectric layer 1091a conformally covers the surface of the STI structure 105a, the top of the first portion 101a-1, and the sidewalls of the first portion 101a-1. The first dielectric layer 1091a has a first thickness.

[0115] See Figure 6d This forms the first structural layer 1101.

[0116] In this step, for example, a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process is used to form a first structural layer 1101. The first structural layer 1101 covers the surface of the first dielectric layer 1091a. Furthermore, the first structural layer 1101 fills the space between the first portions 101a-1 and extends above the first portions 101a-1.

[0117] See Figure 6e The first structural layer 1101 is etched back, and the thickness of the remaining first structural layer 1101 is less than the thickness of the first part 101a-1, so that the first dielectric layer 1091a covering the top of the first part 101a-1 and the first dielectric layer 1091a covering the upper sidewall of the first part 101a-1 are exposed.

[0118] See Figure 6f Using the first structural layer 1101 as a mask layer, the exposed first dielectric layer 1091a is etched to expose the upper sidewall of the first part 101a-1 and the top surface of the first part 101a-1.

[0119] See Figure 6g A second dielectric layer 1092a is formed, which covers the surface of the remaining first structural layer 1101, the exposed top of the first portion 101a-1, and the exposed sidewalls of the first portion 101a-1. The second dielectric layer 1092a has a second thickness, which is greater than the first thickness.

[0120] See Figure 6h This forms a second structural layer 1102. The second structural layer 1102 conformally covers the surface of the second dielectric layer 1092a.

[0121] See Figure 6i The second structural layer 1102 is selectively removed, while the second structural layer 1102 is retained on the top of the first part 101a-1 and on the sidewalls of the first part 101a-1.

[0122] See Figure 6j Using the second structural layer 1102 as a mask and the first structural layer 1101 as an etch stop layer, the exposed second dielectric layer 1092a is removed. In this step, the second dielectric layer 1092a on the surface of the first structural layer 1101 is removed, while the second dielectric layer 1092a on the top and sidewalls of the first portion 101a-1 is retained because it is covered by the second structural layer 1102.

[0123] Furthermore, during the removal of the exposed second dielectric layer 1092a, the second dielectric layer 1092a between the bottom of the second structural layer 1102 and the top of the first structural layer 1101 on the sidewall of the first portion 101a-1 is also removed, creating a lateral notch uc between the bottom of the second structural layer 1102 and the top of the first structural layer 1101. The etchant laterally etches the exposed second dielectric layer 1092a on the sidewall of the first portion 101a-1 through the lateral notch uc to reduce the thickness of the second dielectric layer 1092a on the sidewall of the first portion 101a-1, thereby forming a transition dielectric layer 1093a with a third thickness at the lateral notch uc. The third thickness is greater than the first thickness but less than the second thickness. The transition dielectric layer 1093a forms a transition layer between the first dielectric layer 1091a and the second dielectric layer 1092a, thereby avoiding the abrupt change in electric field distribution caused by the abrupt change in thickness between the first dielectric layer 1091a and the second dielectric layer 1092a.

[0124] See Figure 6k This forms a third structural layer. The third structural layer covers the surfaces of the first structural layer 1101 and the second structural layer 1102, and fills the lateral cutout uc between the first structural layer 1101 and the second structural layer 1102. The first structural layer 1101, the second structural layer 1102, and the third structural layer together form structural layer 110a.

[0125] See Figure 6l The structural layer 110a is etched to form the gate conductor 110. The first dielectric layer 1091a, the transition dielectric layer 1093a, and the second dielectric layer 1092a are further etched to form the gate dielectric 109, which is located between the gate conductor 110 and the fin structure 101a.

[0126] Next, the source region and the drain region are formed.

[0127] The unexpected technical effect of this application is:

[0128] In this embodiment, the thickness of the second gate dielectric in the upper part of the channel region is set to be relatively large, which optimizes the overall electric field distribution of the device, reduces leakage current, and increases the breakdown electric field, thereby improving the performance of the device.

[0129] In a preferred embodiment, a transition gate dielectric is formed between the first gate dielectric and the second gate dielectric, thereby avoiding abrupt changes in the electric field distribution caused by the abrupt change in thickness between the first gate dielectric and the second gate dielectric.

[0130] In a preferred embodiment, the end of the transition gate dielectric 1093 closest to the second gate dielectric 1092 has a larger thickness than the end closest to the first gate dielectric 1091, which further reduces the thickness gradient between the first gate dielectric and the transition gate dielectric, as well as the thickness gradient between the transition gate dielectric and the second gate dielectric.

[0131] In a preferred embodiment, by forming a porous structure on the upper part of the first portion of the fin-shaped structure, the upper part of the porous first portion has a greater adsorption capacity for precursors compared to the lower part of the first portion during the subsequent formation of the dielectric layer. This results in more precursors reacting and forming an oxide layer on the upper part of the first portion. Therefore, the thickness of the dielectric layer formed on the upper part of the first portion is greater than the thickness of the dielectric layer on other parts.

[0132] In a preferred embodiment, a lateral cut is formed at one end of the second dielectric layer near the first dielectric layer, and the exposed second dielectric layer is etched through the lateral cut to reduce the thickness of the second dielectric layer, thereby forming a transition dielectric layer with a third thickness.

[0133] As described above, these embodiments of this application do not exhaustively cover all details, nor do they limit the application to merely the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A method for manufacturing a FinFET device, comprising: A fin-shaped structure is formed in a semiconductor substrate, the fin-shaped structure comprising a first portion and a second portion located below the first portion; An STI structure is formed between the second parts; A grid stack structure is formed, the grid stack structure spanning the first part and contacting the sidewall and top of the first part respectively; A source region and a drain region are formed, which are located in the first part and on both sides of the gate stack structure; The gate stack structure includes a gate dielectric and a gate conductor. The gate dielectric includes a first gate dielectric with a first thickness and a second gate dielectric with a second thickness. The second gate dielectric covers the top surface of the first portion and the upper sidewall of the first portion. The first gate dielectric covers the lower sidewall of the first portion. The second thickness is greater than the first thickness. While forming the STI structure, a porous structure is formed in the upper part of the first part; The method for forming the gate stack structure includes: A medium layer is formed. Compared with the lower part of the first part, the upper part of the porous first part has a greater adsorption capacity for the precursor. The thickness of the medium layer formed on the upper part of the first part is greater than the thickness of the medium layer formed on the lower part of the first part. Form structural layers; The structural layer and dielectric layer are etched to form the gate conductor and gate dielectric.

2. The manufacturing method according to claim 1, wherein, A method for forming a porous structure on the upper part of the first portion while forming an STI structure includes: A first hard mask layer is formed on top of the fin-shaped structure; An isolation medium layer is formed, which fills the gaps between the fin structures, and the top of the isolation medium layer is flush with the top of the first hard mask layer; The isolation dielectric layer is etched back to expose the upper part of the first portion; Electrochemical corrosion treatment is performed on the upper part of the exposed first part to form a porous structure on the upper part of the first part; Continue etching back the isolation dielectric layer to form the STI structure.

3. The manufacturing method according to claim 1, wherein, The gate dielectric further includes a transition gate dielectric with a third thickness, which is located between the first gate dielectric and the second gate dielectric. The third thickness is greater than the first thickness and less than the second thickness.

4. The manufacturing method according to claim 3, wherein, The method of forming the transition gate dielectric includes: A first dielectric layer and a first structural layer are formed. The first dielectric layer covers the surface of the STI structure and the lower sidewall of the first portion. The first structural layer covers the surface of the first dielectric layer, and the top of the first structural layer is flush with the top of the first dielectric layer covering the lower sidewall of the first portion. The first dielectric layer has a first thickness. A second dielectric layer and a second structural layer are formed. The second dielectric layer covers the upper sidewall of the first portion and the top surface of the first portion. The second structural layer covers the surface of the second dielectric layer. A lateral cut is provided between the bottom of the second dielectric layer and the top of the first structural layer to expose the second dielectric layer. The second dielectric layer has a second thickness, which is greater than the first thickness. The second dielectric layer on the first portion of the sidewall exposed by the lateral etching through the lateral cut is used to reduce the thickness of the second dielectric layer and form a transition dielectric layer, the thickness of which is greater than the first thickness and less than the second thickness; The first dielectric layer, the second dielectric layer, and the transition dielectric layer are etched to form the first gate dielectric, the second gate dielectric, and the transition gate dielectric, respectively.

5. The manufacturing method according to claim 4, wherein, The method of forming the first dielectric layer and the first structural layer includes: A first dielectric layer is formed, which conformally covers the surface of the STI structure, the top of the first portion, and the sidewalls of the first portion; A first structural layer is formed, which fills the space between the first portions and extends above the first portions; The first structural layer is etched back, exposing the first dielectric layer covering the top of the first portion and the first dielectric layer covering the upper sidewall of the first portion; Using the first structural layer as a mask, the exposed first dielectric layer is removed, exposing the upper sidewall and the top surface of the first part.

6. The manufacturing method according to claim 4, wherein, Methods for forming the second dielectric layer and the second structural layer include: A second dielectric layer is formed, which covers the surface of the first structural layer, the top of the exposed first portion, and the sidewalls of the exposed first portion; A second structural layer is formed, which conformally covers the surface of the second dielectric layer; The second structural layer is selectively removed, while the second structural layer is retained on the top of the first part and on the sidewalls of the first part; The exposed second dielectric layer is removed using the second structural layer as a mask and the first structural layer as an etch stop layer.

7. A FinFET device, manufactured using the method described in any one of claims 1-6, comprising: Semiconductor substrate; A fin-shaped structure located on the semiconductor substrate, the fin-shaped structure comprising a first portion and a second portion located below the first portion; An STI structure is located on the semiconductor substrate and between adjacent second portions; A grid stack structure spans the first part and contacts the sidewall and top of the first part, respectively; as well as The source region and the drain region are located in the first part and on both sides of the gate stack structure; The gate stack structure includes a gate dielectric and a gate conductor. The gate dielectric includes a first gate dielectric with a first thickness and a second gate dielectric with a second thickness. The second gate dielectric covers the top surface of the first portion and the upper sidewall of the first portion. A first gate dielectric covers the lower sidewall of the first portion, and the second thickness is greater than the first thickness.

8. The Fin FET device according to claim 7, wherein, The gate dielectric further includes a transition gate dielectric with a third thickness, which is located between the first gate dielectric and the second gate dielectric. The third thickness is greater than the first thickness and less than the second thickness.

9. The Fin FET device according to claim 8, wherein, Compared to the end near the first gate dielectric, the end of the transition gate dielectric near the second gate dielectric has a greater thickness.

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