Vertical channel field effect transistor and method of manufacturing the same

Abstract

The present application relates to a kind of vertical channel field effect transistor and its preparation method, belong to semiconductor device technical field.It includes: silicon oxide substrate, its one side is provided with high platform;Wherein, high platform each side is provided with multilayer film structure;First guide groove on the first side of multilayer film structure and first guide groove on the second side of adjacent multilayer film structure are communicated;First guide groove is perpendicular to silicon oxide substrate;Multiple first dielectric layer, is set to the surface of silicon oxide substrate;Wherein, first dielectric layer both sides are provided with second guide groove;Second guide groove is communicated with the nearest first guide groove;First guide groove and second guide groove are provided with nanowire;Source electrode, is set to the side of high platform away from silicon oxide substrate;Multiple gate electrode, each gate electrode is set to the third side of each multilayer film structure, and is connected with dielectric layer.The present application realizes single nanowire high-density multi-independent channel, improves structure utilization.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a vertical channel field-effect transistor and its fabrication method. Background Technology

[0002] As semiconductor device dimensions continue to shrink, vertical nanowire field-effect transistors (VFETs) have become an important research direction in semiconductor devices due to their advantages such as high integration density and strong short-channel effect suppression. In existing technologies, various fabrication and structural schemes for VFETs have been proposed. For example, existing technology (CN112599418A) discloses a VFET that uses nano-metal droplet catalysis to achieve bottom-up growth of silicon nanowires, allowing the nanowires to be arranged along a predetermined path. The nanowire segment perpendicular to the substrate serves as the conductive channel of the field-effect transistor. This technology can eliminate the dependence on photolithography precision and effectively reduce the vertical projection area of ​​the transistor.

[0003] However, the aforementioned existing technologies still have significant shortcomings, as follows: First, although the vertical sections on both sides of the step on the same nanowire can form two vertical channels, the channel spacing is still limited by the photolithography precision, and the current allowed to pass through a single nanowire on one side is limited, resulting in insufficient driving capability.

[0004] Second, while multi-step guidance can improve the current carrying capacity on one side, each nanowire can only provide one channel, resulting in low device structure utilization and poor economic efficiency.

[0005] Third, multiple nanowires arranged side by side on one side cannot be controlled separately as independent transistor channels, which limits the flexibility of device integration. Although the vertical nanowires on both sides of the step can be controlled independently, their spacing is still limited by the precision of the photolithography process, making it difficult to further improve the integration density.

[0006] In addition, the three-dimensional vertical nanowire channel field-effect transistors currently in use generally have two major technical problems: first, it is difficult to obtain high-density multi-channel field-effect transistors in a single nanowire; second, even if a multi-channel structure is achieved, it is difficult to independently control each transistor channel, which cannot meet the requirements of complex integrated circuits for device flexibility and controllability. Summary of the Invention

[0007] Therefore, the technical problem to be solved by the present invention is to overcome the defects of the prior art, such as the limitation of vertical nanowire channel spacing by photolithography precision, insufficient current driving capability of single nanowire, low utilization rate of multi-nanowire structure and inability to be independently controlled, and low integration.

[0008] In a first aspect, to solve the above-mentioned technical problems, the present invention provides a vertical channel field-effect transistor, comprising: A silicon oxide substrate has a raised platform on one side. Each side of the raised platform is provided with a multilayer film structure. Each multilayer film structure includes a first side, a second side, and a third side. The first and second sides are provided with first guiding trenches. The first side of one multilayer film structure is adjacent to the second side of an adjacent multilayer film structure, and the first guiding trench on the first side of the multilayer film structure communicates with the first guiding trench on the second side of the adjacent multilayer film structure. The first guiding trench is perpendicular to the silicon oxide substrate. Multiple first dielectric layers are disposed on the surface of the silicon oxide substrate; wherein, second guide trenches are disposed on both sides of the first dielectric layers; the second guide trenches are connected to the nearest first guide trench; nanowires are disposed within the first guide trenches and the second guide trenches; The source electrode is disposed on the side of the platform away from the silicon oxide substrate; Multiple gate electrodes are provided, each of which is disposed on the third side of each of the multilayer film structures; the first dielectric layer is connected to the gate electrode.

[0009] In one embodiment of the present invention, the first dielectric layer includes a first insulating layer and a second insulating layer; the first insulating layer is disposed on the surface of the silicon oxide substrate, and the second insulating layer is disposed on the surface of the first insulating layer.

[0010] In one embodiment of the present invention, the width of the first insulating layer in a first direction is smaller than the width of the second insulating layer; wherein, the first direction is the direction in which the first insulating layer is parallel to the third side of the nearest multilayer film structure.

[0011] In one embodiment of the present invention, a plurality of drain electrodes are further included, each of the drain electrodes being disposed on the surface of the silicon oxide substrate and connected to both ends of the nanowire.

[0012] In one embodiment of the present invention, the plurality of gate electrodes include a first gate electrode and a second gate electrode; the first gate electrode is disposed on a third side of one of the multilayer film structures, and the second gate electrode is disposed on a third side of another multilayer film structure.

[0013] In one embodiment of the present invention, a plurality of drain electrodes are further included, the drain electrodes being connected to one end of the nanowire; each drain electrode is independent of the others.

[0014] In one embodiment of the present invention, the first side and the second side of the multilayer film structure further include a third guiding trench, the third guiding trench on the first side of the multilayer film structure being connected to the third guiding trench on the second side of the adjacent multilayer film structure; the third guiding trench is perpendicular to the silicon oxide substrate.

[0015] In one embodiment of the present invention, a second dielectric layer is disposed on the upper surface of each first dielectric layer, and a fourth guiding trench is disposed on both sides of the second dielectric layer; the fourth guiding trench is connected to the nearest third guiding trench; nanowires are disposed in the third guiding trench and the fourth guiding trench.

[0016] Secondly, to solve the above-mentioned technical problems, the present invention provides a method for fabricating a vertical channel field-effect transistor, which is used to fabricate the above-mentioned vertical channel field-effect transistor, comprising: A platform is fabricated on a silicon oxide substrate, and a first insulating layer and a second insulating layer are sequentially deposited on the surface of the silicon oxide substrate; the first insulating layer and the second insulating layer are both attached to each side of the platform. The first insulating layer and the second insulating layer are etched to obtain a plurality of first dielectric layers and a plurality of multilayer film structures; wherein, the first side of the multilayer film structure is adjacent to the second side of the adjacent multilayer film structure; Selective lateral etching is performed on each of the first dielectric layers and the first insulating layer in each of the multilayer film structures to cause the first insulating layer to shrink inward on both sides; the shrunken first insulating layer forms a first guide trench with the second insulating layer in the multilayer film structure and a second guide trench with the second insulating layer in the first dielectric layer; wherein, the first guide trench on the first side of the multilayer film structure is connected to the first guide trench on the second side of the adjacent multilayer film structure; Catalytic indium particles are prepared at one end of the second guiding trench; An amorphous silicon thin film is deposited in the first guide trench and the second guide trench; the indium catalytic metal particles are heated to activate the indium catalytic metal particles, and the indium catalytic metal particles crystallize the amorphous silicon thin film along the second guide trench and the first guide trench to form nanowires; A source electrode is prepared on the side of the platform away from the silicon oxide substrate, a gate electrode is prepared on the third side of each multilayer film structure, and a drain electrode is prepared on the surface of the silicon oxide substrate to obtain a vertical channel field-effect transistor; wherein, nanowires perpendicular to the silicon oxide substrate are used as the transistor conductive channel region.

[0017] In one embodiment of the present invention, photolithography is used to etch the first insulating layer and the second insulating layer to obtain a plurality of first dielectric layers and a plurality of multilayer film structures.

[0018] Compared with the prior art, the above-described technical solution of the present invention has the following advantages: (1) The vertical channel field-effect transistor and its fabrication method described in this invention can realize the directional and regular arrangement of trenches, which facilitates the implementation of anisotropic etching processes. By controlling the etching time to regulate the shrinkage depth of the second insulating layer, the vertical segment spacing of the nanowires can be controlled, enabling high-density integration without relying on photolithography precision, and ensuring the forming accuracy of high aspect ratio trenches. At the same time, the interconnected trenches can provide continuous and uniform growth or filling channels for nanowires, improving the orderliness and consistency of nanowire arrangement, avoiding nanowire shifting, agglomeration or collapse, and thus improving the structural stability and uniformity of the device. The first guiding trench and the second guiding trench cooperate to form a complete guiding network, further optimizing the growth path and interface contact state of the nanowires, reducing contact resistance, and improving carrier transport efficiency. The source electrode is positioned on the side of the platform away from the silicon oxide substrate, enabling vertical lead-out, which simplifies the wiring structure and reduces parasitic parameters. The third side of each multilayer film structure is independently provided with a gate electrode, and the first dielectric layer is connected to the gate electrode, which enables independent gate control of each multilayer film structure, enhances gate control capability, improves gate dielectric interface characteristics, and reduces gate leakage current.

[0019] (2) This invention can form high-density vertical multi-channel field-effect transistors in a single nanowire, effectively simplifying the device fabrication process, improving fabrication efficiency, and reducing process costs, thus possessing good economic and practical advantages. At the same time, in this high-density vertical multi-channel field-effect transistor structure, independent gate control of each nanowire channel can be achieved, significantly improving the transistor integration density, which is beneficial for reducing device size and parasitic effects, thereby effectively improving the overall performance of the integrated circuit. Attached Figure Description

[0020] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0021] Figure 1 This is a schematic diagram of a vertical channel field-effect transistor structure in a preferred embodiment of the present invention; Figure 2 This is a schematic diagram of the vertical channel field-effect transistor structure in the first case of a preferred embodiment of the present invention; Figure 3 This is a schematic diagram of the vertical channel field-effect transistor structure in the second case of a preferred embodiment of the present invention; Figure 4 This is a schematic diagram of the vertical channel field-effect transistor structure in the third case of a preferred embodiment of the present invention; Figure 5 This is a schematic diagram of the vertical channel field-effect transistor structure in the fourth case of a preferred embodiment of the present invention; Figure 6This is a flowchart of a method for fabricating a vertical channel field-effect transistor according to a preferred embodiment of the present invention; Figure 7 This is a schematic diagram of the fabrication process of a vertical channel field-effect transistor in a preferred embodiment of the present invention; Figure 8 This is a top view of the structure in the fabrication process of a vertical channel field-effect transistor in a preferred embodiment of the present invention.

[0022] Explanation of reference numerals in the accompanying drawings: 101, silicon oxide substrate; 102, silicon nitride layer; 103, amorphous silicon oxide layer; 104, guide trench; 105, indium particle; 106, nanowire; 107, platform; 1071, multilayer film structure; 201, source electrode; 202, drain electrode; 203, gate electrode; 302, first drain electrode; 303, first gate electrode; 304, second drain electrode; 305, second gate electrode. Detailed Implementation

[0023] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, so that those skilled in the art can better understand and implement the present invention. However, the embodiments described are not intended to limit the present invention.

[0024] Example 1: Reference Figures 1 to 2 As shown, an embodiment of the present invention provides a vertical channel field-effect transistor, comprising: A silicon oxide substrate 101 has a raised platform 107 on one side. Each side of the raised platform 107 has a multilayer film structure 1071. Each multilayer film structure 1071 includes a first side, a second side, and a third side. The first and second sides have first guiding trenches. The first side of the multilayer film structure 1071 is adjacent to the second side of an adjacent multilayer film structure, and the first guiding trench on the first side of the multilayer film structure 1071 communicates with the first guiding trench on the second side of the adjacent multilayer film structure. The first guiding trenches are perpendicular to the silicon oxide substrate 101. Multiple first dielectric layers are disposed on the surface of a silicon oxide substrate 101; wherein, second guide trenches are disposed on both sides of the first dielectric layers; the second guide trenches are connected to the nearest first guide trenches; nanowires 106 are disposed in the first guide trenches and the second guide trenches; The source electrode 201 is disposed on the side of the platform 107 away from the silicon oxide substrate 101; Multiple gate electrodes 203 are provided, each gate electrode 203 being disposed on the third side of each multilayer film structure 1071; a first dielectric layer is connected to the gate electrode 203.

[0025] The present invention discloses a vertical channel field-effect transistor (VFET) employing a platform structure on a silicon oxide substrate. Each side of the platform has a multilayer film structure. The first and second sides of the multilayer film structure have first guiding trenches perpendicular to the silicon oxide substrate, and the first guiding trenches of adjacent multilayer film structures are interconnected. This structure enables the orientation and regular arrangement of trenches, facilitating anisotropic etching processes and ensuring the forming accuracy of high aspect ratio trenches. Simultaneously, the interconnected trenches provide continuous and uniform growth or filling channels for nanowires, improving the orderliness and consistency of nanowire arrangement, preventing nanowire misalignment, aggregation, or collapse, and enhancing structural stability and device uniformity. Second guiding trenches are provided on both sides of a first dielectric layer on the surface of the silicon oxide substrate, and these second guiding trenches are connected to the nearest first guiding trench, forming a complete and continuous guiding network. This further optimizes the growth path and interface contact of the nanowires, reduces contact resistance, and improves carrier transport efficiency. The source electrode is positioned on the side of the platform away from the silicon oxide substrate, enabling vertical lead-out, simplifying the wiring structure, and reducing parasitic parameters. Each multilayer film structure has an independently set gate electrode on its third side, with the first dielectric layer connected to the gate electrode. This allows for independent gate control of each multilayer film structure, enhancing gate control capability, improving gate-dielectric interface characteristics, and reducing gate leakage current. The overall three-dimensional structural design improves device integration while effectively reducing substrate parasitic capacitance and leakage current, enhancing device isolation performance and operational stability, making it suitable for high-density, high-performance nanowire device fabrication. Furthermore, this embodiment of the invention achieves high-density vertical multi-channel field-effect transistors within a single nanowire, improving fabrication efficiency.

[0026] Specifically, the first dielectric layer includes a first insulating layer and a second insulating layer. The first insulating layer is disposed on the upper surface of the silicon oxide substrate 101, and the second insulating layer is disposed on the upper surface of the first insulating layer. The material of the first insulating layer can be a dielectric material such as silicon nitride, and its phase can be amorphous or polycrystalline; the material of the second insulating layer can also be a dielectric material such as silicon oxide, and its phase can also be amorphous or polycrystalline. In this embodiment, the first insulating layer is preferably a silicon nitride layer 102, and the second insulating layer is preferably an amorphous silicon oxide layer 103. The silicon nitride layer 102 is disposed on the surface of the silicon oxide substrate 101, and the amorphous silicon oxide layer 103 is disposed on the surface of the silicon nitride layer 102; wherein, the silicon nitride layer 102 is an amorphous silicon nitride layer or a polycrystalline silicon nitride layer. In this embodiment, the silicon nitride layer 102 is preferably an amorphous silicon nitride layer.

[0027] Furthermore, the width of the silicon nitride layer 102 in the first direction is smaller than the width of the amorphous silicon oxide layer 103, thereby forming trenches on both sides, which are the second guiding trenches. The first direction is the direction in which the silicon nitride layer 102 is parallel to the third side surface of the nearest multilayer film structure, and the sidewalls of the second guiding trench are perpendicular to the nearest multilayer film structure.

[0028] In this embodiment, the first guiding trench on the first side of the multilayer film structure 1071, the first guiding trench on the second side of the adjacent multilayer film structure, and the adjacent second guiding trenches are interconnected to form a complete guiding trench. The nanowire 106 grown along the guiding trench has its vertical section (the portion perpendicular to the silicon oxide substrate 101) serving as the channel region of the transistor, with the top and bottom ends of the nanowire 106 serving as the source and drain of the transistor, respectively. In this embodiment, the nanowire 106 is preferably a silicon nanowire. The guiding trench extends to both sides, forming two vertical sections on the same nanowire 106. Both vertical sections can serve as conductive channels, either sharing the same channel for the same transistor or serving as channels for different transistors. Based on the structure of the silicon nanowire 106, various field-effect transistor structures can be designed. Specifically, through combinations of electrode sharing and gate control methods, the following situations apply: Case 1: Two conductive channels formed by the same nanowire 106 share the same electrode at their top as the source or drain, and the same electrode at their bottom as the drain or source.

[0029] Specifically, refer to Figure 2 As shown, the nanowires 106 on the first side of any multilayer film structure 1071 and the second side of the adjacent multilayer film structure can serve as the channel of the same transistor to increase the channel current. In this case, the two channels share the source, drain, and gate. The gate electrode 203 is separated from the vertical nanowires 106 by a first dielectric layer. The vertical nanowire segment corresponding to the gate electrode 203 forms the transistor channel. The left and right parts of the gate electrode 203 (i.e., the adjacent gate electrodes 203) are electrically connected, and the channel current can be uniformly controlled through the gate electrode 203. Furthermore, this structure also includes multiple drain electrodes 202. Each drain electrode 202 is disposed on the surface of the silicon oxide substrate 101 where the platform 107 is located, and is connected to both ends of the nanowires 106. Specifically, the nanowires 106 extending in two directions (i.e., within the two second guide trenches) share the drain electrode 202.

[0030] Case 2: Two conductive channels formed by the same nanowire 106 share the same electrode as the source at their top ends, and the ends of the nanowire 106 extending in different directions at their bottom ends form two independent drains, and the gates controlling the conductive channels control the two conductive channels respectively.

[0031] Specifically, refer to Figure 3As shown, nanowires 106 on the first side of any multilayer film structure 1071 and the second side of an adjacent multilayer film structure can serve as channels for different transistors. In this case, the two transistors share a source at the top, but do not share a drain or gate at the bottom. Specifically, the multiple gate electrodes include a first gate electrode 303 and a second gate electrode 305; the first gate electrode 303 is disposed on the third side of one of the multilayer film structures 1071, and the second gate electrode 305 is disposed on the third side of another multilayer film structure, with the two multilayer film structures 1071 adjacent to each other. Furthermore, the field-effect transistor in this structure also includes multiple drain electrodes, each drain electrode connected to one end of the nanowire 106, and each drain electrode is independent of the others. Specifically, the drain electrodes include a first drain electrode 302 and a second drain electrode 304, with both ends of the nanowire 106 connected to the first drain electrode 302 and the second drain electrode 304, respectively.

[0032] Furthermore, the first gate electrode 303, the second gate electrode 305, and their corresponding vertical nanowires 106 are all isolated by a first dielectric layer, and the vertical nanowire portions corresponding to the first gate electrode 303 and the second gate electrode 305 respectively constitute the channels of two transistors. Through this structure, the currents of the two vertical nanowire channels are independently controlled by the two gates (the first gate electrode 303 and the second gate electrode 305), forming two mutually interacting transistors.

[0033] Case 3: Two conductive channels formed by the same nanowire 106 share a common electrode at their top as the source, and the nanowire ends extending in different directions at their bottoms form two independent drains, and the gate controlling the conductive channel controls both conductive channels simultaneously.

[0034] Specifically, refer to Figure 4As shown, the nanowires 106 on the first side of any multilayer film structure 1071 and the second side of the adjacent multilayer film structure can serve as channels for different transistors. In this case, the transistors share a source at the top, do not share a drain at the bottom, and share a gate. The third side of the adjacent multilayer film structures is provided with the same gate electrode 203. The gate electrode 203 and the vertical nanowires 106 are separated by a first dielectric layer. The vertical nanowire portion corresponding to the gate is the transistor channel region. The left and right portions of the gate electrode 203 are electrically connected, thus controlling the switching of the conductive channel by controlling the gate electrode 203. Furthermore, the field-effect transistor in this structure also includes multiple drain electrodes, each connected to one end of the nanowire 106, and each drain electrode is independent. Specifically, the drain electrodes include a first drain electrode 302 and a second drain electrode 304. The nanowires 106 extending in two directions from the lower end (i.e., the nanowires 106 in the second guide trench) are respectively connected to the first drain electrode 302 and the second drain electrode 304. This design can control the magnitude of the current flowing to the first drain electrode 302 and the second drain electrode 304 by controlling the voltage of the first drain electrode 302 and the second drain electrode 304 respectively.

[0035] Scenario 4: Increase the number of conductive channels by stacking multiple layers.

[0036] Specifically, refer to Figure 5 As shown, the first and second sides of any multilayer film structure 1071 also include a third guiding trench. The third guiding trench on the first side of the multilayer film structure is connected to the third guiding trench on the second side of the adjacent multilayer film structure. The third guiding trench is perpendicular to the silicon oxide substrate 101.

[0037] Furthermore, a second dielectric layer is disposed on the upper surface of each first dielectric layer. The second dielectric layer has a similar structure to the first dielectric layer, both consisting of a silicon nitride layer 102 and an amorphous silicon oxide layer 103 stacked sequentially. Fourth guiding trenches are disposed on both sides of the second dielectric layer; the fourth guiding trenches are connected to the nearest third guiding trench; nanowires 106 are disposed within the third and fourth guiding trenches. Through the above design, the structure includes two stacked silicon nanowires 106. In this embodiment, the same end of each silicon nanowire 106 layer located on the same side shares the same drain electrode.

[0038] It should be noted that the number of silicon nanowires 106 can be adjusted according to actual application requirements. By increasing the number of guide trenches on the first and second sides of the multilayer film structure, a stacked arrangement of more silicon nanowire layers can be achieved. Furthermore, Figures 1 to 5 The diagram only shows one perspective of the structure. The structures of the other multilayer membrane structure 1071 and the dielectric layer are similar to those shown in the diagram, but are not shown in the diagram.

[0039] This embodiment enables the formation of high-density vertical multi-channel field-effect transistors within a single nanowire, simplifying the device fabrication process, improving fabrication efficiency, reducing process costs, and making it more economical and practical. Furthermore, this high-density vertical multi-channel field-effect transistor structure allows for independent gate control of each nanowire channel, significantly improving transistor integration density, which helps reduce device size and parasitic effects, thereby effectively improving the overall performance of the integrated circuit.

[0040] Example 2: Reference Figure 6 and Figure 7 As shown, this embodiment provides a method for fabricating a vertical channel field-effect transistor (VFET), used to fabricate the VFET described in Embodiment 1, including but not limited to the following steps: S1. A platform 107 is fabricated on a silicon oxide substrate 101, and a first insulating layer and a second insulating layer are sequentially deposited on the surface of the silicon oxide substrate 101; the first insulating layer and the second insulating layer are both attached to each side of the platform 107. S2. The first insulating layer and the second insulating layer are etched to obtain multiple first dielectric layers and multiple multilayer film structures 1071; wherein, the first side of the multilayer film structure 1071 is adjacent to the second side of the adjacent multilayer film structure. S3. Selectively laterally etch each first dielectric layer and each first insulating layer in the multilayer film structure 1071 to shrink the first insulating layer inward on both sides; the shrunken first insulating layer forms a first guide trench with the second insulating layer in the multilayer film structure 1071 and a second guide trench with the second insulating layer in the first dielectric layer; wherein, the first guide trench on the first side of the multilayer film structure 1071 is connected to the first guide trench on the second side of the adjacent multilayer film structure. S4. Prepare catalytic indium particles 105 at one end of the second guide trench; S5. Deposit an amorphous silicon thin film in the first guide trench and the second guide trench; heat the indium catalytic particles 105 to activate the indium catalytic particles 105, and the indium catalytic particles 105 crystallize the amorphous silicon thin film along the second guide trench and the first guide trench to form nanowires 106. S6. A source electrode 201 is prepared on the side of the platform 107 away from the silicon oxide substrate 101, a gate electrode 203 is prepared on the third side of each multilayer film structure, and a drain electrode is prepared on the surface of the silicon oxide substrate 101 to obtain a vertical channel field-effect transistor; wherein, the nanowire perpendicular to the silicon oxide substrate 101 is used as the transistor conductive channel region.

[0041] Specifically, in this embodiment, the first insulating layer is preferably a silicon nitride layer 102, and the second insulating layer is preferably an amorphous silicon oxide layer 103. Furthermore, it should be noted that the first dielectric layer and the corresponding multilayer film structure are integrally formed; the first insulating layer in each multilayer film structure is tightly attached to one side of the platform, and the second insulating layer is disposed on the surface of the first insulating layer.

[0042] Specifically, a platform 107 is fabricated on a silicon oxide substrate 101, and the platform 107 is integrally formed with the silicon oxide substrate 101. In this embodiment, a deposition process can be used to deposit a protrusion structure with a set height in a predetermined area of ​​the substrate. The platform is made of a different material than the silicon nitride layer 102. By utilizing the difference in etching selectivity between the two, the platform 107 can be prevented from being simultaneously etched and worn away during the subsequent etching process of the silicon nitride layer 102, thereby ensuring the integrity and stability of the platform structure morphology.

[0043] Furthermore, referring to Figure 8 As shown, after the deposition of the silicon nitride layer 102 and the amorphous silicon oxide layer 103, the four corners of the structure are etched to expose the internal silicon nitride layer 102. The corner etching process needs to be combined with photolithography. Specifically, photolithography is used to etch the silicon nitride layer 102 and the amorphous silicon oxide layer 103 to obtain multiple first dielectric layers and multiple multilayer film structures 1071. The width of the multilayer film structure 1071 matches the side width of the platform 107, and each first dielectric layer is arranged perpendicularly to its corresponding multilayer film structure 1071.

[0044] For example, in step S2, the step of etching the silicon nitride layer 102 and the amorphous silicon oxide layer 103 using photolithography and etching methods to obtain multiple first dielectric layers and multiple multilayer film structures 1071 is as follows: S210. Using deep reactive ion etching (DRIE) technology, selective etching is performed on the four corner regions of the silicon nitride layer 102 and the amorphous silicon oxide layer 103. The etching area is defined by a photolithographic mask to remove excess material at the corners, forming four equidistant, vertically aligned, and height-consistent multilayer film structures 1071.

[0045] S220. Using an overlay alignment technique, the mask pattern is aligned with the position of each multilayer film structure, and protrusions corresponding to the multilayer film structure 1071 are etched at the corresponding corners of the substrate (i.e., silicon nitride layer 102 and amorphous silicon oxide layer 103). These protrusions are aligned with the multilayer film structure 1071 in the vertical direction, thereby dividing the continuous silicon nitride layer 102 and amorphous silicon oxide layer 103 into multiple independent first dielectric layers.

[0046] Further, in step S3, the silicon nitride layer 102 is laterally etched, causing the silicon nitride layer 102 to shrink inward and form trenches (including a first guide trench and a second guide trench). This trench forming process does not require photolithography. In the above process, the internal insulating structure platform 107 will be exposed after etching. In this embodiment, the platform 107 is made of a non-conductive material.

[0047] Furthermore, the spacing between the two vertical nanowires 106 (i.e., the spacing between the first guiding trench on the first side of the multilayer film structure 1071 and the first guiding trench on the second side of the adjacent multilayer film structure) is controlled by the lateral etching time. This embodiment defines the separation spacing between the vertical nanowires by controlling the lateral etching time, enabling the fabrication of extremely small spacing, overcoming the limitations of photolithography on this critical dimension, and thus achieving high-density integration of vertical structures. The first guiding trenches on each multilayer film structure 1071 and the second guiding trenches in each first dielectric layer can be formed simultaneously using this process, and subsequent processes can be optimized according to actual needs. The high-density vertical nanowire structures fabricated using the method described in this embodiment can be used as conductive channels for independent transistors.

[0048] Furthermore, the first guiding groove on the first side of the multilayer membrane structure, the first guiding groove on the adjacent second side of the multilayer membrane structure, and the adjacent second guiding grooves are interconnected to form a complete guiding groove 104. Catalytic indium particles 105 are disposed at any end of the guiding groove 104.

[0049] Furthermore, the fabrication method for the multiple nanowire structures in Example 1 (corresponding to Case 4) is as follows: First, a platform is fabricated on a silicon oxide substrate 101. Then, multiple layers of silicon nitride and amorphous silicon oxide dielectric films are alternately and cyclically deposited on the substrate and the platform surface. In this example, a first silicon nitride layer, a first amorphous silicon oxide layer, a second silicon nitride layer, and a second amorphous silicon oxide layer can be formed sequentially through at least two deposition processes. After each deposition of the silicon nitride layer and the amorphous silicon oxide layer, the current film layer is patterned using photolithography and etching processes. Multiple first dielectric layers, second dielectric layers, and multilayer film structures 1071 are sequentially etched and distributed in an array. The positional accuracy between the patterns of each layer is ensured by overlay alignment. After patterning, a lateral etching process with high selectivity for silicon nitride is used to selectively etch the first dielectric layer, the second dielectric layer, and the silicon nitride layer inside the multilayer film structure 1071 from both sides inwards. This causes the silicon nitride layer to shrink controllably, thereby forming regular and interconnected guide trenches at the interface between the dielectric layer and the multilayer film structure, namely the third guide trench and the fourth guide trench. Subsequently, catalytic indium particles 105 are prepared at one end of each guide trench 104. Based on the metal-induced crystallization or vapor phase growth mechanism, a planar nanowire directional growth process is used to simultaneously grow multiple regular and independent nanowires 106 within the multiple guide trenches, thereby realizing the fabrication of a multi-channel, high-density nanowire structure. It should be noted that in this multilayer stacked structure, the multilayer film structure 1071 is composed of multiple dielectric layers stacked alternately, which, along the thickness direction, sequentially include: a first silicon nitride layer, a first amorphous silicon oxide layer, a second silicon nitride layer, and a second amorphous silicon oxide layer. The multi-layered structure together forms a stable support framework, providing a structural basis and spatial constraints for the formation of trenches by lateral etching and the directional growth of nanowires.

[0050] Further, in step S6, photolithography is used to define the electrode pattern, and then a source electrode and a drain electrode are prepared by metal deposition. On the third side of each multilayer film structure, the gate region is precisely positioned by side photolithography, and the gate metal layer is deposited in a directional manner. After removing redundant metal by trimming etching, the gate electrode is prepared.

[0051] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A vertical channel field-effect transistor, characterized in that, include: A silicon oxide substrate has a raised platform on one side. Each side of the raised platform is provided with a multilayer film structure. Each multilayer film structure includes a first side, a second side, and a third side. The first and second sides are provided with first guiding trenches. The first side of one multilayer film structure is adjacent to the second side of an adjacent multilayer film structure, and the first guiding trench on the first side of the multilayer film structure communicates with the first guiding trench on the second side of the adjacent multilayer film structure. The first guiding trench is perpendicular to the silicon oxide substrate. Multiple first dielectric layers are disposed on the surface of the silicon oxide substrate; wherein, second guide trenches are disposed on both sides of the first dielectric layers; the second guide trenches are connected to the nearest first guide trench; nanowires are disposed within the first guide trenches and the second guide trenches; The source electrode is disposed on the side of the platform away from the silicon oxide substrate; Multiple gate electrodes are provided, each of which is disposed on the third side of each of the multilayer film structures; the first dielectric layer is connected to the gate electrode.

2. The vertical channel field-effect transistor according to claim 1, characterized in that, The first dielectric layer includes a first insulating layer and a second insulating layer; the first insulating layer is disposed on the surface of the silicon oxide substrate, and the second insulating layer is disposed on the surface of the first insulating layer.

3. A vertical channel field-effect transistor according to claim 2, characterized in that, The width of the first insulating layer in a first direction is smaller than the width of the second insulating layer; wherein, the first direction is the direction in which the first insulating layer is parallel to the third side of the nearest multilayer film structure.

4. A vertical channel field-effect transistor according to claim 1, characterized in that, It also includes multiple drain electrodes, each of which is disposed on the surface of the silicon oxide substrate and connected to both ends of the nanowire.

5. A vertical channel field-effect transistor according to claim 1, characterized in that, The plurality of gate electrodes include a first gate electrode and a second gate electrode; the first gate electrode is disposed on the third side of one of the multilayer film structures, and the second gate electrode is disposed on the third side of another multilayer film structure.

6. A vertical channel field-effect transistor according to claim 5, characterized in that, It also includes multiple drain electrodes, which are connected to one end of the nanowire; each drain electrode is independent of the others.

7. A vertical channel field-effect transistor according to claim 1, characterized in that, The first and second sides of the multilayer film structure also include a third guiding groove, and the third guiding groove on the first side of the multilayer film structure is connected to the third guiding groove on the second side of the adjacent multilayer film structure; the third guiding groove is perpendicular to the silicon oxide substrate.

8. A vertical channel field-effect transistor according to claim 7, characterized in that, A second dielectric layer is disposed on the upper surface of each of the first dielectric layers, and a fourth guide trench is disposed on both sides of the second dielectric layer; the fourth guide trench is connected to the nearest third guide trench; nanowires are disposed in the third guide trench and the fourth guide trench.

9. A method for fabricating a vertical-channel field-effect transistor, used to fabricate the vertical-channel field-effect transistor according to any one of claims 1 to 8, characterized in that... ,include: A platform is fabricated on a silicon oxide substrate, and a first insulating layer and a second insulating layer are sequentially deposited on the surface of the silicon oxide substrate; the first insulating layer and the second insulating layer are both attached to each side of the platform. The first insulating layer and the second insulating layer are etched to obtain a plurality of first dielectric layers and a plurality of multilayer film structures; wherein, the first side of the multilayer film structure is adjacent to the second side of the adjacent multilayer film structure; Selective lateral etching is performed on each of the first dielectric layers and the first insulating layer in each of the multilayer film structures to cause the first insulating layer to shrink inward on both sides; the shrunken first insulating layer forms a first guide trench with the second insulating layer in the multilayer film structure and a second guide trench with the second insulating layer in the first dielectric layer; wherein, the first guide trench on the first side of the multilayer film structure is connected to the first guide trench on the second side of the adjacent multilayer film structure; Catalytic indium particles are prepared at one end of the second guiding trench; An amorphous silicon thin film is deposited in the first guide trench and the second guide trench; the indium catalytic metal particles are heated to activate the indium catalytic metal particles, and the indium catalytic metal particles crystallize the amorphous silicon thin film along the second guide trench and the first guide trench to form nanowires; A source electrode is prepared on the side of the platform away from the silicon oxide substrate, a gate electrode is prepared on the third side of each multilayer film structure, and a drain electrode is prepared on the surface of the silicon oxide substrate to obtain a vertical channel field-effect transistor; wherein, nanowires perpendicular to the silicon oxide substrate are used as the transistor conductive channel region.

10. A method for fabricating a vertical channel field-effect transistor according to claim 9, characterized in that... The first insulating layer and the second insulating layer are etched using photolithography to obtain multiple first dielectric layers and multiple multilayer film structures.

Images