A super-junction lateral mosfet device integrated with a schottky diode

Abstract

The application discloses an integrated Schottky diode super-junction lateral MOSFET device, and belongs to the technical field of semiconductor power devices. The device comprises a doped substrate, a doped structure, a drift region, a doped well region and a doped drain region; a plurality of doped source region units with closed geometric shapes are periodically arranged in the doped well region; the doped well region on the periphery of each source region unit forms a surrounding channel region; a super-junction doped column region is located between the source region unit and the drain region and directly contacts the doped well region; a distributed Schottky contact region is arranged in the gap between adjacent source region units. The application realizes a three-dimensional surrounding high-density channel through a periodic array of source regions, greatly reduces the on-resistance; the distributed Schottky contact restrains the reverse recovery current and reduces the switching loss; the super-junction structure is combined to optimize the electric field distribution, improve the breakdown voltage and reliability, and is suitable for the high-voltage power integration field of SiC and other wide-bandgap semiconductor materials.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor power device technology and relates to a superjunction lateral MOSFET device with integrated Schottky diode. Background Technology

[0002] In the field of power integrated circuits (PICs), the monolithic integration of low-voltage logic control circuits and high-voltage power devices is a key development trend. Lateral power devices (such as lateral MOSFETs), due to their lateral structure where all electrodes are located on the same surface of the chip, have excellent process compatibility and ease of integration, and have become important switching devices for power conversion.

[0003] To break through the performance limits of traditional lateral devices, the industry has introduced superjunction technology into lateral MOSFETs. Utilizing the depletion effect of alternating P-type and N-type semiconductor pillars, the lateral superjunction structure can overcome the trade-off between breakdown voltage and on-resistance. However, the number of conductive channels that can be integrated per unit chip area is severely limited by the cell layout of lateral devices, the photolithographic spacing of the superjunction pillars, and the gate arrangement. This low channel density results in insufficient effective parallel channels when the device is turned on, leading to a high channel resistance ratio. This makes it difficult for lateral superjunction devices to further reduce conduction losses and meet the demands of high power density applications.

[0004] Furthermore, the parasitic body diode inherent in superjunction lateral MOSFETs, acting as a natural freewheeling path in the third quadrant, exhibits minority carrier storage effects. Its long reverse recovery time and high recovery charge easily lead to severe voltage and current spikes and electromagnetic interference (EMI) under hard-switching conditions, also increasing switching losses. To completely eliminate these drawbacks of the body diode, integrating a Schottky barrier diode (SBD) within the device has become a key approach to improving reverse recovery characteristics.

[0005] Currently, integrated SBD technology is mostly found in vertical power devices. However, when it is directly transplanted or applied to lateral superjunction devices, it faces irreconcilable technical contradictions: First, the introduction of the SBD Schottky contact region disrupts the original electric field balance on the surface of the lateral superjunction, which easily leads to local electric field concentration within the cell (especially at the edge of the SBD junction), severely weakening the device's high-voltage withstand capability. Second, under extreme conditions such as short circuits, heat dissipation in the lateral SBD region is limited, and the rapid increase in lattice temperature can easily lead to a surge in leakage current and cause irreversible thermal damage, resulting in poor short-circuit reliability. Finally, within the limited lateral cell size, the SBD region inevitably occupies valuable active area, which further worsens the already low channel density, making it difficult to achieve an optimal trade-off between forward conduction resistance, reverse freewheeling capability, and breakdown voltage reliability.

[0006] In summary, how to cleverly integrate the ease of integration of lateral structures, the high voltage and low loss advantages of superjunction technology, and the excellent reverse recovery characteristics of integrated Schottky diodes, while overcoming the aforementioned problems of electric field distortion, area constraints, and thermal failure, and developing a superjunction lateral MOSFET power device with both high channel density and high reliability has become a technical bottleneck that urgently needs to be overcome in the current power semiconductor field. Summary of the Invention

[0007] The present invention aims to overcome the shortcomings of the prior art and provide a high-performance superjunction lateral MOSFET power device.

[0008] This invention, on the one hand, innovatively optimizes the channel layout inside the device, significantly increasing the channel density and effective conduction area, thereby significantly reducing the overall on-resistance of the device; on the other hand, by cleverly integrating a Schottky barrier junction in the source region of the device, it fundamentally suppresses the reverse recovery current of the superjunction power device, significantly reducing the reverse recovery loss.

[0009] To achieve the above-mentioned technical objectives, the technical solution adopted by the present invention is as follows:

[0010] A superjunction lateral MOSFET device with integrated Schottky diode, comprising:

[0011] Doped substrate and doped structure connected thereto;

[0012] Drift regions located on the doped structure;

[0013] The doped well region and the doped drain region are located within the drift region;

[0014] Multiple doped source units located within the doped well region and arranged periodically, each unit having a closed geometry;

[0015] A gate electrode is disposed on the top layer of the doped well region and the drift region, and is used to control the formation of a surrounding channel region in the doped well region around the doped source region unit.

[0016] The superjunction doped pillar region is located between the doped source region unit and the doped drain region, and is in direct contact with the doped well region;

[0017] Distributed Schottky contact regions are disposed within the gaps between adjacent doped source region units.

[0018] Preferably, the doped well regions around the doped source region unit cooperate with each other to make the channel region have a three-dimensional surrounding layout, so as to form an effective channel width that conducts in parallel in multiple directions within a unit chip area.

[0019] Preferably, the doped source region unit is a square doped source region, and multiple square doped source regions are arranged at intervals along the width direction of the doped substrate, and adjacent units are electrically connected through conductive structures; the doped well region around each square unit forms a semi-enclosed channel segment, forming a high-density channel of the square source region.

[0020] Preferably, the doped source region unit is an interdigitated doped source region with a T-shaped cross-section, including a first arm and a second arm that are perpendicular to each other; the first arm is arranged along the width direction and connected to the first arm of the adjacent unit; the second arm extends from the center point of the first arm in a direction parallel to the doped drain region, and a set spacing is maintained between the second arms of each unit to define the channel region.

[0021] Preferably, the gate electrode adopts a planar gate structure or a shielded gate structure; wherein, when a shielded gate structure is adopted, the shielded gate is used to reduce the conduction loss of the device and improve the switching speed.

[0022] Preferably, the structure of the distributed Schottky contact region is as follows: a portion of the oxide layer is removed between adjacent doped source region units to expose the drift region, and a Schottky contact is formed by extending a source electrode to cover the exposed drift region; the distributed Schottky contact region and the doped source region units are arranged alternately.

[0023] Preferably, the superjunction lateral MOSFET device with integrated Schottky diode further includes:

[0024] The T-type Schottky contact region is formed by etching away the oxide layer between adjacent doped source units and exposing the underlying drift region. The source electrode simultaneously forms an ohmic contact with the doped source unit and a Schottky contact with the exposed drift region.

[0025] Preferably, the superjunction lateral MOSFET device with integrated Schottky diode further includes:

[0026] A strip-shaped Schottky contact region is disposed around the source electrode in a direction parallel to the doped drain region, so that the source electrode and the drift region are in direct contact to form a strip-shaped region of uniform width, which is used to further suppress reverse recovery loss.

[0027] Preferably, the superjunction lateral MOSFET device with integrated Schottky diode further includes:

[0028] An oxide layer is disposed on the doped well region and surrounds the gate electrode;

[0029] The source electrode and drain electrode are exposed above the oxide layer;

[0030] The source electrode partially surrounds the gate electrode and the two are insulated and isolated by the oxide layer. The source electrode is electrically connected to the doped source region and the Schottky contact region through the opening in the oxide layer.

[0031] Preferably, the device is made entirely of silicon carbide material;

[0032] The doped drain region, the doped source region unit, and the drift region are all doped with nitrogen.

[0033] The doped well region, the doped substrate, the doped structure, and the superjunction doped pillar region are all doped with aluminum.

[0034] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0035] 1. This invention innovatively designs the source region as a multi-branch, surrounding, periodic arrangement structure, forming a three-dimensional conductive channel surrounding each source region doped unit within the doped well region. This structure breaks the topological limitations of traditional strip or conventional polygonal cells, enabling the channels to conduct in parallel along multiple directions. This design significantly increases the effective channel width and channel density per unit area without increasing the chip's physical area, thereby significantly reducing channel resistance and the device's specific on-resistance, effectively improving current drive capability.

[0036] 2. This invention, while ensuring high channel density, cleverly integrates Schottky contact regions (SBDs) between adjacent source region doped units. Under third-quadrant reverse freewheeling conditions, the Schottky barrier diode conducts preferentially over the parasitic body diode due to its lower turn-on voltage. Based on the majority carrier conduction mechanism of the Schottky barrier diode, the injection and storage effects of minority carriers can be fundamentally suppressed. This not only significantly reduces reverse recovery charge and reverse recovery current, and substantially lowers switching losses and electromagnetic interference under high-frequency hard-switching conditions, but also achieves synergistic optimization of device conduction performance and reverse freewheeling characteristics.

[0037] 3. This invention enhances the lateral total depletion capability of the drift region by making the P-pillar directly contact the doped well region. This structure optimizes the internal two-dimensional electric field distribution, making it smoother and more uniform, and significantly improves the breakdown voltage of the device. At the same time, it also significantly reduces the local electric field accumulation stress at the bottom of the gate oxide layer, thereby greatly improving the robustness and long-term reliability of the device under extreme conditions such as high voltage blocking, avalanche breakdown, and short circuits.

[0038] 4. The device structure proposed in this invention is particularly suitable for the development of wide-bandgap semiconductor power devices such as silicon carbide (SiC). This structure can fully utilize the excellent physical properties of SiC materials, such as high critical breakdown electric field, high frequency, and high temperature resistance, meeting the needs of medium and high voltage power electronic systems. In addition, this design scheme has a certain degree of versatility and can be applied to superjunction power devices based on traditional silicon (Si) or other semiconductor materials. Attached Figure Description

[0039] To clearly illustrate the technical solutions of the embodiments of the present invention, the relevant drawings will be briefly described below. It should be noted that the drawings only exemplarily show some embodiments of the present invention, and those skilled in the art can derive other equivalent drawings based on these drawings without creative effort.

[0040] Figure 1 This is a schematic diagram of a traditional MOSFET device with electrodes.

[0041] Figure 2 This is a three-dimensional structural diagram of a traditional MOSFET device after the gate electrode, source electrode, drain electrode, and oxide layer have been removed.

[0042] Figure 3 This is a three-dimensional structural diagram of a superjunction device with a periodically arranged channel structure after removing the gate electrode, source electrode, drain electrode, and oxide layer.

[0043] Figure 4 for Figure 3 Cross-sectional view at A1A1';

[0044] Figure 5 for Figure 4 A schematic diagram of a device structure including a shielded gate structure, source electrode, drain electrode, and oxide layer;

[0045] Figure 6 for Figure 4 A schematic diagram of a device structure including a planar gate structure, source electrode, drain electrode, and oxide layer;

[0046] Figure 7 for Figure 3 Cross-sectional view at A2A2';

[0047] Figure 8 for Figure 7 A schematic diagram of a device structure including a gate electrode, a source electrode, and an oxide layer;

[0048] Figure 9 for Figure 3 Top view of the superjunction device;

[0049] Figure 10 yes Figure 3A three-dimensional structural diagram of a superjunction device with a distributed SBD formed through a Schottky contact at the source.

[0050] Figure 11 for Figure 10 Cross-sectional view at B1B1';

[0051] Figure 12 for Figure 11 A schematic diagram of a device structure including a planar gate structure, source electrode, drain electrode, and oxide layer;

[0052] Figure 13 for Figure 11 A schematic diagram of a device structure including a shielded gate structure, source electrode, drain electrode, and oxide layer;

[0053] Figure 14 for Figure 10 A schematic diagram of the device structure including the electrodes, SBD, and oxide layer in the cross section of B2B2';

[0054] Figure 15 for Figure 10 Top view of the superjunction device;

[0055] Figure 16 yes Figure 10 A three-dimensional structural diagram of a superjunction device with an added SBD contact region at the source electrode;

[0056] Figure 17 for Figure 16 A schematic diagram of the structure at D1D1' including the gate electrode, source electrode, drain electrode, SBD, and oxide layer;

[0057] Figure 18 for Figure 16 A schematic diagram of the cross-section at D2D2' including the gate electrode, source electrode, SBD, and oxide layer;

[0058] Figure 19 for Figure 16 Top view of the superjunction device structure;

[0059] Figure 20 for Figure 3 A three-dimensional structural diagram of the T-type Schottky contact region in the source region.

[0060] Figure 21 for Figure 20 A schematic diagram of the structure at the cross-section of C1C1', including the gate electrode, source electrode, drain electrode, SBD, and oxide layer;

[0061] Figure 22 for Figure 20A schematic diagram of the structure at the cross-section of C2C2', including the gate electrode, source electrode, SBD, and oxide layer;

[0062] Figure 23 for Figure 20 Top view of the superjunction device;

[0063] Figure 24 for Figure 3 A schematic diagram of the three-dimensional structure after optimizing the gate structure by making a strip Schottky contact in the source region;

[0064] Figure 25 for Figure 24 A schematic diagram of the structure at the cross-section of E1E1', including the gate electrode, source electrode, drain electrode, SBD, and oxide layer;

[0065] Figure 26 for Figure 24 A schematic diagram of the structure at the cross-section of E2E2', including the gate electrode, source electrode, drain electrode, SBD, and oxide layer;

[0066] Figure 27 for Figure 24 A schematic diagram of the structure at E3E3', including the gate electrode, source electrode, and oxide layer;

[0067] Figure 28 for Figure 24 Top view of the superjunction device;

[0068] Figure 29 A three-dimensional structural diagram of a superjunction device with a stepped, encircling structure of channels;

[0069] Figure 30 for Figure 29 Cross-sectional view at F1F1';

[0070] Figure 31 for Figure 30 A schematic diagram of a device structure including a gate electrode, a source electrode, a drain electrode, and an oxide layer;

[0071] Figure 32 for Figure 29 A schematic diagram of the cross-section at F2F2' including the gate electrode, source electrode, drain electrode, and oxide layer;

[0072] Figure 33 for Figure 29 A schematic diagram of the cross-section at F3F3' including the gate electrode, source electrode, drain electrode, and oxide layer;

[0073] Figure 34 for Figure 29 Top view of the superjunction device;

[0074] Figure 35 for Figure 29 A three-dimensional structural diagram of a superjunction device with an embedded distributed SBD;

[0075] Figure 36 for Figure 35 A schematic diagram of the structure at the cross-section of G1G1', including the gate electrode, source electrode, drain electrode, and oxide layer;

[0076] Figure 37 for Figure 35 A schematic diagram of the structure at the cross-section of G2G2', including the gate electrode, source electrode, drain electrode, SBD, and oxide layer;

[0077] Figure 38 for Figure 35 A schematic diagram of the structure at the cross-section of G3G3', including the gate electrode, source electrode, SBD, and oxide layer;

[0078] Figure 39 for Figure 35 Top view of the superjunction device;

[0079] Figure 40 for Figure 35 A three-dimensional structural diagram showing the addition of a strip-shaped SBD contact region around the source electrode;

[0080] Figure 41 for Figure 40 The cross-section at H1H1' includes the gate electrode, source electrode, drain electrode, SBD, and oxide layer;

[0081] Figure 42 for Figure 40 A schematic diagram of the structure at H2H2', including the gate electrode, source electrode, drain electrode, and oxide layer;

[0082] Figure 43 for Figure 40 A schematic diagram of the structure at H3H3', including the gate electrode, source electrode, SBD, and oxide layer;

[0083] Figure 44 for Figure 40 Top view of the superjunction device.

[0084] The markings in the figure are: 1. Doped substrate; 2. Doped structure; 3. Drift region; 4. Doped drain region; 5. Top compensation region; 6. Doped source region; 7. Doped well region; 8. Channel region; 9. Source electrode; 10. Gate electrode; 11. Drain electrode; 12. Oxide layer; 13. Superjunction doped pillar region; 14. Distributed Schottky contact region; 15. Interdigitated doped source region; 16. Square doped source region; 17. Square source region high-density channel; 18. Interdigitated source region high-density channel; 19. T-type Schottky contact region; 20. Strip Schottky contact region. Detailed Implementation

[0085] The following will illustrate the embodiments of the present invention through specific examples. Those skilled in the art, based on the content disclosed in this specification, can easily understand other advantages and effects of the present invention. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified and adjusted based on different perspectives and application scenarios, without departing from the spirit of the present invention.

[0086] In the detailed description of the embodiments of the present invention, for ease of explanation, the cross-sectional views of the device structure are not drawn to conventional scale, but rather enlarged portions are used; the above schematic diagrams are merely examples and are not intended to limit the scope of protection of the present invention. Furthermore, in actual fabrication, the three-dimensional spatial dimensions constituted by length, width, and depth must also be considered.

[0087] For ease of description, this document may use spatial relation terms such as "below," "below," "below," and "above" to describe the relative positional relationship between a component or feature in the accompanying drawings and other components or features. It should be understood that such spatial relation terms not only cover the orientation shown in the accompanying drawings but also include other orientations of the device in actual use or operation.

[0088] It should be noted that the accompanying drawings provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show components related to the present invention and are not drawn according to the actual number, shape, and size of the components in actual implementation. In actual implementation, the shape, quantity, and proportion of each component can be flexibly adjusted according to requirements, and the overall layout of the components may also be more complex.

[0089] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments described are only some embodiments of the present invention, not all embodiments; the components shown in the accompanying drawings can be laid out and designed in various configurations according to different needs.

[0090] Example 1:

[0091] See appendix Figures 1-2This embodiment provides a conventional power MOSFET device, which includes a doped substrate 1, a doped structure 2, and a drift region 3 stacked sequentially from bottom to top. It also includes an oxide layer 12 disposed on a doped well region 7, and a source electrode 9, a gate electrode 10, and a drain electrode 11 disposed within the oxide layer 12. A P-type doped well region 7 is disposed in the upper region of the drift region 3, and a doped source region 6 is formed within the doped well region 7. A doped drain region 4 is formed on the drift region 3, separated from the doped source region 6 by a portion of the drift region 3. A top compensation region 5 is located between the doped well region 7 and the doped drain region 4. The top compensation region 5 is not in direct contact with the doped well region 7; a certain width of drift region 3 separates them. A channel region 8 is located below the gate electrode 10, on the surface of the doped well region 7 on the side of the doped source region 6 closest to the doped drain region 4. When a forward bias is applied to the gate, a conductive channel is formed, connecting the doped source region 6 and the drift region 3.

[0092] Drain electrode 11 is disposed on the top layer of doped drain region 4, and its top layer is exposed above oxide layer 12. Drain electrode 11 is in contact with doped drain region 4, that is, drain electrode 11 and the top layer surface of doped drain region 4 form an ohmic contact. Source electrode 9 is disposed on the top layer of doped source region 6, and its top layer is exposed above oxide layer 12. Source electrode 9 is in contact with doped source region 6, that is, source electrode 9 and the top layer surface of doped source region 6 form an ohmic contact. Gate electrode 10 is disposed on the top layer of channel region 8 and drift region 3, and gate electrode 10 and the top layer surface of channel region 8 and drift region 3 form an ohmic contact.

[0093] In this traditional structure, the conductive channels are arranged in a continuous linear pattern with a single direction, resulting in limited channel density and relatively high on-resistance. Simultaneously, the JFET region is prone to electric field concentration, affecting reliability, and the uneven electric field distribution reduces the device's breakdown voltage. Furthermore, the device structure and its inherent minority carrier injection and storage effects increase switching losses and result in poor reverse recovery characteristics.

[0094] Example 2:

[0095] See appendix Figures 3-9 This embodiment provides a high-channel-density MOSFET superjunction device, comprising a doped substrate 1, a doped structure 2, and a drift region 3 stacked sequentially from bottom to top, with the doped structure 2 connected to the doped substrate 1. The drift region 3 contains a superjunction doped pillar region 13, a doped drain region 4, and a doped well region 7. The doped well region 7 contains a square doped source region 16 and a square source region high-density channel 17. The square doped source region 16 and the doped drain region 4 are located on opposite sides of the drift region 3, and the superjunction doped pillar region 13 is located between the square doped source region 16 and the doped drain region 4. Conductive channels are formed on the other three sides of the square doped source region 16 away from the superjunction doped pillar region 13; these channels constitute the square source region high-density channel 17.

[0096] Specifically, such as Figure 5 The diagram also includes an oxide layer 12 disposed on the doped well region 7, and a gate electrode 10, a source electrode 9, and a drain electrode 11 disposed within the oxide layer 12. The drain electrode 11 is disposed on the top layer of the doped drain region 4, and its top layer is exposed above the oxide layer 12. The drain electrode 11 is in contact with the doped drain region 4, i.e., the drain electrode 11 and the top surface of the doped drain region 4 form an ohmic contact. The source electrode 9 is disposed on the top layer of the square doped source region 16 and the gate electrode 10, and its top layer is exposed above the oxide layer 12. The source electrode 9 partially surrounds the gate electrode 10, and the two are separated by a portion of the oxide layer 12, without contact. The source electrode 9 is in contact with the square doped source region 16, i.e., the source electrode 9 and the top surface of the square doped source region 16 form an ohmic contact.

[0097] Specifically, such as Figure 6 As shown, in Figure 5 Based on this, the gate electrode 10 can also adopt a planar gate structure. Due to its simple process, low cost, and strong impact resistance, it has obvious advantages in terms of cost and surge current resistance.

[0098] The square doped source regions 16 are arranged in a square, spaced-out pattern, comprising multiple blocky N-type heavily doped region units periodically arranged along the width direction. There is a gap between adjacent units, and the bottom of each unit does not contact the drift region 3. The doped well regions 7 surrounding each blocky unit form a semi-enclosed channel segment. These channel segments are connected in parallel along multiple directions, constituting a high-density channel 17 in the square source region. Compared to traditional MOSFET device structures, by optimizing the source region structure, the channel distribution density per unit area is effectively optimized, significantly improving the channel density and thus effectively reducing the on-resistance of the MOSFET device, thereby improving the overall electrical performance of the device.

[0099] Example 3:

[0100] See appendix Figures 10-19This embodiment provides a high-channel-density MOSFET superjunction device with integrated SBD, comprising a doped substrate 1, a doped structure 2, and a drift region 3 stacked sequentially from bottom to top, with the doped structure 2 connected to the doped substrate 1; a superjunction doped pillar region 13, a doped drain region 4, and a doped well region 7 are disposed within the drift region 3, and a square doped source region 16 and a square source region high-density channel 17 are disposed within the doped well region 7. The square doped source region 16 and the doped drain region 4 are located on opposite sides of the drift region 3, and the superjunction doped pillar region 13 is located between the square doped source region 16 and the doped drain region 4. The gap region between the square doped source regions 16 is etched with an oxide layer 12 to expose the underlying drift region 3, and the source electrode 9 contacts this exposed region to form a distributed Schottky contact region 14. Conductive channels are disposed on the other three sides of the square doped source regions 16 away from the superjunction doped pillar region 13, which are the square source region high-density channels 17.

[0101] Specifically, such as Figure 12 The diagram also includes an oxide layer 12 disposed on the doped well region 7, and a gate electrode 10, a source electrode 9, and a drain electrode 11 disposed within the oxide layer 12. The drain electrode 11 is disposed on the top layer of the doped drain region 4, and its top layer is exposed above the oxide layer 12. The drain electrode 11 is in contact with the doped drain region 4, i.e., the drain electrode 11 and the top surface of the doped drain region 4 form an ohmic contact. The source electrode 9 is disposed on the top layer of the square doped source region 16 and the gate electrode 10, and its top layer is exposed above the oxide layer 12. The source electrode 9 partially surrounds the gate electrode 10, and the two are separated by a portion of the oxide layer 12 and do not contact each other. The source electrode 9 forms an ohmic contact with the top surface of the square doped source region 16. While forming an ohmic contact with the square doped source region 16, the source electrode 9 forms a distributed Schottky contact region 14 by etching a portion of the oxide layer 12 and the drift region 3, which is alternately arranged with the doped region units of the square doped source region 16. The gate electrode 10 is disposed on the top layer of the square source region high-density channel 17 and the square doped source region 16, and is separated by a portion of the oxide layer 12.

[0102] Specifically, such as Figure 14 As shown, along Figure 10 The cross-sectional view generated by B2B2' in the diagram, along with a detailed cross-sectional view of the device structure, also includes the oxide layer 12 on the doped well region 7, and the gate electrode 10, source electrode 9, and distributed Schottky contact region 14 surrounded by the oxide layer 12. The source electrode 9 is disposed on the top layer of the square doped source region 16 and the gate electrode 10, with its top layer exposed above the oxide layer 12. The source electrode 9 partially surrounds the gate electrode 10, and the two are separated by a portion of the oxide layer 12, without contact. The source electrode 9 forms an ohmic contact with the top surface of the square doped source region 16. While forming an ohmic contact with the square doped source region 16, the source electrode 9 forms a distributed Schottky contact region 14 with the drift region 3 by etching the oxide layer 12.

[0103] Each doped region unit is surrounded by a partially doped well region 7 in a semi-enclosed state. These partially doped well regions 7 are spaced apart from the partially doped well regions 7 surrounding adjacent doped region units, thus forming a channel surrounding the square doped source region 16. The channel is disposed above the doped well regions 7, and this channel is a square source region high-density channel 17. The square source region high-density channel 17 is also composed of multiple block-shaped channel units, each block-shaped channel unit semi-enclosing a doped region unit and having a gap with adjacent block-shaped channel units.

[0104] The improved superjunction doped pillar region 13 is set in the drift region 3. Analogous to the superjunction structure, it effectively disperses and smooths the electric field distribution on the device surface and the junction edge, significantly suppresses the electric field concentration phenomenon, thereby improving the breakdown voltage and withstand voltage capability.

[0105] Furthermore, between the doped source regions, part of the oxide layer 12 is removed by etching, exposing the underlying drift region 3. While the source electrode 9 covers the square doped source region 16 to form an ohmic contact, it extends to cover this exposed area, forming a distributed Schottky contact region 14. This region is alternately arranged with the doped units of the square doped source region 16. During reverse freewheeling, the distributed SBD preferentially conducts over the parasitic body diode, significantly reducing reverse recovery charge, decreasing switching losses, and enhancing the device's capabilities at high frequencies and in the third quadrant.

[0106] In the above embodiments, the square source region high-density channel 17 structure employs a geometrically consistent channel configuration in each stepped unit, particularly along the current transmission path, where the channel width is precisely identical and uniformly distributed. This highly consistent width design ensures uniform current distribution throughout the channel region during conduction, effectively avoiding current congestion and electric field concentration caused by local width differences. Simultaneously, it significantly improves the consistency of electrical parameters between channel units, enhances the linearity and response stability of the device's switching process, and further suppresses hot carrier effects and the generation of local hot spots. Thus, while maintaining the advantage of low on-resistance, it comprehensively improves the reliability, lifespan, and overall performance of the MOSFET device under high-frequency, high-power conditions.

[0107] Example 4:

[0108] See appendix Figures 20-23This embodiment provides a MOSFET superjunction device with high channel density T-type Schottky contact, comprising a doped substrate 1, a doped structure 2, and a drift region 3 stacked sequentially from bottom to top, with the doped structure 2 connected to the doped substrate 1. The drift region 3 contains a superjunction doped pillar region 13, a doped drain region 4, and a doped well region 7. The doped well region 7 contains a square doped source region 16, a square source region high-density channel 17, and a T-type Schottky contact region 19. The square doped source region 16 and the doped drain region 4 are located on opposite sides of the drift region 3, and the superjunction doped pillar region 13 is located between the square doped source region 16 and the doped drain region 4. The gap between the square doped source regions 16 is etched with a large-area oxide layer 12, and the source electrode 9 contacts this exposed area to form the T-type Schottky contact region 19. Conductive channels are provided on the other three sides of the square doped source regions 16 away from the superjunction doped pillar region 13; these channels constitute the square source region high-density channel 17.

[0109] Compared with Example 3, in the source region, this example forms an ohmic contact by contacting the source electrode 9 with the square doped source region 16, while etching part of the oxide layer around the doped well region 7 in a semi-enclosed state along each doped region unit to form a T-type Schottky contact region 19 surrounding the doped well region with the drift region 3, thereby increasing the Schottky contact region of the device and further reducing the reverse recovery loss of the device.

[0110] Compared with Example 2, this example etches the oxide layer 12 to form a T-type Schottky contact region 19 between the source electrode 9 and the drift region 3. While maintaining the high channel density of Example 2, it further reduces the reverse recovery charge and current of the device, significantly reduces switching losses and electromagnetic interference, achieves synergistic optimization of forward conduction characteristics and reverse switching characteristics, and improves the reliability of the device.

[0111] Compared with Example 1, this example improves the traditional top compensation region 5 by directly contacting the improved superjunction doped pillar region 13 with the doped well region 7 to alleviate the electric field concentration effect, enhance the lateral depletion capability of the drift region, make the electric field distribution more uniform, reduce the electric field stress at the bottom of the gate oxide layer while increasing the breakdown voltage, and improve the reliability of the device under extreme conditions such as high voltage, avalanche and short circuit.

[0112] Example 5:

[0113] See appendix Figures 24-28This embodiment provides a high-channel-density MOSFET superjunction device with an integrated strip-shaped SBD, comprising a doped substrate 1, a doped structure 2, and a drift region 3 stacked sequentially from bottom to top, with the doped structure 2 connected to the doped substrate 1. The drift region 3 contains a superjunction doped pillar region 13, a doped drain region 4, and a doped well region 7. The doped well region 7 contains a square doped source region 16 and a square source region high-density channel 17. The square doped source region 16 and the doped drain region 4 are located on opposite sides of the drift region 3, and the superjunction doped pillar region 13 is located between the square doped source region 16 and the doped drain region 4. Between the doped well regions 7, the drift region 3 is exposed by etching an oxide layer 12, and the source electrode 9 contacts this exposed area to form a strip-shaped Schottky contact region 20. Square source region high-density channels 17 are provided on the other two sides of the doped well region 7 away from the superjunction doped pillar region 13 and the strip-shaped Schottky contact region 20.

[0114] Specifically, such as Figure 26 As shown, Figure 24 A cross-sectional view at E2E2' showing electrodes includes an oxide layer 12 disposed on the doped well region 7, and a gate electrode 10, a source electrode 9, and a drain electrode 11 disposed within the oxide layer 12. The drain electrode 11 is disposed on the top layer of the doped drain region 4, with its top layer exposed above the oxide layer 12. The drain electrode 11 is in contact with the doped drain region 4, i.e., the drain electrode 11 and the top surface of the doped drain region 4 form an ohmic contact. The source electrode 9 is disposed on the top layer of the square doped source region 16 and the gate electrode 10, with its top layer exposed above the oxide layer 12. The source electrode 9 partially surrounds the gate electrode 10, and the two are separated by a portion of the oxide layer 12, without contact. The source electrode 9 is in contact with the square doped source region 16, i.e., the source electrode 9 and the top surface of the square doped source region 16 form an ohmic contact. While forming an ohmic contact with the square doped source region 16, the source electrode 9 forms a strip-shaped Schottky contact region 20 with the drift region 3 by etching a portion of the oxide layer 12, which is alternately arranged with the doped region units of the square doped source region 16. The gate electrode 10 is disposed on the top layer of the high-density channel 17 of the square source region and the square doped source region 16, and is separated by a portion of the oxide layer 12.

[0115] Specifically, such as Figure 27 As shown, in Figure 24 The cross-sectional view of E3E3' generated by the electrodes, and the detailed cross-sectional view of the device structure, also includes the oxide layer 12 on the doped well region 7, and the gate electrode 10 and source electrode 9 surrounded by the oxide layer 12. The source electrode 9 is disposed on the top layer of the square doped source region 16 and the gate electrode 10, and its top layer is exposed above the oxide layer 12. The source electrode 9 partially surrounds the gate electrode 10, and the two are separated by a portion of the oxide layer 12 and do not make contact. The source electrode 9 forms an ohmic contact with the top surface of the square doped source region 16.

[0116] Compared with Example 4, this example maintains the basic carrier flow path while keeping the effective high-density channel unchanged. By reducing the effective contact area between the gate and the source, the parasitic capacitance of the device is reduced, the charging and discharging time of the capacitor is reduced, thereby improving the application of the device in high frequency and high efficiency and reducing device losses.

[0117] Example 6:

[0118] See appendix Figures 29-34 This invention provides another type of high-channel-density MOSFET superjunction device, comprising a doped substrate 1, a doped structure 2, and a drift region 3 stacked sequentially from bottom to top, with the doped structure 2 connected to the doped substrate 1. The drift region 3 contains a superjunction doped pillar region 13, a doped drain region 4, and a doped well region 7. The doped well region 7 contains an interdigitated doped source region 15 and an interdigitated source region high-density channel 18. The interdigitated doped source region 15 and the doped drain region 4 are located on opposite sides of the drift region 3, and the superjunction doped pillar region 13 is located between the interdigitated doped source region 15 and the doped drain region 4. The interdigitated doped source region 15 has a channel along the width direction of the doped substrate 1 on the side away from the superjunction doped pillar region 13. This channel is the interdigitated source region high-density channel 18. Between the doped units of adjacent interdigitated doped source regions 15, part of the oxide layer 12 is removed by etching, forming an ohmic contact between the source electrode 9 and the drift region 3, and the doped units of the interdigitated doped source regions 15 are arranged between each other. The interdigitated source region high-density channel 18 is generated in other planar directions except for contact with the superjunction doped pillar region 13. The interdigitated source region high-density channel 18 is above the doped well region 7, has a width smaller than the doped well region 7, and does not contact the superjunction doped pillar region 13.

[0119] like Figure 31 As shown, Figure 31 for Figure 29 A cross-sectional view along F1F1' with electrodes includes an oxide layer 12 disposed on the doped well region 7, and a gate electrode 10, a source electrode 9, and a drain electrode 11 disposed within the oxide layer 12. The drain electrode 11 is disposed on the top layer of the doped drain region 4, with its top layer exposed above the oxide layer 12. The drain electrode 11 is in contact with the doped drain region 4, i.e., the drain electrode 11 and the top surface of the doped drain region 4 form an ohmic contact. The source electrode 9 is disposed on the top layer of the interdigitated doped source region 15 and the gate electrode 10, with its top layer exposed above the oxide layer 12. The source electrode 9 partially surrounds the gate electrode 10, and the two are separated by a portion of the oxide layer 12, without contact. The source electrode 9 is in contact with the interdigitated doped source region 15, i.e., the source electrode 9 and the top surface of the interdigitated doped source region 15 form an ohmic contact. The gate electrode 10 is disposed on the top layer of the channel and drift region 3, and is separated by a portion of the oxide layer 12.

[0120] like Figure 33 As shown, Figure 33 for Figure 29 The cross-sectional view showing the electrode at F3F3' should also include a detailed cross-sectional view of the device structure, including the oxide layer 12 on the doped well region 7, and the gate electrode 10 and source electrode 9 surrounded by the oxide layer 12. The source electrode 9 is disposed on the top layer of the interdigitated doped source region 15 and the gate electrode 10, with its top layer exposed above the oxide layer 12. The source electrode 9 partially surrounds the gate electrode 10, and the two are separated by a portion of the oxide layer 12, without contact. The source electrode 9 forms an ohmic contact with the top surface of the interdigitated doped source region 15.

[0121] Compared with Example 2, this example increases the channel density of the device within the same doped unit by increasing the area of ​​the conductive channel, thereby reducing device losses during operation.

[0122] Compared with Example 1, this example improves the traditional top compensation region 5 by directly contacting the improved superjunction doped pillar region 13 with the doped well region 7 to alleviate the electric field concentration effect, enhance the lateral depletion capability of the drift region, and make the electric field distribution more uniform. By optimizing the source region structure of the device, the device can increase the channel density, reduce the channel resistance, and improve the current transport capability of the channel in the same doped unit.

[0123] Example 7:

[0124] See appendix Figures 35-39 This invention provides a high-channel-density MOSFET superjunction device with a distributed integrated SBD, comprising a doped substrate 1, a doped structure 2, and a drift region 3 stacked sequentially from bottom to top, wherein the doped structure 2 and the doped substrate 1 are connected; the drift region 3 contains a superjunction doped pillar region 13, a doped drain region 4, and a doped well region 7, and the doped well region 7 contains an interdigitated doped source region 15 and an interdigitated source region high-density channel 18. The interdigitated doped source region 15 and the doped drain region 4 are located on opposite sides of the drift region 3, and the superjunction doped pillar region 13 is located between the interdigitated doped source region 15 and the doped drain region 4. A channel along the width of the doped substrate 1 is formed on the side of the interdigitated doped source region 15 away from the superjunction doped pillar region 13. This channel is a high-density interdigitated source region channel 18. Between the doped units of adjacent interdigitated doped source regions 15, part of the oxide layer 12 is removed by etching. At the same time as forming an ohmic contact between the source electrode 9 and the drift region 3, a distributed Schottky contact region 14 is formed, which is arranged between the doped units of the interdigitated doped source region 15. After receiving a positive voltage turn-on signal, the gate attracts electrons in the doped well region 7 to form a channel, and then forms an inversion layer. The high-density interdigitated source region channel 18 is generated in the planar directions other than the contact with the superjunction doped pillar region 13. The high-density interdigitated source region channel 18 is above the doped well region 7, has a width smaller than the doped well region 7, and does not contact the superjunction doped pillar region 13.

[0125] like Figure 36 As shown, Figure 36 for Figure 35 A schematic diagram of the structure with electrodes along the G1G1' cross section includes an oxide layer 12 disposed on the doped well region 7, and a gate electrode 10, a source electrode 9, and a drain electrode 11 disposed within the oxide layer 12. The drain electrode 11 is disposed on the top layer of the doped drain region 4, with its top layer exposed above the oxide layer 12. The drain electrode 11 is in contact with the doped drain region 4, i.e., the drain electrode 11 and the top surface of the doped drain region 4 form an ohmic contact. The source electrode 9 is disposed on the top layer of the interdigitated doped source region 15 and the gate electrode 10, with its top layer exposed above the oxide layer 12. The source electrode 9 partially surrounds the gate electrode 10, and the two are separated by a portion of the oxide layer 12, without contact. The source electrode 9 forms an ohmic contact with the top surface of the interdigitated doped source region 15. The gate electrode 10 is disposed on the top layer of the channel and drift region 3, and is separated by a portion of the oxide layer 12.

[0126] like Figure 37 As shown, Figure 37 for Figure 35 A cross-sectional view along G2G2' with electrodes includes an oxide layer 12 disposed on the doped well region 7, and a gate electrode 10, a source electrode 9, and a drain electrode 11 disposed within the oxide layer 12. The drain electrode 11 is disposed on the top layer of the doped drain region 4, and its top layer is exposed above the oxide layer 12. The drain electrode 11 is in contact with the doped drain region 4, i.e., the drain electrode 11 and the top surface of the doped drain region 4 form an ohmic contact. The source electrode 9 is disposed on the top layer of the interdigitated doped source region 15 and the gate electrode 10, and its top layer is exposed above the oxide layer 12. The source electrode 9 partially surrounds the gate electrode 10, and the two are separated by a portion of the oxide layer 12 and do not contact each other. The source electrode 9 is in contact with the interdigitated doped source region 15, i.e., the source electrode 9 and the top surface of the interdigitated doped source region 15 form an ohmic contact. The source electrode 9 directly contacts a portion of the drift region 3 through etching the oxide layer 12, forming a distributed Schottky contact region 14. The gate electrode 10 is disposed on the top layer of the channel and the drift region 3 and is separated by a portion of the oxide layer 12. Unlike the section along G1G1', since the doped well region 7 is not in direct contact with the superjunction doped pillar region 13 along the direction perpendicular to the drain, there is an interdigitated source region high-density channel 18 along the G3G3' direction.

[0127] like Figure 38 As shown, Figure 38 for Figure 35Cross-sectional view at G3G3'. In the above embodiment, the high-density channel of the interdigitated source region maintains a strictly consistent geometric configuration in each stepped unit, especially along the current transmission path, where the channel width is precisely the same and uniformly distributed. This highly consistent width design helps ensure that the current is uniformly distributed throughout the entire channel region during conduction, effectively avoiding current congestion and electric field concentration caused by local width differences.

[0128] like Figure 39 As shown, Figure 39 for Figure 35 A top view. In the above embodiment, a high-density channel structure with a stepped, periodically spaced arrangement surrounds and tightly encloses the doped well regions 7, which are also arranged in a stepped, continuous pattern. This carefully designed stepped, periodically spaced channel layout significantly improves the channel density by optimizing the channel distribution density per unit area, reducing channel resistance and thus effectively reducing the on-resistance of the device, thereby improving the overall electrical performance of the device.

[0129] The interdigitated doped source region 15 is composed of various doped units, which are periodically arranged along the G3G3' direction, and adjacent doped units are directly connected. Each doped unit has a T-shaped cross-section, including a first arm and a second arm that are perpendicular to each other. The first arm is positioned along the G3G3' direction and connected to the first arm of the adjacent doped unit, lying on the same straight line. The second arm is connected to the center point of the first arm and extends towards the G1G1' direction. The second arms of each doped unit are arranged parallel to each other and are spaced apart. The thickness of the second arm of each doped unit is the same as the thickness of the first arm and is not connected to the drift region 3. Preferably, the width of the second arm of each doped unit is the same. The doped well region 7 surrounding the second arm of each doped unit forms a channel around the interdigitated doped source region 15, and is positioned above the doped well region 7, forming the interdigitated source region high-density channel 18. The interdigitated source region high-density channel 18 has the same width surrounding the second arm portion of each doped region unit. The distributed Schottky contact region 14 exists between adjacent second arm source region doped units and is formed by the contact between the source electrode 9 and the drift region 3. Its width is lower than that of the doped well region 7 and it is arranged periodically.

[0130] The difference from Example 1 lies in the following: By improving the traditional top compensation region 5 and directly connecting it to the doped well region, and by optimizing the relationship between doping concentration and doping thickness, the breakdown voltage of the device is improved. By optimizing the stepped source region, compared with the traditional unidirectional channel, the effective channel area is increased, the channel resistance is reduced, and the current transport capability of the channel is improved. When the parasitic body diode in the traditional MOSFET is turned on, since both types of charge carriers participate in conduction, minority carriers are stored in the device, generating a huge reverse recovery current and requiring a long reverse recovery time, resulting in severe switching losses and voltage spikes. By introducing the distributed Schottky contact region 14, the tail current generated by the minority carrier stored charge when the device is turned off will be replaced by the body diode, thereby reducing switching losses.

[0131] Example 8:

[0132] See appendix Figures 40-44 This invention provides another MOSFET superjunction device with integrated SBD and high channel density, comprising a doped substrate 1, a doped structure 2, and a drift region 3 stacked sequentially from bottom to top, with the doped structure 2 connected to the doped substrate 1; a superjunction doped pillar region 13, a doped drain region 4, and a doped well region 7 are disposed within the drift region 3, and an interdigitated doped source region 15 and an interdigitated source region high-density channel 18 are disposed within the doped well region 7. The interdigitated doped source region 15 and the doped drain region 4 are located on opposite sides of the drift region 3, and the superjunction doped pillar region 13 is located between the interdigitated doped source region 15 and the doped drain region 4. The interdigitated doped source region 15 has a channel along the width direction of the doped substrate 1 on the side away from the superjunction doped pillar region 13. This channel is a high-density channel 18 for the interdigitated source region. Between the doped units of adjacent interdigitated doped source regions 15, part of the oxide layer 12 is removed by etching. While the source electrode 9 and the drift region 3 form an ohmic contact, the position of the Schottky contact region is defined by photolithography. The ion doping concentration at a specific position of the drift region 3 is changed and etched to form a distributed Schottky contact region 14 and a strip Schottky contact region 20. The distributed Schottky contact region 14 is located above the drift region 3. The strip Schottky contact region 20 is located on the vertical side of the interdigitated doped source region 15 and above the drift region 3 between the doped well regions 7 of each doped unit. After receiving a positive voltage turn-on signal, the gate attracts electrons in the doped well region 7 to form a conductive channel. Interdigitated high-density source channels 18 are generated in other planar directions except for contact with the superjunction doped pillar region 13. The interdigitated high-density source channels 18 are above the doped well region 7, with a width smaller than the doped well region 7, and do not contact the superjunction doped pillar region 13.

[0133] Specifically, such as Figure 41 As shown, Figure 41 for Figure 40A cross-sectional view along the H1H1' section showing electrodes includes an oxide layer 12 disposed on the doped well region 7, and a gate electrode 10, a source electrode 9, and a drain electrode 11 disposed within the oxide layer 12. The drain electrode 11 is disposed on the top layer of the doped drain region 4, with its top layer exposed above the oxide layer 12. The drain electrode 11 is in contact with the doped drain region 4, forming an ohmic contact with the top surface of the doped drain region 4. The source electrode 9 is disposed on the top layer of the interdigitated doped source region 15 and the gate electrode 10, with its top layer exposed above the oxide layer 12. The source electrode 9 partially surrounds the gate electrode 10, and the two are separated by a portion of the oxide layer 12, without contact. The source electrode 9 is in contact with the interdigitated doped source region 15, forming an ohmic contact with the top surface of the interdigitated doped source region 15. Simultaneously, the source electrode 9 forms a Schottky contact by contacting a portion of the drift region treated by an etching technique, forming a distributed Schottky contact region 14 and a strip-shaped Schottky contact region 20. The gate electrode 10 is disposed on the top layer of the channel and drift region 3 and is spaced by a portion of the oxide layer 12.

[0134] The difference from Example 1 lies in the improvement of the traditional top compensation region 5, forming a superjunction doped pillar region 13. Through the superjunction structure, the electric field distribution is optimized in both the lateral and longitudinal directions of the device, significantly increasing the breakdown voltage and giving the device better withstand voltage capability. By optimizing the source region structure, the device can increase the channel density within the same doped unit, increasing the effective channel density and reducing the channel resistance compared to traditional single-direction channels, thus improving the channel's current transport capability. Since the bipolar injection of electrons and holes during the operation of the body diode causes a drift in the forward voltage drop, leading to increased on-resistance, and the presence of minority carriers stored in the device results in a large reverse recovery current during device turn-off, increasing switching losses and posing a risk of device performance degradation and long-term reliability decline, the formed Schottky contact region replaces the body diode, enabling earlier turn-on in the third quadrant and eliminating reverse recovery charge during device turn-off, significantly reducing switching losses and improving system efficiency.

[0135] The difference from Example 4 is that, within the same doped cells, this embodiment has a higher channel density, meaning that in a device of the same area, it has a lower on-resistance and can support a larger current. This significantly improves the device's power density and current capability.

[0136] The difference from Example 7 lies in the increased area of ​​the Schottky contact within the same area. By increasing the proportion of the Schottky contact in the source region, a wider unipolar conductive channel can be constructed, which further reduces the reverse conduction voltage drop and fundamentally suppresses the bipolar degradation effect of the body diode. The larger area of ​​the Schottky contact provides a more efficient unipolar carrier transport path, thereby further reducing switching losses.

[0137] This embodiment simultaneously achieves three major optimizations: it increases the number of conductive channels during forward conduction, thereby reducing the device's on-resistance; during reverse freewheeling, it reduces reverse recovery loss through a larger Schottky contact area; and by optimizing the thickness and density of the superjunction pillar region, it significantly improves the device's breakdown voltage and enhances its high-frequency characteristics and reliability. This final embodiment represents the optimal implementation of the invention in terms of overall performance.

[0138] It should be noted that:

[0139] The phrase "an embodiment" or "an embodiment" used in this specification means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of this application. Therefore, the phrase "an embodiment" or "an embodiment" appearing in various places throughout the specification does not necessarily refer to the same embodiment.

[0140] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0141] Furthermore, it should be noted that the shapes and names of the parts and components described in the specific embodiments described in this specification may differ. All equivalent or simple variations made to the structure, features, and principles described in this application are included within the scope of protection of this application. Those skilled in the art to which this application pertains may make various modifications or additions to the described specific embodiments or use similar methods to substitute them, as long as they do not deviate from the structure of this application or exceed the scope defined by the claims, all of which should fall within the scope of protection of this application.

Claims

1. A superjunction lateral MOSFET device integrating a Schottky diode, characterized in that, include: Doped substrate (1) and doped structure (2) connected thereto; The drift region (3) located on the doped structure (2); The doped well region (7) and the doped drain region (4) are located within the drift region (3); Multiple doped source units located within the doped well region (7) and arranged periodically, each unit having a closed geometry; A gate electrode (10) is disposed on the top layer of the doped well region (7) and the drift region (3) to control the formation of a surrounding channel region (8) in the doped well region (7) on the periphery of the doped source region unit; The superjunction doped pillar region (13) is located between the doped source region unit and the doped drain region (4), and is in direct contact with the doped well region (7); Distributed Schottky contact regions (14) are disposed in the gaps between adjacent doped source units; An oxide layer (12) is disposed on the doped well region (7) and surrounds the gate electrode (10); The source electrode (9) and drain electrode (11) are exposed above the oxide layer (12).

2. The superjunction lateral MOSFET device with integrated Schottky diode according to claim 1, characterized in that, The doped well regions (7) around the doped source region unit cooperate with each other to make the channel region (8) have a three-dimensional surrounding layout, so as to form an effective channel width that conducts in parallel in multiple directions within a unit chip area.

3. The superjunction lateral MOSFET device with integrated Schottky diode according to claim 1, characterized in that, The doped source region unit is a square doped source region (16). Multiple square doped source regions (16) are arranged at intervals along the width direction of the doped substrate (1), and adjacent units are electrically connected through conductive structures. The doped well region (7) around each square unit forms a semi-enclosed channel segment, forming a high-density channel (17) of the square source region.

4. The superjunction lateral MOSFET device with integrated Schottky diode according to claim 1, characterized in that, The doped source region unit is an interdigitated doped source region (15), which has a T-shaped cross-section and includes a first arm and a second arm that are perpendicular to each other. The first arm is arranged along the width direction and connected to the first arm of the adjacent unit. The second arm extends from the center point of the first arm in a direction parallel to the doped drain region (4), and the second arms of each unit maintain a set spacing to define the channel region.

5. The superjunction lateral MOSFET device with integrated Schottky diode according to any one of claims 1-4, characterized in that, The gate electrode (10) adopts a planar gate structure or a shielded gate structure; wherein, when a shielded gate structure is adopted, the shielded gate is used to reduce the conduction loss of the device and improve the switching speed.

6. The superjunction lateral MOSFET device with integrated Schottky diode according to claim 1, characterized in that, The structure of the distributed Schottky contact region (14) is as follows: a portion of the oxide layer (12) is removed between adjacent doped source region units to expose the drift region (3), and a Schottky contact is formed by extending and covering the exposed drift region through the source electrode (9); the distributed Schottky contact region (14) and the doped source region units are arranged alternately.

7. The superjunction lateral MOSFET device with integrated Schottky diode according to claim 6, characterized in that, Also includes: The T-type Schottky contact region (19) is formed by etching away the oxide layer (12) between adjacent doped source units and exposing the underlying drift region (3), and the source electrode (9) simultaneously forms an ohmic contact with the doped source unit and a Schottky contact with the exposed drift region.

8. The superjunction lateral MOSFET device with integrated Schottky diode according to claim 6, characterized in that, Also includes: A strip-shaped Schottky contact region (20) is disposed around the source electrode in a direction parallel to the doped drain region (4), so that the source electrode (9) and the drift region (3) are in direct contact to form a strip-shaped region with uniform width, which is used to further suppress reverse recovery loss.

9. The superjunction lateral MOSFET device with integrated Schottky diode according to claim 1, characterized in that, The source electrode (9) partially surrounds the gate electrode (10) and the two are insulated and isolated by the oxide layer (12). The source electrode (9) is electrically connected to the doped source unit and the Schottky contact region through the opening of the oxide layer (12).

10. The superjunction lateral MOSFET device with integrated Schottky diode according to claim 1, characterized in that, The entire device is made of silicon carbide material; The doped drain region (4), the doped source region unit, and the drift region (3) are all doped with nitrogen. The doped well region (7), the doped substrate (1), the doped structure (2), and the superjunction doped pillar region (13) are all doped with aluminum.

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