A display panel and display device

Abstract

Embodiments of the present application provide a display panel and a display device, the display panel comprising a substrate, a first metal layer, a first insulating layer, a second metal layer and a second insulating layer; the second metal layer comprises a first drain of a first thin film transistor, a second plate of a first capacitor and a second source of a second thin film transistor, and the second plate is electrically connected with the first drain of the first thin film transistor; the first insulating layer is defined with a first via hole and a second via hole, the first drain of the first thin film transistor is connected with the first metal layer through the first via hole, and the first metal layer is electrically connected with the second source of the second thin film transistor through the second via hole. According to the technology of the present application, the first insulating layer and the second insulating layer between the second plate and the second thin film transistor are partially attached, so as to form a channel with higher density, and ensure that the second thin film transistor is not affected by moisture of the first capacitor in the noise reduction process.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] In display products, high refresh rates are commonly used for audio-visual entertainment and gaming to ensure smooth and stable visuals, while low refresh rates are used in low-power scenarios such as office work to extend battery life and reduce energy consumption. These two approaches contradict each other in terms of power consumption. To simultaneously meet the demands of high refresh rates and low power consumption, the Dynamic Display technology was proposed. Dynamic Display technology is a technique that allows for the compatibility of high and low refresh rates within the same screen. Specifically, it enables a high refresh rate in the video playback area to ensure smooth and stable visuals, while a low refresh rate in the background area reduces power consumption. To achieve this, the gate clock signal CLK and the cascade clock signal CLKC control the display area output and the GOA cascade, respectively. Capacitors need to be placed on the M11 transistor to ensure that the input of only the cascade clock signal CLKC can achieve the bootstrapping of the pull-up node (PUc), guaranteeing that the M11 transistor fully opens the cascade output signal (outC) and outputs it stably.

[0003] However, in related technologies, the second source of the second thin-film transistor is directly connected through a capacitor. The capacitor's plates are bonded to the insulating layer. The capacitor is made of metal, and the contact interface between the metal and the insulating layer has poor density, which easily forms a moisture intrusion channel. Furthermore, the coverage of the second insulating layer is relatively large, and the edge coverage of the second insulating layer is poor. There are gaps between the insulating layer and the capacitor, which easily allow moisture to enter through the gaps between the capacitor and the second insulating layer and corrode the M12 transistor. Summary of the Invention

[0004] This application provides a display panel and a display device to solve or alleviate one or more technical problems in the prior art.

[0005] As one aspect of the embodiments of this application, this application provides a display panel, which includes:

[0006] Substrate;

[0007] A first metal layer is disposed on one side of a substrate and includes the first electrode plate of a first capacitor;

[0008] A first insulating layer is disposed on the side of the first metal layer away from the substrate.

[0009] The second metal layer is disposed on the side of the first insulating layer away from the substrate, and includes the first drain of the first thin film transistor, the second electrode of the first capacitor, and the second source of the second thin film transistor. The second electrode is electrically connected to the first drain of the first thin film transistor.

[0010] The second insulating layer is disposed on the side of the second metal layer away from the substrate and part of its structure covers the first insulating layer;

[0011] The first thin-film transistor is configured to output a cascaded output signal, and the second thin-film transistor is configured to reduce noise in the cascaded output signal. A first via and a second via are defined on the first insulating layer. The first drain of the first thin-film transistor is connected to the first metal layer through the first via, and the first metal layer is electrically connected to the second source of the second thin-film transistor through the second via.

[0012] In some embodiments, the display panel has a display area and a non-display area surrounding the display area, and a first capacitor is located on the side of the first thin-film transistor adjacent to the display area.

[0013] In some embodiments, the orthographic projection of the first via on the substrate is located on the side of the first thin-film transistor on the substrate adjacent to the orthographic projection of the second thin-film transistor, and the orthographic projection of the second via on the substrate is located on the side of the second thin-film transistor on the substrate adjacent to the orthographic projection of the first thin-film transistor.

[0014] In some embodiments, the first via and the second via are arranged alternately along the length of the display panel.

[0015] In some embodiments, the second electrode extends along the width direction of the display panel, and the first metal layer extends along the length direction of the display panel.

[0016] In some embodiments, the orthographic projection of the first capacitor on the substrate is located on the side of the orthographic projection of the first thin-film transistor on the substrate adjacent to the second thin-film transistor.

[0017] In some embodiments, the orthographic projection of the first via on the substrate is located on the side of the orthographic projection of the first thin-film transistor on the substrate that is away from the second thin-film transistor.

[0018] In some embodiments, the first thin-film transistor has a first side away from the second thin-film transistor and a second side adjacent to the second thin-film transistor. A first via is located near the first side of the first thin-film transistor. One end of the first metal layer is connected to the first via, and the other end surrounds the first and second sides and is connected to the second via.

[0019] In some embodiments, the second electrode and the second thin-film transistor are arranged alternately along the length of the display panel.

[0020] In some embodiments, the distance between the first thin-film transistor and the edge of the display area is smaller than the distance between the second thin-film transistor and the edge of the display area.

[0021] In some embodiments, the orthographic projection of the first capacitor on the substrate is located on the side of the orthographic projection of the first metal layer on the substrate adjacent to the display area, and the orthographic projection of the second thin-film transistor on the substrate is located on the side of the orthographic projection of the first metal layer on the substrate away from the display area.

[0022] As another aspect of this application, a display device is also provided, which includes a display panel as described in any of the preceding embodiments.

[0023] The embodiments of this application have the following beneficial effects:

[0024] According to the technology of this application, by defining a first via and a second via on the first insulating layer, the first drain of the first thin-film transistor is connected to the first metal layer through the first via, and then the first metal layer is connected to the second source of the second thin-film transistor through the second via. This replaces the direct metal connection between the second plate of the first capacitor and the second thin-film transistor in related technologies. With this configuration, the second insulating layer is disposed on the side of the second metal layer away from the substrate and part of the structure covers the first insulating layer, so that the first insulating layer and the second insulating layer part of the first insulating layer are attached to the second plate of the first capacitor and the second thin-film transistor, thereby forming a channel with a higher degree of density. This effectively blocks the transmission of moisture from the first capacitor to the second thin-film transistor, ensuring that the performance of the second thin-film transistor during the noise reduction process is not affected by the moisture in the first capacitor. Secondly, this application further extends the transmission path between the second plate of the first capacitor and the second source of the second thin film transistor by defining a first via and a second via on the first insulating layer, thereby extending the transmission distance of water vapor to the second thin film transistor, and further ensuring that the performance of the second thin film transistor during the noise reduction process is not affected by the water vapor in the first capacitor.

[0025] The above overview is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of this application will become readily apparent from the accompanying drawings and the following detailed description. Attached Figure Description

[0026] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0027] Figure 1 A cross-sectional view of a display panel in the related art is shown;

[0028] Figure 2 The circuit diagram of 18T1C (i.e., including 18 transistors and 1 capacitor) is shown;

[0029] Figure 3 A schematic diagram of the planar layout of an 18T1C (i.e., including 18 transistors and 1 capacitor) is shown.

[0030] Figure 4 The circuit diagram of a 32T2C (i.e., including 32 transistors and 2 capacitors) is shown.

[0031] Figure 5 A schematic diagram of a planar layout of a 32T2C (i.e., including 32 transistors and 2 capacitors) is shown.

[0032] Figure 6 A cross-sectional view of the display panel of this application is shown;

[0033] Figure 7 A schematic planar layout diagram (18T1C) of the first embodiment of this application is shown.

[0034] Figure 8 A schematic planar layout diagram (32T2C) of the first embodiment of this application is shown.

[0035] Explanation of reference numerals in the attached figures:

[0036] 1. Display panel;

[0037] 10. First metal layer; 11. First part; 12. Second part;

[0038] 20. First insulating layer; 21. First via; 22. Second via;

[0039] 30. Second metal layer; 31. First thin-film transistor; 311. First drain; 32. Second thin-film transistor; 321. Second source;

[0040] 40. Second insulating layer;

[0041] 50. The third thin-film transistor;

[0042] 60. First capacitor; 61. First plate; 62. Second plate;

[0043] AA, display area; B, non-display area.

[0044] 10', First metal layer;

[0045] 20', First insulating layer;

[0046] 30', Second metal layer;

[0047] 40', Second insulation layer;

[0048] 50', capacitor;

[0049] 60', M11 transistor;

[0050] 70', M12 transistor. Detailed Implementation

[0051] In the following description, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of this application. Therefore, the drawings and description are considered to be exemplary in nature and not restrictive.

[0052] In display products, high refresh rates are commonly used for audio-visual entertainment and gaming to ensure smooth and stable visuals, while low refresh rates are used in low-power scenarios such as office work to extend battery life and reduce energy consumption. These two approaches contradict each other in terms of power consumption. To simultaneously meet the demands of high refresh rates and low power consumption, the Dynamic Display technology was proposed. Dynamic Display technology is a technique that allows for both high and low refresh rates within the same screen. Specifically, it enables a high refresh rate in the video playback area to ensure smooth and stable visuals, while a low refresh rate in the background area reduces power consumption. To achieve this, the gate clock signal CLK and the cascade clock signal CLKC control the display area output and the GOA cascade, respectively. Capacitors need to be placed on the M11 transistor 60' to ensure that the input of only the cascade clock signal CLKC can achieve bootstrapping of the pull-up node (PUc), guaranteeing that the M11 transistor 60' fully opens the cascade output signal (outC) and outputs it stably.

[0053] In the GOA circuit design of the related technology, one of the plates of the capacitor above the M11 transistor 60' is directly connected to the source of the M12 transistor 70' which is responsible for noise reduction in the GOA circuit to achieve signal transmission. However, this structure has obvious defects: due to the large metal step difference at the edge of the capacitor and the poor coverage morphology of the second insulating layer, the interface between the second insulating layer and the capacitor plate is not dense, which easily forms a weak channel for water vapor intrusion.

[0054] As a noise reduction transistor in GOA circuit design, the M12 transistor 70' has a small channel width (typically W≤20), weak current surge resistance, and its gate (PD) is in a high-level operating state for a long time, making it extremely sensitive to moisture interference. In high-temperature and high-humidity reliability environments, external moisture penetrates into the film layer along the weak channels at the capacitor edge and is rapidly transported to the M12 transistor 70' through the gap between the second insulating layer and the capacitor plates. Under the combined effect of moisture and operating current, the M12 transistor 70' is prone to conductor formation and channel corrosion, leading to abnormal output and reliability failure of the GOA circuit.

[0055] Figure 1 A cross-sectional view of a display panel in the related art is shown; Figure 2 The circuit diagram of 18T1C (i.e., including 18 transistors and 1 capacitor) is shown; Figure 3 A schematic diagram of the planar layout of an 18T1C (i.e., including 18 transistors and 1 capacitor) is shown. Figure 4 The circuit diagram of a 32T2C (i.e., including 32 transistors and 2 capacitors) is shown. Figure 5 This diagram shows a planar layout of a 32T2C (i.e., including 32 transistors and 2 capacitors). For details, see [link to relevant documentation]. Figures 1 to 5 In the GOA circuit design of related technologies, the display panel includes a first metal layer 10', a first insulating layer 20', a second metal layer 30', and a second insulating layer 40'. The second metal layer 30' includes the drain of an M11 transistor 60', the source of an M12 thin-film transistor 70', and one of the plates of a capacitor. The first insulating layer 20' is disposed on one side of the first metal layer 10', the second metal layer 30' is disposed on the side of the first insulating layer 20' away from the first metal layer 10', and the second insulating layer 40' is disposed on the side of the second metal layer 30' away from the first metal layer 10'. On one side, the capacitor is made of metal. Direct contact between the metal and the second insulating layer 40' presents a technical problem of low density. Furthermore, the coverage gap of the second insulating layer 40' is large, its edge coverage is poor, and there are gaps between the second insulating layer 40' and the second metal layer 30'. This allows moisture to easily intrude through these gaps, eroding the second thin-film transistor (TFT) and ultimately causing the M12 TFT 70' to fail. Current GOA circuit designs in related technologies focus only on implementing the dynamic display driving function and do not optimize the moisture intrusion path and transmission distance introduced by the capacitor. Therefore, they cannot effectively suppress the impact of moisture on the M12 TFT 70' under high temperature and high humidity conditions.

[0056] See in some examples Figures 1 to 3In the 18T1C circuit structure (i.e., including 18 transistors and 1 capacitor), the black dashed line represents the connection path between the capacitor and transistor M12 70'. See other examples. Figure 1 , Figure 4 as well as Figure 5 The M12 transistor 70' is directly connected to the capacitor, as shown by the black dashed line. In the two exemplary circuit structures described above, the capacitors are made of metal. Direct contact between the metal and the second insulating layer 40' presents a technical problem of low density. Furthermore, the coverage gap of the second insulating layer 40' is large, the edge coverage of the second insulating layer 40' is poor, and there are gaps between the second insulating layer 40' and the second metal layer 30'. This allows moisture to easily intrude through these gaps, eroding the second thin-film transistor and causing it to fail. The GOA circuit design in related technologies only focuses on the implementation of the dynamic display driving function and does not optimize the moisture intrusion path and transmission distance introduced by the capacitor, thus failing to effectively suppress the impact of moisture on the M12 transistor 70' under high temperature and high humidity conditions.

[0057] To address the aforementioned technical problems, this application provides a display panel 1, which has a second insulating layer 40 disposed on the side of the second metal layer 30 away from the substrate and partially covers the first insulating layer 20. This allows the first insulating layer 20 and the second insulating layer 40 to partially adhere to each other between the second electrode 62 of the first capacitor 60 and the second thin-film transistor 32, thereby forming a more dense channel. This effectively blocks moisture entering from the first capacitor 60 from being transmitted to the second thin-film transistor 32, ensuring that the performance of the second thin-film transistor 32 during the noise reduction process is not affected by the moisture in the first capacitor 60.

[0058] The specific implementation methods of the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0059] Figure 6 A cross-sectional view of the display panel 1 of this application is shown; Figure 7 A schematic planar layout diagram (18T1C) of the first embodiment of this application is shown. Figure 8 A schematic planar layout diagram (32T2C) of the first embodiment of this application is shown.

[0060] Specifically, see Figures 1 to 8 The display panel 1 provided in this application embodiment includes a substrate, a first metal layer 10, a first insulating layer 20, a second metal layer 30, and a second insulating layer 40.

[0061] The first metal layer 10 is disposed on one side of the substrate, and the first metal layer 10 includes the first electrode 61 of the first capacitor 60.

[0062] The first insulating layer 20 is disposed on the side of the first metal layer 10 away from the substrate.

[0063] The second metal layer 30 is disposed on the side of the first insulating layer 20 away from the substrate. The second metal layer 30 includes the first drain 311 of the first thin film transistor 31, the second electrode 62 of the first capacitor 60, and the second source 321 of the second thin film transistor 32. The second electrode 62 is electrically connected to the first drain 311 of the first thin film transistor 31.

[0064] The second insulating layer 40 is disposed on the side of the second metal layer 30 away from the substrate and partially covers the first insulating layer 20.

[0065] In some examples, the first insulating layer 20 and the second insulating layer 40 can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be single-layer, multi-layer, or composite layers. For example, the first insulating layer 20 is silicon oxide, and the second insulating layer 40 is silicon nitride. Silicon oxide and silicon nitride are both silicon-based covalently bonded dielectric materials, with compatible atomic arrangements and chemical properties. That is, the interface density and resistance to water vapor penetration of the silicon oxide and silicon nitride bonding are stronger. Furthermore, silicon oxide and metal form a heterogeneous interface with different crystal structures, resulting in gaps at the interface. The size of these gaps is larger than the diameter of a water molecule, thus creating a continuous water vapor transport channel between the silicon oxide and metal. Under high temperature and humidity, water vapor can rapidly diffuse along these gaps. Therefore, this application effectively blocks the transport of water vapor entering from the first capacitor 60 to the second thin-film transistor 32 by combining silicon oxide and silicon nitride.

[0066] The first thin-film transistor 31 is configured to output a cascaded output signal, and the second thin-film transistor 32 is configured to reduce noise in the cascaded output signal. A first via 21 and a second via 22 are defined on the first insulating layer 20. The second electrode 62 is connected to the first metal layer 10 via the first via 21 after passing through the first drain 311 of the first thin-film transistor 31. The first metal layer 10 is electrically connected to the second source 321 of the second thin-film transistor 32 via the second via 22. Exemplarily, the first metal layer 10 further includes a metal portion. The second electrode 62 is connected to the metal portion of the first metal layer 10 via the first via 21 after passing through the first drain 311 of the first thin-film transistor 31. The metal portion is electrically connected to the second source 321 of the second thin-film transistor 32 via the second via 22.

[0067] Specifically, such as Figure 6As shown, the second plate 62 of the first capacitor 60 is located to the left of the first drain 311 of the first thin film transistor 31. The water vapor entering the second plate 62 of the first capacitor 60 passes through the first drain 311 of the first thin film transistor 31 and is blocked by the bonding portion of the first insulating layer 20 and the second insulating layer 40 between the first thin film transistor 31 and the second thin film transistor 32.

[0068] The first thin-film transistor 31 is the output transistor in the gate on array (GOA) circuit and is configured to generate a cascaded output signal (OutC) during gate driving. To ensure that the driving capability is maintained even when the gate clock signal CLK is paused, a first capacitor 60 is added to the first thin-film transistor 31. The bootstrap function of the capacitor increases the gate voltage, enabling the first thin-film transistor 31 to be fully turned on.

[0069] The second thin-film transistor 32 is a noise reduction transistor in the gate drive circuit, used to suppress noise in the cascaded output signal (OutC). The second thin-film transistor 32 receives the cascaded output signal (OutC) from the first thin-film transistor 31 and filters it, thereby reducing or eliminating noise interference to the first thin-film transistor 31 and improving the purity of the signal output.

[0070] In the circuit of this application, the first thin-film transistor 31 is the output unit of the cascaded output signal (OutC), which, together with the bootstrap capacitor, ensures signal stability. The second thin-film transistor 32 is the noise reduction unit of the cascaded output signal (OutC), which improves image quality by stabilizing the cascaded output signal (OutC).

[0071] According to the embodiments of this application, compared with related technologies, the embodiments of this application define a first via 21 and a second via 22 on the first insulating layer 20. The second electrode 62 of the first capacitor 60 is connected to the first drain 311 of the first thin film transistor 31. The first drain 311 of the first thin film transistor 31 is connected to the first metal layer 10 through the first via 21, and then the first metal layer 10 is connected to the second source 321 of the second thin film transistor 32 through the second via 22. This replaces the direct metal connection between the second electrode of the first capacitor and the second thin film transistor in related technologies. Furthermore, the second insulating layer 40 is disposed on the side of the second metal layer 30 away from the substrate and partially covers the first insulating layer 20, so that the first insulating layer 20 and the second insulating layer 40 between the first thin film transistor 31 and the second thin film transistor 32 are partially attached, thereby forming a more dense channel. This effectively blocks the transmission of moisture entering from the first capacitor 60 to the second thin film transistor 32, ensuring that the performance of the second thin film transistor 32 during the noise reduction process is not affected by the moisture in the first capacitor 60. Secondly, this application further extends the transmission path between the second electrode 62 of the first capacitor 60 and the second source 321 of the second thin film transistor 32 by defining a first via 21 and a second via 22 on the first insulating layer 20. This extends the transmission distance of water vapor to the second thin film transistor 32, thereby further ensuring that the performance of the second thin film transistor 32 during the noise reduction process is not affected by the water vapor in the first capacitor 60.

[0072] In some embodiments, the distance between the first thin-film transistor 31 and the edge of the display area AA is smaller than the distance between the second thin-film transistor 32 and the edge of the display area AA. This configuration allows the first thin-film transistor 31, responsible for outputting cascaded signals, to be closer to the display area AA, effectively shortening the transmission path of the cascaded output signals to the scan drive of the display area AA and reducing signal transmission loss.

[0073] In some embodiments, the orthographic projection of the first capacitor 60 on the substrate is located on the side of the orthographic projection of the first metal layer 10 on the substrate adjacent to the display area AA, and the orthographic projection of the second thin-film transistor 32 on the substrate is located on the side of the orthographic projection of the first metal layer 10 on the substrate away from the display area AA. This configuration effectively extends the transmission path between the second electrode 62 of the first capacitor 60 and the second source 321 of the second thin-film transistor 32, thereby extending the transmission distance for moisture to reach the second thin-film transistor 32, and further ensuring that the performance of the second thin-film transistor 32 during noise reduction is not affected by moisture in the first capacitor 60.

[0074] In some embodiments, the driving circuit of this application is applied to a single-stage, single-drive circuit architecture.

[0075] For example, see Figure 2 For example, a shift register cell with an 18T1C circuit structure (i.e., including 18 transistors and 1 capacitor) is used, but it is not limited to this. The following example uses 18T1C:

[0076] In some embodiments, see Figure 2 , Figure 6 as well as Figure 7 The display panel also includes a third thin-film transistor 50, the third thin-film transistor 50 and the first thin-film transistor 31 share a first capacitor 60, the gate signals of the third thin-film transistor 50 and the first thin-film transistor 31 are shared, and the first thin-film transistor 31 and the third thin-film transistor 50 cooperate to drive the same group output signal (OutC).

[0077] In some embodiments, see Figure 6 and Figure 7 The display panel 1 has a display area AA and a non-display area B surrounding the display area AA. The first capacitor 60 is located on the side of the first thin-film transistor 31 adjacent to the display area AA. The proximity of the first capacitor 60 to the first thin-film transistor 31 can improve the stability of the gate bootstrap of the first thin-film transistor 31 and ensure reliable output of the cascaded output signal. Secondly, the large spacing between the first capacitor 60 and the second thin-film transistor 32 helps to reduce the interference of the electric field of the first capacitor 60 on the noise reduction function of the second thin-film transistor 32.

[0078] The non-display area B surrounds the display area AA and is located at the edge of the display panel 1. The non-display area B includes fan-out metal traces, bonding terminals, etc., and serves as the electrical connection channel between the display area AA and external circuitry.

[0079] According to the embodiments of this application, by placing the first capacitor 60 on the side of the first thin-film transistor 31 adjacent to the display area AA, the first capacitor 60 and the second thin-film transistor 32 can be physically further apart, thereby extending the path length of water vapor from the first capacitor 60 to the second thin-film transistor 32, effectively reducing the risk of water vapor eroding the second thin-film transistor 32, and further ensuring that the performance of the second thin-film transistor 32 during the noise reduction process is not affected by the water vapor of the first capacitor 60.

[0080] In some examples, the first thin-film transistor 31 and the second thin-film transistor 32 are staggered along the extension direction of the non-display area B. The first capacitor 60 is located on the side of the first thin-film transistor 31 adjacent to the display area AA. The first capacitor 60 extends along the extension direction of the non-display area B, that is, the extension direction of the first capacitor 60 is the same as the extension direction of the non-display area B. This reduces the space occupied by the first capacitor 60 in the width direction of the non-display area B, effectively avoiding the situation where the width of the non-display area B is excessively increased due to the lateral arrangement of the first capacitor 60. This arrangement, on the one hand, extends the path length of water vapor from the first capacitor 60 to the second thin-film transistor 32, effectively reducing the risk of water vapor corroding the second thin-film transistor 32 and improving the reliability of the display panel 1 in high temperature and high humidity environments. On the other hand, by extending the first capacitor 60 along the extension direction of the non-display area B, the space occupied by the first capacitor 60 in the width direction of the non-display area B is reduced, effectively avoiding the situation where the width of the non-display area B is excessively increased due to the lateral arrangement of the first capacitor 60, thus improving the space utilization rate of the non-display area B.

[0081] In some embodiments, see Figure 6 and Figure 7 The orthographic projection of the first via 21 on the substrate is located on the side of the first thin film transistor 31 on the substrate adjacent to the orthographic projection of the second thin film transistor 32, and the orthographic projection of the second via 22 on the substrate is located on the side of the second thin film transistor 32 on the substrate adjacent to the orthographic projection of the first thin film transistor 31.

[0082] In some embodiments, the first via 21 and the second via 22 are arranged sequentially at intervals along the length of the display panel 1.

[0083] In some examples, the first thin-film transistor 31 and the second thin-film transistor 32 are staggered in the width direction of the non-display area B, thereby forming a gap between the first thin-film transistor 31 and the second thin-film transistor 32 extending along the length direction of the non-display area B. The orthographic projection of the first via 21 on the substrate is located on the side of the first thin-film transistor 31 adjacent to the orthographic projection of the second thin-film transistor 32 on the substrate, and the first via 21 is located within the gap between the first thin-film transistor 31 and the second thin-film transistor 32. The orthographic projection of the second via 22 on the substrate is located on the side of the second thin-film transistor 32 adjacent to the orthographic projection of the first thin-film transistor 31 on the substrate, and the second via 22 is located within the gap between the first thin-film transistor 31 and the second thin-film transistor 32.

[0084] According to the embodiments of this application, the orthogonal projection of the first via 21 on the substrate is located on the side of the orthogonal projection of the first thin film transistor 31 on the substrate adjacent to the side of the second thin film transistor 32, and the orthogonal projection of the second via 22 on the substrate is located on the side of the orthogonal projection of the second thin film transistor 32 on the substrate adjacent to the side of the first thin film transistor 31. This allows the second plate 62 of the first capacitor 60 located near the display area AA of the first thin film transistor 31 to cross the first thin film transistor 31 along the width direction of the non-display area B and then be connected to the first metal layer 10 through the first via 21. Since both the first via 21 and the second via 22 are located in the gap between the first thin film transistor 31 and the second thin film transistor 32, when the first metal layer 10 is connected to the first via 21 and the second via 22, the first metal layer 10 extends along the length direction of the non-display area B, and at this time the length of the first metal layer 10 is the longest. This configuration extends the transmission distance of water vapor from the first capacitor 60 to the second thin-film transistor 32 without affecting the layout of the non-display area B, increases the water vapor blocking time, and utilizes the high density between the first insulating layer 20 and the second insulating layer 40 to change the water vapor intrusion channel, thereby improving the reliability of the display panel 1 under high temperature and high humidity conditions.

[0085] In some embodiments, the orthographic projection of the second electrode 62 onto the substrate at least partially overlaps with the orthographic projection of the first thin-film transistor 31 onto the substrate.

[0086] In some examples, the second electrode plate 62 of the first capacitor 60 located near the display area AA of the first thin film transistor 31 crosses the first thin film transistor 31 along the width direction of the non-display area B and is connected to the first metal layer 10 through the first via 21. As a result, the orthographic projection of the second electrode plate 62 on the substrate overlaps at least partially with the orthographic projection of the first thin film transistor 31 on the substrate, thereby making the layout of the non-display area B of the display panel 1 more compact and realizing the narrow bezel design of the non-display area B.

[0087] In some embodiments, see Figure 6 and Figure 7 The second electrode plate 62 extends along the width direction of the display panel 1, and the first metal layer 10 extends along the length direction of the display panel 1.

[0088] According to the embodiments of this application, by extending the second electrode plate 62 along the width direction of the display panel 1 and the first metal layer 10 along the length direction of the display panel 1, the path of water vapor intrusion into the second thin film transistor 32 of the first capacitor 60 can be effectively extended, increasing the water vapor barrier distance. Furthermore, the high density between the first insulating layer 20 and the second insulating layer 40 is used to change the water vapor intrusion channel, thereby improving the reliability of the display panel 1 under high temperature and high humidity conditions.

[0089] In other embodiments, the driving circuit of this application can also be applied to a single-level two-drive architecture. A single-level one-drive architecture refers to a single-level GOA drive unit driving one row of display pixels. A single-level two-drive architecture, on the other hand, refers to a single-level GOA drive unit driving two rows of display pixels.

[0090] For example, see Figure 4 For example, a shift register cell with a 32T2C circuit structure (i.e., including 32 transistors and 2 capacitors) is used, but it is not limited to this. The following example uses 32T2C as an example:

[0091] In some embodiments, see Figure 4 , Figure 6 as well as Figure 8 The display panel also includes a third thin-film transistor 50. The third thin-film transistor 50 and the first thin-film transistor 31 are set independently. The gate signals of the third thin-film transistor 50 and the first thin-film transistor 31 are not shared. The second plate 62 of the first capacitor 60 is connected to the first drain 311 of the first thin-film transistor 31.

[0092] In some embodiments, see Figure 6 and Figure 8 In this embodiment, the orthographic projection of the first capacitor 60 on the substrate is located on the side of the first thin-film transistor 31 adjacent to the orthographic projection of the second thin-film transistor 32 on the substrate. Exemplarily, the first thin-film transistor 31 and the second thin-film transistor 32 are staggered in the length and width directions of the non-display area B. The first capacitor 60 is located on the side of the first thin-film transistor 31 adjacent to the second thin-film transistor 32 in the length and width directions of the non-display area B. The proximity of the first capacitor 60 to the first thin-film transistor 31 improves the stability of the gate bootstrap of the first thin-film transistor 31, ensuring reliable output of the cascaded output signal.

[0093] According to the embodiments of this application, by positioning the orthographic projection of the first capacitor 60 on the substrate adjacent to the orthographic projection of the first thin-film transistor 31 on the substrate, the transmission distance of moisture from the first capacitor 60 to the second thin-film transistor 32 can be extended without affecting the layout of the non-display area B, thereby increasing the moisture barrier distance. Furthermore, the high density between the first insulating layer 20 and the second insulating layer 40 alters the moisture intrusion channel, blocking moisture intruding from the first capacitor 60 through the high density channel formed between the first insulating layer 20 and the second insulating layer 40, preventing moisture from reaching the second thin-film transistor 32. This improves the reliability of the display panel 1 under high temperature and high humidity conditions.

[0094] In some embodiments, see Figure 6 and Figure 8The orthographic projection of the first via 21 on the substrate is located on the side of the orthographic projection of the first thin film transistor 31 on the substrate that is away from the second thin film transistor 32.

[0095] In some examples, the first metal layer 10 includes a first portion 11 and a second portion 12. The first portion 11 extends along the width direction of the non-display area B, and the second portion 12 extends along the length direction of the non-display area B. One end of the first portion 11 is connected to the second electrode plate 62 through a first via 21, and the other end of the first portion 11 is connected to one end of the second portion 12. The other end of the second portion 12 is electrically connected to the second source 321 of the second thin film transistor 32 through a second via 22.

[0096] According to the embodiments of this application, the orthogonal projection of the first via 21 on the substrate is located on the side of the orthogonal projection of the first thin-film transistor 31 on the substrate that is away from the second thin-film transistor 32. This can further extend the transmission path of water vapor from the first capacitor 60 to the second source 321 of the second thin-film transistor 32 via the first via 21, the first metal layer 10, and the second via 22. This effectively reduces the probability of water vapor intruding into the second thin-film transistor 32 along the first via 21 and the second via 22, thereby further ensuring that the performance of the second thin-film transistor 32 during the noise reduction process is not affected by the water vapor in the first capacitor 60.

[0097] In some embodiments, see Figure 6 and Figure 8 The first thin-film transistor 31 has a first side away from the second thin-film transistor 32 and a second side adjacent to the second thin-film transistor 32. The first via 21 is located near the first side of the first thin-film transistor 31. One end of the first metal layer 10 is connected to the first via 21, and the other end is connected to the second via 22 after surrounding the first and second sides.

[0098] According to the embodiments of this application, by connecting one end of the first metal layer 10 to the first via 21 and the other end around the first and second sides and connecting it to the second via 22, the transmission path of moisture from the first capacitor 60 to the second source 321 of the second thin-film transistor 32 via the first via 21, the first metal layer 10, and the second via 22 can be further extended. This effectively reduces the probability of moisture intruding into the second thin-film transistor 32 along the first and second vias 21 and 22, thereby further ensuring that the performance of the second thin-film transistor 32 during the noise reduction process is not affected by the moisture in the first capacitor 60. Secondly, the wiring method of the first metal layer 10 surrounding the first thin-film transistor 31 can make the layout of the non-display area B of the display panel 1 more compact, realizing the narrow bezel design of the non-display area B.

[0099] In some embodiments, the second electrode plate 62 and the second thin-film transistor 32 are alternately arranged along the length of the display panel 1.

[0100] In another aspect, this application also provides a display device including a display panel 1 as described in any of the preceding embodiments. It will be understood that this display device may possess all the features and advantages of the display panel 1 described above, which will not be repeated here.

[0101] In some embodiments, the display device is a foldable product with image display capabilities. Optionally, the display device can be used to display static images, such as pictures, photographs, etc.; the display device can also be used to display dynamic images, such as videos, game screens, etc.

[0102] In the description of this specification, it should be understood that the terms "center," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0103] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0104] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a communication connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0105] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0106] The foregoing disclosure provides many different implementations or examples for carrying out different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described above. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various implementations and / or arrangements discussed.

[0107] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various variations or substitutions within the technical scope disclosed in this application, and these should all be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A display panel, characterized in that, include: Substrate; A first metal layer is disposed on one side of the substrate and includes the first electrode plate of the first capacitor; A first insulating layer is disposed on the side of the first metal layer away from the substrate. The second metal layer is disposed on the side of the first insulating layer away from the substrate, and includes the first drain of the first thin film transistor, the second electrode of the first capacitor, and the second source of the second thin film transistor. The second electrode is electrically connected to the first drain of the first thin film transistor. The second insulating layer is disposed on the side of the second metal layer away from the substrate and partially covers the first insulating layer. The first thin-film transistor is configured to output a cascaded output signal, and the second thin-film transistor is configured to reduce noise in the cascaded output signal. A first via and a second via are defined on the first insulating layer. The first drain of the first thin-film transistor is connected to the first metal layer through the first via, and the first metal layer is electrically connected to the second source of the second thin-film transistor through the second via.

2. The display panel according to claim 1, characterized in that, The display panel has a display area and a non-display area surrounding the display area, and the first capacitor is located on the side of the first thin-film transistor adjacent to the display area.

3. The display panel according to claim 2, characterized in that, The orthographic projection of the first via on the substrate is located on the side of the first thin-film transistor on the substrate adjacent to the orthographic projection of the second thin-film transistor, and the orthographic projection of the second via on the substrate is located on the side of the second thin-film transistor on the substrate adjacent to the orthographic projection of the first thin-film transistor.

4. The display panel according to claim 2, characterized in that, The first via and the second via are arranged at intervals along the length of the display panel.

5. The display panel according to claim 2, characterized in that, The second electrode extends along the width direction of the display panel, and the first metal layer extends along the length direction of the display panel.

6. The display panel according to claim 1, characterized in that, The orthographic projection of the first capacitor on the substrate is located on the side of the orthographic projection of the first thin-film transistor on the substrate adjacent to the second thin-film transistor.

7. The display panel according to claim 6, characterized in that, The orthographic projection of the first via on the substrate is located on the side of the first thin-film transistor on the substrate away from the orthographic projection of the second thin-film transistor.

8. The display panel according to claim 7, characterized in that, The first thin-film transistor has a first side away from the second thin-film transistor and a second side adjacent to the second thin-film transistor. The first via is located near the first side of the first thin-film transistor. One end of the first metal layer is connected to the first via, and the other end surrounds the first side and the second side and is connected to the second via.

9. The display panel according to any one of claims 1 to 8, characterized in that, Along the length of the display panel, the second electrode plate and the second thin-film transistor are arranged alternately.

10. The display panel according to any one of claims 1 to 8, characterized in that, The distance between the first thin-film transistor and the edge of the display area is smaller than the distance between the second thin-film transistor and the edge of the display area.

11. The display panel according to any one of claims 2 to 8, characterized in that, The orthographic projection of the first capacitor on the substrate is located on the side of the first metal layer on the substrate adjacent to the display area, and the orthographic projection of the second thin-film transistor on the substrate is located on the side of the first metal layer on the substrate away from the display area.

12. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 11.

Images