Array substrate and display panel

Abstract

Embodiments of the present application provide an array substrate and a display panel. The array substrate comprises: a substrate; pixel circuits arranged on the substrate and arrayed along a first direction and a second direction; and first signal lines arranged on a side of the pixel circuits away from the substrate, the first signal lines extending along the second direction and used for connecting a plurality of pixel circuits arranged along the second direction. At least two pixel circuits adjacent along the second direction are symmetrically arranged about a first axis extending along the first direction, and the first signal lines connect two symmetrically arranged pixel circuits via a same first via. The present application can improve the arrangement density of the pixel circuits, thereby facilitating the improvement of the pixel density of the display panel, and can improve the display effect of the display panel, thereby improving the use effect of the display panel.

Description

Technical Field

[0001] This application relates to the field of display device technology, and more particularly to an array substrate and a display panel. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and flat panel displays based on light-emitting diodes (LEDs) are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, energy saving, thin body, and wide range of applications, becoming the mainstream of display devices.

[0003] However, the performance of current OLED display products needs to be improved. Summary of the Invention

[0004] This application provides an array substrate and a display panel, which aim to improve the performance of the display panel.

[0005] An embodiment of the first aspect of this application provides an array substrate, comprising: a substrate; pixel circuits disposed on the substrate and arranged in an array along a first direction and a second direction; a first signal line disposed on the side of the pixel circuits facing away from the substrate, the first signal line extending along the second direction and used to connect a plurality of pixel circuits arranged along the second direction; wherein at least two adjacent pixel circuits along the second direction are symmetrically distributed about a first axis extending along the first direction, and the first signal line connects the two symmetrically arranged pixel circuits via the same first via.

[0006] According to an embodiment of the first aspect of this application, a pixel circuit includes a plurality of transistors, the plurality of transistors including a first transistor, and a first signal line connects the first transistors of two symmetrically arranged pixel circuits via the same first via.

[0007] According to any of the foregoing embodiments of the first aspect of this application, the first signal line is a data signal line and the first transistor is a data write transistor; or, the first signal line is a drive power supply voltage signal line and the first transistor is a drive transistor.

[0008] According to any of the foregoing embodiments of the first aspect of this application, the first signal line is a data signal line, the first transistor is a data write transistor, and the multiplexing of the first transistors in the two pixel circuits arranged symmetrically to each other further includes:

[0009] The second signal line is located on the side of the pixel circuit away from the substrate. The second signal line extends and is formed along the first direction and is used to connect multiple pixel circuits that are spaced apart along the first direction.

[0010] Two pixel circuits, symmetrically arranged relative to the first axis, are connected to the same second signal line.

[0011] According to any of the foregoing embodiments of the first aspect of this application, the plurality of transistors includes a second transistor, and a second signal line is connected to the second transistor of two symmetrically arranged pixel circuits.

[0012] According to any of the foregoing embodiments of the first aspect of this application, the second signal line is a drive power supply voltage signal line and the second transistor is a drive transistor; or, the second signal line is a reference voltage signal line and the second transistor is a reset transistor or a threshold compensation transistor.

[0013] According to any of the foregoing embodiments of the first aspect of this application, it further includes:

[0014] The third signal line extends along the second direction and is used to connect multiple pixel circuits arranged along the second direction;

[0015] At least two pixel circuits are symmetrically distributed about a second axis extending along a second direction, and the two third signal lines connected by the two symmetrical pixel circuits are at least partially overlapped in the orthogonal projection of the substrate.

[0016] According to any of the foregoing embodiments of the first aspect of this application, the pixel circuit includes a plurality of transistors, the plurality of transistors including a data writing transistor, and a third signal line is a data signal line, the third signal line being electrically connected to the data writing transistor of the pixel circuit.

[0017] According to any of the foregoing embodiments of the first aspect of this application, the data writing transistor includes a source electrode and a drain electrode, and two overlapping third signal lines include a first sub-line and a second sub-line. The first sub-line is disposed on the same layer as the source electrode and the drain electrode, and the second sub-line is connected to a connection portion. The connection portion extends along a first direction to connect with the via of the data writing transistor.

[0018] According to any of the foregoing embodiments of the first aspect of this application, the second sub-line is located on the side of the first sub-line facing away from the substrate.

[0019] Alternatively, the substrate may include a first sublayer and a second sublayer stacked together, with the second sub-line located between two adjacent first sublayers.

[0020] An embodiment of the first aspect of this application also provides an array substrate, comprising: a substrate; pixel circuits disposed on the substrate and arrayed along a first direction and a second direction; a third signal line extending along the second direction and used to connect a plurality of pixel circuits arranged along the second direction; at least two pixel circuits are symmetrically distributed about a second axis extending along the second direction, and the two third signal lines connected to the mutually symmetrical pixel circuits at least partially overlap in their orthogonal projections on the substrate.

[0021] An embodiment of the second aspect of this application also provides a display panel including any of the array substrates described in the first aspect above.

[0022] The array substrate provided in this application embodiment includes a substrate and pixel circuits and a first signal line disposed on the substrate. Multiple pixel circuits are arrayed along a first direction and a second direction, enabling them to drive multiple sub-pixels distributed in the display panel array. The first signal line extends along the second direction and connects the multiple pixel circuits arranged along the second direction. When at least two adjacent pixel circuits along the second direction are symmetrically arranged about a first axis, these two pixel circuits can also maintain their arrangement along the second direction and be electrically connected to the same first signal line. The first signal line can connect the two symmetrically arranged pixel circuits through the same first via, which can reduce the number of first vias, reduce the distance between two symmetrically arranged adjacent pixel circuits, increase the pixel circuit density, and thus facilitate increasing the pixel density of the display panel, improving the display effect and ultimately enhancing the usability of the display panel. Attached Figure Description

[0023] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings, wherein the same or similar reference numerals denote the same or similar features.

[0024] Figure 1 This is a partial structural diagram of a display panel provided in an embodiment of this application;

[0025] Figure 2 This is a schematic diagram of the pixel circuit structure of a display panel provided in an embodiment of this application;

[0026] Figure 3 This is a partial structural schematic diagram of a display panel provided in another embodiment of this application;

[0027] Figure 4 This is a partial structural schematic diagram of a display panel provided in another embodiment of this application;

[0028] Figure 5 This is a partial structural schematic diagram of a display panel provided in another embodiment of this application;

[0029] Figure 6 One example Figure 5 A partial sectional view;

[0030] Figure 7 In another example Figure 5 A sectional view.

[0031] Explanation of reference numerals in the attached figures:

[0032] 100, Substrate; 110, First sublayer; 120, Second sublayer;

[0033] 200, Pixel circuit; T1, Driving transistor; T2, Data writing transistor; T3, Threshold compensation transistor; T4, Driving reset transistor; T5, First light-emitting control transistor; T6, Second light-emitting control transistor; T7, Anode reset transistor;

[0034] 310, First signal line; 320, Second signal line; 330, Third signal line; 331, First sub-line; 332, Second sub-line; 340, Connector;

[0035] 410, First via; Data, Data signal line; Scan, Scan signal line; VDD, Drive power supply voltage signal line; Vref, Reference voltage signal line;

[0036] X, first direction; Y, second direction; L1, first axis; L2, second axis. Detailed Implementation

[0037] The features and exemplary embodiments of various aspects of this application will now be described in detail. Numerous specific details are set forth in the following detailed description to provide a comprehensive understanding of this application. However, it will be apparent to those skilled in the art that this application can be implemented without requiring some of these specific details. The following description of embodiments is merely intended to provide a better understanding of this application by illustrating examples. In the accompanying drawings and the following description, at least some well-known structures and techniques are not shown to avoid unnecessarily obscuring the application; and, for clarity, the dimensions of some structures may be exaggerated. Furthermore, the features, structures, or characteristics described below can be combined in any suitable manner in one or more embodiments.

[0038] In the description of this application, it should be noted that, unless otherwise stated, "a plurality of" means two or more; the terms "upper," "lower," "left," "right," "inner," "outer," etc., indicating orientation or positional relationships are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0039] The directional terms appearing in the following description refer to the directions shown in the figures and are not intended to limit the specific structure of the embodiments of this application. It should also be noted in the description of this application that, unless otherwise explicitly specified and limited, the terms "installation" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0040] like Figure 1 and Figure 2 As shown, an embodiment of the first aspect of this application provides an array substrate, including: a substrate 100; pixel circuits 200 disposed on the substrate 100 and arranged in an array along a first direction X and a second direction Y; a first signal line 310 disposed on the side of the pixel circuits 200 away from the substrate 100, the first signal line 310 extending along the second direction Y and used to connect a plurality of pixel circuits 200 arranged along the second direction Y; wherein at least two adjacent pixel circuits 200 along the second direction Y are symmetrically distributed about a first axis L1 extending along the first direction X, and the first signal line 310 connects the two symmetrically arranged pixel circuits 200 via the same first via 410.

[0041] The array substrate provided in this application embodiment includes a substrate 100 and pixel circuits 200 and a first signal line 310 disposed on the substrate 100. Multiple pixel circuits 200 are arrayed along a first direction X and a second direction Y, enabling them to drive multiple sub-pixels distributed in the display panel array. The first signal line 310 extends along the second direction Y and connects to the multiple pixel circuits 200 arranged along the second direction Y. When at least two adjacent pixel circuits 200 along the second direction Y are symmetrically arranged about a first axis L1, these two pixel circuits 200 can also maintain their arrangement along the second direction Y and be electrically connected to the same first signal line 310. The first signal line 310 can connect the two symmetrically arranged pixel circuits 200 through the same first via 410, which reduces the number of first vias 410, decreases the distance between two symmetrically arranged adjacent pixel circuits 200, increases the arrangement density of the pixel circuits 200, and thus facilitates increasing the pixel density of the display panel, improving the display effect and ultimately enhancing the usability of the display panel.

[0042] Optionally, the substrate 100 can be a glass substrate or a flexible substrate 100, such as polyimide.

[0043] Optionally, the circuit structure of the pixel circuit 200 can be any one of a 2T1C circuit, a 7T1C circuit, a 7T2C circuit, or an 8T1C circuit. In this document, a "2T1C circuit" refers to a pixel circuit 200 that includes two thin-film transistors T (T) and one capacitor (C). For example... Figure 3 As shown, this embodiment of the application uses a 7T1C circuit as an example to illustrate the pixel circuit 200.

[0044] Optionally, the pixel circuit 200 may include multiple transistors. For example, the multiple transistors T of the pixel circuit 200 may include a driving transistor T1, a switching transistor, a light-emitting control transistor, a reset transistor, and a threshold compensation transistor T3, etc. The first transistor may be at least one of the driving transistor T1, the switching transistor, the light-emitting control transistor, the reset transistor, and the threshold compensation transistor T3, etc.

[0045] Optionally, the pixel circuit 200 includes a driving transistor T1, which is connected to the anode of the light-emitting unit of the display panel and drives the light-emitting unit to emit light. Optionally, the pixel circuit 200 also includes a data writing transistor T2, which applies a data signal to the gate g of the driving transistor T1. Optionally, the pixel circuit 200 also includes a threshold compensation transistor T3, which is electrically connected to the gate g of the driving transistor T1. The threshold compensation transistor T3 is used to compensate for the threshold voltage of the driving transistor T1. Optionally, the pixel circuit 200 also includes a drive reset transistor T4, which is electrically connected to the gate g of the driving transistor T1. Optionally, the pixel circuit 200 also includes a first light-emitting control transistor T5 and a second light-emitting control transistor T6, one of which is connected to the source s of the driving transistor T1, and the other is connected to the drain d of the driving transistor T1. Optionally, the driving transistor T1 is connected between the first light-emitting control transistor T5 and the second light-emitting control transistor T6. Optionally, the pixel circuit 200 also includes an anode reset transistor T7. The anode reset transistor T7 is used to connect to the anode of the light-emitting unit of the display panel 20, and is used to reset the anode to improve the display effect of the display panel 20.

[0046] In some alternative embodiments, when the pixel circuit 200 includes a plurality of transistors, the plurality of transistors include a first transistor, and a first signal line 310 connects the first transistors of two symmetrically arranged pixel circuits 200 via the same first via 410.

[0047] In these alternative embodiments, when two adjacent pixel circuits 200 along the second direction Y are symmetrically distributed about the first axis L1, the first transistors of the two pixel circuits 200 can be arranged closer together, so that the first signal line 310 can connect the two first transistors through the same first via 410, and the distance from the first signal line 310 to the two first transistors is close, which can improve the uniformity of the display.

[0048] Optionally, the first signal line 310 can be a data signal line Data, and the first transistor can be the aforementioned data writing transistor T2.

[0049] In these alternative embodiments, the data signal line Data can connect two data write transistors T2 through the same first via 410, and these two data write transistors T2 belong to the same column. Therefore, this application can save a first via 410 without affecting the connection between the data signal line Data and the pixel circuit 200, thereby reducing the spacing between the pixel circuits 200 and increasing the distribution density of the pixel circuits 200.

[0050] In another optional embodiment, the first signal line 310 is the drive power supply voltage signal line VDD, and the first transistor is the drive transistor T1.

[0051] In these optional embodiments, the first signal line 310 is a driving power supply voltage signal line VDD, which extends along the second direction Y and is used to drive multiple pixel circuits 200 in the same column. The driving power supply voltage signal line VDD can connect two driving transistors T1 through the same first via 410, and these two driving transistors T1 belong to the same column. Therefore, this application can save a first via 410 and reduce the spacing between pixel circuits 200 without affecting the connection between the driving power supply voltage signal line VDD and the pixel circuits 200, thereby increasing the distribution density of the pixel circuits 200.

[0052] In some optional embodiments, when the first signal line 310 is a data signal line Data and the first transistor is a data write transistor T2, the first transistors of the two pixel circuits 200 arranged symmetrically to each other are multiplexed.

[0053] In these optional embodiments, when the first signal line 310 is a data signal line Data and the first transistor is a data writing transistor T2, the data writing transistors T2 of the two symmetrically arranged pixel circuits 200 will simultaneously apply data signals to the gate g of the driving transistor T1. The multiplexing of the first transistors of the two symmetrically arranged pixel circuits 200 will not affect the performance of each pixel circuit 200, and can further save the space occupied by the pixel circuits 200, reduce the spacing between the pixel circuits 200, and thus improve the distribution density of the pixel circuits 200.

[0054] When the first transistors of two symmetrically arranged pixel circuits 200 are multiplexed, the first transistors can be connected to the gates of the two driving transistors T1, for example, the source or drain of the first transistor is connected to the gates of the two driving transistors T1.

[0055] In some alternative embodiments, such as Figure 2 and Figure 3 As shown, the array substrate also includes a second signal line 320. The second signal line 320 is located on the side of the pixel circuit 200 away from the substrate 100. The second signal line 320 extends and is formed along the first direction X and is used to connect a plurality of pixel circuits 200 that are spaced apart along the first direction X. Two pixel circuits 200 that are symmetrically arranged relative to the first axis L1 are connected to the same second signal line 320.

[0056] In these optional embodiments, the array substrate further includes a second signal line 320 extending along a first direction X for connecting multiple pixel circuits 200 in the same row. Two pixel circuits 200 symmetrically arranged relative to the first axis L1 are connected to the same second signal line 320, which can save the number of second signal lines 320, thereby reducing the spacing between pixel circuits 200 and increasing the distribution density of pixel circuits 200.

[0057] Optionally, the plurality of transistors includes a second transistor, and the second signal line 320 is connected to the second transistors of the two symmetrically arranged pixel circuits 200. The second transistor can be the aforementioned driving transistor T1, reset transistor, compensation transistor, etc.

[0058] In some optional embodiments, the second signal line 320 is the drive power supply voltage signal line VDD, and the second transistor is the drive transistor T1.

[0059] In these optional embodiments, when the second signal line 320 is the driving power supply voltage signal line VDD and the second transistor is the driving transistor T1, the driving power supply voltage signal line VDD extends along the first direction X and is used to drive multiple pixel circuits 200 in the same row. In the embodiments of this application, the driving power supply voltage signal line VDD can drive two adjacent rows of pixel circuits 200, which can improve the distribution density of the pixel circuits 200.

[0060] In some alternative embodiments, the second signal line 320 is a reference voltage signal line Vref, and the second transistor is a reset transistor or a threshold compensation transistor T3.

[0061] In these optional embodiments, when the second signal line 320 is a reference voltage signal line Vref and the second transistor is a reset transistor or a threshold compensation transistor T3, the reference voltage signal line Vref extends along the first direction X and is used to drive multiple pixel circuits 200 in the same row. In the embodiments of this application, the reference voltage signal line Vref can drive two adjacent rows of pixel circuits 200, which can improve the distribution density of the pixel circuits 200.

[0062] Optionally, the second transistor can be at least one of the threshold compensation transistor T3, drive reset transistor T4, and anode reset transistor T7 mentioned above.

[0063] Optionally, the array substrate includes scan signal lines Scan, which are connected to the gate of the data writing transistor T2. Scan extends along a first direction X and is used to connect multiple pixel circuits 200 arranged in the same row. The number of scan signal lines Scan can be the same as the number of rows of pixel circuits 200, so that each row of pixel circuits 200 is correspondingly provided with a scan signal line Scan. When both the scan signal line Scan and the data signal line Data simultaneously input signals to the data writing transistor T2, the data writing transistor T2 is turned on, causing the driving transistor T1 to turn on. The driving power supply voltage signal line VDD can then be transmitted to the light-emitting unit via the driving transistor T1, driving the light-emitting unit to emit light. The number of scan signal lines Scan is the same as the number of rows of pixel circuits 200, allowing each pixel circuit 200 to be driven independently, achieving the purpose of individually lighting each sub-pixel of the display panel.

[0064] With the number of Scan signal lines being the same as the number of rows of pixel circuits 200, the drive power supply voltage signal line VDD can drive two adjacent rows of pixel circuits 200, and the data signal line Data can connect two symmetrical pixel circuits 200, without affecting the individual driving of pixel circuits 200.

[0065] In some alternative embodiments, such as Figure 2 and Figure 4 As shown, the array substrate also includes a third signal line 330, which extends along the second direction Y and is used to connect a plurality of pixel circuits 200 arranged along the second direction Y; at least two pixel circuits 200 are symmetrically distributed about a second axis L2 extending along the second direction Y, and the two third signal lines 330 connecting the two symmetrical pixel circuits 200 are at least partially overlapped in the orthographic projection of the substrate 100.

[0066] In these optional embodiments, the third signal line 330 extends along the second direction Y to connect multiple pixel circuits 200 in the same column. At least two pixel circuits 200 are symmetrical about the second axis L2, which facilitates the arrangement of the third signal line 330 between the two pixel circuits 200. By making the orthographic projections of the two third signal lines 330 connected by the two symmetrical pixel circuits 200 on the substrate 100 at least partially overlap, the area occupied by the projections of the two third signal lines 330 connected by the two pixel circuits 200 can be reduced, the spacing between the two pixel circuits 200 symmetrically arranged relative to the second axis L2 can be reduced, and the distribution density of the pixel circuits 200 can be improved.

[0067] Optionally, the pixel circuit 200 includes multiple transistors, including a data writing transistor T2, and a third signal line 330 is a data signal line Data, which is electrically connected to the data writing transistor T2 of the pixel circuit 200.

[0068] In these optional embodiments, the third signal line 330 is a data signal line Data. The data signal lines Data corresponding to two adjacent columns of pixel circuits 200 at least partially overlap in their orthogonal projections on the substrate. This can reduce the spacing between two pixel circuits 200 that are symmetrically arranged relative to the second axis L2 and improve the distribution density of the pixel circuits 200.

[0069] Optional, such as Figure 5 As shown, when both the first signal line 310 and the third signal line 330 are data signal lines, the first signal line 310 and the third signal line 330 are multiplexed, so that the data signal lines Data can not only connect two adjacent pixel circuits 200 through the same first via 410, but also at least two data signal lines Data have at least partial overlap in their orthogonal projections on the substrate, which can further reduce the spacing between each pixel circuit 200 and increase the distribution density of the pixel circuits 200.

[0070] In some alternative embodiments, such as Figures 4 to 7 As shown, the data writing transistor T2 includes a source electrode and a drain electrode. The two overlapping third signal lines 330 include a first sub-line 331 and a second sub-line 332. The first sub-line 331 is disposed on the same layer as the source electrode and the drain electrode. The second sub-line 332 is connected to a connection portion 340. The connection portion 340 extends along the first direction X to connect with the via of the data writing transistor T2.

[0071] In these alternative embodiments, when the orthographic projections of the two third signal lines 330 on the substrate 100 at least partially overlap, one of the two third signal lines 330 (the first sub-line 331) is disposed on the same layer as the source and drain electrodes of the data writing transistor T2, and the other (the second sub-layer 120) is disposed on a different layer as the source and drain electrodes of the data writing transistor T2. The second sub-line 332 can be connected to the via of the data writing transistor T2 through the connection portion 340.

[0072] Optionally, the second sub-line 332 may be located on the side of the first sub-line 331 away from the substrate 100. For example, a new conductive layer may be added on the side of the array substrate away from the substrate 100, so that the second sub-line 332 is located within the new conductive layer.

[0073] Alternatively, in some other optional embodiments, the substrate 100 includes a first sublayer 110 and a second sublayer 120 stacked together, with the second sub-line 332 located between two adjacent first sublayers 110. That is, a new conductive layer can be added between the first sublayer 110 and the second sublayer 120 of the substrate 100, with the second sub-line 332 located between the first sublayer 110 and the second sublayer 120 of the substrate 100.

[0074] like Figures 1 to 7 As shown, an embodiment of the first aspect of this application also provides an array substrate, including: a substrate 100; pixel circuits 200 disposed on the substrate 100 and arrayed along a first direction X and a second direction Y; a third signal line 330 extending along the second direction Y and used to connect a plurality of pixel circuits 200 arranged along the second direction Y; at least two pixel circuits 200 are symmetrically distributed about a second axis L2 extending along the second direction Y, and the two third signal lines 330 connected to the two symmetrical pixel circuits 200 at least partially overlap in their orthogonal projections on the substrate 100.

[0075] The array substrate provided in this application embodiment includes a substrate 100 and pixel circuits 200 and third signal lines 330 disposed on the substrate 100. Multiple pixel circuits 200 are arrayed along a first direction X and a second direction Y, enabling them to drive multiple sub-pixels distributed in the display panel array. The third signal lines 330 extend along the second direction Y and connect to the multiple pixel circuits 200 arranged along the second direction Y. When at least two adjacent pixel circuits 200 along the second direction Y are symmetrically arranged about a first axis L1, and the two third signal lines 330 connected to the two symmetrically arranged pixel circuits 200 at least partially overlap in their orthographic projections onto the substrate 100, the overall area occupied by the orthographic projections of the third signal lines 330 on the substrate 100 can be reduced, the distance between two symmetrically arranged adjacent pixel circuits 200 can be reduced, the arrangement density of the pixel circuits 200 can be increased, thereby facilitating an increase in the pixel density of the display panel, improving the display effect of the display panel, and ultimately improving the usability of the display panel.

[0076] Optionally, the display panel of this application embodiment and any of the above embodiments can be cross-referenced. For example, the third signal line 330 includes the first sub-line 331 and the second sub-line 332 described above.

[0077] The second aspect of this application also provides a display panel including the array substrate of any of the first aspect embodiments described above. Since the display panel provided in the second aspect of this application includes the array substrate of any of the first aspect embodiments described above, it has the beneficial effects of the array substrate of any of the first aspect embodiments described above, which will not be elaborated further here.

[0078] The third aspect of this application also provides a display device, including the display panel 20 of any of the second aspect embodiments or the array substrate of any of the first aspect embodiments. Since the display device provided in the third aspect of this application includes the display panel 20 of any of the second aspect embodiments or the array substrate of any of the first aspect embodiments, the display device provided in the third aspect of this application has the beneficial effects of the display panel 20 of any of the second aspect embodiments or the array substrate of any of the first aspect embodiments, which will not be elaborated further here.

[0079] The display devices in this application include, but are not limited to, mobile phones, personal digital assistants (PDAs), tablet computers, e-books, televisions, access control systems, smart landline phones, control consoles, and other devices with display functions.

[0080] Although this application has been described with reference to preferred embodiments, various modifications can be made thereto and components can be replaced with equivalents without departing from the scope of this application. In particular, the technical features mentioned in the various embodiments can be combined in any manner, provided there is no structural conflict. This application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. An array substrate, characterized in that, The array substrate includes: Substrate; Pixel circuits are disposed on the substrate and distributed in an array along a first direction and a second direction; A first signal line is disposed on the side of the pixel circuit facing away from the substrate. The first signal line extends along the second direction and is used to connect a plurality of pixel circuits arranged along the second direction. In this configuration, at least two adjacent pixel circuits along the second direction are symmetrically distributed about a first axis extending along the first direction, and the first signal line connects the two symmetrically arranged pixel circuits via the same first via.

2. The array substrate according to claim 1, characterized in that, The pixel circuit includes a plurality of transistors, the plurality of transistors including a first transistor, and the first signal line is connected to the first transistors of two symmetrically arranged pixel circuits via the same first via. Preferably, the first signal line is a data signal line and the first transistor is a data write transistor; or, the first signal line is a drive power supply voltage signal line and the first transistor is a drive transistor.

3. The array substrate according to claim 2, characterized in that, The first signal line is a data signal line, the first transistor is a data write transistor, and the first transistors of the two pixel circuits arranged symmetrically to each other are multiplexed.

4. The array substrate according to claim 2, characterized in that, Also includes: The second signal line is located on the side of the pixel circuit away from the substrate. The second signal line extends and is formed along the first direction and is used to connect a plurality of pixel circuits that are spaced apart along the first direction. The two pixel circuits, which are symmetrically arranged relative to the first axis, are connected to the same second signal line; Preferably, the plurality of transistors includes a second transistor, and the second signal line is connected to the second transistor of two symmetrically arranged pixel circuits; Preferably, the second signal line is a drive power supply voltage signal line, and the second transistor is a drive transistor; or, the second signal line is a reference voltage signal line, and the second transistor is a reset transistor or a threshold compensation transistor.

5. The array substrate according to claim 1, characterized in that, Also includes: A third signal line extends along the second direction and is used to connect a plurality of pixel circuits arranged along the second direction; At least two of the pixel circuits are symmetrically distributed about a second axis extending along the second direction, and the two third signal lines connected by the two symmetrical pixel circuits are at least partially overlapped in their orthogonal projections onto the substrate.

6. The array substrate according to claim 5, characterized in that, The pixel circuit includes multiple transistors, including a data writing transistor. The third signal line is a data signal line and is electrically connected to the data writing transistor of the pixel circuit.

7. The array substrate according to claim 6, characterized in that, The data writing transistor includes a source electrode and a drain electrode. The two overlapping third signal lines include a first sub-line and a second sub-line. The first sub-line is disposed on the same layer as the source electrode and the drain electrode. The second sub-line is connected to a connection portion, which extends along the first direction to connect with the via of the data writing transistor.

8. The array substrate according to claim 7, characterized in that, The second sub-line is located on the side of the first sub-line that faces away from the substrate. Alternatively, the substrate may include a first sublayer and a second sublayer stacked together, with the second sub-line located between two adjacent first sublayers.

9. An array substrate, characterized in that, include: Substrate; Pixel circuits are disposed on the substrate and distributed in an array along a first direction and a second direction; A third signal line extends along the second direction and is used to connect a plurality of pixel circuits arranged along the second direction; At least two of the pixel circuits are symmetrically distributed about a second axis extending along the second direction, and the two third signal lines connected by the two symmetrical pixel circuits are at least partially overlapped in their orthogonal projections onto the substrate.

10. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1-9.

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